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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-17 12:56:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-17 12:56:43 -0400
commitfd34b0dee4d237ce9332cc62b03adebfe4fa9f9d (patch)
treefa37676f7f696be7104ea116ab9c72dc8bbbc70e /drivers
parent40c7f2112ce18fa5eb6dc209c50dd0f046790191 (diff)
parentc9ac1361d2258a667672cf531cd840807daba4f1 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev-2.6: fbdev: sh_mobile_lcdc: Add YUV framebuffer support viafb: split pll configs up viafb: remove duplicated clock storage viafb: always return the best possible clock viafb: remove duplicated clock information fbdev: sh_mobile_lcdcfb: add backlight support viafb: factor lcd scaling parameters out viafb: strip some structures viafb: remove unused data_mode and device_type viafb: kill lcd_panel_id video via: make local variables static video via: fix iomem access video/via: drop deprecated (and unused) i2c_adapter.id
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/Kconfig1
-rw-r--r--drivers/video/sh_mobile_lcdcfb.c222
-rw-r--r--drivers/video/sh_mobile_lcdcfb.h4
-rw-r--r--drivers/video/via/chip.h9
-rw-r--r--drivers/video/via/dvi.c4
-rw-r--r--drivers/video/via/hw.c772
-rw-r--r--drivers/video/via/hw.h2
-rw-r--r--drivers/video/via/lcd.c83
-rw-r--r--drivers/video/via/share.h141
-rw-r--r--drivers/video/via/tblDPASetting.c23
-rw-r--r--drivers/video/via/tblDPASetting.h2
-rw-r--r--drivers/video/via/via_i2c.c3
-rw-r--r--drivers/video/via/viafbdev.c6
-rw-r--r--drivers/video/via/viamode.c507
-rw-r--r--drivers/video/via/viamode.h9
-rw-r--r--drivers/video/via/vt1636.c43
16 files changed, 777 insertions, 1054 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index b57bc273b184..e6791f7ecfb4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1942,6 +1942,7 @@ config FB_SH_MOBILE_LCDC
1942 select FB_SYS_IMAGEBLIT 1942 select FB_SYS_IMAGEBLIT
1943 select FB_SYS_FOPS 1943 select FB_SYS_FOPS
1944 select FB_DEFERRED_IO 1944 select FB_DEFERRED_IO
1945 select FB_BACKLIGHT
1945 select SH_MIPI_DSI if SH_LCD_MIPI_DSI 1946 select SH_MIPI_DSI if SH_LCD_MIPI_DSI
1946 ---help--- 1947 ---help---
1947 Frame buffer driver for the on-chip SH-Mobile LCD controller. 1948 Frame buffer driver for the on-chip SH-Mobile LCD controller.
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index bf12e53aed5c..bf2629f83f40 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -21,6 +21,8 @@
21#include <linux/ioctl.h> 21#include <linux/ioctl.h>
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/console.h> 23#include <linux/console.h>
24#include <linux/backlight.h>
25#include <linux/gpio.h>
24#include <video/sh_mobile_lcdc.h> 26#include <video/sh_mobile_lcdc.h>
25#include <asm/atomic.h> 27#include <asm/atomic.h>
26 28
@@ -67,6 +69,7 @@ static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
67 [LDSM1R] = 0x428, 69 [LDSM1R] = 0x428,
68 [LDSM2R] = 0x42c, 70 [LDSM2R] = 0x42c,
69 [LDSA1R] = 0x430, 71 [LDSA1R] = 0x430,
72 [LDSA2R] = 0x434,
70 [LDMLSR] = 0x438, 73 [LDMLSR] = 0x438,
71 [LDHCNR] = 0x448, 74 [LDHCNR] = 0x448,
72 [LDHSYNR] = 0x44c, 75 [LDHSYNR] = 0x44c,
@@ -151,6 +154,7 @@ static bool banked(int reg_nr)
151 case LDDFR: 154 case LDDFR:
152 case LDSM1R: 155 case LDSM1R:
153 case LDSA1R: 156 case LDSA1R:
157 case LDSA2R:
154 case LDMLSR: 158 case LDMLSR:
155 case LDHCNR: 159 case LDHCNR:
156 case LDHSYNR: 160 case LDHSYNR:
@@ -463,6 +467,7 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
463 struct sh_mobile_lcdc_board_cfg *board_cfg; 467 struct sh_mobile_lcdc_board_cfg *board_cfg;
464 unsigned long tmp; 468 unsigned long tmp;
465 int bpp = 0; 469 int bpp = 0;
470 unsigned long ldddsr;
466 int k, m; 471 int k, m;
467 int ret = 0; 472 int ret = 0;
468 473
@@ -541,16 +546,21 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
541 } 546 }
542 547
543 /* word and long word swap */ 548 /* word and long word swap */
544 switch (bpp) { 549 ldddsr = lcdc_read(priv, _LDDDSR);
545 case 16: 550 if (priv->ch[0].info->var.nonstd)
546 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6); 551 lcdc_write(priv, _LDDDSR, ldddsr | 7);
547 break; 552 else {
548 case 24: 553 switch (bpp) {
549 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 7); 554 case 16:
550 break; 555 lcdc_write(priv, _LDDDSR, ldddsr | 6);
551 case 32: 556 break;
552 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 4); 557 case 24:
553 break; 558 lcdc_write(priv, _LDDDSR, ldddsr | 7);
559 break;
560 case 32:
561 lcdc_write(priv, _LDDDSR, ldddsr | 4);
562 break;
563 }
554 } 564 }
555 565
556 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { 566 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
@@ -561,21 +571,40 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
561 571
562 /* set bpp format in PKF[4:0] */ 572 /* set bpp format in PKF[4:0] */
563 tmp = lcdc_read_chan(ch, LDDFR); 573 tmp = lcdc_read_chan(ch, LDDFR);
564 tmp &= ~0x0001001f; 574 tmp &= ~0x0003031f;
565 switch (ch->info->var.bits_per_pixel) { 575 if (ch->info->var.nonstd) {
566 case 16: 576 tmp |= (ch->info->var.nonstd << 16);
567 tmp |= 0x03; 577 switch (ch->info->var.bits_per_pixel) {
568 break; 578 case 12:
569 case 24: 579 break;
570 tmp |= 0x0b; 580 case 16:
571 break; 581 tmp |= (0x1 << 8);
572 case 32: 582 break;
573 break; 583 case 24:
584 tmp |= (0x2 << 8);
585 break;
586 }
587 } else {
588 switch (ch->info->var.bits_per_pixel) {
589 case 16:
590 tmp |= 0x03;
591 break;
592 case 24:
593 tmp |= 0x0b;
594 break;
595 case 32:
596 break;
597 }
574 } 598 }
575 lcdc_write_chan(ch, LDDFR, tmp); 599 lcdc_write_chan(ch, LDDFR, tmp);
576 600
577 /* point out our frame buffer */ 601 /* point out our frame buffer */
578 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start); 602 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
603 if (ch->info->var.nonstd)
604 lcdc_write_chan(ch, LDSA2R,
605 ch->info->fix.smem_start +
606 ch->info->var.xres *
607 ch->info->var.yres_virtual);
579 608
580 /* set line size */ 609 /* set line size */
581 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length); 610 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
@@ -618,6 +647,11 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
618 board_cfg->display_on(board_cfg->board_data, ch->info); 647 board_cfg->display_on(board_cfg->board_data, ch->info);
619 module_put(board_cfg->owner); 648 module_put(board_cfg->owner);
620 } 649 }
650
651 if (ch->bl) {
652 ch->bl->props.power = FB_BLANK_UNBLANK;
653 backlight_update_status(ch->bl);
654 }
621 } 655 }
622 656
623 return 0; 657 return 0;
@@ -648,6 +682,11 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
648 sh_mobile_lcdc_clk_on(priv); 682 sh_mobile_lcdc_clk_on(priv);
649 } 683 }
650 684
685 if (ch->bl) {
686 ch->bl->props.power = FB_BLANK_POWERDOWN;
687 backlight_update_status(ch->bl);
688 }
689
651 board_cfg = &ch->cfg.board_cfg; 690 board_cfg = &ch->cfg.board_cfg;
652 if (try_module_get(board_cfg->owner) && board_cfg->display_off) { 691 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
653 board_cfg->display_off(board_cfg->board_data); 692 board_cfg->display_off(board_cfg->board_data);
@@ -804,9 +843,15 @@ static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
804 struct sh_mobile_lcdc_priv *priv = ch->lcdc; 843 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
805 unsigned long ldrcntr; 844 unsigned long ldrcntr;
806 unsigned long new_pan_offset; 845 unsigned long new_pan_offset;
846 unsigned long base_addr_y, base_addr_c;
847 unsigned long c_offset;
807 848
808 new_pan_offset = (var->yoffset * info->fix.line_length) + 849 if (!var->nonstd)
809 (var->xoffset * (info->var.bits_per_pixel / 8)); 850 new_pan_offset = (var->yoffset * info->fix.line_length) +
851 (var->xoffset * (info->var.bits_per_pixel / 8));
852 else
853 new_pan_offset = (var->yoffset * info->fix.line_length) +
854 (var->xoffset);
810 855
811 if (new_pan_offset == ch->pan_offset) 856 if (new_pan_offset == ch->pan_offset)
812 return 0; /* No change, do nothing */ 857 return 0; /* No change, do nothing */
@@ -814,7 +859,26 @@ static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
814 ldrcntr = lcdc_read(priv, _LDRCNTR); 859 ldrcntr = lcdc_read(priv, _LDRCNTR);
815 860
816 /* Set the source address for the next refresh */ 861 /* Set the source address for the next refresh */
817 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset); 862 base_addr_y = ch->dma_handle + new_pan_offset;
863 if (var->nonstd) {
864 /* Set y offset */
865 c_offset = (var->yoffset *
866 info->fix.line_length *
867 (info->var.bits_per_pixel - 8)) / 8;
868 base_addr_c = ch->dma_handle + var->xres * var->yres_virtual +
869 c_offset;
870 /* Set x offset */
871 if (info->var.bits_per_pixel == 24)
872 base_addr_c += 2 * var->xoffset;
873 else
874 base_addr_c += var->xoffset;
875 } else
876 base_addr_c = 0;
877
878 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
879 if (base_addr_c)
880 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
881
818 if (lcdc_chan_is_sublcd(ch)) 882 if (lcdc_chan_is_sublcd(ch))
819 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS); 883 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
820 else 884 else
@@ -885,7 +949,10 @@ static void sh_mobile_fb_reconfig(struct fb_info *info)
885 /* Couldn't reconfigure, hopefully, can continue as before */ 949 /* Couldn't reconfigure, hopefully, can continue as before */
886 return; 950 return;
887 951
888 info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8); 952 if (info->var.nonstd)
953 info->fix.line_length = mode1.xres;
954 else
955 info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
889 956
890 /* 957 /*
891 * fb_set_var() calls the notifier change internally, only if 958 * fb_set_var() calls the notifier change internally, only if
@@ -980,8 +1047,80 @@ static struct fb_ops sh_mobile_lcdc_ops = {
980 .fb_check_var = sh_mobile_check_var, 1047 .fb_check_var = sh_mobile_check_var,
981}; 1048};
982 1049
983static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp) 1050static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1051{
1052 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1053 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1054 int brightness = bdev->props.brightness;
1055
1056 if (bdev->props.power != FB_BLANK_UNBLANK ||
1057 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1058 brightness = 0;
1059
1060 return cfg->set_brightness(cfg->board_data, brightness);
1061}
1062
1063static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1064{
1065 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1066 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1067
1068 return cfg->get_brightness(cfg->board_data);
1069}
1070
1071static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1072 struct fb_info *info)
1073{
1074 return (info->bl_dev == bdev);
1075}
1076
1077static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1078 .options = BL_CORE_SUSPENDRESUME,
1079 .update_status = sh_mobile_lcdc_update_bl,
1080 .get_brightness = sh_mobile_lcdc_get_brightness,
1081 .check_fb = sh_mobile_lcdc_check_fb,
1082};
1083
1084static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1085 struct sh_mobile_lcdc_chan *ch)
1086{
1087 struct backlight_device *bl;
1088
1089 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1090 &sh_mobile_lcdc_bl_ops, NULL);
1091 if (!bl) {
1092 dev_err(parent, "unable to register backlight device\n");
1093 return NULL;
1094 }
1095
1096 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1097 bl->props.brightness = bl->props.max_brightness;
1098 backlight_update_status(bl);
1099
1100 return bl;
1101}
1102
1103static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1104{
1105 backlight_device_unregister(bdev);
1106}
1107
1108static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp,
1109 int nonstd)
984{ 1110{
1111 if (nonstd) {
1112 switch (bpp) {
1113 case 12:
1114 case 16:
1115 case 24:
1116 var->bits_per_pixel = bpp;
1117 var->nonstd = nonstd;
1118 return 0;
1119 default:
1120 return -EINVAL;
1121 }
1122 }
1123
985 switch (bpp) { 1124 switch (bpp) {
986 case 16: /* PKF[4:0] = 00011 - RGB 565 */ 1125 case 16: /* PKF[4:0] = 00011 - RGB 565 */
987 var->red.offset = 11; 1126 var->red.offset = 11;
@@ -1198,6 +1337,10 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1198 init_completion(&ch->vsync_completion); 1337 init_completion(&ch->vsync_completion);
1199 ch->pan_offset = 0; 1338 ch->pan_offset = 0;
1200 1339
1340 /* probe the backlight is there is one defined */
1341 if (ch->cfg.bl_info.max_brightness)
1342 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1343
1201 switch (pdata->ch[i].chan) { 1344 switch (pdata->ch[i].chan) {
1202 case LCDC_CHAN_MAINLCD: 1345 case LCDC_CHAN_MAINLCD:
1203 ch->enabled = 1 << 1; 1346 ch->enabled = 1 << 1;
@@ -1260,6 +1403,14 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1260 k < cfg->num_cfg && lcd_cfg; 1403 k < cfg->num_cfg && lcd_cfg;
1261 k++, lcd_cfg++) { 1404 k++, lcd_cfg++) {
1262 unsigned long size = lcd_cfg->yres * lcd_cfg->xres; 1405 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
1406 /* NV12 buffers must have even number of lines */
1407 if ((cfg->nonstd) && cfg->bpp == 12 &&
1408 (lcd_cfg->yres & 0x1)) {
1409 dev_err(&pdev->dev, "yres must be multiple of 2"
1410 " for YCbCr420 mode.\n");
1411 error = -EINVAL;
1412 goto err1;
1413 }
1263 1414
1264 if (size > max_size) { 1415 if (size > max_size) {
1265 max_cfg = lcd_cfg; 1416 max_cfg = lcd_cfg;
@@ -1274,7 +1425,11 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1274 max_cfg->xres, max_cfg->yres); 1425 max_cfg->xres, max_cfg->yres);
1275 1426
1276 info->fix = sh_mobile_lcdc_fix; 1427 info->fix = sh_mobile_lcdc_fix;
1277 info->fix.smem_len = max_size * (cfg->bpp / 8) * 2; 1428 info->fix.smem_len = max_size * 2 * cfg->bpp / 8;
1429
1430 /* Only pan in 2 line steps for NV12 */
1431 if (cfg->nonstd && cfg->bpp == 12)
1432 info->fix.ypanstep = 2;
1278 1433
1279 if (!mode) { 1434 if (!mode) {
1280 mode = &default_720p; 1435 mode = &default_720p;
@@ -1292,7 +1447,7 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1292 var->yres_virtual = var->yres * 2; 1447 var->yres_virtual = var->yres * 2;
1293 var->activate = FB_ACTIVATE_NOW; 1448 var->activate = FB_ACTIVATE_NOW;
1294 1449
1295 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp); 1450 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp, cfg->nonstd);
1296 if (error) 1451 if (error)
1297 break; 1452 break;
1298 1453
@@ -1316,7 +1471,11 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1316 } 1471 }
1317 1472
1318 info->fix.smem_start = ch->dma_handle; 1473 info->fix.smem_start = ch->dma_handle;
1319 info->fix.line_length = var->xres * (cfg->bpp / 8); 1474 if (var->nonstd)
1475 info->fix.line_length = var->xres;
1476 else
1477 info->fix.line_length = var->xres * (cfg->bpp / 8);
1478
1320 info->screen_base = buf; 1479 info->screen_base = buf;
1321 info->device = &pdev->dev; 1480 info->device = &pdev->dev;
1322 ch->display_var = *var; 1481 ch->display_var = *var;
@@ -1345,6 +1504,8 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1345 } 1504 }
1346 } 1505 }
1347 1506
1507 info->bl_dev = ch->bl;
1508
1348 error = register_framebuffer(info); 1509 error = register_framebuffer(info);
1349 if (error < 0) 1510 if (error < 0)
1350 goto err1; 1511 goto err1;
@@ -1404,6 +1565,11 @@ static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1404 framebuffer_release(info); 1565 framebuffer_release(info);
1405 } 1566 }
1406 1567
1568 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1569 if (priv->ch[i].bl)
1570 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1571 }
1572
1407 if (priv->dot_clk) 1573 if (priv->dot_clk)
1408 clk_put(priv->dot_clk); 1574 clk_put(priv->dot_clk);
1409 1575
diff --git a/drivers/video/sh_mobile_lcdcfb.h b/drivers/video/sh_mobile_lcdcfb.h
index 9ecee2fba1d7..4635eed63eee 100644
--- a/drivers/video/sh_mobile_lcdcfb.h
+++ b/drivers/video/sh_mobile_lcdcfb.h
@@ -8,7 +8,7 @@
8 8
9/* per-channel registers */ 9/* per-channel registers */
10enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R, 10enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
11 LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR, 11 LDSM2R, LDSA1R, LDSA2R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
12 LDHAJR, 12 LDHAJR,
13 NR_CH_REGS }; 13 NR_CH_REGS };
14 14
@@ -16,6 +16,7 @@ enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
16 16
17struct sh_mobile_lcdc_priv; 17struct sh_mobile_lcdc_priv;
18struct fb_info; 18struct fb_info;
19struct backlight_device;
19 20
20struct sh_mobile_lcdc_chan { 21struct sh_mobile_lcdc_chan {
21 struct sh_mobile_lcdc_priv *lcdc; 22 struct sh_mobile_lcdc_priv *lcdc;
@@ -26,6 +27,7 @@ struct sh_mobile_lcdc_chan {
26 u32 pseudo_palette[PALETTE_NR]; 27 u32 pseudo_palette[PALETTE_NR];
27 unsigned long saved_ch_regs[NR_CH_REGS]; 28 unsigned long saved_ch_regs[NR_CH_REGS];
28 struct fb_info *info; 29 struct fb_info *info;
30 struct backlight_device *bl;
29 dma_addr_t dma_handle; 31 dma_addr_t dma_handle;
30 struct fb_deferred_io defio; 32 struct fb_deferred_io defio;
31 struct scatterlist *sglist; 33 struct scatterlist *sglist;
diff --git a/drivers/video/via/chip.h b/drivers/video/via/chip.h
index 48f1342897bd..781f3aa66b42 100644
--- a/drivers/video/via/chip.h
+++ b/drivers/video/via/chip.h
@@ -110,16 +110,13 @@
110struct tmds_chip_information { 110struct tmds_chip_information {
111 int tmds_chip_name; 111 int tmds_chip_name;
112 int tmds_chip_slave_addr; 112 int tmds_chip_slave_addr;
113 int data_mode;
114 int output_interface; 113 int output_interface;
115 int i2c_port; 114 int i2c_port;
116 int device_type;
117}; 115};
118 116
119struct lvds_chip_information { 117struct lvds_chip_information {
120 int lvds_chip_name; 118 int lvds_chip_name;
121 int lvds_chip_slave_addr; 119 int lvds_chip_slave_addr;
122 int data_mode;
123 int output_interface; 120 int output_interface;
124 int i2c_port; 121 int i2c_port;
125}; 122};
@@ -142,9 +139,6 @@ struct chip_information {
142 139
143struct crt_setting_information { 140struct crt_setting_information {
144 int iga_path; 141 int iga_path;
145 int h_active;
146 int v_active;
147 int bpp;
148 int refresh_rate; 142 int refresh_rate;
149}; 143};
150 144
@@ -162,8 +156,6 @@ struct lvds_setting_information {
162 int h_active; 156 int h_active;
163 int v_active; 157 int v_active;
164 int bpp; 158 int bpp;
165 int refresh_rate;
166 int lcd_panel_id;
167 int lcd_panel_hres; 159 int lcd_panel_hres;
168 int lcd_panel_vres; 160 int lcd_panel_vres;
169 int display_method; 161 int display_method;
@@ -188,7 +180,6 @@ struct GFX_DPA_SETTING {
188}; 180};
189 181
190struct VT1636_DPA_SETTING { 182struct VT1636_DPA_SETTING {
191 int PanelSizeID;
192 u8 CLK_SEL_ST1; 183 u8 CLK_SEL_ST1;
193 u8 CLK_SEL_ST2; 184 u8 CLK_SEL_ST2;
194}; 185};
diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c
index 84e21b39dd0b..41ca198b5098 100644
--- a/drivers/video/via/dvi.c
+++ b/drivers/video/via/dvi.c
@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
195 struct crt_mode_table *pDviTiming; 195 struct crt_mode_table *pDviTiming;
196 unsigned long desirePixelClock, maxPixelClock; 196 unsigned long desirePixelClock, maxPixelClock;
197 pDviTiming = mode->crtc; 197 pDviTiming = mode->crtc;
198 desirePixelClock = pDviTiming->clk / 1000000; 198 desirePixelClock = pDviTiming->refresh_rate
199 * pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
200 / 1000000;
199 maxPixelClock = (unsigned long)viaparinfo-> 201 maxPixelClock = (unsigned long)viaparinfo->
200 tmds_setting_info->max_pixel_clock; 202 tmds_setting_info->max_pixel_clock;
201 203
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 36d73f940d8b..5728fd76bc11 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -22,342 +22,290 @@
22#include <linux/via-core.h> 22#include <linux/via-core.h>
23#include "global.h" 23#include "global.h"
24 24
25static struct pll_map pll_value[] = { 25static struct pll_config cle266_pll_config[] = {
26 {25175000, 26 {19, 4, 0},
27 {99, 7, 3}, 27 {26, 5, 0},
28 {85, 3, 4}, /* ignoring bit difference: 0x00008000 */ 28 {28, 5, 0},
29 {141, 5, 4}, 29 {31, 5, 0},
30 {141, 5, 4} }, 30 {33, 5, 0},
31 {29581000, 31 {55, 5, 0},
32 {33, 4, 2}, 32 {102, 5, 0},
33 {66, 2, 4}, /* ignoring bit difference: 0x00808000 */ 33 {53, 6, 0},
34 {166, 5, 4}, /* ignoring bit difference: 0x00008000 */ 34 {92, 6, 0},
35 {165, 5, 4} }, 35 {98, 6, 0},
36 {26880000, 36 {112, 6, 0},
37 {15, 4, 1}, 37 {41, 7, 0},
38 {30, 2, 3}, /* ignoring bit difference: 0x00808000 */ 38 {60, 7, 0},
39 {150, 5, 4}, 39 {99, 7, 0},
40 {150, 5, 4} }, 40 {100, 7, 0},
41 {31500000, 41 {83, 8, 0},
42 {53, 3, 3}, /* ignoring bit difference: 0x00008000 */ 42 {86, 8, 0},
43 {141, 4, 4}, /* ignoring bit difference: 0x00008000 */ 43 {108, 8, 0},
44 {176, 5, 4}, 44 {87, 9, 0},
45 {176, 5, 4} }, 45 {118, 9, 0},
46 {31728000, 46 {95, 12, 0},
47 {31, 7, 1}, 47 {115, 12, 0},
48 {177, 5, 4}, /* ignoring bit difference: 0x00008000 */ 48 {108, 13, 0},
49 {177, 5, 4}, 49 {83, 17, 0},
50 {142, 4, 4} }, 50 {67, 20, 0},
51 {32688000, 51 {86, 20, 0},
52 {73, 4, 3}, 52 {98, 20, 0},
53 {146, 4, 4}, /* ignoring bit difference: 0x00008000 */ 53 {121, 24, 0},
54 {183, 5, 4}, 54 {99, 29, 0},
55 {146, 4, 4} }, 55 {33, 3, 1},
56 {36000000, 56 {15, 4, 1},
57 {101, 5, 3}, /* ignoring bit difference: 0x00008000 */ 57 {23, 4, 1},
58 {161, 4, 4}, /* ignoring bit difference: 0x00008000 */ 58 {37, 5, 1},
59 {202, 5, 4}, 59 {83, 5, 1},
60 {161, 4, 4} }, 60 {85, 5, 1},
61 {40000000, 61 {94, 5, 1},
62 {89, 4, 3}, 62 {103, 5, 1},
63 {89, 4, 3}, /* ignoring bit difference: 0x00008000 */ 63 {109, 5, 1},
64 {112, 5, 3}, 64 {113, 5, 1},
65 {112, 5, 3} }, 65 {121, 5, 1},
66 {41291000, 66 {82, 6, 1},
67 {23, 4, 1}, 67 {31, 7, 1},
68 {69, 3, 3}, /* ignoring bit difference: 0x00008000 */ 68 {55, 7, 1},
69 {115, 5, 3}, 69 {84, 7, 1},
70 {115, 5, 3} }, 70 {83, 8, 1},
71 {43163000, 71 {76, 9, 1},
72 {121, 5, 3}, 72 {127, 9, 1},
73 {121, 5, 3}, /* ignoring bit difference: 0x00008000 */ 73 {33, 4, 2},
74 {121, 5, 3}, 74 {75, 4, 2},
75 {121, 5, 3} }, 75 {119, 4, 2},
76 {45250000, 76 {121, 4, 2},
77 {127, 5, 3}, 77 {91, 5, 2},
78 {127, 5, 3}, /* ignoring bit difference: 0x00808000 */ 78 {118, 5, 2},
79 {127, 5, 3}, 79 {83, 6, 2},
80 {127, 5, 3} }, 80 {109, 6, 2},
81 {46000000, 81 {90, 7, 2},
82 {90, 7, 2}, 82 {93, 2, 3},
83 {103, 4, 3}, /* ignoring bit difference: 0x00008000 */ 83 {53, 3, 3},
84 {129, 5, 3}, 84 {73, 4, 3},
85 {103, 4, 3} }, 85 {89, 4, 3},
86 {46996000, 86 {105, 4, 3},
87 {105, 4, 3}, /* ignoring bit difference: 0x00008000 */ 87 {117, 4, 3},
88 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */ 88 {101, 5, 3},
89 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */ 89 {121, 5, 3},
90 {105, 4, 3} }, 90 {127, 5, 3},
91 {48000000, 91 {99, 7, 3}
92 {67, 20, 0}, 92};
93 {134, 5, 3}, /* ignoring bit difference: 0x00808000 */ 93
94 {134, 5, 3}, 94static struct pll_config k800_pll_config[] = {
95 {134, 5, 3} }, 95 {22, 2, 0},
96 {48875000, 96 {28, 3, 0},
97 {99, 29, 0}, 97 {81, 3, 1},
98 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */ 98 {85, 3, 1},
99 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */ 99 {98, 3, 1},
100 {137, 5, 3} }, 100 {112, 3, 1},
101 {49500000, 101 {86, 4, 1},
102 {83, 6, 2}, 102 {166, 4, 1},
103 {83, 3, 3}, /* ignoring bit difference: 0x00008000 */ 103 {109, 5, 1},
104 {138, 5, 3}, 104 {113, 5, 1},
105 {83, 3, 3} }, 105 {121, 5, 1},
106 {52406000, 106 {131, 5, 1},
107 {117, 4, 3}, 107 {143, 5, 1},
108 {117, 4, 3}, /* ignoring bit difference: 0x00008000 */ 108 {153, 5, 1},
109 {117, 4, 3}, 109 {66, 3, 2},
110 {88, 3, 3} }, 110 {68, 3, 2},
111 {52977000, 111 {95, 3, 2},
112 {37, 5, 1}, 112 {106, 3, 2},
113 {148, 5, 3}, /* ignoring bit difference: 0x00808000 */ 113 {116, 3, 2},
114 {148, 5, 3}, 114 {93, 4, 2},
115 {148, 5, 3} }, 115 {119, 4, 2},
116 {56250000, 116 {121, 4, 2},
117 {55, 7, 1}, /* ignoring bit difference: 0x00008000 */ 117 {133, 4, 2},
118 {126, 4, 3}, /* ignoring bit difference: 0x00008000 */ 118 {137, 4, 2},
119 {157, 5, 3}, 119 {117, 5, 2},
120 {157, 5, 3} }, 120 {118, 5, 2},
121 {57275000, 121 {120, 5, 2},
122 {0, 0, 0}, 122 {124, 5, 2},
123 {2, 2, 0}, 123 {132, 5, 2},
124 {2, 2, 0}, 124 {137, 5, 2},
125 {157, 5, 3} }, /* ignoring bit difference: 0x00808000 */ 125 {141, 5, 2},
126 {60466000, 126 {166, 5, 2},
127 {76, 9, 1}, 127 {170, 5, 2},
128 {169, 5, 3}, /* ignoring bit difference: 0x00808000 */ 128 {191, 5, 2},
129 {169, 5, 3}, /* FIXED: old = {72, 2, 3} */ 129 {206, 5, 2},
130 {169, 5, 3} }, 130 {208, 5, 2},
131 {61500000, 131 {30, 2, 3},
132 {86, 20, 0}, 132 {69, 3, 3},
133 {172, 5, 3}, /* ignoring bit difference: 0x00808000 */ 133 {82, 3, 3},
134 {172, 5, 3}, 134 {83, 3, 3},
135 {172, 5, 3} }, 135 {109, 3, 3},
136 {65000000, 136 {114, 3, 3},
137 {109, 6, 2}, /* ignoring bit difference: 0x00008000 */ 137 {125, 3, 3},
138 {109, 3, 3}, /* ignoring bit difference: 0x00008000 */ 138 {89, 4, 3},
139 {109, 3, 3}, 139 {103, 4, 3},
140 {109, 3, 3} }, 140 {117, 4, 3},
141 {65178000, 141 {126, 4, 3},
142 {91, 5, 2}, 142 {150, 4, 3},
143 {182, 5, 3}, /* ignoring bit difference: 0x00808000 */ 143 {161, 4, 3},
144 {109, 3, 3}, 144 {121, 5, 3},
145 {182, 5, 3} }, 145 {127, 5, 3},
146 {66750000, 146 {131, 5, 3},
147 {75, 4, 2}, 147 {134, 5, 3},
148 {150, 4, 3}, /* ignoring bit difference: 0x00808000 */ 148 {148, 5, 3},
149 {150, 4, 3}, 149 {169, 5, 3},
150 {112, 3, 3} }, 150 {172, 5, 3},
151 {68179000, 151 {182, 5, 3},
152 {19, 4, 0}, 152 {195, 5, 3},
153 {114, 3, 3}, /* ignoring bit difference: 0x00008000 */ 153 {196, 5, 3},
154 {190, 5, 3}, 154 {208, 5, 3},
155 {191, 5, 3} }, 155 {66, 2, 4},
156 {69924000, 156 {85, 3, 4},
157 {83, 17, 0}, 157 {141, 4, 4},
158 {195, 5, 3}, /* ignoring bit difference: 0x00808000 */ 158 {146, 4, 4},
159 {195, 5, 3}, 159 {161, 4, 4},
160 {195, 5, 3} }, 160 {177, 5, 4}
161 {70159000, 161};
162 {98, 20, 0}, 162
163 {196, 5, 3}, /* ignoring bit difference: 0x00808000 */ 163static struct pll_config cx700_pll_config[] = {
164 {196, 5, 3}, 164 {98, 3, 1},
165 {195, 5, 3} }, 165 {86, 4, 1},
166 {72000000, 166 {109, 5, 1},
167 {121, 24, 0}, 167 {110, 5, 1},
168 {161, 4, 3}, /* ignoring bit difference: 0x00808000 */ 168 {113, 5, 1},
169 {161, 4, 3}, 169 {121, 5, 1},
170 {161, 4, 3} }, 170 {131, 5, 1},
171 {78750000, 171 {135, 5, 1},
172 {33, 3, 1}, 172 {142, 5, 1},
173 {66, 3, 2}, /* ignoring bit difference: 0x00008000 */ 173 {143, 5, 1},
174 {110, 5, 2}, 174 {153, 5, 1},
175 {110, 5, 2} }, 175 {187, 5, 1},
176 {80136000, 176 {208, 5, 1},
177 {28, 5, 0}, 177 {68, 2, 2},
178 {68, 3, 2}, /* ignoring bit difference: 0x00008000 */ 178 {95, 3, 2},
179 {112, 5, 2}, 179 {116, 3, 2},
180 {112, 5, 2} }, 180 {93, 4, 2},
181 {83375000, 181 {119, 4, 2},
182 {93, 2, 3}, 182 {133, 4, 2},
183 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */ 183 {137, 4, 2},
184 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */ 184 {151, 4, 2},
185 {117, 5, 2} }, 185 {166, 4, 2},
186 {83950000, 186 {110, 5, 2},
187 {41, 7, 0}, 187 {112, 5, 2},
188 {117, 5, 2}, /* ignoring bit difference: 0x00008000 */ 188 {117, 5, 2},
189 {117, 5, 2}, 189 {118, 5, 2},
190 {117, 5, 2} }, 190 {120, 5, 2},
191 {84750000, 191 {132, 5, 2},
192 {118, 5, 2}, 192 {137, 5, 2},
193 {118, 5, 2}, /* ignoring bit difference: 0x00808000 */ 193 {141, 5, 2},
194 {118, 5, 2}, 194 {151, 5, 2},
195 {118, 5, 2} }, 195 {166, 5, 2},
196 {85860000, 196 {175, 5, 2},
197 {84, 7, 1}, 197 {191, 5, 2},
198 {120, 5, 2}, /* ignoring bit difference: 0x00808000 */ 198 {206, 5, 2},
199 {120, 5, 2}, 199 {174, 7, 2},
200 {118, 5, 2} }, 200 {82, 3, 3},
201 {88750000, 201 {109, 3, 3},
202 {31, 5, 0}, 202 {117, 4, 3},
203 {124, 5, 2}, /* ignoring bit difference: 0x00808000 */ 203 {150, 4, 3},
204 {174, 7, 2}, /* ignoring bit difference: 0x00808000 */ 204 {161, 4, 3},
205 {124, 5, 2} }, 205 {112, 5, 3},
206 {94500000, 206 {115, 5, 3},
207 {33, 5, 0}, 207 {121, 5, 3},
208 {132, 5, 2}, /* ignoring bit difference: 0x00008000 */ 208 {127, 5, 3},
209 {132, 5, 2}, 209 {129, 5, 3},
210 {132, 5, 2} }, 210 {131, 5, 3},
211 {97750000, 211 {134, 5, 3},
212 {82, 6, 1}, 212 {138, 5, 3},
213 {137, 5, 2}, /* ignoring bit difference: 0x00808000 */ 213 {148, 5, 3},
214 {137, 5, 2}, 214 {157, 5, 3},
215 {137, 5, 2} }, 215 {169, 5, 3},
216 {101000000, 216 {172, 5, 3},
217 {127, 9, 1}, 217 {190, 5, 3},
218 {141, 5, 2}, /* ignoring bit difference: 0x00808000 */ 218 {195, 5, 3},
219 {141, 5, 2}, 219 {196, 5, 3},
220 {141, 5, 2} }, 220 {208, 5, 3},
221 {106500000, 221 {141, 5, 4},
222 {119, 4, 2}, 222 {150, 5, 4},
223 {119, 4, 2}, /* ignoring bit difference: 0x00808000 */ 223 {166, 5, 4},
224 {119, 4, 2}, 224 {176, 5, 4},
225 {149, 5, 2} }, 225 {177, 5, 4},
226 {108000000, 226 {183, 5, 4},
227 {121, 4, 2}, 227 {202, 5, 4}
228 {121, 4, 2}, /* ignoring bit difference: 0x00808000 */ 228};
229 {151, 5, 2}, 229
230 {151, 5, 2} }, 230static struct pll_config vx855_pll_config[] = {
231 {113309000, 231 {86, 4, 1},
232 {95, 12, 0}, 232 {108, 5, 1},
233 {95, 3, 2}, /* ignoring bit difference: 0x00808000 */ 233 {110, 5, 1},
234 {95, 3, 2}, 234 {113, 5, 1},
235 {159, 5, 2} }, 235 {121, 5, 1},
236 {118840000, 236 {131, 5, 1},
237 {83, 5, 1}, 237 {135, 5, 1},
238 {166, 5, 2}, /* ignoring bit difference: 0x00808000 */ 238 {142, 5, 1},
239 {166, 5, 2}, 239 {143, 5, 1},
240 {166, 5, 2} }, 240 {153, 5, 1},
241 {119000000, 241 {164, 5, 1},
242 {108, 13, 0}, 242 {187, 5, 1},
243 {133, 4, 2}, /* ignoring bit difference: 0x00808000 */ 243 {208, 5, 1},
244 {133, 4, 2}, 244 {110, 5, 2},
245 {167, 5, 2} }, 245 {112, 5, 2},
246 {121750000, 246 {117, 5, 2},
247 {85, 5, 1}, 247 {118, 5, 2},
248 {170, 5, 2}, /* ignoring bit difference: 0x00808000 */ 248 {124, 5, 2},
249 {68, 2, 2}, 249 {132, 5, 2},
250 {0, 0, 0} }, 250 {137, 5, 2},
251 {125104000, 251 {141, 5, 2},
252 {53, 6, 0}, /* ignoring bit difference: 0x00008000 */ 252 {149, 5, 2},
253 {106, 3, 2}, /* ignoring bit difference: 0x00008000 */ 253 {151, 5, 2},
254 {175, 5, 2}, 254 {159, 5, 2},
255 {0, 0, 0} }, 255 {166, 5, 2},
256 {135000000, 256 {167, 5, 2},
257 {94, 5, 1}, 257 {172, 5, 2},
258 {28, 3, 0}, /* ignoring bit difference: 0x00804000 */ 258 {189, 5, 2},
259 {151, 4, 2}, 259 {191, 5, 2},
260 {189, 5, 2} }, 260 {194, 5, 2},
261 {136700000, 261 {206, 5, 2},
262 {115, 12, 0}, 262 {208, 5, 2},
263 {191, 5, 2}, /* ignoring bit difference: 0x00808000 */ 263 {83, 3, 3},
264 {191, 5, 2}, 264 {88, 3, 3},
265 {191, 5, 2} }, 265 {109, 3, 3},
266 {138400000, 266 {112, 3, 3},
267 {87, 9, 0}, 267 {103, 4, 3},
268 {116, 3, 2}, /* ignoring bit difference: 0x00808000 */ 268 {105, 4, 3},
269 {116, 3, 2}, 269 {161, 4, 3},
270 {194, 5, 2} }, 270 {112, 5, 3},
271 {146760000, 271 {115, 5, 3},
272 {103, 5, 1}, 272 {121, 5, 3},
273 {206, 5, 2}, /* ignoring bit difference: 0x00808000 */ 273 {127, 5, 3},
274 {206, 5, 2}, 274 {134, 5, 3},
275 {206, 5, 2} }, 275 {137, 5, 3},
276 {153920000, 276 {148, 5, 3},
277 {86, 8, 0}, 277 {157, 5, 3},
278 {86, 4, 1}, /* ignoring bit difference: 0x00808000 */ 278 {169, 5, 3},
279 {86, 4, 1}, 279 {172, 5, 3},
280 {86, 4, 1} }, /* FIXED: old = {84, 2, 1} */ 280 {182, 5, 3},
281 {156000000, 281 {191, 5, 3},
282 {109, 5, 1}, 282 {195, 5, 3},
283 {109, 5, 1}, /* ignoring bit difference: 0x00808000 */ 283 {209, 5, 3},
284 {109, 5, 1}, 284 {142, 4, 4},
285 {108, 5, 1} }, 285 {146, 4, 4},
286 {157500000, 286 {161, 4, 4},
287 {55, 5, 0}, /* ignoring bit difference: 0x00008000 */ 287 {141, 5, 4},
288 {22, 2, 0}, /* ignoring bit difference: 0x00802000 */ 288 {150, 5, 4},
289 {110, 5, 1}, 289 {165, 5, 4},
290 {110, 5, 1} }, 290 {176, 5, 4}
291 {162000000, 291};
292 {113, 5, 1}, 292
293 {113, 5, 1}, /* ignoring bit difference: 0x00808000 */ 293/* according to VIA Technologies these values are based on experiment */
294 {113, 5, 1}, 294static struct io_reg scaling_parameters[] = {
295 {113, 5, 1} }, 295 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
296 {187000000, 296 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
297 {118, 9, 0}, 297 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
298 {131, 5, 1}, /* ignoring bit difference: 0x00808000 */ 298 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
299 {131, 5, 1}, 299 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
300 {131, 5, 1} }, 300 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
301 {193295000, 301 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
302 {108, 8, 0}, 302 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
303 {81, 3, 1}, /* ignoring bit difference: 0x00808000 */ 303 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
304 {135, 5, 1}, 304 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
305 {135, 5, 1} }, 305 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
306 {202500000, 306 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
307 {99, 7, 0}, 307 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
308 {85, 3, 1}, /* ignoring bit difference: 0x00808000 */ 308 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
309 {142, 5, 1},
310 {142, 5, 1} },
311 {204000000,
312 {100, 7, 0},
313 {143, 5, 1}, /* ignoring bit difference: 0x00808000 */
314 {143, 5, 1},
315 {143, 5, 1} },
316 {218500000,
317 {92, 6, 0},
318 {153, 5, 1}, /* ignoring bit difference: 0x00808000 */
319 {153, 5, 1},
320 {153, 5, 1} },
321 {234000000,
322 {98, 6, 0},
323 {98, 3, 1}, /* ignoring bit difference: 0x00008000 */
324 {98, 3, 1},
325 {164, 5, 1} },
326 {267250000,
327 {112, 6, 0},
328 {112, 3, 1}, /* ignoring bit difference: 0x00808000 */
329 {187, 5, 1},
330 {187, 5, 1} },
331 {297500000,
332 {102, 5, 0}, /* ignoring bit difference: 0x00008000 */
333 {166, 4, 1}, /* ignoring bit difference: 0x00008000 */
334 {208, 5, 1},
335 {208, 5, 1} },
336 {74481000,
337 {26, 5, 0},
338 {125, 3, 3}, /* ignoring bit difference: 0x00808000 */
339 {208, 5, 3},
340 {209, 5, 3} },
341 {172798000,
342 {121, 5, 1},
343 {121, 5, 1}, /* ignoring bit difference: 0x00808000 */
344 {121, 5, 1},
345 {121, 5, 1} },
346 {122614000,
347 {60, 7, 0},
348 {137, 4, 2}, /* ignoring bit difference: 0x00808000 */
349 {137, 4, 2},
350 {172, 5, 2} },
351 {74270000,
352 {83, 8, 1},
353 {208, 5, 3},
354 {208, 5, 3},
355 {0, 0, 0} },
356 {148500000,
357 {83, 8, 0},
358 {208, 5, 2},
359 {166, 4, 2},
360 {208, 5, 2} }
361}; 309};
362 310
363static struct fifo_depth_select display_fifo_depth_reg = { 311static struct fifo_depth_select display_fifo_depth_reg = {
@@ -751,7 +699,7 @@ void viafb_unlock_crt(void)
751 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); 699 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
752} 700}
753 701
754void write_dac_reg(u8 index, u8 r, u8 g, u8 b) 702static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
755{ 703{
756 outb(index, LUT_INDEX_WRITE); 704 outb(index, LUT_INDEX_WRITE);
757 outb(r, LUT_DATA); 705 outb(r, LUT_DATA);
@@ -1674,43 +1622,63 @@ static u32 vx855_encode_pll(struct pll_config pll)
1674 | pll.multiplier; 1622 | pll.multiplier;
1675} 1623}
1676 1624
1677u32 viafb_get_clk_value(int clk) 1625static inline u32 get_pll_internal_frequency(u32 ref_freq,
1626 struct pll_config pll)
1678{ 1627{
1679 u32 value = 0; 1628 return ref_freq / pll.divisor * pll.multiplier;
1680 int i = 0; 1629}
1681 1630
1682 while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk) 1631static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)
1683 i++; 1632{
1633 return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;
1634}
1684 1635
1685 if (i == NUM_TOTAL_PLL_TABLE) { 1636static struct pll_config get_pll_config(struct pll_config *config, int size,
1686 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!"); 1637 int clk)
1687 } else { 1638{
1688 switch (viaparinfo->chip_info->gfx_chip_name) { 1639 struct pll_config best = config[0];
1689 case UNICHROME_CLE266: 1640 const u32 f0 = 14318180; /* X1 frequency */
1690 case UNICHROME_K400: 1641 int i;
1691 value = cle266_encode_pll(pll_value[i].cle266_pll);
1692 break;
1693 1642
1694 case UNICHROME_K800: 1643 for (i = 1; i < size; i++) {
1695 case UNICHROME_PM800: 1644 if (abs(get_pll_output_frequency(f0, config[i]) - clk)
1696 case UNICHROME_CN700: 1645 < abs(get_pll_output_frequency(f0, best) - clk))
1697 value = k800_encode_pll(pll_value[i].k800_pll); 1646 best = config[i];
1698 break; 1647 }
1699 1648
1700 case UNICHROME_CX700: 1649 return best;
1701 case UNICHROME_CN750: 1650}
1702 case UNICHROME_K8M890:
1703 case UNICHROME_P4M890:
1704 case UNICHROME_P4M900:
1705 case UNICHROME_VX800:
1706 value = k800_encode_pll(pll_value[i].cx700_pll);
1707 break;
1708 1651
1709 case UNICHROME_VX855: 1652u32 viafb_get_clk_value(int clk)
1710 case UNICHROME_VX900: 1653{
1711 value = vx855_encode_pll(pll_value[i].vx855_pll); 1654 u32 value = 0;
1712 break; 1655
1713 } 1656 switch (viaparinfo->chip_info->gfx_chip_name) {
1657 case UNICHROME_CLE266:
1658 case UNICHROME_K400:
1659 value = cle266_encode_pll(get_pll_config(cle266_pll_config,
1660 ARRAY_SIZE(cle266_pll_config), clk));
1661 break;
1662 case UNICHROME_K800:
1663 case UNICHROME_PM800:
1664 case UNICHROME_CN700:
1665 value = k800_encode_pll(get_pll_config(k800_pll_config,
1666 ARRAY_SIZE(k800_pll_config), clk));
1667 break;
1668 case UNICHROME_CX700:
1669 case UNICHROME_CN750:
1670 case UNICHROME_K8M890:
1671 case UNICHROME_P4M890:
1672 case UNICHROME_P4M900:
1673 case UNICHROME_VX800:
1674 value = k800_encode_pll(get_pll_config(cx700_pll_config,
1675 ARRAY_SIZE(cx700_pll_config), clk));
1676 break;
1677 case UNICHROME_VX855:
1678 case UNICHROME_VX900:
1679 value = vx855_encode_pll(get_pll_config(vx855_pll_config,
1680 ARRAY_SIZE(vx855_pll_config), clk));
1681 break;
1714 } 1682 }
1715 1683
1716 return value; 1684 return value;
@@ -2034,7 +2002,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2034 int i; 2002 int i;
2035 int index = 0; 2003 int index = 0;
2036 int h_addr, v_addr; 2004 int h_addr, v_addr;
2037 u32 pll_D_N; 2005 u32 pll_D_N, clock;
2038 2006
2039 for (i = 0; i < video_mode->mode_array; i++) { 2007 for (i = 0; i < video_mode->mode_array; i++) {
2040 index = i; 2008 index = i;
@@ -2087,7 +2055,9 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2087 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) 2055 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
2088 viafb_load_FIFO_reg(set_iga, h_addr, v_addr); 2056 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
2089 2057
2090 pll_D_N = viafb_get_clk_value(crt_table[index].clk); 2058 clock = crt_reg.hor_total * crt_reg.ver_total
2059 * crt_table[index].refresh_rate;
2060 pll_D_N = viafb_get_clk_value(clock);
2091 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N); 2061 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2092 viafb_set_vclock(pll_D_N, set_iga); 2062 viafb_set_vclock(pll_D_N, set_iga);
2093 2063
@@ -2117,9 +2087,6 @@ void viafb_update_device_setting(int hres, int vres,
2117 int bpp, int vmode_refresh, int flag) 2087 int bpp, int vmode_refresh, int flag)
2118{ 2088{
2119 if (flag == 0) { 2089 if (flag == 0) {
2120 viaparinfo->crt_setting_info->h_active = hres;
2121 viaparinfo->crt_setting_info->v_active = vres;
2122 viaparinfo->crt_setting_info->bpp = bpp;
2123 viaparinfo->crt_setting_info->refresh_rate = 2090 viaparinfo->crt_setting_info->refresh_rate =
2124 vmode_refresh; 2091 vmode_refresh;
2125 2092
@@ -2129,13 +2096,9 @@ void viafb_update_device_setting(int hres, int vres,
2129 viaparinfo->lvds_setting_info->h_active = hres; 2096 viaparinfo->lvds_setting_info->h_active = hres;
2130 viaparinfo->lvds_setting_info->v_active = vres; 2097 viaparinfo->lvds_setting_info->v_active = vres;
2131 viaparinfo->lvds_setting_info->bpp = bpp; 2098 viaparinfo->lvds_setting_info->bpp = bpp;
2132 viaparinfo->lvds_setting_info->refresh_rate =
2133 vmode_refresh;
2134 viaparinfo->lvds_setting_info2->h_active = hres; 2099 viaparinfo->lvds_setting_info2->h_active = hres;
2135 viaparinfo->lvds_setting_info2->v_active = vres; 2100 viaparinfo->lvds_setting_info2->v_active = vres;
2136 viaparinfo->lvds_setting_info2->bpp = bpp; 2101 viaparinfo->lvds_setting_info2->bpp = bpp;
2137 viaparinfo->lvds_setting_info2->refresh_rate =
2138 vmode_refresh;
2139 } else { 2102 } else {
2140 2103
2141 if (viaparinfo->tmds_setting_info->iga_path == IGA2) { 2104 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
@@ -2147,15 +2110,11 @@ void viafb_update_device_setting(int hres, int vres,
2147 viaparinfo->lvds_setting_info->h_active = hres; 2110 viaparinfo->lvds_setting_info->h_active = hres;
2148 viaparinfo->lvds_setting_info->v_active = vres; 2111 viaparinfo->lvds_setting_info->v_active = vres;
2149 viaparinfo->lvds_setting_info->bpp = bpp; 2112 viaparinfo->lvds_setting_info->bpp = bpp;
2150 viaparinfo->lvds_setting_info->refresh_rate =
2151 vmode_refresh;
2152 } 2113 }
2153 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) { 2114 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2154 viaparinfo->lvds_setting_info2->h_active = hres; 2115 viaparinfo->lvds_setting_info2->h_active = hres;
2155 viaparinfo->lvds_setting_info2->v_active = vres; 2116 viaparinfo->lvds_setting_info2->v_active = vres;
2156 viaparinfo->lvds_setting_info2->bpp = bpp; 2117 viaparinfo->lvds_setting_info2->bpp = bpp;
2157 viaparinfo->lvds_setting_info2->refresh_rate =
2158 vmode_refresh;
2159 } 2118 }
2160 } 2119 }
2161} 2120}
@@ -2430,6 +2389,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2430 break; 2389 break;
2431 } 2390 }
2432 2391
2392 viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
2433 device_off(); 2393 device_off();
2434 via_set_state(devices, VIA_STATE_OFF); 2394 via_set_state(devices, VIA_STATE_OFF);
2435 2395
@@ -2608,35 +2568,43 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2608int viafb_get_pixclock(int hres, int vres, int vmode_refresh) 2568int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2609{ 2569{
2610 int i; 2570 int i;
2571 struct crt_mode_table *best;
2572 struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2573
2574 if (!vmode)
2575 return RES_640X480_60HZ_PIXCLOCK;
2611 2576
2612 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { 2577 best = &vmode->crtc[0];
2613 if ((hres == res_map_refresh_tbl[i].hres) 2578 for (i = 1; i < vmode->mode_array; i++) {
2614 && (vres == res_map_refresh_tbl[i].vres) 2579 if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)
2615 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh)) 2580 < abs(best->refresh_rate - vmode_refresh))
2616 return res_map_refresh_tbl[i].pixclock; 2581 best = &vmode->crtc[i];
2617 } 2582 }
2618 return RES_640X480_60HZ_PIXCLOCK;
2619 2583
2584 return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)
2585 * 1000 / best->refresh_rate;
2620} 2586}
2621 2587
2622int viafb_get_refresh(int hres, int vres, u32 long_refresh) 2588int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2623{ 2589{
2624#define REFRESH_TOLERANCE 3 2590 int i;
2625 int i, nearest = -1, diff = REFRESH_TOLERANCE; 2591 struct crt_mode_table *best;
2626 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { 2592 struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2627 if ((hres == res_map_refresh_tbl[i].hres) 2593
2628 && (vres == res_map_refresh_tbl[i].vres) 2594 if (!vmode)
2629 && (diff > (abs(long_refresh - 2595 return 60;
2630 res_map_refresh_tbl[i].vmode_refresh)))) { 2596
2631 diff = abs(long_refresh - res_map_refresh_tbl[i]. 2597 best = &vmode->crtc[0];
2632 vmode_refresh); 2598 for (i = 1; i < vmode->mode_array; i++) {
2633 nearest = i; 2599 if (abs(vmode->crtc[i].refresh_rate - long_refresh)
2634 } 2600 < abs(best->refresh_rate - long_refresh))
2601 best = &vmode->crtc[i];
2635 } 2602 }
2636#undef REFRESH_TOLERANCE 2603
2637 if (nearest > 0) 2604 if (abs(best->refresh_rate - long_refresh) > 3)
2638 return res_map_refresh_tbl[nearest].vmode_refresh; 2605 return 60;
2639 return 60; 2606
2607 return best->refresh_rate;
2640} 2608}
2641 2609
2642static void device_off(void) 2610static void device_off(void)
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 668d534542ef..7295263299f7 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
893/* VT3410 chipset*/ 893/* VT3410 chipset*/
894#define VX900_FUNCTION3 0x3410 894#define VX900_FUNCTION3 0x3410
895 895
896#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
897
898struct IODATA { 896struct IODATA {
899 u8 Index; 897 u8 Index;
900 u8 Mask; 898 u8 Mask;
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index 3425c3969806..64bc7e763103 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -26,10 +26,12 @@
26 26
27/* CLE266 Software Power Sequence */ 27/* CLE266 Software Power Sequence */
28/* {Mask}, {Data}, {Delay} */ 28/* {Mask}, {Data}, {Delay} */
29int PowerSequenceOn[3][3] = { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, 29static const int PowerSequenceOn[3][3] = {
30 {0x19, 0x1FE, 0x01} }; 30 {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01}
31int PowerSequenceOff[3][3] = { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, 31};
32 {0xD2, 0x19, 0x01} }; 32static const int PowerSequenceOff[3][3] = {
33 {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01}
34};
33 35
34static struct _lcd_scaling_factor lcd_scaling_factor = { 36static struct _lcd_scaling_factor lcd_scaling_factor = {
35 /* LCD Horizontal Scaling Factor Register */ 37 /* LCD Horizontal Scaling Factor Register */
@@ -95,8 +97,6 @@ void __devinit viafb_init_lcd_size(void)
95 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n"); 97 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
96 98
97 fp_id_to_vindex(viafb_lcd_panel_id); 99 fp_id_to_vindex(viafb_lcd_panel_id);
98 viaparinfo->lvds_setting_info2->lcd_panel_id =
99 viaparinfo->lvds_setting_info->lcd_panel_id;
100 viaparinfo->lvds_setting_info2->lcd_panel_hres = 100 viaparinfo->lvds_setting_info2->lcd_panel_hres =
101 viaparinfo->lvds_setting_info->lcd_panel_hres; 101 viaparinfo->lvds_setting_info->lcd_panel_hres;
102 viaparinfo->lvds_setting_info2->lcd_panel_vres = 102 viaparinfo->lvds_setting_info2->lcd_panel_vres =
@@ -203,176 +203,132 @@ static void __devinit fp_id_to_vindex(int panel_id)
203 case 0x0: 203 case 0x0:
204 viaparinfo->lvds_setting_info->lcd_panel_hres = 640; 204 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
205 viaparinfo->lvds_setting_info->lcd_panel_vres = 480; 205 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
206 viaparinfo->lvds_setting_info->lcd_panel_id =
207 LCD_PANEL_ID0_640X480;
208 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 206 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
209 viaparinfo->lvds_setting_info->LCDDithering = 1; 207 viaparinfo->lvds_setting_info->LCDDithering = 1;
210 break; 208 break;
211 case 0x1: 209 case 0x1:
212 viaparinfo->lvds_setting_info->lcd_panel_hres = 800; 210 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
213 viaparinfo->lvds_setting_info->lcd_panel_vres = 600; 211 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
214 viaparinfo->lvds_setting_info->lcd_panel_id =
215 LCD_PANEL_ID1_800X600;
216 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 212 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
217 viaparinfo->lvds_setting_info->LCDDithering = 1; 213 viaparinfo->lvds_setting_info->LCDDithering = 1;
218 break; 214 break;
219 case 0x2: 215 case 0x2:
220 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 216 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
221 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 217 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
222 viaparinfo->lvds_setting_info->lcd_panel_id =
223 LCD_PANEL_ID2_1024X768;
224 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 218 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
225 viaparinfo->lvds_setting_info->LCDDithering = 1; 219 viaparinfo->lvds_setting_info->LCDDithering = 1;
226 break; 220 break;
227 case 0x3: 221 case 0x3:
228 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 222 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
229 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 223 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
230 viaparinfo->lvds_setting_info->lcd_panel_id =
231 LCD_PANEL_ID3_1280X768;
232 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 224 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
233 viaparinfo->lvds_setting_info->LCDDithering = 1; 225 viaparinfo->lvds_setting_info->LCDDithering = 1;
234 break; 226 break;
235 case 0x4: 227 case 0x4:
236 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 228 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
237 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024; 229 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
238 viaparinfo->lvds_setting_info->lcd_panel_id =
239 LCD_PANEL_ID4_1280X1024;
240 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 230 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
241 viaparinfo->lvds_setting_info->LCDDithering = 1; 231 viaparinfo->lvds_setting_info->LCDDithering = 1;
242 break; 232 break;
243 case 0x5: 233 case 0x5:
244 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400; 234 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
245 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050; 235 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
246 viaparinfo->lvds_setting_info->lcd_panel_id =
247 LCD_PANEL_ID5_1400X1050;
248 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 236 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
249 viaparinfo->lvds_setting_info->LCDDithering = 1; 237 viaparinfo->lvds_setting_info->LCDDithering = 1;
250 break; 238 break;
251 case 0x6: 239 case 0x6:
252 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600; 240 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
253 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200; 241 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
254 viaparinfo->lvds_setting_info->lcd_panel_id =
255 LCD_PANEL_ID6_1600X1200;
256 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 242 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
257 viaparinfo->lvds_setting_info->LCDDithering = 1; 243 viaparinfo->lvds_setting_info->LCDDithering = 1;
258 break; 244 break;
259 case 0x8: 245 case 0x8:
260 viaparinfo->lvds_setting_info->lcd_panel_hres = 800; 246 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
261 viaparinfo->lvds_setting_info->lcd_panel_vres = 480; 247 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
262 viaparinfo->lvds_setting_info->lcd_panel_id =
263 LCD_PANEL_IDA_800X480;
264 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 248 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
265 viaparinfo->lvds_setting_info->LCDDithering = 1; 249 viaparinfo->lvds_setting_info->LCDDithering = 1;
266 break; 250 break;
267 case 0x9: 251 case 0x9:
268 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 252 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
269 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 253 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
270 viaparinfo->lvds_setting_info->lcd_panel_id =
271 LCD_PANEL_ID2_1024X768;
272 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 254 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
273 viaparinfo->lvds_setting_info->LCDDithering = 1; 255 viaparinfo->lvds_setting_info->LCDDithering = 1;
274 break; 256 break;
275 case 0xA: 257 case 0xA:
276 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 258 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
277 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 259 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
278 viaparinfo->lvds_setting_info->lcd_panel_id =
279 LCD_PANEL_ID2_1024X768;
280 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 260 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
281 viaparinfo->lvds_setting_info->LCDDithering = 0; 261 viaparinfo->lvds_setting_info->LCDDithering = 0;
282 break; 262 break;
283 case 0xB: 263 case 0xB:
284 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 264 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
285 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 265 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
286 viaparinfo->lvds_setting_info->lcd_panel_id =
287 LCD_PANEL_ID2_1024X768;
288 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 266 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
289 viaparinfo->lvds_setting_info->LCDDithering = 0; 267 viaparinfo->lvds_setting_info->LCDDithering = 0;
290 break; 268 break;
291 case 0xC: 269 case 0xC:
292 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 270 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
293 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 271 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
294 viaparinfo->lvds_setting_info->lcd_panel_id =
295 LCD_PANEL_ID3_1280X768;
296 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 272 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
297 viaparinfo->lvds_setting_info->LCDDithering = 0; 273 viaparinfo->lvds_setting_info->LCDDithering = 0;
298 break; 274 break;
299 case 0xD: 275 case 0xD:
300 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 276 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
301 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024; 277 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
302 viaparinfo->lvds_setting_info->lcd_panel_id =
303 LCD_PANEL_ID4_1280X1024;
304 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 278 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
305 viaparinfo->lvds_setting_info->LCDDithering = 0; 279 viaparinfo->lvds_setting_info->LCDDithering = 0;
306 break; 280 break;
307 case 0xE: 281 case 0xE:
308 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400; 282 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
309 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050; 283 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
310 viaparinfo->lvds_setting_info->lcd_panel_id =
311 LCD_PANEL_ID5_1400X1050;
312 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 284 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
313 viaparinfo->lvds_setting_info->LCDDithering = 0; 285 viaparinfo->lvds_setting_info->LCDDithering = 0;
314 break; 286 break;
315 case 0xF: 287 case 0xF:
316 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600; 288 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
317 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200; 289 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
318 viaparinfo->lvds_setting_info->lcd_panel_id =
319 LCD_PANEL_ID6_1600X1200;
320 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 290 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
321 viaparinfo->lvds_setting_info->LCDDithering = 0; 291 viaparinfo->lvds_setting_info->LCDDithering = 0;
322 break; 292 break;
323 case 0x10: 293 case 0x10:
324 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366; 294 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
325 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 295 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
326 viaparinfo->lvds_setting_info->lcd_panel_id =
327 LCD_PANEL_ID7_1366X768;
328 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 296 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
329 viaparinfo->lvds_setting_info->LCDDithering = 0; 297 viaparinfo->lvds_setting_info->LCDDithering = 0;
330 break; 298 break;
331 case 0x11: 299 case 0x11:
332 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 300 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
333 viaparinfo->lvds_setting_info->lcd_panel_vres = 600; 301 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
334 viaparinfo->lvds_setting_info->lcd_panel_id =
335 LCD_PANEL_ID8_1024X600;
336 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 302 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
337 viaparinfo->lvds_setting_info->LCDDithering = 1; 303 viaparinfo->lvds_setting_info->LCDDithering = 1;
338 break; 304 break;
339 case 0x12: 305 case 0x12:
340 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 306 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
341 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 307 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
342 viaparinfo->lvds_setting_info->lcd_panel_id =
343 LCD_PANEL_ID3_1280X768;
344 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 308 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
345 viaparinfo->lvds_setting_info->LCDDithering = 1; 309 viaparinfo->lvds_setting_info->LCDDithering = 1;
346 break; 310 break;
347 case 0x13: 311 case 0x13:
348 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 312 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
349 viaparinfo->lvds_setting_info->lcd_panel_vres = 800; 313 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
350 viaparinfo->lvds_setting_info->lcd_panel_id =
351 LCD_PANEL_ID9_1280X800;
352 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 314 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
353 viaparinfo->lvds_setting_info->LCDDithering = 1; 315 viaparinfo->lvds_setting_info->LCDDithering = 1;
354 break; 316 break;
355 case 0x14: 317 case 0x14:
356 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360; 318 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
357 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 319 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
358 viaparinfo->lvds_setting_info->lcd_panel_id =
359 LCD_PANEL_IDB_1360X768;
360 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 320 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
361 viaparinfo->lvds_setting_info->LCDDithering = 0; 321 viaparinfo->lvds_setting_info->LCDDithering = 0;
362 break; 322 break;
363 case 0x15: 323 case 0x15:
364 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 324 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
365 viaparinfo->lvds_setting_info->lcd_panel_vres = 768; 325 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
366 viaparinfo->lvds_setting_info->lcd_panel_id =
367 LCD_PANEL_ID3_1280X768;
368 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 326 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
369 viaparinfo->lvds_setting_info->LCDDithering = 0; 327 viaparinfo->lvds_setting_info->LCDDithering = 0;
370 break; 328 break;
371 case 0x16: 329 case 0x16:
372 viaparinfo->lvds_setting_info->lcd_panel_hres = 480; 330 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
373 viaparinfo->lvds_setting_info->lcd_panel_vres = 640; 331 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
374 viaparinfo->lvds_setting_info->lcd_panel_id =
375 LCD_PANEL_IDC_480X640;
376 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 332 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
377 viaparinfo->lvds_setting_info->LCDDithering = 1; 333 viaparinfo->lvds_setting_info->LCDDithering = 1;
378 break; 334 break;
@@ -380,16 +336,12 @@ static void __devinit fp_id_to_vindex(int panel_id)
380 /* OLPC XO-1.5 panel */ 336 /* OLPC XO-1.5 panel */
381 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200; 337 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
382 viaparinfo->lvds_setting_info->lcd_panel_vres = 900; 338 viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
383 viaparinfo->lvds_setting_info->lcd_panel_id =
384 LCD_PANEL_IDD_1200X900;
385 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 339 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
386 viaparinfo->lvds_setting_info->LCDDithering = 0; 340 viaparinfo->lvds_setting_info->LCDDithering = 0;
387 break; 341 break;
388 default: 342 default:
389 viaparinfo->lvds_setting_info->lcd_panel_hres = 800; 343 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
390 viaparinfo->lvds_setting_info->lcd_panel_vres = 600; 344 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
391 viaparinfo->lvds_setting_info->lcd_panel_id =
392 LCD_PANEL_ID1_800X600;
393 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 345 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
394 viaparinfo->lvds_setting_info->LCDDithering = 1; 346 viaparinfo->lvds_setting_info->LCDDithering = 1;
395 } 347 }
@@ -610,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
610 int set_vres = plvds_setting_info->v_active; 562 int set_vres = plvds_setting_info->v_active;
611 int panel_hres = plvds_setting_info->lcd_panel_hres; 563 int panel_hres = plvds_setting_info->lcd_panel_hres;
612 int panel_vres = plvds_setting_info->lcd_panel_vres; 564 int panel_vres = plvds_setting_info->lcd_panel_vres;
613 u32 pll_D_N; 565 u32 pll_D_N, clock;
614 struct display_timing mode_crt_reg, panel_crt_reg; 566 struct display_timing mode_crt_reg, panel_crt_reg;
615 struct crt_mode_table *panel_crt_table = NULL; 567 struct crt_mode_table *panel_crt_table = NULL;
616 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, 568 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
@@ -625,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
625 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n"); 577 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
626 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) 578 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
627 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info); 579 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
628 plvds_setting_info->vclk = panel_crt_table->clk; 580 clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
581 * panel_crt_table->refresh_rate;
582 plvds_setting_info->vclk = clock;
629 if (set_iga == IGA1) { 583 if (set_iga == IGA1) {
630 /* IGA1 doesn't have LCD scaling, so set it as centering. */ 584 /* IGA1 doesn't have LCD scaling, so set it as centering. */
631 viafb_load_crtc_timing(lcd_centering_timging 585 viafb_load_crtc_timing(lcd_centering_timging
@@ -660,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
660 614
661 fill_lcd_format(); 615 fill_lcd_format();
662 616
663 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk); 617 pll_D_N = viafb_get_clk_value(clock);
664 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N); 618 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
665 viafb_set_vclock(pll_D_N, set_iga); 619 viafb_set_vclock(pll_D_N, set_iga);
666 lcd_patch_skew(plvds_setting_info, plvds_chip_info); 620 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
@@ -1064,34 +1018,33 @@ static struct display_timing lcd_centering_timging(struct display_timing
1064 1018
1065bool viafb_lcd_get_mobile_state(bool *mobile) 1019bool viafb_lcd_get_mobile_state(bool *mobile)
1066{ 1020{
1067 unsigned char *romptr, *tableptr; 1021 unsigned char __iomem *romptr, *tableptr, *biosptr;
1068 u8 core_base; 1022 u8 core_base;
1069 unsigned char *biosptr;
1070 /* Rom address */ 1023 /* Rom address */
1071 u32 romaddr = 0x000C0000; 1024 const u32 romaddr = 0x000C0000;
1072 u16 start_pattern = 0; 1025 u16 start_pattern;
1073 1026
1074 biosptr = ioremap(romaddr, 0x10000); 1027 biosptr = ioremap(romaddr, 0x10000);
1028 start_pattern = readw(biosptr);
1075 1029
1076 memcpy(&start_pattern, biosptr, 2);
1077 /* Compare pattern */ 1030 /* Compare pattern */
1078 if (start_pattern == 0xAA55) { 1031 if (start_pattern == 0xAA55) {
1079 /* Get the start of Table */ 1032 /* Get the start of Table */
1080 /* 0x1B means BIOS offset position */ 1033 /* 0x1B means BIOS offset position */
1081 romptr = biosptr + 0x1B; 1034 romptr = biosptr + 0x1B;
1082 tableptr = biosptr + *((u16 *) romptr); 1035 tableptr = biosptr + readw(romptr);
1083 1036
1084 /* Get the start of biosver structure */ 1037 /* Get the start of biosver structure */
1085 /* 18 means BIOS version position. */ 1038 /* 18 means BIOS version position. */
1086 romptr = tableptr + 18; 1039 romptr = tableptr + 18;
1087 romptr = biosptr + *((u16 *) romptr); 1040 romptr = biosptr + readw(romptr);
1088 1041
1089 /* The offset should be 44, but the 1042 /* The offset should be 44, but the
1090 actual image is less three char. */ 1043 actual image is less three char. */
1091 /* pRom += 44; */ 1044 /* pRom += 44; */
1092 romptr += 41; 1045 romptr += 41;
1093 1046
1094 core_base = *romptr++; 1047 core_base = readb(romptr);
1095 1048
1096 if (core_base & 0x8) 1049 if (core_base & 0x8)
1097 *mobile = false; 1050 *mobile = false;
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
index 2cbe1031b421..4b7831f0d012 100644
--- a/drivers/video/via/share.h
+++ b/drivers/video/via/share.h
@@ -627,77 +627,6 @@
627#define M2048x1536_R60_HSP NEGATIVE 627#define M2048x1536_R60_HSP NEGATIVE
628#define M2048x1536_R60_VSP POSITIVE 628#define M2048x1536_R60_VSP POSITIVE
629 629
630/* define PLL index: */
631#define CLK_25_175M 25175000
632#define CLK_26_880M 26880000
633#define CLK_29_581M 29581000
634#define CLK_31_500M 31500000
635#define CLK_31_728M 31728000
636#define CLK_32_668M 32688000
637#define CLK_36_000M 36000000
638#define CLK_40_000M 40000000
639#define CLK_41_291M 41291000
640#define CLK_43_163M 43163000
641#define CLK_45_250M 45250000 /* 45.46MHz */
642#define CLK_46_000M 46000000
643#define CLK_46_996M 46996000
644#define CLK_48_000M 48000000
645#define CLK_48_875M 48875000
646#define CLK_49_500M 49500000
647#define CLK_52_406M 52406000
648#define CLK_52_977M 52977000
649#define CLK_56_250M 56250000
650#define CLK_57_275M 57275000
651#define CLK_60_466M 60466000
652#define CLK_61_500M 61500000
653#define CLK_65_000M 65000000
654#define CLK_65_178M 65178000
655#define CLK_66_750M 66750000 /* 67.116MHz */
656#define CLK_68_179M 68179000
657#define CLK_69_924M 69924000
658#define CLK_70_159M 70159000
659#define CLK_72_000M 72000000
660#define CLK_74_270M 74270000
661#define CLK_78_750M 78750000
662#define CLK_80_136M 80136000
663#define CLK_83_375M 83375000
664#define CLK_83_950M 83950000
665#define CLK_84_750M 84750000 /* 84.537Mhz */
666#define CLK_85_860M 85860000
667#define CLK_88_750M 88750000
668#define CLK_94_500M 94500000
669#define CLK_97_750M 97750000
670#define CLK_101_000M 101000000
671#define CLK_106_500M 106500000
672#define CLK_108_000M 108000000
673#define CLK_113_309M 113309000
674#define CLK_118_840M 118840000
675#define CLK_119_000M 119000000
676#define CLK_121_750M 121750000 /* 121.704MHz */
677#define CLK_125_104M 125104000
678#define CLK_135_000M 135000000
679#define CLK_136_700M 136700000
680#define CLK_138_400M 138400000
681#define CLK_146_760M 146760000
682#define CLK_148_500M 148500000
683
684#define CLK_153_920M 153920000
685#define CLK_156_000M 156000000
686#define CLK_157_500M 157500000
687#define CLK_162_000M 162000000
688#define CLK_187_000M 187000000
689#define CLK_193_295M 193295000
690#define CLK_202_500M 202500000
691#define CLK_204_000M 204000000
692#define CLK_218_500M 218500000
693#define CLK_234_000M 234000000
694#define CLK_267_250M 267250000
695#define CLK_297_500M 297500000
696#define CLK_74_481M 74481000
697#define CLK_172_798M 172798000
698#define CLK_122_614M 122614000
699
700
701/* Definition CRTC Timing Index */ 630/* Definition CRTC Timing Index */
702#define H_TOTAL_INDEX 0 631#define H_TOTAL_INDEX 0
703#define H_ADDR_INDEX 1 632#define H_ADDR_INDEX 1
@@ -722,76 +651,7 @@
722 651
723/* Definition Video Mode Pixel Clock (picoseconds) 652/* Definition Video Mode Pixel Clock (picoseconds)
724*/ 653*/
725#define RES_480X640_60HZ_PIXCLOCK 39722
726#define RES_640X480_60HZ_PIXCLOCK 39722 654#define RES_640X480_60HZ_PIXCLOCK 39722
727#define RES_640X480_75HZ_PIXCLOCK 31747
728#define RES_640X480_85HZ_PIXCLOCK 27777
729#define RES_640X480_100HZ_PIXCLOCK 23168
730#define RES_640X480_120HZ_PIXCLOCK 19081
731#define RES_720X480_60HZ_PIXCLOCK 37020
732#define RES_720X576_60HZ_PIXCLOCK 30611
733#define RES_800X600_60HZ_PIXCLOCK 25000
734#define RES_800X600_75HZ_PIXCLOCK 20203
735#define RES_800X600_85HZ_PIXCLOCK 17777
736#define RES_800X600_100HZ_PIXCLOCK 14667
737#define RES_800X600_120HZ_PIXCLOCK 11912
738#define RES_800X480_60HZ_PIXCLOCK 33805
739#define RES_848X480_60HZ_PIXCLOCK 31756
740#define RES_856X480_60HZ_PIXCLOCK 31518
741#define RES_1024X512_60HZ_PIXCLOCK 24218
742#define RES_1024X600_60HZ_PIXCLOCK 20460
743#define RES_1024X768_60HZ_PIXCLOCK 15385
744#define RES_1024X768_75HZ_PIXCLOCK 12699
745#define RES_1024X768_85HZ_PIXCLOCK 10582
746#define RES_1024X768_100HZ_PIXCLOCK 8825
747#define RES_1152X864_75HZ_PIXCLOCK 9259
748#define RES_1280X768_60HZ_PIXCLOCK 12480
749#define RES_1280X800_60HZ_PIXCLOCK 11994
750#define RES_1280X960_60HZ_PIXCLOCK 9259
751#define RES_1280X1024_60HZ_PIXCLOCK 9260
752#define RES_1280X1024_75HZ_PIXCLOCK 7408
753#define RES_1280X768_85HZ_PIXCLOCK 6349
754#define RES_1440X1050_60HZ_PIXCLOCK 7993
755#define RES_1600X1200_60HZ_PIXCLOCK 6172
756#define RES_1600X1200_75HZ_PIXCLOCK 4938
757#define RES_1280X720_60HZ_PIXCLOCK 13426
758#define RES_1200X900_60HZ_PIXCLOCK 17459
759#define RES_1920X1080_60HZ_PIXCLOCK 5787
760#define RES_1400X1050_60HZ_PIXCLOCK 8214
761#define RES_1400X1050_75HZ_PIXCLOCK 6410
762#define RES_1368X768_60HZ_PIXCLOCK 11647
763#define RES_960X600_60HZ_PIXCLOCK 22099
764#define RES_1000X600_60HZ_PIXCLOCK 20834
765#define RES_1024X576_60HZ_PIXCLOCK 21278
766#define RES_1088X612_60HZ_PIXCLOCK 18877
767#define RES_1152X720_60HZ_PIXCLOCK 14981
768#define RES_1200X720_60HZ_PIXCLOCK 14253
769#define RES_1280X600_60HZ_PIXCLOCK 16260
770#define RES_1280X720_50HZ_PIXCLOCK 16538
771#define RES_1280X768_50HZ_PIXCLOCK 15342
772#define RES_1366X768_50HZ_PIXCLOCK 14301
773#define RES_1366X768_60HZ_PIXCLOCK 11646
774#define RES_1360X768_60HZ_PIXCLOCK 11799
775#define RES_1440X900_60HZ_PIXCLOCK 9390
776#define RES_1440X900_75HZ_PIXCLOCK 7315
777#define RES_1600X900_60HZ_PIXCLOCK 8415
778#define RES_1600X1024_60HZ_PIXCLOCK 7315
779#define RES_1680X1050_60HZ_PIXCLOCK 6814
780#define RES_1680X1050_75HZ_PIXCLOCK 5348
781#define RES_1792X1344_60HZ_PIXCLOCK 4902
782#define RES_1856X1392_60HZ_PIXCLOCK 4577
783#define RES_1920X1200_60HZ_PIXCLOCK 5173
784#define RES_1920X1440_60HZ_PIXCLOCK 4274
785#define RES_1920X1440_75HZ_PIXCLOCK 3367
786#define RES_2048X1536_60HZ_PIXCLOCK 3742
787
788#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
789#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
790#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
791#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
792#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
793#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
794#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
795 655
796/* LCD display method 656/* LCD display method
797*/ 657*/
@@ -822,7 +682,6 @@ struct display_timing {
822 682
823struct crt_mode_table { 683struct crt_mode_table {
824 int refresh_rate; 684 int refresh_rate;
825 unsigned long clk;
826 int h_sync_polarity; 685 int h_sync_polarity;
827 int v_sync_polarity; 686 int v_sync_polarity;
828 struct display_timing crtc; 687 struct display_timing crtc;
diff --git a/drivers/video/via/tblDPASetting.c b/drivers/video/via/tblDPASetting.c
index 0c4c8cc712f4..73bb554e7c1e 100644
--- a/drivers/video/via/tblDPASetting.c
+++ b/drivers/video/via/tblDPASetting.c
@@ -20,17 +20,6 @@
20 */ 20 */
21 21
22#include "global.h" 22#include "global.h"
23/* For VT3324: */
24struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[] = {
25 /* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
26 {LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
27 {LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
28 {LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
29 {LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
30 {LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
31 {LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
32 {LCD_PANEL_ID6_1600X1200, 0x0B, 0x03} /* For 1600x1200 */
33};
34 23
35struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = { 24struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
36/* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, 25/* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
@@ -57,18 +46,6 @@ struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
57 0x00}, 46 0x00},
58}; 47};
59 48
60/* For VT3327: */
61struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[] = {
62 /* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
63 {LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
64 {LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
65 {LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
66 {LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
67 {LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
68 {LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
69 {LCD_PANEL_ID6_1600X1200, 0x00, 0x00} /* For 1600x1200 */
70};
71
72struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = { 49struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
73/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, 50/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
74 DVP1Driving, DFPHigh, DFPLow */ 51 DVP1Driving, DFPHigh, DFPLow */
diff --git a/drivers/video/via/tblDPASetting.h b/drivers/video/via/tblDPASetting.h
index b065a83481d3..6db61519cb5d 100644
--- a/drivers/video/via/tblDPASetting.h
+++ b/drivers/video/via/tblDPASetting.h
@@ -38,9 +38,7 @@ enum DPA_RANGE {
38 DPA_CLK_RANGE_150M 38 DPA_CLK_RANGE_150M
39}; 39};
40 40
41extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[7];
42extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[6]; 41extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[6];
43extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[7];
44extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[]; 42extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[];
45extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[6]; 43extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[6];
46 44
diff --git a/drivers/video/via/via_i2c.c b/drivers/video/via/via_i2c.c
index 3844b558b7bd..78f1405dbab7 100644
--- a/drivers/video/via/via_i2c.c
+++ b/drivers/video/via/via_i2c.c
@@ -32,7 +32,7 @@
32 */ 32 */
33#define VIAFB_NUM_I2C 5 33#define VIAFB_NUM_I2C 5
34static struct via_i2c_stuff via_i2c_par[VIAFB_NUM_I2C]; 34static struct via_i2c_stuff via_i2c_par[VIAFB_NUM_I2C];
35struct viafb_dev *i2c_vdev; /* Passed in from core */ 35static struct viafb_dev *i2c_vdev; /* Passed in from core */
36 36
37static void via_i2c_setscl(void *data, int state) 37static void via_i2c_setscl(void *data, int state)
38{ 38{
@@ -209,7 +209,6 @@ static int create_i2c_bus(struct i2c_adapter *adapter,
209 sprintf(adapter->name, "viafb i2c io_port idx 0x%02x", 209 sprintf(adapter->name, "viafb i2c io_port idx 0x%02x",
210 adap_cfg->ioport_index); 210 adap_cfg->ioport_index);
211 adapter->owner = THIS_MODULE; 211 adapter->owner = THIS_MODULE;
212 adapter->id = 0x01FFFF;
213 adapter->class = I2C_CLASS_DDC; 212 adapter->class = I2C_CLASS_DDC;
214 adapter->algo_data = algo; 213 adapter->algo_data = algo;
215 if (pdev) 214 if (pdev)
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index 4e66349e4366..f555b891cc72 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -43,11 +43,11 @@ static int viafb_second_size;
43static int viafb_accel = 1; 43static int viafb_accel = 1;
44 44
45/* Added for specifying active devices.*/ 45/* Added for specifying active devices.*/
46char *viafb_active_dev; 46static char *viafb_active_dev;
47 47
48/*Added for specify lcd output port*/ 48/*Added for specify lcd output port*/
49char *viafb_lcd_port = ""; 49static char *viafb_lcd_port = "";
50char *viafb_dvi_port = ""; 50static char *viafb_dvi_port = "";
51 51
52static void retrieve_device_setting(struct viafb_ioctl_setting 52static void retrieve_device_setting(struct viafb_ioctl_setting
53 *setting_info); 53 *setting_info);
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
index 2dbad3c0f679..8c5bc41ff6a4 100644
--- a/drivers/video/via/viamode.c
+++ b/drivers/video/via/viamode.c
@@ -21,72 +21,6 @@
21 21
22#include <linux/via-core.h> 22#include <linux/via-core.h>
23#include "global.h" 23#include "global.h"
24struct res_map_refresh res_map_refresh_tbl[] = {
25/*hres, vres, vclock, vmode_refresh*/
26 {480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
27 {640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
28 {640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
29 {640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
30 {640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
31 {640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
32 {720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
33 {720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
34 {800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
35 {800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
36 {800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
37 {800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
38 {800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
39 {800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
40 {848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
41 {856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
42 {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
43 {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
44 {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
45 {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
46 {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
47 {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
48/* {1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},*/
49 {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
50 {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
51 {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
52 {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
53 {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
54 {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
55 {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
56 {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
57 {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
58 {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
59 {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
60 {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
61 {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
62 {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
63 {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
64 {960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
65 {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
66 {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
67 {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
68 {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
69 {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
70 {1200, 900, RES_1200X900_60HZ_PIXCLOCK, 60},
71 {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
72 {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
73 {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
74 {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
75 {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
76 {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
77 {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
78 {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
79 {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
80 {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
81 {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
82 {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
83 {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
84 {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
85 {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
86 {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
87 {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
88 {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
89};
90 24
91struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, 25struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
92{VIASR, SR15, 0x02, 0x02}, 26{VIASR, SR15, 0x02, 0x02},
@@ -108,20 +42,6 @@ struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
108{VIACR, CR6A, 0xFF, 0x40}, 42{VIACR, CR6A, 0xFF, 0x40},
109{VIACR, CR6B, 0xFF, 0x00}, 43{VIACR, CR6B, 0xFF, 0x00},
110{VIACR, CR6C, 0xFF, 0x00}, 44{VIACR, CR6C, 0xFF, 0x00},
111{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
112{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
113{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
114{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
115{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
116{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
117{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
118{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
119{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
120{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
121{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
122{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
123{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
124{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
125{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 45{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
126{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 46{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
127{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 47{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
@@ -172,20 +92,6 @@ struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
172{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */ 92{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
173{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */ 93{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
174{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */ 94{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */
175{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
176{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
177{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
178{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
179{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
180{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
181{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
182{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
183{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
184{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
185{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
186{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
187{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
188{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
189{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 95{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
190{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 96{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
191{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 97{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
@@ -229,20 +135,6 @@ struct io_reg KM400_ModeXregs[] = {
229 {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */ 135 {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
230 {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */ 136 {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
231 {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */ 137 {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
232 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
233 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
234 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
235 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
236 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
237 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
238 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
239 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
240 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
241 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
242 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
243 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
244 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
245 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
246 {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 138 {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
247 {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 139 {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
248 {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 140 {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
@@ -283,20 +175,6 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
283{VIACR, CR6A, 0xFF, 0x40}, 175{VIACR, CR6A, 0xFF, 0x40},
284{VIACR, CR6B, 0xFF, 0x00}, 176{VIACR, CR6B, 0xFF, 0x00},
285{VIACR, CR6C, 0xFF, 0x00}, 177{VIACR, CR6C, 0xFF, 0x00},
286{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
287{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
288{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
289{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
290{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
291{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
292{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
293{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
294{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
295{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
296{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
297{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
298{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
299{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
300{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 178{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
301{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 179{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
302{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 180{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
@@ -342,20 +220,6 @@ struct io_reg VX855_ModeXregs[] = {
342{VIACR, CR6A, 0xFD, 0x60}, 220{VIACR, CR6A, 0xFD, 0x60},
343{VIACR, CR6B, 0xFF, 0x00}, 221{VIACR, CR6B, 0xFF, 0x00},
344{VIACR, CR6C, 0xFF, 0x00}, 222{VIACR, CR6C, 0xFF, 0x00},
345{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
346{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
347{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
348{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
349{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
350{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
351{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
352{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
353{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
354{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
355{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
356{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
357{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
358{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
359{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 223{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
360{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 224{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
361{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 225{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
@@ -390,21 +254,6 @@ struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
390{VIAGR, GR20, 0xFF, 0x00}, 254{VIAGR, GR20, 0xFF, 0x00},
391{VIAGR, GR21, 0xFF, 0x00}, 255{VIAGR, GR21, 0xFF, 0x00},
392{VIAGR, GR22, 0xFF, 0x00}, 256{VIAGR, GR22, 0xFF, 0x00},
393 /* LCD Parameters */
394{VIACR, CR7A, 0xFF, 0x01}, /* LCD Parameter 1 */
395{VIACR, CR7B, 0xFF, 0x02}, /* LCD Parameter 2 */
396{VIACR, CR7C, 0xFF, 0x03}, /* LCD Parameter 3 */
397{VIACR, CR7D, 0xFF, 0x04}, /* LCD Parameter 4 */
398{VIACR, CR7E, 0xFF, 0x07}, /* LCD Parameter 5 */
399{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Parameter 6 */
400{VIACR, CR80, 0xFF, 0x0D}, /* LCD Parameter 7 */
401{VIACR, CR81, 0xFF, 0x13}, /* LCD Parameter 8 */
402{VIACR, CR82, 0xFF, 0x16}, /* LCD Parameter 9 */
403{VIACR, CR83, 0xFF, 0x19}, /* LCD Parameter 10 */
404{VIACR, CR84, 0xFF, 0x1C}, /* LCD Parameter 11 */
405{VIACR, CR85, 0xFF, 0x1D}, /* LCD Parameter 12 */
406{VIACR, CR86, 0xFF, 0x1E}, /* LCD Parameter 13 */
407{VIACR, CR87, 0xFF, 0x1F}, /* LCD Parameter 14 */
408 257
409}; 258};
410 259
@@ -443,328 +292,321 @@ struct VPITTable VPIT = {
443/********************/ 292/********************/
444 293
445/* 480x640 */ 294/* 480x640 */
446struct crt_mode_table CRTM480x640[] = { 295static struct crt_mode_table CRTM480x640[] = {
447 /* r_rate, vclk, hsp, vsp */ 296 /* r_rate, hsp, vsp */
448 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 297 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
449 {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP, 298 {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP,
450 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/ 299 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/
451}; 300};
452 301
453/* 640x480*/ 302/* 640x480*/
454struct crt_mode_table CRTM640x480[] = { 303static struct crt_mode_table CRTM640x480[] = {
455 /*r_rate,vclk,hsp,vsp */ 304 /*r_rate,hsp,vsp */
456 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 305 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
457 {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP, 306 {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP,
458 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} }, 307 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
459 {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP, 308 {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP,
460 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} }, 309 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
461 {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP, 310 {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP,
462 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} }, 311 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
463 {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP, 312 {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP,
464 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/ 313 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
465 {REFRESH_120, CLK_52_406M, M640X480_R120_HSP, 314 {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP,
466 M640X480_R120_VSP, 315 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/
467 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481,
468 3} } /*GTF*/
469}; 316};
470 317
471/*720x480 (GTF)*/ 318/*720x480 (GTF)*/
472struct crt_mode_table CRTM720x480[] = { 319static struct crt_mode_table CRTM720x480[] = {
473 /*r_rate,vclk,hsp,vsp */ 320 /*r_rate,hsp,vsp */
474 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 321 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
475 {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP, 322 {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP,
476 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} } 323 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
477 324
478}; 325};
479 326
480/*720x576 (GTF)*/ 327/*720x576 (GTF)*/
481struct crt_mode_table CRTM720x576[] = { 328static struct crt_mode_table CRTM720x576[] = {
482 /*r_rate,vclk,hsp,vsp */ 329 /*r_rate,hsp,vsp */
483 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 330 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
484 {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP, 331 {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP,
485 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} } 332 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
486}; 333};
487 334
488/* 800x480 (CVT) */ 335/* 800x480 (CVT) */
489struct crt_mode_table CRTM800x480[] = { 336static struct crt_mode_table CRTM800x480[] = {
490 /* r_rate, vclk, hsp, vsp */ 337 /* r_rate, hsp, vsp */
491 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 338 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
492 {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP, 339 {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP,
493 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} } 340 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
494}; 341};
495 342
496/* 800x600*/ 343/* 800x600*/
497struct crt_mode_table CRTM800x600[] = { 344static struct crt_mode_table CRTM800x600[] = {
498 /*r_rate,vclk,hsp,vsp */ 345 /*r_rate,hsp,vsp */
499 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 346 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
500 {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP, 347 {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP,
501 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} }, 348 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
502 {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP, 349 {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP,
503 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} }, 350 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
504 {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP, 351 {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP,
505 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} }, 352 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
506 {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP, 353 {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP,
507 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} }, 354 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
508 {REFRESH_120, CLK_83_950M, M800X600_R120_HSP, 355 {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP,
509 M800X600_R120_VSP, 356 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} }
510 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601,
511 3} }
512}; 357};
513 358
514/* 848x480 (CVT) */ 359/* 848x480 (CVT) */
515struct crt_mode_table CRTM848x480[] = { 360static struct crt_mode_table CRTM848x480[] = {
516 /* r_rate, vclk, hsp, vsp */ 361 /* r_rate, hsp, vsp */
517 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 362 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
518 {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP, 363 {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP,
519 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} } 364 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
520}; 365};
521 366
522/*856x480 (GTF) convert to 852x480*/ 367/*856x480 (GTF) convert to 852x480*/
523struct crt_mode_table CRTM852x480[] = { 368static struct crt_mode_table CRTM852x480[] = {
524 /*r_rate,vclk,hsp,vsp */ 369 /*r_rate,hsp,vsp */
525 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 370 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
526 {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP, 371 {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
527 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} } 372 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
528}; 373};
529 374
530/*1024x512 (GTF)*/ 375/*1024x512 (GTF)*/
531struct crt_mode_table CRTM1024x512[] = { 376static struct crt_mode_table CRTM1024x512[] = {
532 /*r_rate,vclk,hsp,vsp */ 377 /*r_rate,hsp,vsp */
533 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 378 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
534 {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP, 379 {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
535 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} } 380 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
536 381
537}; 382};
538 383
539/* 1024x600*/ 384/* 1024x600*/
540struct crt_mode_table CRTM1024x600[] = { 385static struct crt_mode_table CRTM1024x600[] = {
541 /*r_rate,vclk,hsp,vsp */ 386 /*r_rate,hsp,vsp */
542 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 387 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
543 {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP, 388 {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
544 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} }, 389 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
545}; 390};
546 391
547/* 1024x768*/ 392/* 1024x768*/
548struct crt_mode_table CRTM1024x768[] = { 393static struct crt_mode_table CRTM1024x768[] = {
549 /*r_rate,vclk,hsp,vsp */ 394 /*r_rate,hsp,vsp */
550 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 395 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
551 {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP, 396 {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
552 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} }, 397 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
553 {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP, 398 {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
554 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} }, 399 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
555 {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP, 400 {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
556 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} }, 401 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
557 {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP, 402 {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
558 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} } 403 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
559}; 404};
560 405
561/* 1152x864*/ 406/* 1152x864*/
562struct crt_mode_table CRTM1152x864[] = { 407static struct crt_mode_table CRTM1152x864[] = {
563 /*r_rate,vclk,hsp,vsp */ 408 /*r_rate,hsp,vsp */
564 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 409 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
565 {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP, 410 {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
566 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} } 411 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
567 412
568}; 413};
569 414
570/* 1280x720 (HDMI 720P)*/ 415/* 1280x720 (HDMI 720P)*/
571struct crt_mode_table CRTM1280x720[] = { 416static struct crt_mode_table CRTM1280x720[] = {
572 /*r_rate,vclk,hsp,vsp */ 417 /*r_rate,hsp,vsp */
573 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 418 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
574 {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP, 419 {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
575 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} }, 420 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
576 {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP, 421 {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
577 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} } 422 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
578}; 423};
579 424
580/*1280x768 (GTF)*/ 425/*1280x768 (GTF)*/
581struct crt_mode_table CRTM1280x768[] = { 426static struct crt_mode_table CRTM1280x768[] = {
582 /*r_rate,vclk,hsp,vsp */ 427 /*r_rate,hsp,vsp */
583 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 428 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
584 {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP, 429 {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
585 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} }, 430 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
586 {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP, 431 {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
587 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} } 432 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
588}; 433};
589 434
590/* 1280x800 (CVT) */ 435/* 1280x800 (CVT) */
591struct crt_mode_table CRTM1280x800[] = { 436static struct crt_mode_table CRTM1280x800[] = {
592 /* r_rate, vclk, hsp, vsp */ 437 /* r_rate, hsp, vsp */
593 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 438 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
594 {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP, 439 {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
595 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} } 440 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
596}; 441};
597 442
598/*1280x960*/ 443/*1280x960*/
599struct crt_mode_table CRTM1280x960[] = { 444static struct crt_mode_table CRTM1280x960[] = {
600 /*r_rate,vclk,hsp,vsp */ 445 /*r_rate,hsp,vsp */
601 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 446 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
602 {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP, 447 {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
603 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} } 448 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
604}; 449};
605 450
606/* 1280x1024*/ 451/* 1280x1024*/
607struct crt_mode_table CRTM1280x1024[] = { 452static struct crt_mode_table CRTM1280x1024[] = {
608 /*r_rate,vclk,,hsp,vsp */ 453 /*r_rate,hsp,vsp */
609 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 454 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
610 {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP, 455 {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
611 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025, 456 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
612 3} }, 457 3} },
613 {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP, 458 {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
614 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025, 459 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
615 3} }, 460 3} },
616 {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP, 461 {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
617 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} } 462 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
618}; 463};
619 464
620/* 1368x768 (GTF) */ 465/* 1368x768 (GTF) */
621struct crt_mode_table CRTM1368x768[] = { 466static struct crt_mode_table CRTM1368x768[] = {
622 /* r_rate, vclk, hsp, vsp */ 467 /* r_rate, hsp, vsp */
623 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 468 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
624 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, 469 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
625 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} } 470 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
626}; 471};
627 472
628/*1440x1050 (GTF)*/ 473/*1440x1050 (GTF)*/
629struct crt_mode_table CRTM1440x1050[] = { 474static struct crt_mode_table CRTM1440x1050[] = {
630 /*r_rate,vclk,hsp,vsp */ 475 /*r_rate,hsp,vsp */
631 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 476 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
632 {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP, 477 {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
633 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} } 478 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
634}; 479};
635 480
636/* 1600x1200*/ 481/* 1600x1200*/
637struct crt_mode_table CRTM1600x1200[] = { 482static struct crt_mode_table CRTM1600x1200[] = {
638 /*r_rate,vclk,hsp,vsp */ 483 /*r_rate,hsp,vsp */
639 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 484 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
640 {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP, 485 {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
641 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 486 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
642 3} }, 487 3} },
643 {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP, 488 {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
644 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} } 489 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
645 490
646}; 491};
647 492
648/* 1680x1050 (CVT) */ 493/* 1680x1050 (CVT) */
649struct crt_mode_table CRTM1680x1050[] = { 494static struct crt_mode_table CRTM1680x1050[] = {
650 /* r_rate, vclk, hsp, vsp */ 495 /* r_rate, hsp, vsp */
651 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 496 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
652 {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP, 497 {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
653 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053, 498 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
654 6} }, 499 6} },
655 {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP, 500 {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
656 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} } 501 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
657}; 502};
658 503
659/* 1680x1050 (CVT Reduce Blanking) */ 504/* 1680x1050 (CVT Reduce Blanking) */
660struct crt_mode_table CRTM1680x1050_RB[] = { 505static struct crt_mode_table CRTM1680x1050_RB[] = {
661 /* r_rate, vclk, hsp, vsp */ 506 /* r_rate, hsp, vsp */
662 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 507 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
663 {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP, 508 {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
664 M1680x1050_RB_R60_VSP,
665 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} } 509 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
666}; 510};
667 511
668/* 1920x1080 (CVT)*/ 512/* 1920x1080 (CVT)*/
669struct crt_mode_table CRTM1920x1080[] = { 513static struct crt_mode_table CRTM1920x1080[] = {
670 /*r_rate,vclk,hsp,vsp */ 514 /*r_rate,hsp,vsp */
671 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 515 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
672 {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP, 516 {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
673 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} } 517 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
674}; 518};
675 519
676/* 1920x1080 (CVT with Reduce Blanking) */ 520/* 1920x1080 (CVT with Reduce Blanking) */
677struct crt_mode_table CRTM1920x1080_RB[] = { 521static struct crt_mode_table CRTM1920x1080_RB[] = {
678 /* r_rate, vclk, hsp, vsp */ 522 /* r_rate, hsp, vsp */
679 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 523 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
680 {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP, 524 {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
681 M1920X1080_RB_R60_VSP,
682 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} } 525 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
683}; 526};
684 527
685/* 1920x1440*/ 528/* 1920x1440*/
686struct crt_mode_table CRTM1920x1440[] = { 529static struct crt_mode_table CRTM1920x1440[] = {
687 /*r_rate,vclk,hsp,vsp */ 530 /*r_rate,hsp,vsp */
688 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 531 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
689 {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP, 532 {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
690 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441, 533 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
691 3} }, 534 3} },
692 {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP, 535 {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
693 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} } 536 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
694}; 537};
695 538
696/* 1400x1050 (CVT) */ 539/* 1400x1050 (CVT) */
697struct crt_mode_table CRTM1400x1050[] = { 540static struct crt_mode_table CRTM1400x1050[] = {
698 /* r_rate, vclk, hsp, vsp */ 541 /* r_rate, hsp, vsp */
699 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 542 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
700 {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP, 543 {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
701 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053, 544 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
702 4} }, 545 4} },
703 {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP, 546 {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
704 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} } 547 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
705}; 548};
706 549
707/* 1400x1050 (CVT Reduce Blanking) */ 550/* 1400x1050 (CVT Reduce Blanking) */
708struct crt_mode_table CRTM1400x1050_RB[] = { 551static struct crt_mode_table CRTM1400x1050_RB[] = {
709 /* r_rate, vclk, hsp, vsp */ 552 /* r_rate, hsp, vsp */
710 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 553 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
711 {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP, 554 {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
712 M1400X1050_RB_R60_VSP,
713 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} } 555 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
714}; 556};
715 557
716/* 960x600 (CVT) */ 558/* 960x600 (CVT) */
717struct crt_mode_table CRTM960x600[] = { 559static struct crt_mode_table CRTM960x600[] = {
718 /* r_rate, vclk, hsp, vsp */ 560 /* r_rate, hsp, vsp */
719 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 561 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
720 {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP, 562 {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
721 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} } 563 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
722}; 564};
723 565
724/* 1000x600 (GTF) */ 566/* 1000x600 (GTF) */
725struct crt_mode_table CRTM1000x600[] = { 567static struct crt_mode_table CRTM1000x600[] = {
726 /* r_rate, vclk, hsp, vsp */ 568 /* r_rate, hsp, vsp */
727 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 569 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
728 {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP, 570 {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
729 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} } 571 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
730}; 572};
731 573
732/* 1024x576 (GTF) */ 574/* 1024x576 (GTF) */
733struct crt_mode_table CRTM1024x576[] = { 575static struct crt_mode_table CRTM1024x576[] = {
734 /* r_rate, vclk, hsp, vsp */ 576 /* r_rate, hsp, vsp */
735 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 577 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
736 {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP, 578 {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
737 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} } 579 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
738}; 580};
739 581
740/* 1088x612 (CVT) */ 582/* 1088x612 (CVT) */
741struct crt_mode_table CRTM1088x612[] = { 583static struct crt_mode_table CRTM1088x612[] = {
742 /* r_rate, vclk, hsp, vsp */ 584 /* r_rate, hsp, vsp */
743 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 585 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
744 {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP, 586 {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
745 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} } 587 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
746}; 588};
747 589
748/* 1152x720 (CVT) */ 590/* 1152x720 (CVT) */
749struct crt_mode_table CRTM1152x720[] = { 591static struct crt_mode_table CRTM1152x720[] = {
750 /* r_rate, vclk, hsp, vsp */ 592 /* r_rate, hsp, vsp */
751 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 593 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
752 {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP, 594 {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
753 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} } 595 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
754}; 596};
755 597
756/* 1200x720 (GTF) */ 598/* 1200x720 (GTF) */
757struct crt_mode_table CRTM1200x720[] = { 599static struct crt_mode_table CRTM1200x720[] = {
758 /* r_rate, vclk, hsp, vsp */ 600 /* r_rate, hsp, vsp */
759 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 601 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
760 {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP, 602 {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
761 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} } 603 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
762}; 604};
763 605
764/* 1200x900 (DCON) */ 606/* 1200x900 (DCON) */
765struct crt_mode_table DCON1200x900[] = { 607static struct crt_mode_table DCON1200x900[] = {
766 /* r_rate, vclk, hsp, vsp */ 608 /* r_rate, hsp, vsp */
767 {REFRESH_60, CLK_57_275M, M1200X900_R60_HSP, M1200X900_R60_VSP, 609 {REFRESH_60, M1200X900_R60_HSP, M1200X900_R60_VSP,
768 /* The correct htotal is 1240, but this doesn't raster on VX855. */ 610 /* The correct htotal is 1240, but this doesn't raster on VX855. */
769 /* Via suggested changing to a multiple of 16, hence 1264. */ 611 /* Via suggested changing to a multiple of 16, hence 1264. */
770 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 612 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
@@ -772,126 +614,122 @@ struct crt_mode_table DCON1200x900[] = {
772}; 614};
773 615
774/* 1280x600 (GTF) */ 616/* 1280x600 (GTF) */
775struct crt_mode_table CRTM1280x600[] = { 617static struct crt_mode_table CRTM1280x600[] = {
776 /* r_rate, vclk, hsp, vsp */ 618 /* r_rate, hsp, vsp */
777 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 619 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
778 {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP, 620 {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
779 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} } 621 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
780}; 622};
781 623
782/* 1360x768 (CVT) */ 624/* 1360x768 (CVT) */
783struct crt_mode_table CRTM1360x768[] = { 625static struct crt_mode_table CRTM1360x768[] = {
784 /* r_rate, vclk, hsp, vsp */ 626 /* r_rate, hsp, vsp */
785 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 627 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
786 {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP, 628 {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
787 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} } 629 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
788}; 630};
789 631
790/* 1360x768 (CVT Reduce Blanking) */ 632/* 1360x768 (CVT Reduce Blanking) */
791struct crt_mode_table CRTM1360x768_RB[] = { 633static struct crt_mode_table CRTM1360x768_RB[] = {
792 /* r_rate, vclk, hsp, vsp */ 634 /* r_rate, hsp, vsp */
793 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 635 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
794 {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP, 636 {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
795 M1360X768_RB_R60_VSP,
796 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} } 637 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
797}; 638};
798 639
799/* 1366x768 (GTF) */ 640/* 1366x768 (GTF) */
800struct crt_mode_table CRTM1366x768[] = { 641static struct crt_mode_table CRTM1366x768[] = {
801 /* r_rate, vclk, hsp, vsp */ 642 /* r_rate, hsp, vsp */
802 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 643 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
803 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, 644 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
804 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }, 645 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
805 {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP, 646 {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
806 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} } 647 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
807}; 648};
808 649
809/* 1440x900 (CVT) */ 650/* 1440x900 (CVT) */
810struct crt_mode_table CRTM1440x900[] = { 651static struct crt_mode_table CRTM1440x900[] = {
811 /* r_rate, vclk, hsp, vsp */ 652 /* r_rate, hsp, vsp */
812 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 653 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
813 {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP, 654 {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
814 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} }, 655 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
815 {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP, 656 {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
816 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} } 657 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
817}; 658};
818 659
819/* 1440x900 (CVT Reduce Blanking) */ 660/* 1440x900 (CVT Reduce Blanking) */
820struct crt_mode_table CRTM1440x900_RB[] = { 661static struct crt_mode_table CRTM1440x900_RB[] = {
821 /* r_rate, vclk, hsp, vsp */ 662 /* r_rate, hsp, vsp */
822 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 663 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
823 {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP, 664 {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
824 M1440X900_RB_R60_VSP,
825 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} } 665 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
826}; 666};
827 667
828/* 1600x900 (CVT) */ 668/* 1600x900 (CVT) */
829struct crt_mode_table CRTM1600x900[] = { 669static struct crt_mode_table CRTM1600x900[] = {
830 /* r_rate, vclk, hsp, vsp */ 670 /* r_rate, hsp, vsp */
831 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 671 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
832 {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP, 672 {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
833 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} } 673 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
834}; 674};
835 675
836/* 1600x900 (CVT Reduce Blanking) */ 676/* 1600x900 (CVT Reduce Blanking) */
837struct crt_mode_table CRTM1600x900_RB[] = { 677static struct crt_mode_table CRTM1600x900_RB[] = {
838 /* r_rate, vclk, hsp, vsp */ 678 /* r_rate, hsp, vsp */
839 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 679 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
840 {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP, 680 {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
841 M1600X900_RB_R60_VSP,
842 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} } 681 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
843}; 682};
844 683
845/* 1600x1024 (GTF) */ 684/* 1600x1024 (GTF) */
846struct crt_mode_table CRTM1600x1024[] = { 685static struct crt_mode_table CRTM1600x1024[] = {
847 /* r_rate, vclk, hsp, vsp */ 686 /* r_rate, hsp, vsp */
848 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 687 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
849 {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP, 688 {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
850 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} } 689 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
851}; 690};
852 691
853/* 1792x1344 (DMT) */ 692/* 1792x1344 (DMT) */
854struct crt_mode_table CRTM1792x1344[] = { 693static struct crt_mode_table CRTM1792x1344[] = {
855 /* r_rate, vclk, hsp, vsp */ 694 /* r_rate, hsp, vsp */
856 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 695 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
857 {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP, 696 {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
858 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} } 697 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
859}; 698};
860 699
861/* 1856x1392 (DMT) */ 700/* 1856x1392 (DMT) */
862struct crt_mode_table CRTM1856x1392[] = { 701static struct crt_mode_table CRTM1856x1392[] = {
863 /* r_rate, vclk, hsp, vsp */ 702 /* r_rate, hsp, vsp */
864 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 703 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
865 {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP, 704 {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
866 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} } 705 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
867}; 706};
868 707
869/* 1920x1200 (CVT) */ 708/* 1920x1200 (CVT) */
870struct crt_mode_table CRTM1920x1200[] = { 709static struct crt_mode_table CRTM1920x1200[] = {
871 /* r_rate, vclk, hsp, vsp */ 710 /* r_rate, hsp, vsp */
872 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 711 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
873 {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP, 712 {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
874 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} } 713 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
875}; 714};
876 715
877/* 1920x1200 (CVT with Reduce Blanking) */ 716/* 1920x1200 (CVT with Reduce Blanking) */
878struct crt_mode_table CRTM1920x1200_RB[] = { 717static struct crt_mode_table CRTM1920x1200_RB[] = {
879 /* r_rate, vclk, hsp, vsp */ 718 /* r_rate, hsp, vsp */
880 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 719 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
881 {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP, 720 {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
882 M1920X1200_RB_R60_VSP,
883 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} } 721 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
884}; 722};
885 723
886/* 2048x1536 (CVT) */ 724/* 2048x1536 (CVT) */
887struct crt_mode_table CRTM2048x1536[] = { 725static struct crt_mode_table CRTM2048x1536[] = {
888 /* r_rate, vclk, hsp, vsp */ 726 /* r_rate, hsp, vsp */
889 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 727 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
890 {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP, 728 {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
891 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} } 729 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
892}; 730};
893 731
894struct VideoModeTable viafb_modes[] = { 732static struct VideoModeTable viafb_modes[] = {
895 /* Display : 480x640 (GTF) */ 733 /* Display : 480x640 (GTF) */
896 {CRTM480x640, ARRAY_SIZE(CRTM480x640)}, 734 {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
897 735
@@ -1016,7 +854,7 @@ struct VideoModeTable viafb_modes[] = {
1016 {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)} 854 {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
1017}; 855};
1018 856
1019struct VideoModeTable viafb_rb_modes[] = { 857static struct VideoModeTable viafb_rb_modes[] = {
1020 /* Display : 1360x768 (CVT Reduce Blanking) */ 858 /* Display : 1360x768 (CVT Reduce Blanking) */
1021 {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)}, 859 {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
1022 860
@@ -1040,14 +878,12 @@ struct VideoModeTable viafb_rb_modes[] = {
1040}; 878};
1041 879
1042struct crt_mode_table CEAM1280x720[] = { 880struct crt_mode_table CEAM1280x720[] = {
1043 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP, 881 {REFRESH_60, M1280X720_CEA_R60_HSP, M1280X720_CEA_R60_VSP,
1044 M1280X720_CEA_R60_VSP,
1045 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 882 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
1046 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} } 883 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
1047}; 884};
1048struct crt_mode_table CEAM1920x1080[] = { 885struct crt_mode_table CEAM1920x1080[] = {
1049 {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP, 886 {REFRESH_60, M1920X1080_CEA_R60_HSP, M1920X1080_CEA_R60_VSP,
1050 M1920X1080_CEA_R60_VSP,
1051 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 887 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
1052 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} } 888 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
1053}; 889};
@@ -1057,7 +893,6 @@ struct VideoModeTable CEA_HDMI_Modes[] = {
1057 {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)} 893 {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
1058}; 894};
1059 895
1060int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl);
1061int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes); 896int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
1062int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs); 897int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
1063int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs); 898int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
index 5b1ced86514b..8a67ea1b5ef0 100644
--- a/drivers/video/via/viamode.h
+++ b/drivers/video/via/viamode.h
@@ -41,14 +41,6 @@ struct patch_table {
41 struct io_reg *io_reg_table; 41 struct io_reg *io_reg_table;
42}; 42};
43 43
44struct res_map_refresh {
45 int hres;
46 int vres;
47 int pixclock;
48 int vmode_refresh;
49};
50
51extern int NUM_TOTAL_RES_MAP_REFRESH;
52extern int NUM_TOTAL_CEA_MODES; 44extern int NUM_TOTAL_CEA_MODES;
53extern int NUM_TOTAL_CN400_ModeXregs; 45extern int NUM_TOTAL_CN400_ModeXregs;
54extern int NUM_TOTAL_CN700_ModeXregs; 46extern int NUM_TOTAL_CN700_ModeXregs;
@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[];
66extern struct crt_mode_table CEAM1920x1080[]; 58extern struct crt_mode_table CEAM1920x1080[];
67extern struct VideoModeTable CEA_HDMI_Modes[]; 59extern struct VideoModeTable CEA_HDMI_Modes[];
68 60
69extern struct res_map_refresh res_map_refresh_tbl[];
70extern struct io_reg CN400_ModeXregs[]; 61extern struct io_reg CN400_ModeXregs[];
71extern struct io_reg CN700_ModeXregs[]; 62extern struct io_reg CN700_ModeXregs[];
72extern struct io_reg KM400_ModeXregs[]; 63extern struct io_reg KM400_ModeXregs[];
diff --git a/drivers/video/via/vt1636.c b/drivers/video/via/vt1636.c
index 60e4192c2b34..ee2903b472cf 100644
--- a/drivers/video/via/vt1636.c
+++ b/drivers/video/via/vt1636.c
@@ -167,22 +167,6 @@ static int get_clk_range_index(u32 Clk)
167 return DPA_CLK_RANGE_150M; 167 return DPA_CLK_RANGE_150M;
168} 168}
169 169
170static int get_lvds_dpa_setting_index(int panel_size_id,
171 struct VT1636_DPA_SETTING *p_vt1636_dpasetting_tbl,
172 int tbl_size)
173{
174 int i;
175
176 for (i = 0; i < tbl_size; i++) {
177 if (panel_size_id == p_vt1636_dpasetting_tbl->PanelSizeID)
178 return i;
179
180 p_vt1636_dpasetting_tbl++;
181 }
182
183 return 0;
184}
185
186static void set_dpa_vt1636(struct lvds_setting_information 170static void set_dpa_vt1636(struct lvds_setting_information
187 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info, 171 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
188 struct VT1636_DPA_SETTING *p_vt1636_dpa_setting) 172 struct VT1636_DPA_SETTING *p_vt1636_dpa_setting)
@@ -206,7 +190,9 @@ void viafb_vt1636_patch_skew_on_vt3324(
206 struct lvds_setting_information *plvds_setting_info, 190 struct lvds_setting_information *plvds_setting_info,
207 struct lvds_chip_information *plvds_chip_info) 191 struct lvds_chip_information *plvds_chip_info)
208{ 192{
209 int index, size; 193 struct VT1636_DPA_SETTING dpa = {0x00, 0x00}, dpa_16x12 = {0x0B, 0x03},
194 *pdpa;
195 int index;
210 196
211 DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n"); 197 DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n");
212 198
@@ -216,19 +202,21 @@ void viafb_vt1636_patch_skew_on_vt3324(
216 &GFX_DPA_SETTING_TBL_VT3324[index]); 202 &GFX_DPA_SETTING_TBL_VT3324[index]);
217 203
218 /* LVDS Transmitter DPA settings: */ 204 /* LVDS Transmitter DPA settings: */
219 size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3324); 205 if (plvds_setting_info->lcd_panel_hres == 1600 &&
220 index = 206 plvds_setting_info->lcd_panel_vres == 1200)
221 get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id, 207 pdpa = &dpa_16x12;
222 VT1636_DPA_SETTING_TBL_VT3324, size); 208 else
223 set_dpa_vt1636(plvds_setting_info, plvds_chip_info, 209 pdpa = &dpa;
224 &VT1636_DPA_SETTING_TBL_VT3324[index]); 210
211 set_dpa_vt1636(plvds_setting_info, plvds_chip_info, pdpa);
225} 212}
226 213
227void viafb_vt1636_patch_skew_on_vt3327( 214void viafb_vt1636_patch_skew_on_vt3327(
228 struct lvds_setting_information *plvds_setting_info, 215 struct lvds_setting_information *plvds_setting_info,
229 struct lvds_chip_information *plvds_chip_info) 216 struct lvds_chip_information *plvds_chip_info)
230{ 217{
231 int index, size; 218 struct VT1636_DPA_SETTING dpa = {0x00, 0x00};
219 int index;
232 220
233 DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n"); 221 DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n");
234 222
@@ -238,12 +226,7 @@ void viafb_vt1636_patch_skew_on_vt3327(
238 &GFX_DPA_SETTING_TBL_VT3327[index]); 226 &GFX_DPA_SETTING_TBL_VT3327[index]);
239 227
240 /* LVDS Transmitter DPA settings: */ 228 /* LVDS Transmitter DPA settings: */
241 size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3327); 229 set_dpa_vt1636(plvds_setting_info, plvds_chip_info, &dpa);
242 index =
243 get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id,
244 VT1636_DPA_SETTING_TBL_VT3327, size);
245 set_dpa_vt1636(plvds_setting_info, plvds_chip_info,
246 &VT1636_DPA_SETTING_TBL_VT3327[index]);
247} 230}
248 231
249void viafb_vt1636_patch_skew_on_vt3364( 232void viafb_vt1636_patch_skew_on_vt3364(
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 10:11:37 -0500