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authorJoe Perches <joe@perches.com>2010-11-29 02:41:59 -0500
committerDavid S. Miller <davem@davemloft.net>2010-11-29 14:44:55 -0500
commitcd66328bdab782ee40d17b573a3067a591cb7b4f (patch)
treea3f619795b311c23ce467ec9848c076ccb2c5c83 /drivers
parentc41d41e1687dcf344f55dd15c7121532e5c195d4 (diff)
forcedeth: Separate vendor specific initializations into functions
Neaten the phy_init function by adding and calling vendor specific functions. object size is reduced by ~1kb: $ size drivers/net/forcedeth.o.* text data bss dec hex filename 83475 1848 19304 104627 198b3 drivers/net/forcedeth.o.new 84459 1848 19544 105851 19d7b drivers/net/forcedeth.o.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/forcedeth.c367
1 files changed, 188 insertions, 179 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 300748ccc5c1..0b1d562ec4a2 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -1198,21 +1198,179 @@ static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1198 int i; 1198 int i;
1199 1199
1200 for (i = 0; i < ARRAY_SIZE(ri); i++) { 1200 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1201 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) { 1201 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1202 netdev_info(dev, "%s: phy init failed\n", 1202 return PHY_ERROR;
1203 pci_name(np->pci_dev)); 1203 }
1204
1205 return 0;
1206}
1207
1208static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1209{
1210 u32 reg;
1211 u8 __iomem *base = get_hwbase(dev);
1212 u32 powerstate = readl(base + NvRegPowerState2);
1213
1214 /* need to perform hw phy reset */
1215 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1216 writel(powerstate, base + NvRegPowerState2);
1217 msleep(25);
1218
1219 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1220 writel(powerstate, base + NvRegPowerState2);
1221 msleep(25);
1222
1223 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1224 reg |= PHY_REALTEK_INIT9;
1225 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1226 return PHY_ERROR;
1227 if (mii_rw(dev, np->phyaddr,
1228 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1229 return PHY_ERROR;
1230 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1231 if (!(reg & PHY_REALTEK_INIT11)) {
1232 reg |= PHY_REALTEK_INIT11;
1233 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1234 return PHY_ERROR;
1235 }
1236 if (mii_rw(dev, np->phyaddr,
1237 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1238 return PHY_ERROR;
1239
1240 return 0;
1241}
1242
1243static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1244{
1245 u32 phy_reserved;
1246
1247 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1248 phy_reserved = mii_rw(dev, np->phyaddr,
1249 PHY_REALTEK_INIT_REG6, MII_READ);
1250 phy_reserved |= PHY_REALTEK_INIT7;
1251 if (mii_rw(dev, np->phyaddr,
1252 PHY_REALTEK_INIT_REG6, phy_reserved))
1204 return PHY_ERROR; 1253 return PHY_ERROR;
1205 }
1206 } 1254 }
1207 1255
1208 return 0; 1256 return 0;
1209} 1257}
1210 1258
1259static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1260{
1261 u32 phy_reserved;
1262
1263 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1264 if (mii_rw(dev, np->phyaddr,
1265 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1266 return PHY_ERROR;
1267 phy_reserved = mii_rw(dev, np->phyaddr,
1268 PHY_REALTEK_INIT_REG2, MII_READ);
1269 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1270 phy_reserved |= PHY_REALTEK_INIT3;
1271 if (mii_rw(dev, np->phyaddr,
1272 PHY_REALTEK_INIT_REG2, phy_reserved))
1273 return PHY_ERROR;
1274 if (mii_rw(dev, np->phyaddr,
1275 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1276 return PHY_ERROR;
1277 }
1278
1279 return 0;
1280}
1281
1282static int init_cicada(struct net_device *dev, struct fe_priv *np,
1283 u32 phyinterface)
1284{
1285 u32 phy_reserved;
1286
1287 if (phyinterface & PHY_RGMII) {
1288 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1289 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1290 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1291 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1292 return PHY_ERROR;
1293 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1294 phy_reserved |= PHY_CICADA_INIT5;
1295 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1296 return PHY_ERROR;
1297 }
1298 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1299 phy_reserved |= PHY_CICADA_INIT6;
1300 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1301 return PHY_ERROR;
1302
1303 return 0;
1304}
1305
1306static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1307{
1308 u32 phy_reserved;
1309
1310 if (mii_rw(dev, np->phyaddr,
1311 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1312 return PHY_ERROR;
1313 if (mii_rw(dev, np->phyaddr,
1314 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1315 return PHY_ERROR;
1316 phy_reserved = mii_rw(dev, np->phyaddr,
1317 PHY_VITESSE_INIT_REG4, MII_READ);
1318 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1319 return PHY_ERROR;
1320 phy_reserved = mii_rw(dev, np->phyaddr,
1321 PHY_VITESSE_INIT_REG3, MII_READ);
1322 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1323 phy_reserved |= PHY_VITESSE_INIT3;
1324 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1325 return PHY_ERROR;
1326 if (mii_rw(dev, np->phyaddr,
1327 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1328 return PHY_ERROR;
1329 if (mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1331 return PHY_ERROR;
1332 phy_reserved = mii_rw(dev, np->phyaddr,
1333 PHY_VITESSE_INIT_REG4, MII_READ);
1334 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1335 phy_reserved |= PHY_VITESSE_INIT3;
1336 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1337 return PHY_ERROR;
1338 phy_reserved = mii_rw(dev, np->phyaddr,
1339 PHY_VITESSE_INIT_REG3, MII_READ);
1340 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1341 return PHY_ERROR;
1342 if (mii_rw(dev, np->phyaddr,
1343 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1344 return PHY_ERROR;
1345 if (mii_rw(dev, np->phyaddr,
1346 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1347 return PHY_ERROR;
1348 phy_reserved = mii_rw(dev, np->phyaddr,
1349 PHY_VITESSE_INIT_REG4, MII_READ);
1350 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1351 return PHY_ERROR;
1352 phy_reserved = mii_rw(dev, np->phyaddr,
1353 PHY_VITESSE_INIT_REG3, MII_READ);
1354 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1355 phy_reserved |= PHY_VITESSE_INIT8;
1356 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1357 return PHY_ERROR;
1358 if (mii_rw(dev, np->phyaddr,
1359 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1360 return PHY_ERROR;
1361 if (mii_rw(dev, np->phyaddr,
1362 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1363 return PHY_ERROR;
1364
1365 return 0;
1366}
1367
1211static int phy_init(struct net_device *dev) 1368static int phy_init(struct net_device *dev)
1212{ 1369{
1213 struct fe_priv *np = get_nvpriv(dev); 1370 struct fe_priv *np = get_nvpriv(dev);
1214 u8 __iomem *base = get_hwbase(dev); 1371 u8 __iomem *base = get_hwbase(dev);
1215 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000, reg; 1372 u32 phyinterface;
1373 u32 mii_status, mii_control, mii_control_1000, reg;
1216 1374
1217 /* phy errata for E3016 phy */ 1375 /* phy errata for E3016 phy */
1218 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { 1376 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
@@ -1227,64 +1385,32 @@ static int phy_init(struct net_device *dev)
1227 if (np->phy_oui == PHY_OUI_REALTEK) { 1385 if (np->phy_oui == PHY_OUI_REALTEK) {
1228 if (np->phy_model == PHY_MODEL_REALTEK_8211 && 1386 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1229 np->phy_rev == PHY_REV_REALTEK_8211B) { 1387 np->phy_rev == PHY_REV_REALTEK_8211B) {
1230 if (init_realtek_8211b(dev, np)) 1388 if (init_realtek_8211b(dev, np)) {
1231 return PHY_ERROR;
1232 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1233 np->phy_rev == PHY_REV_REALTEK_8211C) {
1234 u32 powerstate = readl(base + NvRegPowerState2);
1235
1236 /* need to perform hw phy reset */
1237 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1238 writel(powerstate, base + NvRegPowerState2);
1239 msleep(25);
1240
1241 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1242 writel(powerstate, base + NvRegPowerState2);
1243 msleep(25);
1244
1245 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1246 reg |= PHY_REALTEK_INIT9;
1247 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1248 netdev_info(dev, "%s: phy init failed\n", 1389 netdev_info(dev, "%s: phy init failed\n",
1249 pci_name(np->pci_dev)); 1390 pci_name(np->pci_dev));
1250 return PHY_ERROR; 1391 return PHY_ERROR;
1251 } 1392 }
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { 1393 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1394 np->phy_rev == PHY_REV_REALTEK_8211C) {
1395 if (init_realtek_8211c(dev, np)) {
1253 netdev_info(dev, "%s: phy init failed\n", 1396 netdev_info(dev, "%s: phy init failed\n",
1254 pci_name(np->pci_dev)); 1397 pci_name(np->pci_dev));
1255 return PHY_ERROR; 1398 return PHY_ERROR;
1256 } 1399 }
1257 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); 1400 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1258 if (!(reg & PHY_REALTEK_INIT11)) { 1401 if (init_realtek_8201(dev, np)) {
1259 reg |= PHY_REALTEK_INIT11;
1260 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1261 netdev_info(dev, "%s: phy init failed\n",
1262 pci_name(np->pci_dev));
1263 return PHY_ERROR;
1264 }
1265 }
1266 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1267 netdev_info(dev, "%s: phy init failed\n", 1402 netdev_info(dev, "%s: phy init failed\n",
1268 pci_name(np->pci_dev)); 1403 pci_name(np->pci_dev));
1269 return PHY_ERROR; 1404 return PHY_ERROR;
1270 } 1405 }
1271 } 1406 }
1272 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1273 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1274 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1275 phy_reserved |= PHY_REALTEK_INIT7;
1276 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1277 netdev_info(dev, "%s: phy init failed\n",
1278 pci_name(np->pci_dev));
1279 return PHY_ERROR;
1280 }
1281 }
1282 }
1283 } 1407 }
1284 1408
1285 /* set advertise register */ 1409 /* set advertise register */
1286 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); 1410 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1287 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); 1411 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1412 ADVERTISE_100HALF | ADVERTISE_100FULL |
1413 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1288 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { 1414 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1289 netdev_info(dev, "%s: phy write to advertise failed\n", 1415 netdev_info(dev, "%s: phy write to advertise failed\n",
1290 pci_name(np->pci_dev)); 1416 pci_name(np->pci_dev));
@@ -1298,7 +1424,8 @@ static int phy_init(struct net_device *dev)
1298 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); 1424 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1299 if (mii_status & PHY_GIGABIT) { 1425 if (mii_status & PHY_GIGABIT) {
1300 np->gigabit = PHY_GIGABIT; 1426 np->gigabit = PHY_GIGABIT;
1301 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); 1427 mii_control_1000 = mii_rw(dev, np->phyaddr,
1428 MII_CTRL1000, MII_READ);
1302 mii_control_1000 &= ~ADVERTISE_1000HALF; 1429 mii_control_1000 &= ~ADVERTISE_1000HALF;
1303 if (phyinterface & PHY_RGMII) 1430 if (phyinterface & PHY_RGMII)
1304 mii_control_1000 |= ADVERTISE_1000FULL; 1431 mii_control_1000 |= ADVERTISE_1000FULL;
@@ -1338,151 +1465,33 @@ static int phy_init(struct net_device *dev)
1338 } 1465 }
1339 1466
1340 /* phy vendor specific configuration */ 1467 /* phy vendor specific configuration */
1341 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) { 1468 if ((np->phy_oui == PHY_OUI_CICADA)) {
1342 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); 1469 if (init_cicada(dev, np, phyinterface)) {
1343 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1344 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1345 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1346 netdev_info(dev, "%s: phy init failed\n",
1347 pci_name(np->pci_dev));
1348 return PHY_ERROR;
1349 }
1350 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1351 phy_reserved |= PHY_CICADA_INIT5;
1352 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1353 netdev_info(dev, "%s: phy init failed\n",
1354 pci_name(np->pci_dev));
1355 return PHY_ERROR;
1356 }
1357 }
1358 if (np->phy_oui == PHY_OUI_CICADA) {
1359 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1360 phy_reserved |= PHY_CICADA_INIT6;
1361 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1362 netdev_info(dev, "%s: phy init failed\n",
1363 pci_name(np->pci_dev));
1364 return PHY_ERROR;
1365 }
1366 }
1367 if (np->phy_oui == PHY_OUI_VITESSE) {
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1369 netdev_info(dev, "%s: phy init failed\n",
1370 pci_name(np->pci_dev));
1371 return PHY_ERROR;
1372 }
1373 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1374 netdev_info(dev, "%s: phy init failed\n",
1375 pci_name(np->pci_dev));
1376 return PHY_ERROR;
1377 }
1378 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1379 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1380 netdev_info(dev, "%s: phy init failed\n",
1381 pci_name(np->pci_dev));
1382 return PHY_ERROR;
1383 }
1384 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1385 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1386 phy_reserved |= PHY_VITESSE_INIT3;
1387 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1388 netdev_info(dev, "%s: phy init failed\n",
1389 pci_name(np->pci_dev));
1390 return PHY_ERROR;
1391 }
1392 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1393 netdev_info(dev, "%s: phy init failed\n",
1394 pci_name(np->pci_dev));
1395 return PHY_ERROR;
1396 }
1397 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1398 netdev_info(dev, "%s: phy init failed\n", 1470 netdev_info(dev, "%s: phy init failed\n",
1399 pci_name(np->pci_dev)); 1471 pci_name(np->pci_dev));
1400 return PHY_ERROR; 1472 return PHY_ERROR;
1401 } 1473 }
1402 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); 1474 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1403 phy_reserved &= ~PHY_VITESSE_INIT_MSK1; 1475 if (init_vitesse(dev, np)) {
1404 phy_reserved |= PHY_VITESSE_INIT3;
1405 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1406 netdev_info(dev, "%s: phy init failed\n", 1476 netdev_info(dev, "%s: phy init failed\n",
1407 pci_name(np->pci_dev)); 1477 pci_name(np->pci_dev));
1408 return PHY_ERROR; 1478 return PHY_ERROR;
1409 } 1479 }
1410 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); 1480 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1411 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1412 netdev_info(dev, "%s: phy init failed\n",
1413 pci_name(np->pci_dev));
1414 return PHY_ERROR;
1415 }
1416 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1417 netdev_info(dev, "%s: phy init failed\n",
1418 pci_name(np->pci_dev));
1419 return PHY_ERROR;
1420 }
1421 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1422 netdev_info(dev, "%s: phy init failed\n",
1423 pci_name(np->pci_dev));
1424 return PHY_ERROR;
1425 }
1426 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1427 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1428 netdev_info(dev, "%s: phy init failed\n",
1429 pci_name(np->pci_dev));
1430 return PHY_ERROR;
1431 }
1432 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1433 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1434 phy_reserved |= PHY_VITESSE_INIT8;
1435 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1436 netdev_info(dev, "%s: phy init failed\n",
1437 pci_name(np->pci_dev));
1438 return PHY_ERROR;
1439 }
1440 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1441 netdev_info(dev, "%s: phy init failed\n",
1442 pci_name(np->pci_dev));
1443 return PHY_ERROR;
1444 }
1445 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1446 netdev_info(dev, "%s: phy init failed\n",
1447 pci_name(np->pci_dev));
1448 return PHY_ERROR;
1449 }
1450 }
1451 if (np->phy_oui == PHY_OUI_REALTEK) {
1452 if (np->phy_model == PHY_MODEL_REALTEK_8211 && 1481 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1453 np->phy_rev == PHY_REV_REALTEK_8211B) { 1482 np->phy_rev == PHY_REV_REALTEK_8211B) {
1454 /* reset could have cleared these out, set them back */ 1483 /* reset could have cleared these out, set them back */
1455 if (init_realtek_8211b(dev, np)) 1484 if (init_realtek_8211b(dev, np)) {
1485 netdev_info(dev, "%s: phy init failed\n",
1486 pci_name(np->pci_dev));
1456 return PHY_ERROR; 1487 return PHY_ERROR;
1457 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1458 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1459 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1460 phy_reserved |= PHY_REALTEK_INIT7;
1461 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1462 netdev_info(dev, "%s: phy init failed\n",
1463 pci_name(np->pci_dev));
1464 return PHY_ERROR;
1465 }
1466 } 1488 }
1467 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { 1489 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1468 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { 1490 if (init_realtek_8201(dev, np) ||
1469 netdev_info(dev, "%s: phy init failed\n", 1491 init_realtek_8201_cross(dev, np)) {
1470 pci_name(np->pci_dev)); 1492 netdev_info(dev, "%s: phy init failed\n",
1471 return PHY_ERROR; 1493 pci_name(np->pci_dev));
1472 } 1494 return PHY_ERROR;
1473 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1474 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1475 phy_reserved |= PHY_REALTEK_INIT3;
1476 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1477 netdev_info(dev, "%s: phy init failed\n",
1478 pci_name(np->pci_dev));
1479 return PHY_ERROR;
1480 }
1481 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1482 netdev_info(dev, "%s: phy init failed\n",
1483 pci_name(np->pci_dev));
1484 return PHY_ERROR;
1485 }
1486 } 1495 }
1487 } 1496 }
1488 } 1497 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 00:59:29 -0500