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authorLinus Torvalds <torvalds@linux-foundation.org>2010-06-08 22:48:50 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-06-08 22:48:50 -0400
commitf5c98a40947af7e8226fff584151c9ce6eaed03b (patch)
tree94ce8f5c4188c0cb831d25cd208803f0b6f213bc /drivers
parentfbe33a7c3f388f7b8b2642bfadb1b5914f635a5b (diff)
parentb62e948fd00bda1be2af31b591e5284374de551f (diff)
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (23 commits) drm/radeon: don't poll tv dac if crtc2 is in use. drm/radeon: reset i2c valid to avoid incorrect tv-out polling. drm/nv50: fix iommu errors caused by device reading from address 0 drm/nouveau: off by one in init_i2c_device_find() nouveau: off by one in nv50_gpio_location() drm/nouveau: completely fail init if we fail to map the PRAMIN BAR drm/nouveau: match U/DP script against SOR link drm/radeon/kms/pm: resurrect printing power states drm/radeon/kms: add trivial debugging for voltage drm/radeon/kms/r600+: use voltage from requested clock mode (v3) drm/radeon/kms/pm: track current voltage (v2) drm/radeon/kms/pm: Disable voltage adjust on RS780/RS880 drm/radeon/kms: fix typo in printing the HPD info drm/radeon/kms/pm: add mid profile drm/radeon/kms/pm: Misc fixes drm/radeon/kms/combios: fix typo in voltage fix drm/radeon/kms/evergreen: set accel_enabled drm/vmwgfx: return -EFAULT for copy_to_user errors drm/drm_crtc: return -EFAULT on copy_to_user errors drm/fb: use printk to print out the switching to text mode error. ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/drm_crtc.c4
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c2
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c19
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c25
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c19
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fb.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv50_gpio.c2
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c20
-rw-r--r--drivers/gpu/drm/radeon/r100.c10
-rw-r--r--drivers/gpu/drm/radeon/r420.c12
-rw-r--r--drivers/gpu/drm/radeon/r600.c111
-rw-r--r--drivers/gpu/drm/radeon/radeon.h12
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c95
-rw-r--r--drivers/gpu/drm/radeon/rv770.c18
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c1
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c8
27 files changed, 339 insertions, 105 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 994d23beeb1d..57cea01c4ffb 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1840,8 +1840,10 @@ int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
1840 1840
1841 ret = copy_from_user(clips, clips_ptr, 1841 ret = copy_from_user(clips, clips_ptr,
1842 num_clips * sizeof(*clips)); 1842 num_clips * sizeof(*clips));
1843 if (ret) 1843 if (ret) {
1844 ret = -EFAULT;
1844 goto out_err2; 1845 goto out_err2;
1846 }
1845 } 1847 }
1846 1848
1847 if (fb->funcs->dirty) { 1849 if (fb->funcs->dirty) {
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index b3779d243aef..08c4c926e65f 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -264,7 +264,7 @@ bool drm_fb_helper_force_kernel_mode(void)
264int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed, 264int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed,
265 void *panic_str) 265 void *panic_str)
266{ 266{
267 DRM_ERROR("panic occurred, switching back to text console\n"); 267 printk(KERN_ERR "panic occurred, switching back to text console\n");
268 return drm_fb_helper_force_kernel_mode(); 268 return drm_fb_helper_force_kernel_mode();
269 return 0; 269 return 0;
270} 270}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index b2ebf02e4f8a..59a2bf8592ec 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1402,19 +1402,19 @@ static int i915_load_modeset_init(struct drm_device *dev,
1402 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1402 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1403 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); 1403 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1404 if (ret) 1404 if (ret)
1405 goto destroy_ringbuffer; 1405 goto cleanup_ringbuffer;
1406 1406
1407 ret = vga_switcheroo_register_client(dev->pdev, 1407 ret = vga_switcheroo_register_client(dev->pdev,
1408 i915_switcheroo_set_state, 1408 i915_switcheroo_set_state,
1409 i915_switcheroo_can_switch); 1409 i915_switcheroo_can_switch);
1410 if (ret) 1410 if (ret)
1411 goto destroy_ringbuffer; 1411 goto cleanup_vga_client;
1412 1412
1413 intel_modeset_init(dev); 1413 intel_modeset_init(dev);
1414 1414
1415 ret = drm_irq_install(dev); 1415 ret = drm_irq_install(dev);
1416 if (ret) 1416 if (ret)
1417 goto destroy_ringbuffer; 1417 goto cleanup_vga_switcheroo;
1418 1418
1419 /* Always safe in the mode setting case. */ 1419 /* Always safe in the mode setting case. */
1420 /* FIXME: do pre/post-mode set stuff in core KMS code */ 1420 /* FIXME: do pre/post-mode set stuff in core KMS code */
@@ -1426,11 +1426,20 @@ static int i915_load_modeset_init(struct drm_device *dev,
1426 1426
1427 I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); 1427 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1428 1428
1429 intel_fbdev_init(dev); 1429 ret = intel_fbdev_init(dev);
1430 if (ret)
1431 goto cleanup_irq;
1432
1430 drm_kms_helper_poll_init(dev); 1433 drm_kms_helper_poll_init(dev);
1431 return 0; 1434 return 0;
1432 1435
1433destroy_ringbuffer: 1436cleanup_irq:
1437 drm_irq_uninstall(dev);
1438cleanup_vga_switcheroo:
1439 vga_switcheroo_unregister_client(dev->pdev);
1440cleanup_vga_client:
1441 vga_client_register(dev->pdev, NULL, NULL, NULL);
1442cleanup_ringbuffer:
1434 mutex_lock(&dev->struct_mutex); 1443 mutex_lock(&dev->struct_mutex);
1435 i915_gem_cleanup_ringbuffer(dev); 1444 i915_gem_cleanup_ringbuffer(dev);
1436 mutex_unlock(&dev->struct_mutex); 1445 mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9ed8ecd95801..276583159847 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -278,6 +278,7 @@ typedef struct drm_i915_private {
278 struct mem_block *agp_heap; 278 struct mem_block *agp_heap;
279 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 279 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
280 int vblank_pipe; 280 int vblank_pipe;
281 int num_pipe;
281 282
282 /* For hangcheck timer */ 283 /* For hangcheck timer */
283#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ 284#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 04e1bb499ff8..2861da3aaf7e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5470,7 +5470,6 @@ static void intel_init_display(struct drm_device *dev)
5470void intel_modeset_init(struct drm_device *dev) 5470void intel_modeset_init(struct drm_device *dev)
5471{ 5471{
5472 struct drm_i915_private *dev_priv = dev->dev_private; 5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 int num_pipe;
5474 int i; 5473 int i;
5475 5474
5476 drm_mode_config_init(dev); 5475 drm_mode_config_init(dev);
@@ -5500,13 +5499,13 @@ void intel_modeset_init(struct drm_device *dev)
5500 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); 5499 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5501 5500
5502 if (IS_MOBILE(dev) || IS_I9XX(dev)) 5501 if (IS_MOBILE(dev) || IS_I9XX(dev))
5503 num_pipe = 2; 5502 dev_priv->num_pipe = 2;
5504 else 5503 else
5505 num_pipe = 1; 5504 dev_priv->num_pipe = 1;
5506 DRM_DEBUG_KMS("%d display pipe%s available.\n", 5505 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5507 num_pipe, num_pipe > 1 ? "s" : ""); 5506 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5508 5507
5509 for (i = 0; i < num_pipe; i++) { 5508 for (i = 0; i < dev_priv->num_pipe; i++) {
5510 intel_crtc_init(dev, i); 5509 intel_crtc_init(dev, i);
5511 } 5510 }
5512 5511
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index f8c76e64bb77..c3c505244e07 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -245,6 +245,7 @@ int intel_fbdev_init(struct drm_device *dev)
245{ 245{
246 struct intel_fbdev *ifbdev; 246 struct intel_fbdev *ifbdev;
247 drm_i915_private_t *dev_priv = dev->dev_private; 247 drm_i915_private_t *dev_priv = dev->dev_private;
248 int ret;
248 249
249 ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); 250 ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
250 if (!ifbdev) 251 if (!ifbdev)
@@ -253,8 +254,13 @@ int intel_fbdev_init(struct drm_device *dev)
253 dev_priv->fbdev = ifbdev; 254 dev_priv->fbdev = ifbdev;
254 ifbdev->helper.funcs = &intel_fb_helper_funcs; 255 ifbdev->helper.funcs = &intel_fb_helper_funcs;
255 256
256 drm_fb_helper_init(dev, &ifbdev->helper, 2, 257 ret = drm_fb_helper_init(dev, &ifbdev->helper,
257 INTELFB_CONN_LIMIT); 258 dev_priv->num_pipe,
259 INTELFB_CONN_LIMIT);
260 if (ret) {
261 kfree(ifbdev);
262 return ret;
263 }
258 264
259 drm_fb_helper_single_add_all_connectors(&ifbdev->helper); 265 drm_fb_helper_single_add_all_connectors(&ifbdev->helper);
260 drm_fb_helper_initial_config(&ifbdev->helper, 32); 266 drm_fb_helper_initial_config(&ifbdev->helper, 32);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 9ba2deaadcc7..fc924b649195 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -834,7 +834,7 @@ init_i2c_device_find(struct drm_device *dev, int i2c_index)
834 if (i2c_index == 0x81) 834 if (i2c_index == 0x81)
835 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 835 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
836 836
837 if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) { 837 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
838 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 838 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
839 return NULL; 839 return NULL;
840 } 840 }
@@ -3920,7 +3920,8 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
3920 3920
3921static uint8_t * 3921static uint8_t *
3922bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 3922bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3923 uint16_t record, int record_len, int record_nr) 3923 uint16_t record, int record_len, int record_nr,
3924 bool match_link)
3924{ 3925{
3925 struct drm_nouveau_private *dev_priv = dev->dev_private; 3926 struct drm_nouveau_private *dev_priv = dev->dev_private;
3926 struct nvbios *bios = &dev_priv->vbios; 3927 struct nvbios *bios = &dev_priv->vbios;
@@ -3928,12 +3929,28 @@ bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3928 uint16_t table; 3929 uint16_t table;
3929 int i, v; 3930 int i, v;
3930 3931
3932 switch (dcbent->type) {
3933 case OUTPUT_TMDS:
3934 case OUTPUT_LVDS:
3935 case OUTPUT_DP:
3936 break;
3937 default:
3938 match_link = false;
3939 break;
3940 }
3941
3931 for (i = 0; i < record_nr; i++, record += record_len) { 3942 for (i = 0; i < record_nr; i++, record += record_len) {
3932 table = ROM16(bios->data[record]); 3943 table = ROM16(bios->data[record]);
3933 if (!table) 3944 if (!table)
3934 continue; 3945 continue;
3935 entry = ROM32(bios->data[table]); 3946 entry = ROM32(bios->data[table]);
3936 3947
3948 if (match_link) {
3949 v = (entry & 0x00c00000) >> 22;
3950 if (!(v & dcbent->sorconf.link))
3951 continue;
3952 }
3953
3937 v = (entry & 0x000f0000) >> 16; 3954 v = (entry & 0x000f0000) >> 16;
3938 if (!(v & dcbent->or)) 3955 if (!(v & dcbent->or))
3939 continue; 3956 continue;
@@ -3975,7 +3992,7 @@ nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3975 *length = table[4]; 3992 *length = table[4];
3976 return bios_output_config_match(dev, dcbent, 3993 return bios_output_config_match(dev, dcbent,
3977 bios->display.dp_table_ptr + table[1], 3994 bios->display.dp_table_ptr + table[1],
3978 table[2], table[3]); 3995 table[2], table[3], table[0] >= 0x21);
3979} 3996}
3980 3997
3981int 3998int
@@ -4064,7 +4081,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4064 dcbent->type, dcbent->location, dcbent->or); 4081 dcbent->type, dcbent->location, dcbent->or);
4065 otable = bios_output_config_match(dev, dcbent, table[1] + 4082 otable = bios_output_config_match(dev, dcbent, table[1] +
4066 bios->display.script_table_ptr, 4083 bios->display.script_table_ptr,
4067 table[2], table[3]); 4084 table[2], table[3], table[0] >= 0x21);
4068 if (!otable) { 4085 if (!otable) {
4069 NV_ERROR(dev, "Couldn't find matching output script table\n"); 4086 NV_ERROR(dev, "Couldn't find matching output script table\n");
4070 return 1; 4087 return 1;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index fd4a2df715e9..c9a4a0d2a115 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -377,6 +377,7 @@ int nouveau_fbcon_init(struct drm_device *dev)
377{ 377{
378 struct drm_nouveau_private *dev_priv = dev->dev_private; 378 struct drm_nouveau_private *dev_priv = dev->dev_private;
379 struct nouveau_fbdev *nfbdev; 379 struct nouveau_fbdev *nfbdev;
380 int ret;
380 381
381 nfbdev = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL); 382 nfbdev = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL);
382 if (!nfbdev) 383 if (!nfbdev)
@@ -386,7 +387,12 @@ int nouveau_fbcon_init(struct drm_device *dev)
386 dev_priv->nfbdev = nfbdev; 387 dev_priv->nfbdev = nfbdev;
387 nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs; 388 nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
388 389
389 drm_fb_helper_init(dev, &nfbdev->helper, 2, 4); 390 ret = drm_fb_helper_init(dev, &nfbdev->helper, 2, 4);
391 if (ret) {
392 kfree(nfbdev);
393 return ret;
394 }
395
390 drm_fb_helper_single_add_all_connectors(&nfbdev->helper); 396 drm_fb_helper_single_add_all_connectors(&nfbdev->helper);
391 drm_fb_helper_initial_config(&nfbdev->helper, 32); 397 drm_fb_helper_initial_config(&nfbdev->helper, 32);
392 return 0; 398 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 147e59c40151..b02a231d6937 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -779,29 +779,24 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
779 return ret; 779 return ret;
780 } 780 }
781 781
782 /* map larger RAMIN aperture on NV40 cards */ 782 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
783 dev_priv->ramin = NULL;
784 if (dev_priv->card_type >= NV_40) { 783 if (dev_priv->card_type >= NV_40) {
785 int ramin_bar = 2; 784 int ramin_bar = 2;
786 if (pci_resource_len(dev->pdev, ramin_bar) == 0) 785 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
787 ramin_bar = 3; 786 ramin_bar = 3;
788 787
789 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar); 788 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
790 dev_priv->ramin = ioremap( 789 dev_priv->ramin =
791 pci_resource_start(dev->pdev, ramin_bar), 790 ioremap(pci_resource_start(dev->pdev, ramin_bar),
792 dev_priv->ramin_size); 791 dev_priv->ramin_size);
793 if (!dev_priv->ramin) { 792 if (!dev_priv->ramin) {
794 NV_ERROR(dev, "Failed to init RAMIN mapping, " 793 NV_ERROR(dev, "Failed to PRAMIN BAR");
795 "limited instance memory available\n"); 794 return -ENOMEM;
796 } 795 }
797 } 796 } else {
798
799 /* On older cards (or if the above failed), create a map covering
800 * the BAR0 PRAMIN aperture */
801 if (!dev_priv->ramin) {
802 dev_priv->ramin_size = 1 * 1024 * 1024; 797 dev_priv->ramin_size = 1 * 1024 * 1024;
803 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN, 798 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
804 dev_priv->ramin_size); 799 dev_priv->ramin_size);
805 if (!dev_priv->ramin) { 800 if (!dev_priv->ramin) {
806 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); 801 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
807 return -ENOMEM; 802 return -ENOMEM;
diff --git a/drivers/gpu/drm/nouveau/nv50_fb.c b/drivers/gpu/drm/nouveau/nv50_fb.c
index a95e6941ba88..32611bd30e6d 100644
--- a/drivers/gpu/drm/nouveau/nv50_fb.c
+++ b/drivers/gpu/drm/nouveau/nv50_fb.c
@@ -6,10 +6,16 @@
6int 6int
7nv50_fb_init(struct drm_device *dev) 7nv50_fb_init(struct drm_device *dev)
8{ 8{
9 /* This is needed to get meaningful information from 100c90
10 * on traps. No idea what these values mean exactly. */
11 struct drm_nouveau_private *dev_priv = dev->dev_private; 9 struct drm_nouveau_private *dev_priv = dev->dev_private;
12 10
11 /* Not a clue what this is exactly. Without pointing it at a
12 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
13 * cause IOMMU "read from address 0" errors (rh#561267)
14 */
15 nv_wr32(dev, 0x100c08, dev_priv->gart_info.sg_dummy_bus >> 8);
16
17 /* This is needed to get meaningful information from 100c90
18 * on traps. No idea what these values mean exactly. */
13 switch (dev_priv->chipset) { 19 switch (dev_priv->chipset) {
14 case 0x50: 20 case 0x50:
15 nv_wr32(dev, 0x100c90, 0x0707ff); 21 nv_wr32(dev, 0x100c90, 0x0707ff);
diff --git a/drivers/gpu/drm/nouveau/nv50_gpio.c b/drivers/gpu/drm/nouveau/nv50_gpio.c
index c61782b314e7..bb47ad737267 100644
--- a/drivers/gpu/drm/nouveau/nv50_gpio.c
+++ b/drivers/gpu/drm/nouveau/nv50_gpio.c
@@ -31,7 +31,7 @@ nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
31{ 31{
32 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 32 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
33 33
34 if (gpio->line > 32) 34 if (gpio->line >= 32)
35 return -EINVAL; 35 return -EINVAL;
36 36
37 *reg = nv50_gpio_reg[gpio->line >> 3]; 37 *reg = nv50_gpio_reg[gpio->line >> 3];
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 0440c0939bdd..4b6623df3b96 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -41,12 +41,18 @@ void evergreen_fini(struct radeon_device *rdev);
41 41
42void evergreen_pm_misc(struct radeon_device *rdev) 42void evergreen_pm_misc(struct radeon_device *rdev)
43{ 43{
44 int requested_index = rdev->pm.requested_power_state_index; 44 int req_ps_idx = rdev->pm.requested_power_state_index;
45 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 45 int req_cm_idx = rdev->pm.requested_clock_mode_index;
46 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 46 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
47 47 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
48 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) 48
49 radeon_atom_set_voltage(rdev, voltage->voltage); 49 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
50 if (voltage->voltage != rdev->pm.current_vddc) {
51 radeon_atom_set_voltage(rdev, voltage->voltage);
52 rdev->pm.current_vddc = voltage->voltage;
53 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
54 }
55 }
50} 56}
51 57
52void evergreen_pm_prepare(struct radeon_device *rdev) 58void evergreen_pm_prepare(struct radeon_device *rdev)
@@ -2153,7 +2159,7 @@ int evergreen_init(struct radeon_device *rdev)
2153 if (r) 2159 if (r)
2154 return r; 2160 return r;
2155 2161
2156 rdev->accel_working = false; 2162 rdev->accel_working = true;
2157 r = evergreen_startup(rdev); 2163 r = evergreen_startup(rdev);
2158 if (r) { 2164 if (r) {
2159 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2165 dev_err(rdev->dev, "disabling GPU acceleration\n");
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index cc004b05d63e..cf89aa2eb28c 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -162,6 +162,11 @@ void r100_pm_init_profile(struct radeon_device *rdev)
162 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 162 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
163 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 163 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
164 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 164 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
165 /* mid sh */
166 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
167 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
168 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
169 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
165 /* high sh */ 170 /* high sh */
166 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 171 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
167 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 172 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
@@ -172,6 +177,11 @@ void r100_pm_init_profile(struct radeon_device *rdev)
172 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 177 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
173 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 178 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
174 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 179 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
180 /* mid mh */
181 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
182 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
183 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
184 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
175 /* high mh */ 185 /* high mh */
176 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 186 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
177 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 187 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 4415a5ee5871..e6c89142bb4d 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -45,9 +45,14 @@ void r420_pm_init_profile(struct radeon_device *rdev)
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
46 /* low sh */ 46 /* low sh */
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
51 /* mid sh */
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
51 /* high sh */ 56 /* high sh */
52 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
@@ -58,6 +63,11 @@ void r420_pm_init_profile(struct radeon_device *rdev)
58 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
60 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
66 /* mid mh */
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
61 /* high mh */ 71 /* high mh */
62 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index e14f59748e65..0e91871f45be 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -291,6 +291,11 @@ void rs780_pm_init_profile(struct radeon_device *rdev)
291 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 291 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
294 /* mid sh */
295 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
294 /* high sh */ 299 /* high sh */
295 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 300 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 301 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
@@ -301,6 +306,11 @@ void rs780_pm_init_profile(struct radeon_device *rdev)
301 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 306 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 307 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
309 /* mid mh */
310 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
304 /* high mh */ 314 /* high mh */
305 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 315 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 316 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
@@ -317,6 +327,11 @@ void rs780_pm_init_profile(struct radeon_device *rdev)
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 327 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
330 /* mid sh */
331 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
332 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
333 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
320 /* high sh */ 335 /* high sh */
321 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 336 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
322 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 337 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
@@ -327,6 +342,11 @@ void rs780_pm_init_profile(struct radeon_device *rdev)
327 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 342 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 344 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
345 /* mid mh */
346 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
330 /* high mh */ 350 /* high mh */
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 351 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 352 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
@@ -343,6 +363,11 @@ void rs780_pm_init_profile(struct radeon_device *rdev)
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 363 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
344 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 364 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 365 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
366 /* mid sh */
367 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
368 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
369 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
370 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
346 /* high sh */ 371 /* high sh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 372 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 373 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
@@ -353,6 +378,11 @@ void rs780_pm_init_profile(struct radeon_device *rdev)
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 378 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 379 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 380 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
381 /* mid mh */
382 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
356 /* high mh */ 386 /* high mh */
357 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 387 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
358 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 388 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
@@ -375,6 +405,11 @@ void r600_pm_init_profile(struct radeon_device *rdev)
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 405 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 406 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
377 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 407 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
408 /* mid sh */
409 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
410 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
411 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
378 /* high sh */ 413 /* high sh */
379 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 414 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
380 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 415 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
@@ -385,6 +420,11 @@ void r600_pm_init_profile(struct radeon_device *rdev)
385 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 420 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
386 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 421 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 422 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
423 /* mid mh */
424 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
426 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
427 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
388 /* high mh */ 428 /* high mh */
389 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 429 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
390 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 430 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
@@ -401,7 +441,12 @@ void r600_pm_init_profile(struct radeon_device *rdev)
401 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 441 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
402 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 442 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
403 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 443 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 1; 444 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
445 /* mid sh */
446 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
447 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
448 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
405 /* high sh */ 450 /* high sh */
406 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 451 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
407 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 452 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
@@ -411,7 +456,12 @@ void r600_pm_init_profile(struct radeon_device *rdev)
411 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 456 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
412 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 457 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
413 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 458 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
414 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 1; 459 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
460 /* low mh */
461 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
462 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
463 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
464 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
415 /* high mh */ 465 /* high mh */
416 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 466 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 467 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
@@ -430,14 +480,30 @@ void r600_pm_init_profile(struct radeon_device *rdev)
430 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 480 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
431 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 481 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
432 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 482 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
433 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 1; 483 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
434 } else { 484 } else {
435 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 485 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
436 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 486 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
437 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 487 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
438 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 488 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
439 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 489 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 1; 490 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
491 }
492 /* mid sh */
493 if (rdev->flags & RADEON_IS_MOBILITY) {
494 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
495 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
496 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
497 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
500 } else {
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
502 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
503 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
504 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
441 } 507 }
442 /* high sh */ 508 /* high sh */
443 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 509 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
@@ -453,14 +519,30 @@ void r600_pm_init_profile(struct radeon_device *rdev)
453 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 519 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
454 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 520 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
455 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 521 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
456 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 2; 522 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
457 } else { 523 } else {
458 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 524 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
459 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 525 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
460 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 526 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
461 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 527 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
462 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 528 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
463 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 1; 529 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
530 }
531 /* mid mh */
532 if (rdev->flags & RADEON_IS_MOBILITY) {
533 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
534 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
535 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
536 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
537 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
539 } else {
540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
541 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
542 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
543 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
464 } 546 }
465 /* high mh */ 547 /* high mh */
466 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 548 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
@@ -475,13 +557,18 @@ void r600_pm_init_profile(struct radeon_device *rdev)
475 557
476void r600_pm_misc(struct radeon_device *rdev) 558void r600_pm_misc(struct radeon_device *rdev)
477{ 559{
478 int requested_index = rdev->pm.requested_power_state_index; 560 int req_ps_idx = rdev->pm.requested_power_state_index;
479 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 561 int req_cm_idx = rdev->pm.requested_clock_mode_index;
480 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 562 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
481 563 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
482 if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
483 radeon_atom_set_voltage(rdev, voltage->voltage);
484 564
565 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
566 if (voltage->voltage != rdev->pm.current_vddc) {
567 radeon_atom_set_voltage(rdev, voltage->voltage);
568 rdev->pm.current_vddc = voltage->voltage;
569 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
570 }
571 }
485} 572}
486 573
487bool r600_gui_idle(struct radeon_device *rdev) 574bool r600_gui_idle(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5f96fe871b3f..8e1d44ca26ec 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -648,15 +648,18 @@ enum radeon_pm_profile_type {
648 PM_PROFILE_DEFAULT, 648 PM_PROFILE_DEFAULT,
649 PM_PROFILE_AUTO, 649 PM_PROFILE_AUTO,
650 PM_PROFILE_LOW, 650 PM_PROFILE_LOW,
651 PM_PROFILE_MID,
651 PM_PROFILE_HIGH, 652 PM_PROFILE_HIGH,
652}; 653};
653 654
654#define PM_PROFILE_DEFAULT_IDX 0 655#define PM_PROFILE_DEFAULT_IDX 0
655#define PM_PROFILE_LOW_SH_IDX 1 656#define PM_PROFILE_LOW_SH_IDX 1
656#define PM_PROFILE_HIGH_SH_IDX 2 657#define PM_PROFILE_MID_SH_IDX 2
657#define PM_PROFILE_LOW_MH_IDX 3 658#define PM_PROFILE_HIGH_SH_IDX 3
658#define PM_PROFILE_HIGH_MH_IDX 4 659#define PM_PROFILE_LOW_MH_IDX 4
659#define PM_PROFILE_MAX 5 660#define PM_PROFILE_MID_MH_IDX 5
661#define PM_PROFILE_HIGH_MH_IDX 6
662#define PM_PROFILE_MAX 7
660 663
661struct radeon_pm_profile { 664struct radeon_pm_profile {
662 int dpms_off_ps_idx; 665 int dpms_off_ps_idx;
@@ -745,6 +748,7 @@ struct radeon_pm {
745 int default_power_state_index; 748 int default_power_state_index;
746 u32 current_sclk; 749 u32 current_sclk;
747 u32 current_mclk; 750 u32 current_mclk;
751 u32 current_vddc;
748 struct radeon_i2c_chan *i2c_bus; 752 struct radeon_i2c_chan *i2c_bus;
749 /* selected pm method */ 753 /* selected pm method */
750 enum radeon_pm_method pm_method; 754 enum radeon_pm_method pm_method;
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 4305cd55d0ac..99bd8a9c56b3 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1833,10 +1833,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1833 /* skip invalid modes */ 1833 /* skip invalid modes */
1834 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 1834 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1835 continue; 1835 continue;
1836 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 1836 /* voltage works differently on IGPs */
1837 VOLTAGE_SW;
1838 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1839 clock_info->usVDDC;
1840 mode_index++; 1837 mode_index++;
1841 } else if (ASIC_IS_DCE4(rdev)) { 1838 } else if (ASIC_IS_DCE4(rdev)) {
1842 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info = 1839 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
@@ -1969,6 +1966,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1969 1966
1970 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1967 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1971 rdev->pm.current_clock_mode_index = 0; 1968 rdev->pm.current_clock_mode_index = 0;
1969 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1972} 1970}
1973 1971
1974void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 1972void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 102c744eaf5a..1bee2f9e24a5 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -2026,6 +2026,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2026 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 2026 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2027 break; 2027 break;
2028 default: 2028 default:
2029 ddc_i2c.valid = false;
2029 break; 2030 break;
2030 } 2031 }
2031 2032
@@ -2339,6 +2340,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2339 if (RBIOS8(tv_info + 6) == 'T') { 2340 if (RBIOS8(tv_info + 6) == 'T') {
2340 if (radeon_apply_legacy_tv_quirks(dev)) { 2341 if (radeon_apply_legacy_tv_quirks(dev)) {
2341 hpd.hpd = RADEON_HPD_NONE; 2342 hpd.hpd = RADEON_HPD_NONE;
2343 ddc_i2c.valid = false;
2342 radeon_add_legacy_encoder(dev, 2344 radeon_add_legacy_encoder(dev,
2343 radeon_get_encoder_id 2345 radeon_get_encoder_id
2344 (dev, 2346 (dev,
@@ -2455,7 +2457,7 @@ default_mode:
2455 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2457 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2456 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2458 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2457 if ((state_index > 0) && 2459 if ((state_index > 0) &&
2458 (rdev->pm.power_state[0].clock_info[0].voltage.type = VOLTAGE_GPIO)) 2460 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2459 rdev->pm.power_state[state_index].clock_info[0].voltage = 2461 rdev->pm.power_state[state_index].clock_info[0].voltage =
2460 rdev->pm.power_state[0].clock_info[0].voltage; 2462 rdev->pm.power_state[0].clock_info[0].voltage;
2461 else 2463 else
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 1006549d1570..8154cdf796e4 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -284,8 +284,7 @@ static const char *connector_names[15] = {
284 "eDP", 284 "eDP",
285}; 285};
286 286
287static const char *hpd_names[7] = { 287static const char *hpd_names[6] = {
288 "NONE",
289 "HPD1", 288 "HPD1",
290 "HPD2", 289 "HPD2",
291 "HPD3", 290 "HPD3",
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 902d1731a652..e166fe4d7c30 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -45,9 +45,10 @@
45 * - 2.2.0 - add r6xx/r7xx const buffer support 45 * - 2.2.0 - add r6xx/r7xx const buffer support
46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
47 * - 2.4.0 - add crtc id query 47 * - 2.4.0 - add crtc id query
48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
48 */ 49 */
49#define KMS_DRIVER_MAJOR 2 50#define KMS_DRIVER_MAJOR 2
50#define KMS_DRIVER_MINOR 4 51#define KMS_DRIVER_MINOR 5
51#define KMS_DRIVER_PATCHLEVEL 0 52#define KMS_DRIVER_PATCHLEVEL 0
52int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 53int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
53int radeon_driver_unload_kms(struct drm_device *dev); 54int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index e192acfbf0cd..dc1634bb0c11 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -363,6 +363,7 @@ int radeon_fbdev_init(struct radeon_device *rdev)
363{ 363{
364 struct radeon_fbdev *rfbdev; 364 struct radeon_fbdev *rfbdev;
365 int bpp_sel = 32; 365 int bpp_sel = 32;
366 int ret;
366 367
367 /* select 8 bpp console on RN50 or 16MB cards */ 368 /* select 8 bpp console on RN50 or 16MB cards */
368 if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) 369 if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
@@ -376,9 +377,14 @@ int radeon_fbdev_init(struct radeon_device *rdev)
376 rdev->mode_info.rfbdev = rfbdev; 377 rdev->mode_info.rfbdev = rfbdev;
377 rfbdev->helper.funcs = &radeon_fb_helper_funcs; 378 rfbdev->helper.funcs = &radeon_fb_helper_funcs;
378 379
379 drm_fb_helper_init(rdev->ddev, &rfbdev->helper, 380 ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
380 rdev->num_crtc, 381 rdev->num_crtc,
381 RADEONFB_CONN_LIMIT); 382 RADEONFB_CONN_LIMIT);
383 if (ret) {
384 kfree(rfbdev);
385 return ret;
386 }
387
382 drm_fb_helper_single_add_all_connectors(&rfbdev->helper); 388 drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
383 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); 389 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
384 return 0; 390 return 0;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 04068352ccd2..6a70c0dc7f92 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -118,7 +118,11 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
118 value = rdev->num_z_pipes; 118 value = rdev->num_z_pipes;
119 break; 119 break;
120 case RADEON_INFO_ACCEL_WORKING: 120 case RADEON_INFO_ACCEL_WORKING:
121 value = rdev->accel_working; 121 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
122 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
123 value = false;
124 else
125 value = rdev->accel_working;
122 break; 126 break;
123 case RADEON_INFO_CRTC_FROM_ID: 127 case RADEON_INFO_CRTC_FROM_ID:
124 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 128 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
@@ -134,6 +138,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
134 return -EINVAL; 138 return -EINVAL;
135 } 139 }
136 break; 140 break;
141 case RADEON_INFO_ACCEL_WORKING2:
142 value = rdev->accel_working;
143 break;
137 default: 144 default:
138 DRM_DEBUG("Invalid request %d\n", info->request); 145 DRM_DEBUG("Invalid request %d\n", info->request);
139 return -EINVAL; 146 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 5a13b3eeef19..5b07b8848e09 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -1168,6 +1168,17 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
1168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1169 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1169 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1170 bool color = true; 1170 bool color = true;
1171 struct drm_crtc *crtc;
1172
1173 /* find out if crtc2 is in use or if this encoder is using it */
1174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1175 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1176 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1177 if (encoder->crtc != crtc) {
1178 return connector_status_disconnected;
1179 }
1180 }
1181 }
1171 1182
1172 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || 1183 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1173 connector->connector_type == DRM_MODE_CONNECTOR_Composite || 1184 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 02281269a881..63f679a04b25 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -33,6 +33,14 @@
33#define RADEON_WAIT_VBLANK_TIMEOUT 200 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
34#define RADEON_WAIT_IDLE_TIMEOUT 200 34#define RADEON_WAIT_IDLE_TIMEOUT 200
35 35
36static const char *radeon_pm_state_type_name[5] = {
37 "Default",
38 "Powersave",
39 "Battery",
40 "Balanced",
41 "Performance",
42};
43
36static void radeon_dynpm_idle_work_handler(struct work_struct *work); 44static void radeon_dynpm_idle_work_handler(struct work_struct *work);
37static int radeon_debugfs_pm_init(struct radeon_device *rdev); 45static int radeon_debugfs_pm_init(struct radeon_device *rdev);
38static bool radeon_pm_in_vbl(struct radeon_device *rdev); 46static bool radeon_pm_in_vbl(struct radeon_device *rdev);
@@ -84,9 +92,9 @@ static void radeon_pm_update_profile(struct radeon_device *rdev)
84 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 92 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
85 } else { 93 } else {
86 if (rdev->pm.active_crtc_count > 1) 94 if (rdev->pm.active_crtc_count > 1)
87 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 95 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
88 else 96 else
89 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 97 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
90 } 98 }
91 break; 99 break;
92 case PM_PROFILE_LOW: 100 case PM_PROFILE_LOW:
@@ -95,6 +103,12 @@ static void radeon_pm_update_profile(struct radeon_device *rdev)
95 else 103 else
96 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 104 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
97 break; 105 break;
106 case PM_PROFILE_MID:
107 if (rdev->pm.active_crtc_count > 1)
108 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
109 else
110 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
111 break;
98 case PM_PROFILE_HIGH: 112 case PM_PROFILE_HIGH:
99 if (rdev->pm.active_crtc_count > 1) 113 if (rdev->pm.active_crtc_count > 1)
100 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 114 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
@@ -127,15 +141,6 @@ static void radeon_unmap_vram_bos(struct radeon_device *rdev)
127 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 141 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
128 ttm_bo_unmap_virtual(&bo->tbo); 142 ttm_bo_unmap_virtual(&bo->tbo);
129 } 143 }
130
131 if (rdev->gart.table.vram.robj)
132 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
133
134 if (rdev->stollen_vga_memory)
135 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
136
137 if (rdev->r600_blit.shader_obj)
138 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
139} 144}
140 145
141static void radeon_sync_with_vblank(struct radeon_device *rdev) 146static void radeon_sync_with_vblank(struct radeon_device *rdev)
@@ -281,6 +286,42 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
281 mutex_unlock(&rdev->ddev->struct_mutex); 286 mutex_unlock(&rdev->ddev->struct_mutex);
282} 287}
283 288
289static void radeon_pm_print_states(struct radeon_device *rdev)
290{
291 int i, j;
292 struct radeon_power_state *power_state;
293 struct radeon_pm_clock_info *clock_info;
294
295 DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states);
296 for (i = 0; i < rdev->pm.num_power_states; i++) {
297 power_state = &rdev->pm.power_state[i];
298 DRM_DEBUG("State %d: %s\n", i,
299 radeon_pm_state_type_name[power_state->type]);
300 if (i == rdev->pm.default_power_state_index)
301 DRM_DEBUG("\tDefault");
302 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
303 DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes);
304 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
305 DRM_DEBUG("\tSingle display only\n");
306 DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
307 for (j = 0; j < power_state->num_clock_modes; j++) {
308 clock_info = &(power_state->clock_info[j]);
309 if (rdev->flags & RADEON_IS_IGP)
310 DRM_DEBUG("\t\t%d e: %d%s\n",
311 j,
312 clock_info->sclk * 10,
313 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
314 else
315 DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n",
316 j,
317 clock_info->sclk * 10,
318 clock_info->mclk * 10,
319 clock_info->voltage.voltage,
320 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
321 }
322 }
323}
324
284static ssize_t radeon_get_pm_profile(struct device *dev, 325static ssize_t radeon_get_pm_profile(struct device *dev,
285 struct device_attribute *attr, 326 struct device_attribute *attr,
286 char *buf) 327 char *buf)
@@ -311,6 +352,8 @@ static ssize_t radeon_set_pm_profile(struct device *dev,
311 rdev->pm.profile = PM_PROFILE_AUTO; 352 rdev->pm.profile = PM_PROFILE_AUTO;
312 else if (strncmp("low", buf, strlen("low")) == 0) 353 else if (strncmp("low", buf, strlen("low")) == 0)
313 rdev->pm.profile = PM_PROFILE_LOW; 354 rdev->pm.profile = PM_PROFILE_LOW;
355 else if (strncmp("mid", buf, strlen("mid")) == 0)
356 rdev->pm.profile = PM_PROFILE_MID;
314 else if (strncmp("high", buf, strlen("high")) == 0) 357 else if (strncmp("high", buf, strlen("high")) == 0)
315 rdev->pm.profile = PM_PROFILE_HIGH; 358 rdev->pm.profile = PM_PROFILE_HIGH;
316 else { 359 else {
@@ -377,15 +420,19 @@ void radeon_pm_suspend(struct radeon_device *rdev)
377{ 420{
378 mutex_lock(&rdev->pm.mutex); 421 mutex_lock(&rdev->pm.mutex);
379 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 422 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
380 rdev->pm.current_power_state_index = -1;
381 rdev->pm.current_clock_mode_index = -1;
382 rdev->pm.current_sclk = 0;
383 rdev->pm.current_mclk = 0;
384 mutex_unlock(&rdev->pm.mutex); 423 mutex_unlock(&rdev->pm.mutex);
385} 424}
386 425
387void radeon_pm_resume(struct radeon_device *rdev) 426void radeon_pm_resume(struct radeon_device *rdev)
388{ 427{
428 /* asic init will reset the default power state */
429 mutex_lock(&rdev->pm.mutex);
430 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
431 rdev->pm.current_clock_mode_index = 0;
432 rdev->pm.current_sclk = rdev->clock.default_sclk;
433 rdev->pm.current_mclk = rdev->clock.default_mclk;
434 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
435 mutex_unlock(&rdev->pm.mutex);
389 radeon_pm_compute_clocks(rdev); 436 radeon_pm_compute_clocks(rdev);
390} 437}
391 438
@@ -394,32 +441,24 @@ int radeon_pm_init(struct radeon_device *rdev)
394 int ret; 441 int ret;
395 /* default to profile method */ 442 /* default to profile method */
396 rdev->pm.pm_method = PM_METHOD_PROFILE; 443 rdev->pm.pm_method = PM_METHOD_PROFILE;
444 rdev->pm.profile = PM_PROFILE_DEFAULT;
397 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 445 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
398 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 446 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
399 rdev->pm.dynpm_can_upclock = true; 447 rdev->pm.dynpm_can_upclock = true;
400 rdev->pm.dynpm_can_downclock = true; 448 rdev->pm.dynpm_can_downclock = true;
401 rdev->pm.current_sclk = 0; 449 rdev->pm.current_sclk = rdev->clock.default_sclk;
402 rdev->pm.current_mclk = 0; 450 rdev->pm.current_mclk = rdev->clock.default_mclk;
403 451
404 if (rdev->bios) { 452 if (rdev->bios) {
405 if (rdev->is_atom_bios) 453 if (rdev->is_atom_bios)
406 radeon_atombios_get_power_modes(rdev); 454 radeon_atombios_get_power_modes(rdev);
407 else 455 else
408 radeon_combios_get_power_modes(rdev); 456 radeon_combios_get_power_modes(rdev);
457 radeon_pm_print_states(rdev);
409 radeon_pm_init_profile(rdev); 458 radeon_pm_init_profile(rdev);
410 rdev->pm.current_power_state_index = -1;
411 rdev->pm.current_clock_mode_index = -1;
412 } 459 }
413 460
414 if (rdev->pm.num_power_states > 1) { 461 if (rdev->pm.num_power_states > 1) {
415 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
416 mutex_lock(&rdev->pm.mutex);
417 rdev->pm.profile = PM_PROFILE_DEFAULT;
418 radeon_pm_update_profile(rdev);
419 radeon_pm_set_clocks(rdev);
420 mutex_unlock(&rdev->pm.mutex);
421 }
422
423 /* where's the best place to put these? */ 462 /* where's the best place to put these? */
424 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 463 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
425 if (ret) 464 if (ret)
@@ -705,6 +744,8 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
705 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); 744 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
706 if (rdev->asic->get_memory_clock) 745 if (rdev->asic->get_memory_clock)
707 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 746 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
747 if (rdev->pm.current_vddc)
748 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
708 if (rdev->asic->get_pcie_lanes) 749 if (rdev->asic->get_pcie_lanes)
709 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 750 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
710 751
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 33952da65340..cec536c222c5 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -44,12 +44,18 @@ void rv770_fini(struct radeon_device *rdev);
44 44
45void rv770_pm_misc(struct radeon_device *rdev) 45void rv770_pm_misc(struct radeon_device *rdev)
46{ 46{
47 int requested_index = rdev->pm.requested_power_state_index; 47 int req_ps_idx = rdev->pm.requested_power_state_index;
48 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 48 int req_cm_idx = rdev->pm.requested_clock_mode_index;
49 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 49 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
50 50 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
51 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) 51
52 radeon_atom_set_voltage(rdev, voltage->voltage); 52 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
53 if (voltage->voltage != rdev->pm.current_vddc) {
54 radeon_atom_set_voltage(rdev, voltage->voltage);
55 rdev->pm.current_vddc = voltage->voltage;
56 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
57 }
58 }
53} 59}
54 60
55/* 61/*
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index bdd67cf83315..8e396850513c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -644,6 +644,7 @@ int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
644 ret = copy_from_user(cmd, user_cmd, arg->command_size); 644 ret = copy_from_user(cmd, user_cmd, arg->command_size);
645 645
646 if (unlikely(ret != 0)) { 646 if (unlikely(ret != 0)) {
647 ret = -EFAULT;
647 DRM_ERROR("Failed copying commands.\n"); 648 DRM_ERROR("Failed copying commands.\n");
648 goto out_commit; 649 goto out_commit;
649 } 650 }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index f8fbbc67a406..8612378b131e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -597,8 +597,10 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
597 597
598 ret = copy_from_user(srf->sizes, user_sizes, 598 ret = copy_from_user(srf->sizes, user_sizes,
599 srf->num_sizes * sizeof(*srf->sizes)); 599 srf->num_sizes * sizeof(*srf->sizes));
600 if (unlikely(ret != 0)) 600 if (unlikely(ret != 0)) {
601 ret = -EFAULT;
601 goto out_err1; 602 goto out_err1;
603 }
602 604
603 if (srf->scanout && 605 if (srf->scanout &&
604 srf->num_sizes == 1 && 606 srf->num_sizes == 1 &&
@@ -697,9 +699,11 @@ int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
697 if (user_sizes) 699 if (user_sizes)
698 ret = copy_to_user(user_sizes, srf->sizes, 700 ret = copy_to_user(user_sizes, srf->sizes,
699 srf->num_sizes * sizeof(*srf->sizes)); 701 srf->num_sizes * sizeof(*srf->sizes));
700 if (unlikely(ret != 0)) 702 if (unlikely(ret != 0)) {
701 DRM_ERROR("copy_to_user failed %p %u\n", 703 DRM_ERROR("copy_to_user failed %p %u\n",
702 user_sizes, srf->num_sizes); 704 user_sizes, srf->num_sizes);
705 ret = -EFAULT;
706 }
703out_bad_resource: 707out_bad_resource:
704out_no_reference: 708out_no_reference:
705 ttm_base_object_unref(&base); 709 ttm_base_object_unref(&base);