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authorLinus Torvalds <torvalds@linux-foundation.org>2008-05-14 16:31:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-05-14 16:31:25 -0400
commit4717df58304b60ac26cdb157d57f39ae1e3a336f (patch)
tree9cf37756aca53f79702a90b062369d60c7c97eff /drivers
parentfc99824c427ed998e3c5e376bd9c640fde1c407c (diff)
parentc2b7bbea83b239b1877f3cafe0cdcbbd08e65648 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb
* git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb: (70 commits) V4L/DVB (7900): pvrusb: Fix Kconfig if DVB=m V4L_core=y V4L/DVB (7899): Fixes a few remaining Kbuild issues at common/tuners V4L/DVB (7898): Fix VIDEO_MEDIA Kconfig logic V4L/DVB (7895): tveeprom: update Hauppauge analog audio and video decoders V4L/DVB (7893): xc5000: bug-fix: allow multiple devices in a single system V4L/DVB (7891): cx18/ivtv: fix open() kernel oops V4L/DVB (7890): cx18: removed bogus and confusing conditional V4L/DVB (7889): cx18: improve HVR-1600 detection. V4L/DVB (7888): cx18: minor card definition updates. V4L/DVB (7887): cx18: fix Compro H900 analog support. V4L/DVB (7881): saa7134: fixed a compile warning in saa7134-core.c V4L/DVB (7880): saa7134: remove explicit GPIO initialization V4L/DVB(7879): Adding cx18 Support for mxl5005s V4L/DVB(7878): mxl55005s: Makefile and Kconfig additions V4L/DVB(7877): mxl5005s: Ensure debug is off V4L/DVB(7876): mxl5005s: Remove incorrect copyright holders V4L/DVB(7875): mxl5005s: Remove redundant functions V4L/DVB(7874): mxl5005s: Fix function statics V4L/DVB(7873): mxl5005s: Fix header includes. V4L/DVB(7872): mxl5005s: checkpatch.pl compliance ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/Kconfig3
-rw-r--r--drivers/media/common/tuners/Kconfig50
-rw-r--r--drivers/media/common/tuners/Makefile1
-rw-r--r--drivers/media/common/tuners/mxl5005s.c4110
-rw-r--r--drivers/media/common/tuners/mxl5005s.h131
-rw-r--r--drivers/media/common/tuners/tda18271-common.c24
-rw-r--r--drivers/media/common/tuners/tda18271-fe.c168
-rw-r--r--drivers/media/common/tuners/tda18271-priv.h9
-rw-r--r--drivers/media/common/tuners/tea5767.c6
-rw-r--r--drivers/media/common/tuners/xc5000.c9
-rw-r--r--drivers/media/common/tuners/xc5000.h22
-rw-r--r--drivers/media/common/tuners/xc5000_priv.h2
-rw-r--r--drivers/media/dvb/b2c2/flexcop-fe-tuner.c2
-rw-r--r--drivers/media/dvb/bt8xx/Kconfig1
-rw-r--r--drivers/media/dvb/cinergyT2/Kconfig2
-rw-r--r--drivers/media/dvb/dvb-core/dvb_ca_en50221.c28
-rw-r--r--drivers/media/dvb/dvb-usb/Kconfig1
-rw-r--r--drivers/media/dvb/frontends/Kconfig18
-rw-r--r--drivers/media/dvb/frontends/itd1000.c2
-rw-r--r--drivers/media/dvb/frontends/mt312.c9
-rw-r--r--drivers/media/dvb/frontends/mt312.h4
-rw-r--r--drivers/media/dvb/ttpci/Kconfig2
-rw-r--r--drivers/media/dvb/ttusb-dec/Kconfig1
-rw-r--r--drivers/media/video/Kconfig10
-rw-r--r--drivers/media/video/Makefile2
-rw-r--r--drivers/media/video/au0828/Kconfig3
-rw-r--r--drivers/media/video/au0828/au0828-dvb.c6
-rw-r--r--drivers/media/video/bt8xx/Kconfig3
-rw-r--r--drivers/media/video/cx18/Kconfig5
-rw-r--r--drivers/media/video/cx18/cx18-cards.c25
-rw-r--r--drivers/media/video/cx18/cx18-cards.h5
-rw-r--r--drivers/media/video/cx18/cx18-driver.c29
-rw-r--r--drivers/media/video/cx18/cx18-driver.h3
-rw-r--r--drivers/media/video/cx18/cx18-dvb.c40
-rw-r--r--drivers/media/video/cx18/cx18-fileops.c6
-rw-r--r--drivers/media/video/cx18/cx18-fileops.h9
-rw-r--r--drivers/media/video/cx18/cx18-gpio.c47
-rw-r--r--drivers/media/video/cx18/cx18-i2c.c1
-rw-r--r--drivers/media/video/cx18/cx18-queue.c22
-rw-r--r--drivers/media/video/cx18/cx18-queue.h4
-rw-r--r--drivers/media/video/cx18/cx18-streams.c13
-rw-r--r--drivers/media/video/cx18/cx18-streams.h2
-rw-r--r--drivers/media/video/cx23885/Kconfig6
-rw-r--r--drivers/media/video/cx23885/cx23885-cards.c36
-rw-r--r--drivers/media/video/cx23885/cx23885-dvb.c7
-rw-r--r--drivers/media/video/cx25840/Kconfig1
-rw-r--r--drivers/media/video/cx88/Kconfig6
-rw-r--r--drivers/media/video/cx88/cx88-dvb.c253
-rw-r--r--drivers/media/video/em28xx/Kconfig3
-rw-r--r--drivers/media/video/em28xx/em28xx-cards.c8
-rw-r--r--drivers/media/video/em28xx/em28xx-dvb.c1
-rw-r--r--drivers/media/video/ivtv/Kconfig4
-rw-r--r--drivers/media/video/ivtv/ivtv-controls.c4
-rw-r--r--drivers/media/video/ivtv/ivtv-driver.c8
-rw-r--r--drivers/media/video/ivtv/ivtv-fileops.c2
-rw-r--r--drivers/media/video/ivtv/ivtv-ioctl.c16
-rw-r--r--drivers/media/video/ivtv/ivtv-ioctl.h6
-rw-r--r--drivers/media/video/ivtv/ivtv-queue.c12
-rw-r--r--drivers/media/video/ivtv/ivtv-streams.c13
-rw-r--r--drivers/media/video/ivtv/ivtv-streams.h2
-rw-r--r--drivers/media/video/ivtv/ivtv-vbi.c3
-rw-r--r--drivers/media/video/ivtv/ivtv-yuv.c2
-rw-r--r--drivers/media/video/ivtv/ivtvfb.c6
-rw-r--r--drivers/media/video/mt9m001.c5
-rw-r--r--drivers/media/video/mt9v022.c7
-rw-r--r--drivers/media/video/pvrusb2/Kconfig4
-rw-r--r--drivers/media/video/saa7134/Kconfig3
-rw-r--r--drivers/media/video/saa7134/saa7134-core.c6
-rw-r--r--drivers/media/video/saa7134/saa7134-dvb.c140
-rw-r--r--drivers/media/video/stk-webcam.c7
-rw-r--r--drivers/media/video/tuner-core.c38
-rw-r--r--drivers/media/video/tveeprom.c10
-rw-r--r--drivers/media/video/usbvision/Kconfig2
73 files changed, 4965 insertions, 496 deletions
diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig
index ddf57e135c6c..7a7803b5d497 100644
--- a/drivers/media/Kconfig
+++ b/drivers/media/Kconfig
@@ -89,8 +89,7 @@ config DVB_CORE
89 89
90config VIDEO_MEDIA 90config VIDEO_MEDIA
91 tristate 91 tristate
92 default DVB_CORE || VIDEO_DEV 92 default (DVB_CORE && (VIDEO_DEV = n)) || (VIDEO_DEV && (DVB_CORE = n)) || (DVB_CORE && VIDEO_DEV)
93 depends on DVB_CORE || VIDEO_DEV
94 93
95comment "Multimedia drivers" 94comment "Multimedia drivers"
96 95
diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig
index 5be85ff53e12..d6206540476b 100644
--- a/drivers/media/common/tuners/Kconfig
+++ b/drivers/media/common/tuners/Kconfig
@@ -1,6 +1,6 @@
1config MEDIA_ATTACH 1config MEDIA_ATTACH
2 bool "Load and attach frontend and tuner driver modules as needed" 2 bool "Load and attach frontend and tuner driver modules as needed"
3 depends on DVB_CORE 3 depends on VIDEO_MEDIA
4 depends on MODULES 4 depends on MODULES
5 help 5 help
6 Remove the static dependency of DVB card drivers on all 6 Remove the static dependency of DVB card drivers on all
@@ -19,10 +19,10 @@ config MEDIA_ATTACH
19 19
20config MEDIA_TUNER 20config MEDIA_TUNER
21 tristate 21 tristate
22 default DVB_CORE || VIDEO_DEV 22 default VIDEO_MEDIA && I2C
23 depends on DVB_CORE || VIDEO_DEV 23 depends on VIDEO_MEDIA && I2C
24 select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE 24 select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG
25 select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE 25 select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG
26 select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE 26 select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE
27 select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE 27 select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE
28 select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMIZE 28 select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMIZE
@@ -46,7 +46,7 @@ if MEDIA_TUNER_CUSTOMIZE
46 46
47config MEDIA_TUNER_SIMPLE 47config MEDIA_TUNER_SIMPLE
48 tristate "Simple tuner support" 48 tristate "Simple tuner support"
49 depends on I2C 49 depends on VIDEO_MEDIA && I2C
50 select MEDIA_TUNER_TDA9887 50 select MEDIA_TUNER_TDA9887
51 default m if MEDIA_TUNER_CUSTOMIZE 51 default m if MEDIA_TUNER_CUSTOMIZE
52 help 52 help
@@ -54,7 +54,7 @@ config MEDIA_TUNER_SIMPLE
54 54
55config MEDIA_TUNER_TDA8290 55config MEDIA_TUNER_TDA8290
56 tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo" 56 tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo"
57 depends on I2C 57 depends on VIDEO_MEDIA && I2C
58 select MEDIA_TUNER_TDA827X 58 select MEDIA_TUNER_TDA827X
59 select MEDIA_TUNER_TDA18271 59 select MEDIA_TUNER_TDA18271
60 default m if MEDIA_TUNER_CUSTOMIZE 60 default m if MEDIA_TUNER_CUSTOMIZE
@@ -63,21 +63,21 @@ config MEDIA_TUNER_TDA8290
63 63
64config MEDIA_TUNER_TDA827X 64config MEDIA_TUNER_TDA827X
65 tristate "Philips TDA827X silicon tuner" 65 tristate "Philips TDA827X silicon tuner"
66 depends on DVB_CORE && I2C 66 depends on VIDEO_MEDIA && I2C
67 default m if DVB_FE_CUSTOMISE 67 default m if DVB_FE_CUSTOMISE
68 help 68 help
69 A DVB-T silicon tuner module. Say Y when you want to support this tuner. 69 A DVB-T silicon tuner module. Say Y when you want to support this tuner.
70 70
71config MEDIA_TUNER_TDA18271 71config MEDIA_TUNER_TDA18271
72 tristate "NXP TDA18271 silicon tuner" 72 tristate "NXP TDA18271 silicon tuner"
73 depends on I2C 73 depends on VIDEO_MEDIA && I2C
74 default m if DVB_FE_CUSTOMISE 74 default m if DVB_FE_CUSTOMISE
75 help 75 help
76 A silicon tuner module. Say Y when you want to support this tuner. 76 A silicon tuner module. Say Y when you want to support this tuner.
77 77
78config MEDIA_TUNER_TDA9887 78config MEDIA_TUNER_TDA9887
79 tristate "TDA 9885/6/7 analog IF demodulator" 79 tristate "TDA 9885/6/7 analog IF demodulator"
80 depends on I2C 80 depends on VIDEO_MEDIA && I2C
81 default m if MEDIA_TUNER_CUSTOMIZE 81 default m if MEDIA_TUNER_CUSTOMIZE
82 help 82 help
83 Say Y here to include support for Philips TDA9885/6/7 83 Say Y here to include support for Philips TDA9885/6/7
@@ -85,67 +85,79 @@ config MEDIA_TUNER_TDA9887
85 85
86config MEDIA_TUNER_TEA5761 86config MEDIA_TUNER_TEA5761
87 tristate "TEA 5761 radio tuner (EXPERIMENTAL)" 87 tristate "TEA 5761 radio tuner (EXPERIMENTAL)"
88 depends on I2C && EXPERIMENTAL 88 depends on VIDEO_MEDIA && I2C
89 depends on EXPERIMENTAL
89 default m if MEDIA_TUNER_CUSTOMIZE 90 default m if MEDIA_TUNER_CUSTOMIZE
90 help 91 help
91 Say Y here to include support for the Philips TEA5761 radio tuner. 92 Say Y here to include support for the Philips TEA5761 radio tuner.
92 93
93config MEDIA_TUNER_TEA5767 94config MEDIA_TUNER_TEA5767
94 tristate "TEA 5767 radio tuner" 95 tristate "TEA 5767 radio tuner"
95 depends on I2C 96 depends on VIDEO_MEDIA && I2C
96 default m if MEDIA_TUNER_CUSTOMIZE 97 default m if MEDIA_TUNER_CUSTOMIZE
97 help 98 help
98 Say Y here to include support for the Philips TEA5767 radio tuner. 99 Say Y here to include support for the Philips TEA5767 radio tuner.
99 100
100config MEDIA_TUNER_MT20XX 101config MEDIA_TUNER_MT20XX
101 tristate "Microtune 2032 / 2050 tuners" 102 tristate "Microtune 2032 / 2050 tuners"
102 depends on I2C 103 depends on VIDEO_MEDIA && I2C
103 default m if MEDIA_TUNER_CUSTOMIZE 104 default m if MEDIA_TUNER_CUSTOMIZE
104 help 105 help
105 Say Y here to include support for the MT2032 / MT2050 tuner. 106 Say Y here to include support for the MT2032 / MT2050 tuner.
106 107
107config MEDIA_TUNER_MT2060 108config MEDIA_TUNER_MT2060
108 tristate "Microtune MT2060 silicon IF tuner" 109 tristate "Microtune MT2060 silicon IF tuner"
109 depends on I2C 110 depends on VIDEO_MEDIA && I2C
110 default m if DVB_FE_CUSTOMISE 111 default m if DVB_FE_CUSTOMISE
111 help 112 help
112 A driver for the silicon IF tuner MT2060 from Microtune. 113 A driver for the silicon IF tuner MT2060 from Microtune.
113 114
114config MEDIA_TUNER_MT2266 115config MEDIA_TUNER_MT2266
115 tristate "Microtune MT2266 silicon tuner" 116 tristate "Microtune MT2266 silicon tuner"
116 depends on I2C 117 depends on VIDEO_MEDIA && I2C
117 default m if DVB_FE_CUSTOMISE 118 default m if DVB_FE_CUSTOMISE
118 help 119 help
119 A driver for the silicon baseband tuner MT2266 from Microtune. 120 A driver for the silicon baseband tuner MT2266 from Microtune.
120 121
121config MEDIA_TUNER_MT2131 122config MEDIA_TUNER_MT2131
122 tristate "Microtune MT2131 silicon tuner" 123 tristate "Microtune MT2131 silicon tuner"
123 depends on I2C 124 depends on VIDEO_MEDIA && I2C
124 default m if DVB_FE_CUSTOMISE 125 default m if DVB_FE_CUSTOMISE
125 help 126 help
126 A driver for the silicon baseband tuner MT2131 from Microtune. 127 A driver for the silicon baseband tuner MT2131 from Microtune.
127 128
128config MEDIA_TUNER_QT1010 129config MEDIA_TUNER_QT1010
129 tristate "Quantek QT1010 silicon tuner" 130 tristate "Quantek QT1010 silicon tuner"
130 depends on DVB_CORE && I2C 131 depends on VIDEO_MEDIA && I2C
131 default m if DVB_FE_CUSTOMISE 132 default m if DVB_FE_CUSTOMISE
132 help 133 help
133 A driver for the silicon tuner QT1010 from Quantek. 134 A driver for the silicon tuner QT1010 from Quantek.
134 135
135config MEDIA_TUNER_XC2028 136config MEDIA_TUNER_XC2028
136 tristate "XCeive xc2028/xc3028 tuners" 137 tristate "XCeive xc2028/xc3028 tuners"
137 depends on I2C && FW_LOADER 138 depends on VIDEO_MEDIA && I2C
139 depends on HOTPLUG
140 select FW_LOADER
138 default m if MEDIA_TUNER_CUSTOMIZE 141 default m if MEDIA_TUNER_CUSTOMIZE
139 help 142 help
140 Say Y here to include support for the xc2028/xc3028 tuners. 143 Say Y here to include support for the xc2028/xc3028 tuners.
141 144
142config MEDIA_TUNER_XC5000 145config MEDIA_TUNER_XC5000
143 tristate "Xceive XC5000 silicon tuner" 146 tristate "Xceive XC5000 silicon tuner"
144 depends on I2C 147 depends on VIDEO_MEDIA && I2C
148 depends on HOTPLUG
149 select FW_LOADER
145 default m if DVB_FE_CUSTOMISE 150 default m if DVB_FE_CUSTOMISE
146 help 151 help
147 A driver for the silicon tuner XC5000 from Xceive. 152 A driver for the silicon tuner XC5000 from Xceive.
148 This device is only used inside a SiP called togther with a 153 This device is only used inside a SiP called togther with a
149 demodulator for now. 154 demodulator for now.
150 155
156config MEDIA_TUNER_MXL5005S
157 tristate "MaxLinear MSL5005S silicon tuner"
158 depends on VIDEO_MEDIA && I2C
159 default m if DVB_FE_CUSTOMISE
160 help
161 A driver for the silicon tuner MXL5005S from MaxLinear.
162
151endif # MEDIA_TUNER_CUSTOMIZE 163endif # MEDIA_TUNER_CUSTOMIZE
diff --git a/drivers/media/common/tuners/Makefile b/drivers/media/common/tuners/Makefile
index 236d9932fd92..55f7e6706297 100644
--- a/drivers/media/common/tuners/Makefile
+++ b/drivers/media/common/tuners/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_MEDIA_TUNER_MT2060) += mt2060.o
20obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o 20obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o
21obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o 21obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o
22obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o 22obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o
23obj-$(CONFIG_MEDIA_TUNER_MXL5005S) += mxl5005s.o
23 24
24EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core 25EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
25EXTRA_CFLAGS += -Idrivers/media/dvb/frontends 26EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
new file mode 100644
index 000000000000..5d05b5390f66
--- /dev/null
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -0,0 +1,4110 @@
1/*
2 MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
3
4 Copyright (C) 2008 MaxLinear
5 Copyright (C) 2006 Steven Toth <stoth@hauppauge.com>
6 Functions:
7 mxl5005s_reset()
8 mxl5005s_writereg()
9 mxl5005s_writeregs()
10 mxl5005s_init()
11 mxl5005s_reconfigure()
12 mxl5005s_AssignTunerMode()
13 mxl5005s_set_params()
14 mxl5005s_get_frequency()
15 mxl5005s_get_bandwidth()
16 mxl5005s_release()
17 mxl5005s_attach()
18
19 Copyright (C) 2008 Realtek
20 Copyright (C) 2008 Jan Hoogenraad
21 Functions:
22 mxl5005s_SetRfFreqHz()
23
24 This program is free software; you can redistribute it and/or modify
25 it under the terms of the GNU General Public License as published by
26 the Free Software Foundation; either version 2 of the License, or
27 (at your option) any later version.
28
29 This program is distributed in the hope that it will be useful,
30 but WITHOUT ANY WARRANTY; without even the implied warranty of
31 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 GNU General Public License for more details.
33
34 You should have received a copy of the GNU General Public License
35 along with this program; if not, write to the Free Software
36 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
37
38*/
39
40/*
41 History of this driver (Steven Toth):
42 I was given a public release of a linux driver that included
43 support for the MaxLinear MXL5005S silicon tuner. Analysis of
44 the tuner driver showed clearly three things.
45
46 1. The tuner driver didn't support the LinuxTV tuner API
47 so the code Realtek added had to be removed.
48
49 2. A significant amount of the driver is reference driver code
50 from MaxLinear, I felt it was important to identify and
51 preserve this.
52
53 3. New code has to be added to interface correctly with the
54 LinuxTV API, as a regular kernel module.
55
56 Other than the reference driver enum's, I've clearly marked
57 sections of the code and retained the copyright of the
58 respective owners.
59*/
60#include <linux/kernel.h>
61#include <linux/init.h>
62#include <linux/module.h>
63#include <linux/string.h>
64#include <linux/slab.h>
65#include <linux/delay.h>
66#include "dvb_frontend.h"
67#include "mxl5005s.h"
68
69static int debug;
70
71#define dprintk(level, arg...) do { \
72 if (level <= debug) \
73 printk(arg); \
74 } while (0)
75
76#define TUNER_REGS_NUM 104
77#define INITCTRL_NUM 40
78
79#ifdef _MXL_PRODUCTION
80#define CHCTRL_NUM 39
81#else
82#define CHCTRL_NUM 36
83#endif
84
85#define MXLCTRL_NUM 189
86#define MASTER_CONTROL_ADDR 9
87
88/* Enumeration of Master Control Register State */
89enum master_control_state {
90 MC_LOAD_START = 1,
91 MC_POWER_DOWN,
92 MC_SYNTH_RESET,
93 MC_SEQ_OFF
94};
95
96/* Enumeration of MXL5005 Tuner Modulation Type */
97enum {
98 MXL_DEFAULT_MODULATION = 0,
99 MXL_DVBT,
100 MXL_ATSC,
101 MXL_QAM,
102 MXL_ANALOG_CABLE,
103 MXL_ANALOG_OTA
104} tuner_modu_type;
105
106/* MXL5005 Tuner Register Struct */
107struct TunerReg {
108 u16 Reg_Num; /* Tuner Register Address */
109 u16 Reg_Val; /* Current sw programmed value waiting to be writen */
110};
111
112enum {
113 /* Initialization Control Names */
114 DN_IQTN_AMP_CUT = 1, /* 1 */
115 BB_MODE, /* 2 */
116 BB_BUF, /* 3 */
117 BB_BUF_OA, /* 4 */
118 BB_ALPF_BANDSELECT, /* 5 */
119 BB_IQSWAP, /* 6 */
120 BB_DLPF_BANDSEL, /* 7 */
121 RFSYN_CHP_GAIN, /* 8 */
122 RFSYN_EN_CHP_HIGAIN, /* 9 */
123 AGC_IF, /* 10 */
124 AGC_RF, /* 11 */
125 IF_DIVVAL, /* 12 */
126 IF_VCO_BIAS, /* 13 */
127 CHCAL_INT_MOD_IF, /* 14 */
128 CHCAL_FRAC_MOD_IF, /* 15 */
129 DRV_RES_SEL, /* 16 */
130 I_DRIVER, /* 17 */
131 EN_AAF, /* 18 */
132 EN_3P, /* 19 */
133 EN_AUX_3P, /* 20 */
134 SEL_AAF_BAND, /* 21 */
135 SEQ_ENCLK16_CLK_OUT, /* 22 */
136 SEQ_SEL4_16B, /* 23 */
137 XTAL_CAPSELECT, /* 24 */
138 IF_SEL_DBL, /* 25 */
139 RFSYN_R_DIV, /* 26 */
140 SEQ_EXTSYNTHCALIF, /* 27 */
141 SEQ_EXTDCCAL, /* 28 */
142 AGC_EN_RSSI, /* 29 */
143 RFA_ENCLKRFAGC, /* 30 */
144 RFA_RSSI_REFH, /* 31 */
145 RFA_RSSI_REF, /* 32 */
146 RFA_RSSI_REFL, /* 33 */
147 RFA_FLR, /* 34 */
148 RFA_CEIL, /* 35 */
149 SEQ_EXTIQFSMPULSE, /* 36 */
150 OVERRIDE_1, /* 37 */
151 BB_INITSTATE_DLPF_TUNE, /* 38 */
152 TG_R_DIV, /* 39 */
153 EN_CHP_LIN_B, /* 40 */
154
155 /* Channel Change Control Names */
156 DN_POLY = 51, /* 51 */
157 DN_RFGAIN, /* 52 */
158 DN_CAP_RFLPF, /* 53 */
159 DN_EN_VHFUHFBAR, /* 54 */
160 DN_GAIN_ADJUST, /* 55 */
161 DN_IQTNBUF_AMP, /* 56 */
162 DN_IQTNGNBFBIAS_BST, /* 57 */
163 RFSYN_EN_OUTMUX, /* 58 */
164 RFSYN_SEL_VCO_OUT, /* 59 */
165 RFSYN_SEL_VCO_HI, /* 60 */
166 RFSYN_SEL_DIVM, /* 61 */
167 RFSYN_RF_DIV_BIAS, /* 62 */
168 DN_SEL_FREQ, /* 63 */
169 RFSYN_VCO_BIAS, /* 64 */
170 CHCAL_INT_MOD_RF, /* 65 */
171 CHCAL_FRAC_MOD_RF, /* 66 */
172 RFSYN_LPF_R, /* 67 */
173 CHCAL_EN_INT_RF, /* 68 */
174 TG_LO_DIVVAL, /* 69 */
175 TG_LO_SELVAL, /* 70 */
176 TG_DIV_VAL, /* 71 */
177 TG_VCO_BIAS, /* 72 */
178 SEQ_EXTPOWERUP, /* 73 */
179 OVERRIDE_2, /* 74 */
180 OVERRIDE_3, /* 75 */
181 OVERRIDE_4, /* 76 */
182 SEQ_FSM_PULSE, /* 77 */
183 GPIO_4B, /* 78 */
184 GPIO_3B, /* 79 */
185 GPIO_4, /* 80 */
186 GPIO_3, /* 81 */
187 GPIO_1B, /* 82 */
188 DAC_A_ENABLE, /* 83 */
189 DAC_B_ENABLE, /* 84 */
190 DAC_DIN_A, /* 85 */
191 DAC_DIN_B, /* 86 */
192#ifdef _MXL_PRODUCTION
193 RFSYN_EN_DIV, /* 87 */
194 RFSYN_DIVM, /* 88 */
195 DN_BYPASS_AGC_I2C /* 89 */
196#endif
197} MXL5005_ControlName;
198
199/*
200 * The following context is source code provided by MaxLinear.
201 * MaxLinear source code - Common_MXL.h (?)
202 */
203
204/* Constants */
205#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
206#define MXL5005S_LATCH_BYTE 0xfe
207
208/* Register address, MSB, and LSB */
209#define MXL5005S_BB_IQSWAP_ADDR 59
210#define MXL5005S_BB_IQSWAP_MSB 0
211#define MXL5005S_BB_IQSWAP_LSB 0
212
213#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
214#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
215#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
216
217/* Standard modes */
218enum {
219 MXL5005S_STANDARD_DVBT,
220 MXL5005S_STANDARD_ATSC,
221};
222#define MXL5005S_STANDARD_MODE_NUM 2
223
224/* Bandwidth modes */
225enum {
226 MXL5005S_BANDWIDTH_6MHZ = 6000000,
227 MXL5005S_BANDWIDTH_7MHZ = 7000000,
228 MXL5005S_BANDWIDTH_8MHZ = 8000000,
229};
230#define MXL5005S_BANDWIDTH_MODE_NUM 3
231
232/* MXL5005 Tuner Control Struct */
233struct TunerControl {
234 u16 Ctrl_Num; /* Control Number */
235 u16 size; /* Number of bits to represent Value */
236 u16 addr[25]; /* Array of Tuner Register Address for each bit pos */
237 u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */
238 u16 val[25]; /* Binary representation of Value */
239};
240
241/* MXL5005 Tuner Struct */
242struct mxl5005s_state {
243 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
244 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
245 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
246 u32 IF_OUT; /* Desired IF Out Frequency */
247 u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
248 u32 RF_IN; /* RF Input Frequency */
249 u32 Fxtal; /* XTAL Frequency */
250 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
251 u16 TOP; /* Value: take over point */
252 u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */
253 u8 DIV_OUT; /* 4MHz or 16MHz */
254 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
255 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
256
257 /* Modulation Type; */
258 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
259 u8 Mod_Type;
260
261 /* Tracking Filter Type */
262 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
263 u8 TF_Type;
264
265 /* Calculated Settings */
266 u32 RF_LO; /* Synth RF LO Frequency */
267 u32 IF_LO; /* Synth IF LO Frequency */
268 u32 TG_LO; /* Synth TG_LO Frequency */
269
270 /* Pointers to ControlName Arrays */
271 u16 Init_Ctrl_Num; /* Number of INIT Control Names */
272 struct TunerControl
273 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
274
275 u16 CH_Ctrl_Num; /* Number of CH Control Names */
276 struct TunerControl
277 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
278
279 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
280 struct TunerControl
281 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
282
283 /* Pointer to Tuner Register Array */
284 u16 TunerRegs_Num; /* Number of Tuner Registers */
285 struct TunerReg
286 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
287
288 /* Linux driver framework specific */
289 struct mxl5005s_config *config;
290 struct dvb_frontend *frontend;
291 struct i2c_adapter *i2c;
292
293 /* Cache values */
294 u32 current_mode;
295
296};
297
298static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
299static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
300static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
301static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
302 u8 bitVal);
303static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
304 u8 *RegVal, int *count);
305static u32 MXL_Ceiling(u32 value, u32 resolution);
306static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
307static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
308 u32 value, u16 controlGroup);
309static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
310static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
311 u8 *RegVal, int *count);
312static u32 MXL_GetXtalInt(u32 Xtal_Freq);
313static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
314static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
315static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
316static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
317 u8 *RegVal, int *count);
318static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
319 u8 *datatable, u8 len);
320static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
321static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
322 u32 bandwidth);
323static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
324 u32 bandwidth);
325
326/* ----------------------------------------------------------------
327 * Begin: Custom code salvaged from the Realtek driver.
328 * Copyright (C) 2008 Realtek
329 * Copyright (C) 2008 Jan Hoogenraad
330 * This code is placed under the terms of the GNU General Public License
331 *
332 * Released by Realtek under GPLv2.
333 * Thanks to Realtek for a lot of support we received !
334 *
335 * Revision: 080314 - original version
336 */
337
338static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
339{
340 struct mxl5005s_state *state = fe->tuner_priv;
341 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
342 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
343 int TableLen;
344
345 u32 IfDivval = 0;
346 unsigned char MasterControlByte;
347
348 dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
349
350 /* Set MxL5005S tuner RF frequency according to example code. */
351
352 /* Tuner RF frequency setting stage 0 */
353 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
354 AddrTable[0] = MASTER_CONTROL_ADDR;
355 ByteTable[0] |= state->config->AgcMasterByte;
356
357 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
358
359 /* Tuner RF frequency setting stage 1 */
360 MXL_TuneRF(fe, RfFreqHz);
361
362 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
363
364 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
365 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
366 MXL_ControlWrite(fe, IF_DIVVAL, 8);
367 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
368
369 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
370 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
371 ByteTable[TableLen] = MasterControlByte |
372 state->config->AgcMasterByte;
373 TableLen += 1;
374
375 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
376
377 /* Wait 30 ms. */
378 msleep(150);
379
380 /* Tuner RF frequency setting stage 2 */
381 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
382 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
383 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
384
385 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
386 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
387 ByteTable[TableLen] = MasterControlByte |
388 state->config->AgcMasterByte ;
389 TableLen += 1;
390
391 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
392
393 msleep(100);
394
395 return 0;
396}
397/* End: Custom code taken from the Realtek driver */
398
399/* ----------------------------------------------------------------
400 * Begin: Reference driver code found in the Realtek driver.
401 * Copyright (C) 2008 MaxLinear
402 */
403static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
404{
405 struct mxl5005s_state *state = fe->tuner_priv;
406 state->TunerRegs_Num = TUNER_REGS_NUM ;
407
408 state->TunerRegs[0].Reg_Num = 9 ;
409 state->TunerRegs[0].Reg_Val = 0x40 ;
410
411 state->TunerRegs[1].Reg_Num = 11 ;
412 state->TunerRegs[1].Reg_Val = 0x19 ;
413
414 state->TunerRegs[2].Reg_Num = 12 ;
415 state->TunerRegs[2].Reg_Val = 0x60 ;
416
417 state->TunerRegs[3].Reg_Num = 13 ;
418 state->TunerRegs[3].Reg_Val = 0x00 ;
419
420 state->TunerRegs[4].Reg_Num = 14 ;
421 state->TunerRegs[4].Reg_Val = 0x00 ;
422
423 state->TunerRegs[5].Reg_Num = 15 ;
424 state->TunerRegs[5].Reg_Val = 0xC0 ;
425
426 state->TunerRegs[6].Reg_Num = 16 ;
427 state->TunerRegs[6].Reg_Val = 0x00 ;
428
429 state->TunerRegs[7].Reg_Num = 17 ;
430 state->TunerRegs[7].Reg_Val = 0x00 ;
431
432 state->TunerRegs[8].Reg_Num = 18 ;
433 state->TunerRegs[8].Reg_Val = 0x00 ;
434
435 state->TunerRegs[9].Reg_Num = 19 ;
436 state->TunerRegs[9].Reg_Val = 0x34 ;
437
438 state->TunerRegs[10].Reg_Num = 21 ;
439 state->TunerRegs[10].Reg_Val = 0x00 ;
440
441 state->TunerRegs[11].Reg_Num = 22 ;
442 state->TunerRegs[11].Reg_Val = 0x6B ;
443
444 state->TunerRegs[12].Reg_Num = 23 ;
445 state->TunerRegs[12].Reg_Val = 0x35 ;
446
447 state->TunerRegs[13].Reg_Num = 24 ;
448 state->TunerRegs[13].Reg_Val = 0x70 ;
449
450 state->TunerRegs[14].Reg_Num = 25 ;
451 state->TunerRegs[14].Reg_Val = 0x3E ;
452
453 state->TunerRegs[15].Reg_Num = 26 ;
454 state->TunerRegs[15].Reg_Val = 0x82 ;
455
456 state->TunerRegs[16].Reg_Num = 31 ;
457 state->TunerRegs[16].Reg_Val = 0x00 ;
458
459 state->TunerRegs[17].Reg_Num = 32 ;
460 state->TunerRegs[17].Reg_Val = 0x40 ;
461
462 state->TunerRegs[18].Reg_Num = 33 ;
463 state->TunerRegs[18].Reg_Val = 0x53 ;
464
465 state->TunerRegs[19].Reg_Num = 34 ;
466 state->TunerRegs[19].Reg_Val = 0x81 ;
467
468 state->TunerRegs[20].Reg_Num = 35 ;
469 state->TunerRegs[20].Reg_Val = 0xC9 ;
470
471 state->TunerRegs[21].Reg_Num = 36 ;
472 state->TunerRegs[21].Reg_Val = 0x01 ;
473
474 state->TunerRegs[22].Reg_Num = 37 ;
475 state->TunerRegs[22].Reg_Val = 0x00 ;
476
477 state->TunerRegs[23].Reg_Num = 41 ;
478 state->TunerRegs[23].Reg_Val = 0x00 ;
479
480 state->TunerRegs[24].Reg_Num = 42 ;
481 state->TunerRegs[24].Reg_Val = 0xF8 ;
482
483 state->TunerRegs[25].Reg_Num = 43 ;
484 state->TunerRegs[25].Reg_Val = 0x43 ;
485
486 state->TunerRegs[26].Reg_Num = 44 ;
487 state->TunerRegs[26].Reg_Val = 0x20 ;
488
489 state->TunerRegs[27].Reg_Num = 45 ;
490 state->TunerRegs[27].Reg_Val = 0x80 ;
491
492 state->TunerRegs[28].Reg_Num = 46 ;
493 state->TunerRegs[28].Reg_Val = 0x88 ;
494
495 state->TunerRegs[29].Reg_Num = 47 ;
496 state->TunerRegs[29].Reg_Val = 0x86 ;
497
498 state->TunerRegs[30].Reg_Num = 48 ;
499 state->TunerRegs[30].Reg_Val = 0x00 ;
500
501 state->TunerRegs[31].Reg_Num = 49 ;
502 state->TunerRegs[31].Reg_Val = 0x00 ;
503
504 state->TunerRegs[32].Reg_Num = 53 ;
505 state->TunerRegs[32].Reg_Val = 0x94 ;
506
507 state->TunerRegs[33].Reg_Num = 54 ;
508 state->TunerRegs[33].Reg_Val = 0xFA ;
509
510 state->TunerRegs[34].Reg_Num = 55 ;
511 state->TunerRegs[34].Reg_Val = 0x92 ;
512
513 state->TunerRegs[35].Reg_Num = 56 ;
514 state->TunerRegs[35].Reg_Val = 0x80 ;
515
516 state->TunerRegs[36].Reg_Num = 57 ;
517 state->TunerRegs[36].Reg_Val = 0x41 ;
518
519 state->TunerRegs[37].Reg_Num = 58 ;
520 state->TunerRegs[37].Reg_Val = 0xDB ;
521
522 state->TunerRegs[38].Reg_Num = 59 ;
523 state->TunerRegs[38].Reg_Val = 0x00 ;
524
525 state->TunerRegs[39].Reg_Num = 60 ;
526 state->TunerRegs[39].Reg_Val = 0x00 ;
527
528 state->TunerRegs[40].Reg_Num = 61 ;
529 state->TunerRegs[40].Reg_Val = 0x00 ;
530
531 state->TunerRegs[41].Reg_Num = 62 ;
532 state->TunerRegs[41].Reg_Val = 0x00 ;
533
534 state->TunerRegs[42].Reg_Num = 65 ;
535 state->TunerRegs[42].Reg_Val = 0xF8 ;
536
537 state->TunerRegs[43].Reg_Num = 66 ;
538 state->TunerRegs[43].Reg_Val = 0xE4 ;
539
540 state->TunerRegs[44].Reg_Num = 67 ;
541 state->TunerRegs[44].Reg_Val = 0x90 ;
542
543 state->TunerRegs[45].Reg_Num = 68 ;
544 state->TunerRegs[45].Reg_Val = 0xC0 ;
545
546 state->TunerRegs[46].Reg_Num = 69 ;
547 state->TunerRegs[46].Reg_Val = 0x01 ;
548
549 state->TunerRegs[47].Reg_Num = 70 ;
550 state->TunerRegs[47].Reg_Val = 0x50 ;
551
552 state->TunerRegs[48].Reg_Num = 71 ;
553 state->TunerRegs[48].Reg_Val = 0x06 ;
554
555 state->TunerRegs[49].Reg_Num = 72 ;
556 state->TunerRegs[49].Reg_Val = 0x00 ;
557
558 state->TunerRegs[50].Reg_Num = 73 ;
559 state->TunerRegs[50].Reg_Val = 0x20 ;
560
561 state->TunerRegs[51].Reg_Num = 76 ;
562 state->TunerRegs[51].Reg_Val = 0xBB ;
563
564 state->TunerRegs[52].Reg_Num = 77 ;
565 state->TunerRegs[52].Reg_Val = 0x13 ;
566
567 state->TunerRegs[53].Reg_Num = 81 ;
568 state->TunerRegs[53].Reg_Val = 0x04 ;
569
570 state->TunerRegs[54].Reg_Num = 82 ;
571 state->TunerRegs[54].Reg_Val = 0x75 ;
572
573 state->TunerRegs[55].Reg_Num = 83 ;
574 state->TunerRegs[55].Reg_Val = 0x00 ;
575
576 state->TunerRegs[56].Reg_Num = 84 ;
577 state->TunerRegs[56].Reg_Val = 0x00 ;
578
579 state->TunerRegs[57].Reg_Num = 85 ;
580 state->TunerRegs[57].Reg_Val = 0x00 ;
581
582 state->TunerRegs[58].Reg_Num = 91 ;
583 state->TunerRegs[58].Reg_Val = 0x70 ;
584
585 state->TunerRegs[59].Reg_Num = 92 ;
586 state->TunerRegs[59].Reg_Val = 0x00 ;
587
588 state->TunerRegs[60].Reg_Num = 93 ;
589 state->TunerRegs[60].Reg_Val = 0x00 ;
590
591 state->TunerRegs[61].Reg_Num = 94 ;
592 state->TunerRegs[61].Reg_Val = 0x00 ;
593
594 state->TunerRegs[62].Reg_Num = 95 ;
595 state->TunerRegs[62].Reg_Val = 0x0C ;
596
597 state->TunerRegs[63].Reg_Num = 96 ;
598 state->TunerRegs[63].Reg_Val = 0x00 ;
599
600 state->TunerRegs[64].Reg_Num = 97 ;
601 state->TunerRegs[64].Reg_Val = 0x00 ;
602
603 state->TunerRegs[65].Reg_Num = 98 ;
604 state->TunerRegs[65].Reg_Val = 0xE2 ;
605
606 state->TunerRegs[66].Reg_Num = 99 ;
607 state->TunerRegs[66].Reg_Val = 0x00 ;
608
609 state->TunerRegs[67].Reg_Num = 100 ;
610 state->TunerRegs[67].Reg_Val = 0x00 ;
611
612 state->TunerRegs[68].Reg_Num = 101 ;
613 state->TunerRegs[68].Reg_Val = 0x12 ;
614
615 state->TunerRegs[69].Reg_Num = 102 ;
616 state->TunerRegs[69].Reg_Val = 0x80 ;
617
618 state->TunerRegs[70].Reg_Num = 103 ;
619 state->TunerRegs[70].Reg_Val = 0x32 ;
620
621 state->TunerRegs[71].Reg_Num = 104 ;
622 state->TunerRegs[71].Reg_Val = 0xB4 ;
623
624 state->TunerRegs[72].Reg_Num = 105 ;
625 state->TunerRegs[72].Reg_Val = 0x60 ;
626
627 state->TunerRegs[73].Reg_Num = 106 ;
628 state->TunerRegs[73].Reg_Val = 0x83 ;
629
630 state->TunerRegs[74].Reg_Num = 107 ;
631 state->TunerRegs[74].Reg_Val = 0x84 ;
632
633 state->TunerRegs[75].Reg_Num = 108 ;
634 state->TunerRegs[75].Reg_Val = 0x9C ;
635
636 state->TunerRegs[76].Reg_Num = 109 ;
637 state->TunerRegs[76].Reg_Val = 0x02 ;
638
639 state->TunerRegs[77].Reg_Num = 110 ;
640 state->TunerRegs[77].Reg_Val = 0x81 ;
641
642 state->TunerRegs[78].Reg_Num = 111 ;
643 state->TunerRegs[78].Reg_Val = 0xC0 ;
644
645 state->TunerRegs[79].Reg_Num = 112 ;
646 state->TunerRegs[79].Reg_Val = 0x10 ;
647
648 state->TunerRegs[80].Reg_Num = 131 ;
649 state->TunerRegs[80].Reg_Val = 0x8A ;
650
651 state->TunerRegs[81].Reg_Num = 132 ;
652 state->TunerRegs[81].Reg_Val = 0x10 ;
653
654 state->TunerRegs[82].Reg_Num = 133 ;
655 state->TunerRegs[82].Reg_Val = 0x24 ;
656
657 state->TunerRegs[83].Reg_Num = 134 ;
658 state->TunerRegs[83].Reg_Val = 0x00 ;
659
660 state->TunerRegs[84].Reg_Num = 135 ;
661 state->TunerRegs[84].Reg_Val = 0x00 ;
662
663 state->TunerRegs[85].Reg_Num = 136 ;
664 state->TunerRegs[85].Reg_Val = 0x7E ;
665
666 state->TunerRegs[86].Reg_Num = 137 ;
667 state->TunerRegs[86].Reg_Val = 0x40 ;
668
669 state->TunerRegs[87].Reg_Num = 138 ;
670 state->TunerRegs[87].Reg_Val = 0x38 ;
671
672 state->TunerRegs[88].Reg_Num = 146 ;
673 state->TunerRegs[88].Reg_Val = 0xF6 ;
674
675 state->TunerRegs[89].Reg_Num = 147 ;
676 state->TunerRegs[89].Reg_Val = 0x1A ;
677
678 state->TunerRegs[90].Reg_Num = 148 ;
679 state->TunerRegs[90].Reg_Val = 0x62 ;
680
681 state->TunerRegs[91].Reg_Num = 149 ;
682 state->TunerRegs[91].Reg_Val = 0x33 ;
683
684 state->TunerRegs[92].Reg_Num = 150 ;
685 state->TunerRegs[92].Reg_Val = 0x80 ;
686
687 state->TunerRegs[93].Reg_Num = 156 ;
688 state->TunerRegs[93].Reg_Val = 0x56 ;
689
690 state->TunerRegs[94].Reg_Num = 157 ;
691 state->TunerRegs[94].Reg_Val = 0x17 ;
692
693 state->TunerRegs[95].Reg_Num = 158 ;
694 state->TunerRegs[95].Reg_Val = 0xA9 ;
695
696 state->TunerRegs[96].Reg_Num = 159 ;
697 state->TunerRegs[96].Reg_Val = 0x00 ;
698
699 state->TunerRegs[97].Reg_Num = 160 ;
700 state->TunerRegs[97].Reg_Val = 0x00 ;
701
702 state->TunerRegs[98].Reg_Num = 161 ;
703 state->TunerRegs[98].Reg_Val = 0x00 ;
704
705 state->TunerRegs[99].Reg_Num = 162 ;
706 state->TunerRegs[99].Reg_Val = 0x40 ;
707
708 state->TunerRegs[100].Reg_Num = 166 ;
709 state->TunerRegs[100].Reg_Val = 0xAE ;
710
711 state->TunerRegs[101].Reg_Num = 167 ;
712 state->TunerRegs[101].Reg_Val = 0x1B ;
713
714 state->TunerRegs[102].Reg_Num = 168 ;
715 state->TunerRegs[102].Reg_Val = 0xF2 ;
716
717 state->TunerRegs[103].Reg_Num = 195 ;
718 state->TunerRegs[103].Reg_Val = 0x00 ;
719
720 return 0 ;
721}
722
723static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
724{
725 struct mxl5005s_state *state = fe->tuner_priv;
726 state->Init_Ctrl_Num = INITCTRL_NUM;
727
728 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
729 state->Init_Ctrl[0].size = 1 ;
730 state->Init_Ctrl[0].addr[0] = 73;
731 state->Init_Ctrl[0].bit[0] = 7;
732 state->Init_Ctrl[0].val[0] = 0;
733
734 state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
735 state->Init_Ctrl[1].size = 1 ;
736 state->Init_Ctrl[1].addr[0] = 53;
737 state->Init_Ctrl[1].bit[0] = 2;
738 state->Init_Ctrl[1].val[0] = 1;
739
740 state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
741 state->Init_Ctrl[2].size = 2 ;
742 state->Init_Ctrl[2].addr[0] = 53;
743 state->Init_Ctrl[2].bit[0] = 1;
744 state->Init_Ctrl[2].val[0] = 0;
745 state->Init_Ctrl[2].addr[1] = 57;
746 state->Init_Ctrl[2].bit[1] = 0;
747 state->Init_Ctrl[2].val[1] = 1;
748
749 state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
750 state->Init_Ctrl[3].size = 1 ;
751 state->Init_Ctrl[3].addr[0] = 53;
752 state->Init_Ctrl[3].bit[0] = 0;
753 state->Init_Ctrl[3].val[0] = 0;
754
755 state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
756 state->Init_Ctrl[4].size = 3 ;
757 state->Init_Ctrl[4].addr[0] = 53;
758 state->Init_Ctrl[4].bit[0] = 5;
759 state->Init_Ctrl[4].val[0] = 0;
760 state->Init_Ctrl[4].addr[1] = 53;
761 state->Init_Ctrl[4].bit[1] = 6;
762 state->Init_Ctrl[4].val[1] = 0;
763 state->Init_Ctrl[4].addr[2] = 53;
764 state->Init_Ctrl[4].bit[2] = 7;
765 state->Init_Ctrl[4].val[2] = 1;
766
767 state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
768 state->Init_Ctrl[5].size = 1 ;
769 state->Init_Ctrl[5].addr[0] = 59;
770 state->Init_Ctrl[5].bit[0] = 0;
771 state->Init_Ctrl[5].val[0] = 0;
772
773 state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
774 state->Init_Ctrl[6].size = 2 ;
775 state->Init_Ctrl[6].addr[0] = 53;
776 state->Init_Ctrl[6].bit[0] = 3;
777 state->Init_Ctrl[6].val[0] = 0;
778 state->Init_Ctrl[6].addr[1] = 53;
779 state->Init_Ctrl[6].bit[1] = 4;
780 state->Init_Ctrl[6].val[1] = 1;
781
782 state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
783 state->Init_Ctrl[7].size = 4 ;
784 state->Init_Ctrl[7].addr[0] = 22;
785 state->Init_Ctrl[7].bit[0] = 4;
786 state->Init_Ctrl[7].val[0] = 0;
787 state->Init_Ctrl[7].addr[1] = 22;
788 state->Init_Ctrl[7].bit[1] = 5;
789 state->Init_Ctrl[7].val[1] = 1;
790 state->Init_Ctrl[7].addr[2] = 22;
791 state->Init_Ctrl[7].bit[2] = 6;
792 state->Init_Ctrl[7].val[2] = 1;
793 state->Init_Ctrl[7].addr[3] = 22;
794 state->Init_Ctrl[7].bit[3] = 7;
795 state->Init_Ctrl[7].val[3] = 0;
796
797 state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
798 state->Init_Ctrl[8].size = 1 ;
799 state->Init_Ctrl[8].addr[0] = 22;
800 state->Init_Ctrl[8].bit[0] = 2;
801 state->Init_Ctrl[8].val[0] = 0;
802
803 state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
804 state->Init_Ctrl[9].size = 4 ;
805 state->Init_Ctrl[9].addr[0] = 76;
806 state->Init_Ctrl[9].bit[0] = 0;
807 state->Init_Ctrl[9].val[0] = 1;
808 state->Init_Ctrl[9].addr[1] = 76;
809 state->Init_Ctrl[9].bit[1] = 1;
810 state->Init_Ctrl[9].val[1] = 1;
811 state->Init_Ctrl[9].addr[2] = 76;
812 state->Init_Ctrl[9].bit[2] = 2;
813 state->Init_Ctrl[9].val[2] = 0;
814 state->Init_Ctrl[9].addr[3] = 76;
815 state->Init_Ctrl[9].bit[3] = 3;
816 state->Init_Ctrl[9].val[3] = 1;
817
818 state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
819 state->Init_Ctrl[10].size = 4 ;
820 state->Init_Ctrl[10].addr[0] = 76;
821 state->Init_Ctrl[10].bit[0] = 4;
822 state->Init_Ctrl[10].val[0] = 1;
823 state->Init_Ctrl[10].addr[1] = 76;
824 state->Init_Ctrl[10].bit[1] = 5;
825 state->Init_Ctrl[10].val[1] = 1;
826 state->Init_Ctrl[10].addr[2] = 76;
827 state->Init_Ctrl[10].bit[2] = 6;
828 state->Init_Ctrl[10].val[2] = 0;
829 state->Init_Ctrl[10].addr[3] = 76;
830 state->Init_Ctrl[10].bit[3] = 7;
831 state->Init_Ctrl[10].val[3] = 1;
832
833 state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
834 state->Init_Ctrl[11].size = 5 ;
835 state->Init_Ctrl[11].addr[0] = 43;
836 state->Init_Ctrl[11].bit[0] = 3;
837 state->Init_Ctrl[11].val[0] = 0;
838 state->Init_Ctrl[11].addr[1] = 43;
839 state->Init_Ctrl[11].bit[1] = 4;
840 state->Init_Ctrl[11].val[1] = 0;
841 state->Init_Ctrl[11].addr[2] = 43;
842 state->Init_Ctrl[11].bit[2] = 5;
843 state->Init_Ctrl[11].val[2] = 0;
844 state->Init_Ctrl[11].addr[3] = 43;
845 state->Init_Ctrl[11].bit[3] = 6;
846 state->Init_Ctrl[11].val[3] = 1;
847 state->Init_Ctrl[11].addr[4] = 43;
848 state->Init_Ctrl[11].bit[4] = 7;
849 state->Init_Ctrl[11].val[4] = 0;
850
851 state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
852 state->Init_Ctrl[12].size = 6 ;
853 state->Init_Ctrl[12].addr[0] = 44;
854 state->Init_Ctrl[12].bit[0] = 2;
855 state->Init_Ctrl[12].val[0] = 0;
856 state->Init_Ctrl[12].addr[1] = 44;
857 state->Init_Ctrl[12].bit[1] = 3;
858 state->Init_Ctrl[12].val[1] = 0;
859 state->Init_Ctrl[12].addr[2] = 44;
860 state->Init_Ctrl[12].bit[2] = 4;
861 state->Init_Ctrl[12].val[2] = 0;
862 state->Init_Ctrl[12].addr[3] = 44;
863 state->Init_Ctrl[12].bit[3] = 5;
864 state->Init_Ctrl[12].val[3] = 1;
865 state->Init_Ctrl[12].addr[4] = 44;
866 state->Init_Ctrl[12].bit[4] = 6;
867 state->Init_Ctrl[12].val[4] = 0;
868 state->Init_Ctrl[12].addr[5] = 44;
869 state->Init_Ctrl[12].bit[5] = 7;
870 state->Init_Ctrl[12].val[5] = 0;
871
872 state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
873 state->Init_Ctrl[13].size = 7 ;
874 state->Init_Ctrl[13].addr[0] = 11;
875 state->Init_Ctrl[13].bit[0] = 0;
876 state->Init_Ctrl[13].val[0] = 1;
877 state->Init_Ctrl[13].addr[1] = 11;
878 state->Init_Ctrl[13].bit[1] = 1;
879 state->Init_Ctrl[13].val[1] = 0;
880 state->Init_Ctrl[13].addr[2] = 11;
881 state->Init_Ctrl[13].bit[2] = 2;
882 state->Init_Ctrl[13].val[2] = 0;
883 state->Init_Ctrl[13].addr[3] = 11;
884 state->Init_Ctrl[13].bit[3] = 3;
885 state->Init_Ctrl[13].val[3] = 1;
886 state->Init_Ctrl[13].addr[4] = 11;
887 state->Init_Ctrl[13].bit[4] = 4;
888 state->Init_Ctrl[13].val[4] = 1;
889 state->Init_Ctrl[13].addr[5] = 11;
890 state->Init_Ctrl[13].bit[5] = 5;
891 state->Init_Ctrl[13].val[5] = 0;
892 state->Init_Ctrl[13].addr[6] = 11;
893 state->Init_Ctrl[13].bit[6] = 6;
894 state->Init_Ctrl[13].val[6] = 0;
895
896 state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
897 state->Init_Ctrl[14].size = 16 ;
898 state->Init_Ctrl[14].addr[0] = 13;
899 state->Init_Ctrl[14].bit[0] = 0;
900 state->Init_Ctrl[14].val[0] = 0;
901 state->Init_Ctrl[14].addr[1] = 13;
902 state->Init_Ctrl[14].bit[1] = 1;
903 state->Init_Ctrl[14].val[1] = 0;
904 state->Init_Ctrl[14].addr[2] = 13;
905 state->Init_Ctrl[14].bit[2] = 2;
906 state->Init_Ctrl[14].val[2] = 0;
907 state->Init_Ctrl[14].addr[3] = 13;
908 state->Init_Ctrl[14].bit[3] = 3;
909 state->Init_Ctrl[14].val[3] = 0;
910 state->Init_Ctrl[14].addr[4] = 13;
911 state->Init_Ctrl[14].bit[4] = 4;
912 state->Init_Ctrl[14].val[4] = 0;
913 state->Init_Ctrl[14].addr[5] = 13;
914 state->Init_Ctrl[14].bit[5] = 5;
915 state->Init_Ctrl[14].val[5] = 0;
916 state->Init_Ctrl[14].addr[6] = 13;
917 state->Init_Ctrl[14].bit[6] = 6;
918 state->Init_Ctrl[14].val[6] = 0;
919 state->Init_Ctrl[14].addr[7] = 13;
920 state->Init_Ctrl[14].bit[7] = 7;
921 state->Init_Ctrl[14].val[7] = 0;
922 state->Init_Ctrl[14].addr[8] = 12;
923 state->Init_Ctrl[14].bit[8] = 0;
924 state->Init_Ctrl[14].val[8] = 0;
925 state->Init_Ctrl[14].addr[9] = 12;
926 state->Init_Ctrl[14].bit[9] = 1;
927 state->Init_Ctrl[14].val[9] = 0;
928 state->Init_Ctrl[14].addr[10] = 12;
929 state->Init_Ctrl[14].bit[10] = 2;
930 state->Init_Ctrl[14].val[10] = 0;
931 state->Init_Ctrl[14].addr[11] = 12;
932 state->Init_Ctrl[14].bit[11] = 3;
933 state->Init_Ctrl[14].val[11] = 0;
934 state->Init_Ctrl[14].addr[12] = 12;
935 state->Init_Ctrl[14].bit[12] = 4;
936 state->Init_Ctrl[14].val[12] = 0;
937 state->Init_Ctrl[14].addr[13] = 12;
938 state->Init_Ctrl[14].bit[13] = 5;
939 state->Init_Ctrl[14].val[13] = 1;
940 state->Init_Ctrl[14].addr[14] = 12;
941 state->Init_Ctrl[14].bit[14] = 6;
942 state->Init_Ctrl[14].val[14] = 1;
943 state->Init_Ctrl[14].addr[15] = 12;
944 state->Init_Ctrl[14].bit[15] = 7;
945 state->Init_Ctrl[14].val[15] = 0;
946
947 state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
948 state->Init_Ctrl[15].size = 3 ;
949 state->Init_Ctrl[15].addr[0] = 147;
950 state->Init_Ctrl[15].bit[0] = 2;
951 state->Init_Ctrl[15].val[0] = 0;
952 state->Init_Ctrl[15].addr[1] = 147;
953 state->Init_Ctrl[15].bit[1] = 3;
954 state->Init_Ctrl[15].val[1] = 1;
955 state->Init_Ctrl[15].addr[2] = 147;
956 state->Init_Ctrl[15].bit[2] = 4;
957 state->Init_Ctrl[15].val[2] = 1;
958
959 state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
960 state->Init_Ctrl[16].size = 2 ;
961 state->Init_Ctrl[16].addr[0] = 147;
962 state->Init_Ctrl[16].bit[0] = 0;
963 state->Init_Ctrl[16].val[0] = 0;
964 state->Init_Ctrl[16].addr[1] = 147;
965 state->Init_Ctrl[16].bit[1] = 1;
966 state->Init_Ctrl[16].val[1] = 1;
967
968 state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
969 state->Init_Ctrl[17].size = 1 ;
970 state->Init_Ctrl[17].addr[0] = 147;
971 state->Init_Ctrl[17].bit[0] = 7;
972 state->Init_Ctrl[17].val[0] = 0;
973
974 state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
975 state->Init_Ctrl[18].size = 1 ;
976 state->Init_Ctrl[18].addr[0] = 147;
977 state->Init_Ctrl[18].bit[0] = 6;
978 state->Init_Ctrl[18].val[0] = 0;
979
980 state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
981 state->Init_Ctrl[19].size = 1 ;
982 state->Init_Ctrl[19].addr[0] = 156;
983 state->Init_Ctrl[19].bit[0] = 0;
984 state->Init_Ctrl[19].val[0] = 0;
985
986 state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
987 state->Init_Ctrl[20].size = 1 ;
988 state->Init_Ctrl[20].addr[0] = 147;
989 state->Init_Ctrl[20].bit[0] = 5;
990 state->Init_Ctrl[20].val[0] = 0;
991
992 state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
993 state->Init_Ctrl[21].size = 1 ;
994 state->Init_Ctrl[21].addr[0] = 137;
995 state->Init_Ctrl[21].bit[0] = 4;
996 state->Init_Ctrl[21].val[0] = 0;
997
998 state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
999 state->Init_Ctrl[22].size = 1 ;
1000 state->Init_Ctrl[22].addr[0] = 137;
1001 state->Init_Ctrl[22].bit[0] = 7;
1002 state->Init_Ctrl[22].val[0] = 0;
1003
1004 state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1005 state->Init_Ctrl[23].size = 1 ;
1006 state->Init_Ctrl[23].addr[0] = 91;
1007 state->Init_Ctrl[23].bit[0] = 5;
1008 state->Init_Ctrl[23].val[0] = 1;
1009
1010 state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1011 state->Init_Ctrl[24].size = 1 ;
1012 state->Init_Ctrl[24].addr[0] = 43;
1013 state->Init_Ctrl[24].bit[0] = 0;
1014 state->Init_Ctrl[24].val[0] = 1;
1015
1016 state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1017 state->Init_Ctrl[25].size = 2 ;
1018 state->Init_Ctrl[25].addr[0] = 22;
1019 state->Init_Ctrl[25].bit[0] = 0;
1020 state->Init_Ctrl[25].val[0] = 1;
1021 state->Init_Ctrl[25].addr[1] = 22;
1022 state->Init_Ctrl[25].bit[1] = 1;
1023 state->Init_Ctrl[25].val[1] = 1;
1024
1025 state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1026 state->Init_Ctrl[26].size = 1 ;
1027 state->Init_Ctrl[26].addr[0] = 134;
1028 state->Init_Ctrl[26].bit[0] = 2;
1029 state->Init_Ctrl[26].val[0] = 0;
1030
1031 state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1032 state->Init_Ctrl[27].size = 1 ;
1033 state->Init_Ctrl[27].addr[0] = 137;
1034 state->Init_Ctrl[27].bit[0] = 3;
1035 state->Init_Ctrl[27].val[0] = 0;
1036
1037 state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1038 state->Init_Ctrl[28].size = 1 ;
1039 state->Init_Ctrl[28].addr[0] = 77;
1040 state->Init_Ctrl[28].bit[0] = 7;
1041 state->Init_Ctrl[28].val[0] = 0;
1042
1043 state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1044 state->Init_Ctrl[29].size = 1 ;
1045 state->Init_Ctrl[29].addr[0] = 166;
1046 state->Init_Ctrl[29].bit[0] = 7;
1047 state->Init_Ctrl[29].val[0] = 1;
1048
1049 state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1050 state->Init_Ctrl[30].size = 3 ;
1051 state->Init_Ctrl[30].addr[0] = 166;
1052 state->Init_Ctrl[30].bit[0] = 0;
1053 state->Init_Ctrl[30].val[0] = 0;
1054 state->Init_Ctrl[30].addr[1] = 166;
1055 state->Init_Ctrl[30].bit[1] = 1;
1056 state->Init_Ctrl[30].val[1] = 1;
1057 state->Init_Ctrl[30].addr[2] = 166;
1058 state->Init_Ctrl[30].bit[2] = 2;
1059 state->Init_Ctrl[30].val[2] = 1;
1060
1061 state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1062 state->Init_Ctrl[31].size = 3 ;
1063 state->Init_Ctrl[31].addr[0] = 166;
1064 state->Init_Ctrl[31].bit[0] = 3;
1065 state->Init_Ctrl[31].val[0] = 1;
1066 state->Init_Ctrl[31].addr[1] = 166;
1067 state->Init_Ctrl[31].bit[1] = 4;
1068 state->Init_Ctrl[31].val[1] = 0;
1069 state->Init_Ctrl[31].addr[2] = 166;
1070 state->Init_Ctrl[31].bit[2] = 5;
1071 state->Init_Ctrl[31].val[2] = 1;
1072
1073 state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1074 state->Init_Ctrl[32].size = 3 ;
1075 state->Init_Ctrl[32].addr[0] = 167;
1076 state->Init_Ctrl[32].bit[0] = 0;
1077 state->Init_Ctrl[32].val[0] = 1;
1078 state->Init_Ctrl[32].addr[1] = 167;
1079 state->Init_Ctrl[32].bit[1] = 1;
1080 state->Init_Ctrl[32].val[1] = 1;
1081 state->Init_Ctrl[32].addr[2] = 167;
1082 state->Init_Ctrl[32].bit[2] = 2;
1083 state->Init_Ctrl[32].val[2] = 0;
1084
1085 state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1086 state->Init_Ctrl[33].size = 4 ;
1087 state->Init_Ctrl[33].addr[0] = 168;
1088 state->Init_Ctrl[33].bit[0] = 0;
1089 state->Init_Ctrl[33].val[0] = 0;
1090 state->Init_Ctrl[33].addr[1] = 168;
1091 state->Init_Ctrl[33].bit[1] = 1;
1092 state->Init_Ctrl[33].val[1] = 1;
1093 state->Init_Ctrl[33].addr[2] = 168;
1094 state->Init_Ctrl[33].bit[2] = 2;
1095 state->Init_Ctrl[33].val[2] = 0;
1096 state->Init_Ctrl[33].addr[3] = 168;
1097 state->Init_Ctrl[33].bit[3] = 3;
1098 state->Init_Ctrl[33].val[3] = 0;
1099
1100 state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1101 state->Init_Ctrl[34].size = 4 ;
1102 state->Init_Ctrl[34].addr[0] = 168;
1103 state->Init_Ctrl[34].bit[0] = 4;
1104 state->Init_Ctrl[34].val[0] = 1;
1105 state->Init_Ctrl[34].addr[1] = 168;
1106 state->Init_Ctrl[34].bit[1] = 5;
1107 state->Init_Ctrl[34].val[1] = 1;
1108 state->Init_Ctrl[34].addr[2] = 168;
1109 state->Init_Ctrl[34].bit[2] = 6;
1110 state->Init_Ctrl[34].val[2] = 1;
1111 state->Init_Ctrl[34].addr[3] = 168;
1112 state->Init_Ctrl[34].bit[3] = 7;
1113 state->Init_Ctrl[34].val[3] = 1;
1114
1115 state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1116 state->Init_Ctrl[35].size = 1 ;
1117 state->Init_Ctrl[35].addr[0] = 135;
1118 state->Init_Ctrl[35].bit[0] = 0;
1119 state->Init_Ctrl[35].val[0] = 0;
1120
1121 state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1122 state->Init_Ctrl[36].size = 1 ;
1123 state->Init_Ctrl[36].addr[0] = 56;
1124 state->Init_Ctrl[36].bit[0] = 3;
1125 state->Init_Ctrl[36].val[0] = 0;
1126
1127 state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1128 state->Init_Ctrl[37].size = 7 ;
1129 state->Init_Ctrl[37].addr[0] = 59;
1130 state->Init_Ctrl[37].bit[0] = 1;
1131 state->Init_Ctrl[37].val[0] = 0;
1132 state->Init_Ctrl[37].addr[1] = 59;
1133 state->Init_Ctrl[37].bit[1] = 2;
1134 state->Init_Ctrl[37].val[1] = 0;
1135 state->Init_Ctrl[37].addr[2] = 59;
1136 state->Init_Ctrl[37].bit[2] = 3;
1137 state->Init_Ctrl[37].val[2] = 0;
1138 state->Init_Ctrl[37].addr[3] = 59;
1139 state->Init_Ctrl[37].bit[3] = 4;
1140 state->Init_Ctrl[37].val[3] = 0;
1141 state->Init_Ctrl[37].addr[4] = 59;
1142 state->Init_Ctrl[37].bit[4] = 5;
1143 state->Init_Ctrl[37].val[4] = 0;
1144 state->Init_Ctrl[37].addr[5] = 59;
1145 state->Init_Ctrl[37].bit[5] = 6;
1146 state->Init_Ctrl[37].val[5] = 0;
1147 state->Init_Ctrl[37].addr[6] = 59;
1148 state->Init_Ctrl[37].bit[6] = 7;
1149 state->Init_Ctrl[37].val[6] = 0;
1150
1151 state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1152 state->Init_Ctrl[38].size = 6 ;
1153 state->Init_Ctrl[38].addr[0] = 32;
1154 state->Init_Ctrl[38].bit[0] = 2;
1155 state->Init_Ctrl[38].val[0] = 0;
1156 state->Init_Ctrl[38].addr[1] = 32;
1157 state->Init_Ctrl[38].bit[1] = 3;
1158 state->Init_Ctrl[38].val[1] = 0;
1159 state->Init_Ctrl[38].addr[2] = 32;
1160 state->Init_Ctrl[38].bit[2] = 4;
1161 state->Init_Ctrl[38].val[2] = 0;
1162 state->Init_Ctrl[38].addr[3] = 32;
1163 state->Init_Ctrl[38].bit[3] = 5;
1164 state->Init_Ctrl[38].val[3] = 0;
1165 state->Init_Ctrl[38].addr[4] = 32;
1166 state->Init_Ctrl[38].bit[4] = 6;
1167 state->Init_Ctrl[38].val[4] = 1;
1168 state->Init_Ctrl[38].addr[5] = 32;
1169 state->Init_Ctrl[38].bit[5] = 7;
1170 state->Init_Ctrl[38].val[5] = 0;
1171
1172 state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1173 state->Init_Ctrl[39].size = 1 ;
1174 state->Init_Ctrl[39].addr[0] = 25;
1175 state->Init_Ctrl[39].bit[0] = 3;
1176 state->Init_Ctrl[39].val[0] = 1;
1177
1178
1179 state->CH_Ctrl_Num = CHCTRL_NUM ;
1180
1181 state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1182 state->CH_Ctrl[0].size = 2 ;
1183 state->CH_Ctrl[0].addr[0] = 68;
1184 state->CH_Ctrl[0].bit[0] = 6;
1185 state->CH_Ctrl[0].val[0] = 1;
1186 state->CH_Ctrl[0].addr[1] = 68;
1187 state->CH_Ctrl[0].bit[1] = 7;
1188 state->CH_Ctrl[0].val[1] = 1;
1189
1190 state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1191 state->CH_Ctrl[1].size = 2 ;
1192 state->CH_Ctrl[1].addr[0] = 70;
1193 state->CH_Ctrl[1].bit[0] = 6;
1194 state->CH_Ctrl[1].val[0] = 1;
1195 state->CH_Ctrl[1].addr[1] = 70;
1196 state->CH_Ctrl[1].bit[1] = 7;
1197 state->CH_Ctrl[1].val[1] = 0;
1198
1199 state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1200 state->CH_Ctrl[2].size = 9 ;
1201 state->CH_Ctrl[2].addr[0] = 69;
1202 state->CH_Ctrl[2].bit[0] = 5;
1203 state->CH_Ctrl[2].val[0] = 0;
1204 state->CH_Ctrl[2].addr[1] = 69;
1205 state->CH_Ctrl[2].bit[1] = 6;
1206 state->CH_Ctrl[2].val[1] = 0;
1207 state->CH_Ctrl[2].addr[2] = 69;
1208 state->CH_Ctrl[2].bit[2] = 7;
1209 state->CH_Ctrl[2].val[2] = 0;
1210 state->CH_Ctrl[2].addr[3] = 68;
1211 state->CH_Ctrl[2].bit[3] = 0;
1212 state->CH_Ctrl[2].val[3] = 0;
1213 state->CH_Ctrl[2].addr[4] = 68;
1214 state->CH_Ctrl[2].bit[4] = 1;
1215 state->CH_Ctrl[2].val[4] = 0;
1216 state->CH_Ctrl[2].addr[5] = 68;
1217 state->CH_Ctrl[2].bit[5] = 2;
1218 state->CH_Ctrl[2].val[5] = 0;
1219 state->CH_Ctrl[2].addr[6] = 68;
1220 state->CH_Ctrl[2].bit[6] = 3;
1221 state->CH_Ctrl[2].val[6] = 0;
1222 state->CH_Ctrl[2].addr[7] = 68;
1223 state->CH_Ctrl[2].bit[7] = 4;
1224 state->CH_Ctrl[2].val[7] = 0;
1225 state->CH_Ctrl[2].addr[8] = 68;
1226 state->CH_Ctrl[2].bit[8] = 5;
1227 state->CH_Ctrl[2].val[8] = 0;
1228
1229 state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1230 state->CH_Ctrl[3].size = 1 ;
1231 state->CH_Ctrl[3].addr[0] = 70;
1232 state->CH_Ctrl[3].bit[0] = 5;
1233 state->CH_Ctrl[3].val[0] = 0;
1234
1235 state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1236 state->CH_Ctrl[4].size = 3 ;
1237 state->CH_Ctrl[4].addr[0] = 73;
1238 state->CH_Ctrl[4].bit[0] = 4;
1239 state->CH_Ctrl[4].val[0] = 0;
1240 state->CH_Ctrl[4].addr[1] = 73;
1241 state->CH_Ctrl[4].bit[1] = 5;
1242 state->CH_Ctrl[4].val[1] = 1;
1243 state->CH_Ctrl[4].addr[2] = 73;
1244 state->CH_Ctrl[4].bit[2] = 6;
1245 state->CH_Ctrl[4].val[2] = 0;
1246
1247 state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1248 state->CH_Ctrl[5].size = 4 ;
1249 state->CH_Ctrl[5].addr[0] = 70;
1250 state->CH_Ctrl[5].bit[0] = 0;
1251 state->CH_Ctrl[5].val[0] = 0;
1252 state->CH_Ctrl[5].addr[1] = 70;
1253 state->CH_Ctrl[5].bit[1] = 1;
1254 state->CH_Ctrl[5].val[1] = 0;
1255 state->CH_Ctrl[5].addr[2] = 70;
1256 state->CH_Ctrl[5].bit[2] = 2;
1257 state->CH_Ctrl[5].val[2] = 0;
1258 state->CH_Ctrl[5].addr[3] = 70;
1259 state->CH_Ctrl[5].bit[3] = 3;
1260 state->CH_Ctrl[5].val[3] = 0;
1261
1262 state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1263 state->CH_Ctrl[6].size = 1 ;
1264 state->CH_Ctrl[6].addr[0] = 70;
1265 state->CH_Ctrl[6].bit[0] = 4;
1266 state->CH_Ctrl[6].val[0] = 1;
1267
1268 state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1269 state->CH_Ctrl[7].size = 1 ;
1270 state->CH_Ctrl[7].addr[0] = 111;
1271 state->CH_Ctrl[7].bit[0] = 4;
1272 state->CH_Ctrl[7].val[0] = 0;
1273
1274 state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1275 state->CH_Ctrl[8].size = 1 ;
1276 state->CH_Ctrl[8].addr[0] = 111;
1277 state->CH_Ctrl[8].bit[0] = 7;
1278 state->CH_Ctrl[8].val[0] = 1;
1279
1280 state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1281 state->CH_Ctrl[9].size = 1 ;
1282 state->CH_Ctrl[9].addr[0] = 111;
1283 state->CH_Ctrl[9].bit[0] = 6;
1284 state->CH_Ctrl[9].val[0] = 1;
1285
1286 state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1287 state->CH_Ctrl[10].size = 1 ;
1288 state->CH_Ctrl[10].addr[0] = 111;
1289 state->CH_Ctrl[10].bit[0] = 5;
1290 state->CH_Ctrl[10].val[0] = 0;
1291
1292 state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1293 state->CH_Ctrl[11].size = 2 ;
1294 state->CH_Ctrl[11].addr[0] = 110;
1295 state->CH_Ctrl[11].bit[0] = 0;
1296 state->CH_Ctrl[11].val[0] = 1;
1297 state->CH_Ctrl[11].addr[1] = 110;
1298 state->CH_Ctrl[11].bit[1] = 1;
1299 state->CH_Ctrl[11].val[1] = 0;
1300
1301 state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1302 state->CH_Ctrl[12].size = 3 ;
1303 state->CH_Ctrl[12].addr[0] = 69;
1304 state->CH_Ctrl[12].bit[0] = 2;
1305 state->CH_Ctrl[12].val[0] = 0;
1306 state->CH_Ctrl[12].addr[1] = 69;
1307 state->CH_Ctrl[12].bit[1] = 3;
1308 state->CH_Ctrl[12].val[1] = 0;
1309 state->CH_Ctrl[12].addr[2] = 69;
1310 state->CH_Ctrl[12].bit[2] = 4;
1311 state->CH_Ctrl[12].val[2] = 0;
1312
1313 state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1314 state->CH_Ctrl[13].size = 6 ;
1315 state->CH_Ctrl[13].addr[0] = 110;
1316 state->CH_Ctrl[13].bit[0] = 2;
1317 state->CH_Ctrl[13].val[0] = 0;
1318 state->CH_Ctrl[13].addr[1] = 110;
1319 state->CH_Ctrl[13].bit[1] = 3;
1320 state->CH_Ctrl[13].val[1] = 0;
1321 state->CH_Ctrl[13].addr[2] = 110;
1322 state->CH_Ctrl[13].bit[2] = 4;
1323 state->CH_Ctrl[13].val[2] = 0;
1324 state->CH_Ctrl[13].addr[3] = 110;
1325 state->CH_Ctrl[13].bit[3] = 5;
1326 state->CH_Ctrl[13].val[3] = 0;
1327 state->CH_Ctrl[13].addr[4] = 110;
1328 state->CH_Ctrl[13].bit[4] = 6;
1329 state->CH_Ctrl[13].val[4] = 0;
1330 state->CH_Ctrl[13].addr[5] = 110;
1331 state->CH_Ctrl[13].bit[5] = 7;
1332 state->CH_Ctrl[13].val[5] = 1;
1333
1334 state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1335 state->CH_Ctrl[14].size = 7 ;
1336 state->CH_Ctrl[14].addr[0] = 14;
1337 state->CH_Ctrl[14].bit[0] = 0;
1338 state->CH_Ctrl[14].val[0] = 0;
1339 state->CH_Ctrl[14].addr[1] = 14;
1340 state->CH_Ctrl[14].bit[1] = 1;
1341 state->CH_Ctrl[14].val[1] = 0;
1342 state->CH_Ctrl[14].addr[2] = 14;
1343 state->CH_Ctrl[14].bit[2] = 2;
1344 state->CH_Ctrl[14].val[2] = 0;
1345 state->CH_Ctrl[14].addr[3] = 14;
1346 state->CH_Ctrl[14].bit[3] = 3;
1347 state->CH_Ctrl[14].val[3] = 0;
1348 state->CH_Ctrl[14].addr[4] = 14;
1349 state->CH_Ctrl[14].bit[4] = 4;
1350 state->CH_Ctrl[14].val[4] = 0;
1351 state->CH_Ctrl[14].addr[5] = 14;
1352 state->CH_Ctrl[14].bit[5] = 5;
1353 state->CH_Ctrl[14].val[5] = 0;
1354 state->CH_Ctrl[14].addr[6] = 14;
1355 state->CH_Ctrl[14].bit[6] = 6;
1356 state->CH_Ctrl[14].val[6] = 0;
1357
1358 state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1359 state->CH_Ctrl[15].size = 18 ;
1360 state->CH_Ctrl[15].addr[0] = 17;
1361 state->CH_Ctrl[15].bit[0] = 6;
1362 state->CH_Ctrl[15].val[0] = 0;
1363 state->CH_Ctrl[15].addr[1] = 17;
1364 state->CH_Ctrl[15].bit[1] = 7;
1365 state->CH_Ctrl[15].val[1] = 0;
1366 state->CH_Ctrl[15].addr[2] = 16;
1367 state->CH_Ctrl[15].bit[2] = 0;
1368 state->CH_Ctrl[15].val[2] = 0;
1369 state->CH_Ctrl[15].addr[3] = 16;
1370 state->CH_Ctrl[15].bit[3] = 1;
1371 state->CH_Ctrl[15].val[3] = 0;
1372 state->CH_Ctrl[15].addr[4] = 16;
1373 state->CH_Ctrl[15].bit[4] = 2;
1374 state->CH_Ctrl[15].val[4] = 0;
1375 state->CH_Ctrl[15].addr[5] = 16;
1376 state->CH_Ctrl[15].bit[5] = 3;
1377 state->CH_Ctrl[15].val[5] = 0;
1378 state->CH_Ctrl[15].addr[6] = 16;
1379 state->CH_Ctrl[15].bit[6] = 4;
1380 state->CH_Ctrl[15].val[6] = 0;
1381 state->CH_Ctrl[15].addr[7] = 16;
1382 state->CH_Ctrl[15].bit[7] = 5;
1383 state->CH_Ctrl[15].val[7] = 0;
1384 state->CH_Ctrl[15].addr[8] = 16;
1385 state->CH_Ctrl[15].bit[8] = 6;
1386 state->CH_Ctrl[15].val[8] = 0;
1387 state->CH_Ctrl[15].addr[9] = 16;
1388 state->CH_Ctrl[15].bit[9] = 7;
1389 state->CH_Ctrl[15].val[9] = 0;
1390 state->CH_Ctrl[15].addr[10] = 15;
1391 state->CH_Ctrl[15].bit[10] = 0;
1392 state->CH_Ctrl[15].val[10] = 0;
1393 state->CH_Ctrl[15].addr[11] = 15;
1394 state->CH_Ctrl[15].bit[11] = 1;
1395 state->CH_Ctrl[15].val[11] = 0;
1396 state->CH_Ctrl[15].addr[12] = 15;
1397 state->CH_Ctrl[15].bit[12] = 2;
1398 state->CH_Ctrl[15].val[12] = 0;
1399 state->CH_Ctrl[15].addr[13] = 15;
1400 state->CH_Ctrl[15].bit[13] = 3;
1401 state->CH_Ctrl[15].val[13] = 0;
1402 state->CH_Ctrl[15].addr[14] = 15;
1403 state->CH_Ctrl[15].bit[14] = 4;
1404 state->CH_Ctrl[15].val[14] = 0;
1405 state->CH_Ctrl[15].addr[15] = 15;
1406 state->CH_Ctrl[15].bit[15] = 5;
1407 state->CH_Ctrl[15].val[15] = 0;
1408 state->CH_Ctrl[15].addr[16] = 15;
1409 state->CH_Ctrl[15].bit[16] = 6;
1410 state->CH_Ctrl[15].val[16] = 1;
1411 state->CH_Ctrl[15].addr[17] = 15;
1412 state->CH_Ctrl[15].bit[17] = 7;
1413 state->CH_Ctrl[15].val[17] = 1;
1414
1415 state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1416 state->CH_Ctrl[16].size = 5 ;
1417 state->CH_Ctrl[16].addr[0] = 112;
1418 state->CH_Ctrl[16].bit[0] = 0;
1419 state->CH_Ctrl[16].val[0] = 0;
1420 state->CH_Ctrl[16].addr[1] = 112;
1421 state->CH_Ctrl[16].bit[1] = 1;
1422 state->CH_Ctrl[16].val[1] = 0;
1423 state->CH_Ctrl[16].addr[2] = 112;
1424 state->CH_Ctrl[16].bit[2] = 2;
1425 state->CH_Ctrl[16].val[2] = 0;
1426 state->CH_Ctrl[16].addr[3] = 112;
1427 state->CH_Ctrl[16].bit[3] = 3;
1428 state->CH_Ctrl[16].val[3] = 0;
1429 state->CH_Ctrl[16].addr[4] = 112;
1430 state->CH_Ctrl[16].bit[4] = 4;
1431 state->CH_Ctrl[16].val[4] = 1;
1432
1433 state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1434 state->CH_Ctrl[17].size = 1 ;
1435 state->CH_Ctrl[17].addr[0] = 14;
1436 state->CH_Ctrl[17].bit[0] = 7;
1437 state->CH_Ctrl[17].val[0] = 0;
1438
1439 state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1440 state->CH_Ctrl[18].size = 4 ;
1441 state->CH_Ctrl[18].addr[0] = 107;
1442 state->CH_Ctrl[18].bit[0] = 3;
1443 state->CH_Ctrl[18].val[0] = 0;
1444 state->CH_Ctrl[18].addr[1] = 107;
1445 state->CH_Ctrl[18].bit[1] = 4;
1446 state->CH_Ctrl[18].val[1] = 0;
1447 state->CH_Ctrl[18].addr[2] = 107;
1448 state->CH_Ctrl[18].bit[2] = 5;
1449 state->CH_Ctrl[18].val[2] = 0;
1450 state->CH_Ctrl[18].addr[3] = 107;
1451 state->CH_Ctrl[18].bit[3] = 6;
1452 state->CH_Ctrl[18].val[3] = 0;
1453
1454 state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1455 state->CH_Ctrl[19].size = 3 ;
1456 state->CH_Ctrl[19].addr[0] = 107;
1457 state->CH_Ctrl[19].bit[0] = 7;
1458 state->CH_Ctrl[19].val[0] = 1;
1459 state->CH_Ctrl[19].addr[1] = 106;
1460 state->CH_Ctrl[19].bit[1] = 0;
1461 state->CH_Ctrl[19].val[1] = 1;
1462 state->CH_Ctrl[19].addr[2] = 106;
1463 state->CH_Ctrl[19].bit[2] = 1;
1464 state->CH_Ctrl[19].val[2] = 1;
1465
1466 state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1467 state->CH_Ctrl[20].size = 11 ;
1468 state->CH_Ctrl[20].addr[0] = 109;
1469 state->CH_Ctrl[20].bit[0] = 2;
1470 state->CH_Ctrl[20].val[0] = 0;
1471 state->CH_Ctrl[20].addr[1] = 109;
1472 state->CH_Ctrl[20].bit[1] = 3;
1473 state->CH_Ctrl[20].val[1] = 0;
1474 state->CH_Ctrl[20].addr[2] = 109;
1475 state->CH_Ctrl[20].bit[2] = 4;
1476 state->CH_Ctrl[20].val[2] = 0;
1477 state->CH_Ctrl[20].addr[3] = 109;
1478 state->CH_Ctrl[20].bit[3] = 5;
1479 state->CH_Ctrl[20].val[3] = 0;
1480 state->CH_Ctrl[20].addr[4] = 109;
1481 state->CH_Ctrl[20].bit[4] = 6;
1482 state->CH_Ctrl[20].val[4] = 0;
1483 state->CH_Ctrl[20].addr[5] = 109;
1484 state->CH_Ctrl[20].bit[5] = 7;
1485 state->CH_Ctrl[20].val[5] = 0;
1486 state->CH_Ctrl[20].addr[6] = 108;
1487 state->CH_Ctrl[20].bit[6] = 0;
1488 state->CH_Ctrl[20].val[6] = 0;
1489 state->CH_Ctrl[20].addr[7] = 108;
1490 state->CH_Ctrl[20].bit[7] = 1;
1491 state->CH_Ctrl[20].val[7] = 0;
1492 state->CH_Ctrl[20].addr[8] = 108;
1493 state->CH_Ctrl[20].bit[8] = 2;
1494 state->CH_Ctrl[20].val[8] = 1;
1495 state->CH_Ctrl[20].addr[9] = 108;
1496 state->CH_Ctrl[20].bit[9] = 3;
1497 state->CH_Ctrl[20].val[9] = 1;
1498 state->CH_Ctrl[20].addr[10] = 108;
1499 state->CH_Ctrl[20].bit[10] = 4;
1500 state->CH_Ctrl[20].val[10] = 1;
1501
1502 state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1503 state->CH_Ctrl[21].size = 6 ;
1504 state->CH_Ctrl[21].addr[0] = 106;
1505 state->CH_Ctrl[21].bit[0] = 2;
1506 state->CH_Ctrl[21].val[0] = 0;
1507 state->CH_Ctrl[21].addr[1] = 106;
1508 state->CH_Ctrl[21].bit[1] = 3;
1509 state->CH_Ctrl[21].val[1] = 0;
1510 state->CH_Ctrl[21].addr[2] = 106;
1511 state->CH_Ctrl[21].bit[2] = 4;
1512 state->CH_Ctrl[21].val[2] = 0;
1513 state->CH_Ctrl[21].addr[3] = 106;
1514 state->CH_Ctrl[21].bit[3] = 5;
1515 state->CH_Ctrl[21].val[3] = 0;
1516 state->CH_Ctrl[21].addr[4] = 106;
1517 state->CH_Ctrl[21].bit[4] = 6;
1518 state->CH_Ctrl[21].val[4] = 0;
1519 state->CH_Ctrl[21].addr[5] = 106;
1520 state->CH_Ctrl[21].bit[5] = 7;
1521 state->CH_Ctrl[21].val[5] = 1;
1522
1523 state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1524 state->CH_Ctrl[22].size = 1 ;
1525 state->CH_Ctrl[22].addr[0] = 138;
1526 state->CH_Ctrl[22].bit[0] = 4;
1527 state->CH_Ctrl[22].val[0] = 1;
1528
1529 state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1530 state->CH_Ctrl[23].size = 1 ;
1531 state->CH_Ctrl[23].addr[0] = 17;
1532 state->CH_Ctrl[23].bit[0] = 5;
1533 state->CH_Ctrl[23].val[0] = 0;
1534
1535 state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1536 state->CH_Ctrl[24].size = 1 ;
1537 state->CH_Ctrl[24].addr[0] = 111;
1538 state->CH_Ctrl[24].bit[0] = 3;
1539 state->CH_Ctrl[24].val[0] = 0;
1540
1541 state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1542 state->CH_Ctrl[25].size = 1 ;
1543 state->CH_Ctrl[25].addr[0] = 112;
1544 state->CH_Ctrl[25].bit[0] = 7;
1545 state->CH_Ctrl[25].val[0] = 0;
1546
1547 state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1548 state->CH_Ctrl[26].size = 1 ;
1549 state->CH_Ctrl[26].addr[0] = 136;
1550 state->CH_Ctrl[26].bit[0] = 7;
1551 state->CH_Ctrl[26].val[0] = 0;
1552
1553 state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1554 state->CH_Ctrl[27].size = 1 ;
1555 state->CH_Ctrl[27].addr[0] = 149;
1556 state->CH_Ctrl[27].bit[0] = 7;
1557 state->CH_Ctrl[27].val[0] = 0;
1558
1559 state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1560 state->CH_Ctrl[28].size = 1 ;
1561 state->CH_Ctrl[28].addr[0] = 149;
1562 state->CH_Ctrl[28].bit[0] = 6;
1563 state->CH_Ctrl[28].val[0] = 0;
1564
1565 state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1566 state->CH_Ctrl[29].size = 1 ;
1567 state->CH_Ctrl[29].addr[0] = 149;
1568 state->CH_Ctrl[29].bit[0] = 5;
1569 state->CH_Ctrl[29].val[0] = 1;
1570
1571 state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1572 state->CH_Ctrl[30].size = 1 ;
1573 state->CH_Ctrl[30].addr[0] = 149;
1574 state->CH_Ctrl[30].bit[0] = 4;
1575 state->CH_Ctrl[30].val[0] = 1;
1576
1577 state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1578 state->CH_Ctrl[31].size = 1 ;
1579 state->CH_Ctrl[31].addr[0] = 149;
1580 state->CH_Ctrl[31].bit[0] = 3;
1581 state->CH_Ctrl[31].val[0] = 0;
1582
1583 state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1584 state->CH_Ctrl[32].size = 1 ;
1585 state->CH_Ctrl[32].addr[0] = 93;
1586 state->CH_Ctrl[32].bit[0] = 1;
1587 state->CH_Ctrl[32].val[0] = 0;
1588
1589 state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1590 state->CH_Ctrl[33].size = 1 ;
1591 state->CH_Ctrl[33].addr[0] = 93;
1592 state->CH_Ctrl[33].bit[0] = 0;
1593 state->CH_Ctrl[33].val[0] = 0;
1594
1595 state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1596 state->CH_Ctrl[34].size = 6 ;
1597 state->CH_Ctrl[34].addr[0] = 92;
1598 state->CH_Ctrl[34].bit[0] = 2;
1599 state->CH_Ctrl[34].val[0] = 0;
1600 state->CH_Ctrl[34].addr[1] = 92;
1601 state->CH_Ctrl[34].bit[1] = 3;
1602 state->CH_Ctrl[34].val[1] = 0;
1603 state->CH_Ctrl[34].addr[2] = 92;
1604 state->CH_Ctrl[34].bit[2] = 4;
1605 state->CH_Ctrl[34].val[2] = 0;
1606 state->CH_Ctrl[34].addr[3] = 92;
1607 state->CH_Ctrl[34].bit[3] = 5;
1608 state->CH_Ctrl[34].val[3] = 0;
1609 state->CH_Ctrl[34].addr[4] = 92;
1610 state->CH_Ctrl[34].bit[4] = 6;
1611 state->CH_Ctrl[34].val[4] = 0;
1612 state->CH_Ctrl[34].addr[5] = 92;
1613 state->CH_Ctrl[34].bit[5] = 7;
1614 state->CH_Ctrl[34].val[5] = 0;
1615
1616 state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1617 state->CH_Ctrl[35].size = 6 ;
1618 state->CH_Ctrl[35].addr[0] = 93;
1619 state->CH_Ctrl[35].bit[0] = 2;
1620 state->CH_Ctrl[35].val[0] = 0;
1621 state->CH_Ctrl[35].addr[1] = 93;
1622 state->CH_Ctrl[35].bit[1] = 3;
1623 state->CH_Ctrl[35].val[1] = 0;
1624 state->CH_Ctrl[35].addr[2] = 93;
1625 state->CH_Ctrl[35].bit[2] = 4;
1626 state->CH_Ctrl[35].val[2] = 0;
1627 state->CH_Ctrl[35].addr[3] = 93;
1628 state->CH_Ctrl[35].bit[3] = 5;
1629 state->CH_Ctrl[35].val[3] = 0;
1630 state->CH_Ctrl[35].addr[4] = 93;
1631 state->CH_Ctrl[35].bit[4] = 6;
1632 state->CH_Ctrl[35].val[4] = 0;
1633 state->CH_Ctrl[35].addr[5] = 93;
1634 state->CH_Ctrl[35].bit[5] = 7;
1635 state->CH_Ctrl[35].val[5] = 0;
1636
1637#ifdef _MXL_PRODUCTION
1638 state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1639 state->CH_Ctrl[36].size = 1 ;
1640 state->CH_Ctrl[36].addr[0] = 109;
1641 state->CH_Ctrl[36].bit[0] = 1;
1642 state->CH_Ctrl[36].val[0] = 1;
1643
1644 state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1645 state->CH_Ctrl[37].size = 2 ;
1646 state->CH_Ctrl[37].addr[0] = 112;
1647 state->CH_Ctrl[37].bit[0] = 5;
1648 state->CH_Ctrl[37].val[0] = 0;
1649 state->CH_Ctrl[37].addr[1] = 112;
1650 state->CH_Ctrl[37].bit[1] = 6;
1651 state->CH_Ctrl[37].val[1] = 0;
1652
1653 state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1654 state->CH_Ctrl[38].size = 1 ;
1655 state->CH_Ctrl[38].addr[0] = 65;
1656 state->CH_Ctrl[38].bit[0] = 1;
1657 state->CH_Ctrl[38].val[0] = 0;
1658#endif
1659
1660 return 0 ;
1661}
1662
1663static void InitTunerControls(struct dvb_frontend *fe)
1664{
1665 MXL5005_RegisterInit(fe);
1666 MXL5005_ControlInit(fe);
1667#ifdef _MXL_INTERNAL
1668 MXL5005_MXLControlInit(fe);
1669#endif
1670}
1671
1672static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1673 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
1674 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
1675 u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
1676 u32 IF_out, /* Desired IF Out Frequency */
1677 u32 Fxtal, /* XTAL Frequency */
1678 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1679 u16 TOP, /* 0: Dual AGC; Value: take over point */
1680 u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
1681 u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */
1682 u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
1683 u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
1684 u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
1685
1686 /* Modulation Type; */
1687 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1688 u8 Mod_Type,
1689
1690 /* Tracking Filter */
1691 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
1692 u8 TF_Type
1693 )
1694{
1695 struct mxl5005s_state *state = fe->tuner_priv;
1696 u16 status = 0;
1697
1698 state->Mode = Mode;
1699 state->IF_Mode = IF_mode;
1700 state->Chan_Bandwidth = Bandwidth;
1701 state->IF_OUT = IF_out;
1702 state->Fxtal = Fxtal;
1703 state->AGC_Mode = AGC_Mode;
1704 state->TOP = TOP;
1705 state->IF_OUT_LOAD = IF_OUT_LOAD;
1706 state->CLOCK_OUT = CLOCK_OUT;
1707 state->DIV_OUT = DIV_OUT;
1708 state->CAPSELECT = CAPSELECT;
1709 state->EN_RSSI = EN_RSSI;
1710 state->Mod_Type = Mod_Type;
1711 state->TF_Type = TF_Type;
1712
1713 /* Initialize all the controls and registers */
1714 InitTunerControls(fe);
1715
1716 /* Synthesizer LO frequency calculation */
1717 MXL_SynthIFLO_Calc(fe);
1718
1719 return status;
1720}
1721
1722static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1723{
1724 struct mxl5005s_state *state = fe->tuner_priv;
1725 if (state->Mode == 1) /* Digital Mode */
1726 state->IF_LO = state->IF_OUT;
1727 else /* Analog Mode */ {
1728 if (state->IF_Mode == 0) /* Analog Zero IF mode */
1729 state->IF_LO = state->IF_OUT + 400000;
1730 else /* Analog Low IF mode */
1731 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1732 }
1733}
1734
1735static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1736{
1737 struct mxl5005s_state *state = fe->tuner_priv;
1738
1739 if (state->Mode == 1) /* Digital Mode */ {
1740 /* remove 20.48MHz setting for 2.6.10 */
1741 state->RF_LO = state->RF_IN;
1742 /* change for 2.6.6 */
1743 state->TG_LO = state->RF_IN - 750000;
1744 } else /* Analog Mode */ {
1745 if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
1746 state->RF_LO = state->RF_IN - 400000;
1747 state->TG_LO = state->RF_IN - 1750000;
1748 } else /* Analog Low IF mode */ {
1749 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1750 state->TG_LO = state->RF_IN -
1751 state->Chan_Bandwidth + 500000;
1752 }
1753 }
1754}
1755
1756static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1757{
1758 u16 status = 0;
1759
1760 status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1761 status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1762 status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1763 status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
1764
1765 return status;
1766}
1767
1768static u16 MXL_BlockInit(struct dvb_frontend *fe)
1769{
1770 struct mxl5005s_state *state = fe->tuner_priv;
1771 u16 status = 0;
1772
1773 status += MXL_OverwriteICDefault(fe);
1774
1775 /* Downconverter Control Dig Ana */
1776 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1777
1778 /* Filter Control Dig Ana */
1779 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1780 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1781 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1782 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1783 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1784
1785 /* Initialize Low-Pass Filter */
1786 if (state->Mode) { /* Digital Mode */
1787 switch (state->Chan_Bandwidth) {
1788 case 8000000:
1789 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1790 break;
1791 case 7000000:
1792 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1793 break;
1794 case 6000000:
1795 status += MXL_ControlWrite(fe,
1796 BB_DLPF_BANDSEL, 3);
1797 break;
1798 }
1799 } else { /* Analog Mode */
1800 switch (state->Chan_Bandwidth) {
1801 case 8000000: /* Low Zero */
1802 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1803 (state->IF_Mode ? 0 : 3));
1804 break;
1805 case 7000000:
1806 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1807 (state->IF_Mode ? 1 : 4));
1808 break;
1809 case 6000000:
1810 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1811 (state->IF_Mode ? 2 : 5));
1812 break;
1813 }
1814 }
1815
1816 /* Charge Pump Control Dig Ana */
1817 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1818 status += MXL_ControlWrite(fe,
1819 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1820 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1821
1822 /* AGC TOP Control */
1823 if (state->AGC_Mode == 0) /* Dual AGC */ {
1824 status += MXL_ControlWrite(fe, AGC_IF, 15);
1825 status += MXL_ControlWrite(fe, AGC_RF, 15);
1826 } else /* Single AGC Mode Dig Ana */
1827 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1828
1829 if (state->TOP == 55) /* TOP == 5.5 */
1830 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
1831
1832 if (state->TOP == 72) /* TOP == 7.2 */
1833 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
1834
1835 if (state->TOP == 92) /* TOP == 9.2 */
1836 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
1837
1838 if (state->TOP == 110) /* TOP == 11.0 */
1839 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
1840
1841 if (state->TOP == 129) /* TOP == 12.9 */
1842 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
1843
1844 if (state->TOP == 147) /* TOP == 14.7 */
1845 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
1846
1847 if (state->TOP == 168) /* TOP == 16.8 */
1848 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
1849
1850 if (state->TOP == 194) /* TOP == 19.4 */
1851 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
1852
1853 if (state->TOP == 212) /* TOP == 21.2 */
1854 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
1855
1856 if (state->TOP == 232) /* TOP == 23.2 */
1857 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
1858
1859 if (state->TOP == 252) /* TOP == 25.2 */
1860 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
1861
1862 if (state->TOP == 271) /* TOP == 27.1 */
1863 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
1864
1865 if (state->TOP == 292) /* TOP == 29.2 */
1866 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
1867
1868 if (state->TOP == 317) /* TOP == 31.7 */
1869 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
1870
1871 if (state->TOP == 349) /* TOP == 34.9 */
1872 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
1873
1874 /* IF Synthesizer Control */
1875 status += MXL_IFSynthInit(fe);
1876
1877 /* IF UpConverter Control */
1878 if (state->IF_OUT_LOAD == 200) {
1879 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
1880 status += MXL_ControlWrite(fe, I_DRIVER, 2);
1881 }
1882 if (state->IF_OUT_LOAD == 300) {
1883 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
1884 status += MXL_ControlWrite(fe, I_DRIVER, 1);
1885 }
1886
1887 /* Anti-Alias Filtering Control
1888 * initialise Anti-Aliasing Filter
1889 */
1890 if (state->Mode) { /* Digital Mode */
1891 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
1892 status += MXL_ControlWrite(fe, EN_AAF, 1);
1893 status += MXL_ControlWrite(fe, EN_3P, 1);
1894 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1895 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1896 }
1897 if ((state->IF_OUT == 36125000UL) ||
1898 (state->IF_OUT == 36150000UL)) {
1899 status += MXL_ControlWrite(fe, EN_AAF, 1);
1900 status += MXL_ControlWrite(fe, EN_3P, 1);
1901 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1902 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1903 }
1904 if (state->IF_OUT > 36150000UL) {
1905 status += MXL_ControlWrite(fe, EN_AAF, 0);
1906 status += MXL_ControlWrite(fe, EN_3P, 1);
1907 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1908 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1909 }
1910 } else { /* Analog Mode */
1911 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
1912 status += MXL_ControlWrite(fe, EN_AAF, 1);
1913 status += MXL_ControlWrite(fe, EN_3P, 1);
1914 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1915 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1916 }
1917 if (state->IF_OUT > 5000000UL) {
1918 status += MXL_ControlWrite(fe, EN_AAF, 0);
1919 status += MXL_ControlWrite(fe, EN_3P, 0);
1920 status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
1921 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1922 }
1923 }
1924
1925 /* Demod Clock Out */
1926 if (state->CLOCK_OUT)
1927 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
1928 else
1929 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
1930
1931 if (state->DIV_OUT == 1)
1932 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
1933 if (state->DIV_OUT == 0)
1934 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
1935
1936 /* Crystal Control */
1937 if (state->CAPSELECT)
1938 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
1939 else
1940 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
1941
1942 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
1943 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
1944 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
1945 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
1946
1947 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
1948 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
1949 if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
1950 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
1951
1952 /* Misc Controls */
1953 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
1954 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
1955 else
1956 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
1957
1958 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
1959
1960 /* Set TG_R_DIV */
1961 status += MXL_ControlWrite(fe, TG_R_DIV,
1962 MXL_Ceiling(state->Fxtal, 1000000));
1963
1964 /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
1965
1966 /* RSSI Control */
1967 if (state->EN_RSSI) {
1968 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1969 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1970 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1971 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1972
1973 /* RSSI reference point */
1974 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
1975 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
1976 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1977
1978 /* TOP point */
1979 status += MXL_ControlWrite(fe, RFA_FLR, 0);
1980 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
1981 }
1982
1983 /* Modulation type bit settings
1984 * Override the control values preset
1985 */
1986 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
1987 state->AGC_Mode = 1; /* Single AGC Mode */
1988
1989 /* Enable RSSI */
1990 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1991 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1992 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1993 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1994
1995 /* RSSI reference point */
1996 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
1997 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
1998 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1999
2000 /* TOP point */
2001 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2002 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2003 if (state->IF_OUT <= 6280000UL) /* Low IF */
2004 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2005 else /* High IF */
2006 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2007
2008 }
2009 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
2010 state->AGC_Mode = 1; /* Single AGC Mode */
2011
2012 /* Enable RSSI */
2013 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2014 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2015 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2016 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2017
2018 /* RSSI reference point */
2019 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2020 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2021 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2022
2023 /* TOP point */
2024 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2025 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2026 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2027 /* Low Zero */
2028 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
2029
2030 if (state->IF_OUT <= 6280000UL) /* Low IF */
2031 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2032 else /* High IF */
2033 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2034 }
2035 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
2036 state->Mode = MXL_DIGITAL_MODE;
2037
2038 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2039
2040 /* Disable RSSI */ /* change here for v2.6.5 */
2041 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2042 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2043 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2044 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2045
2046 /* RSSI reference point */
2047 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2048 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2049 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2050 /* change here for v2.6.5 */
2051 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2052
2053 if (state->IF_OUT <= 6280000UL) /* Low IF */
2054 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2055 else /* High IF */
2056 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2057 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2058
2059 }
2060 if (state->Mod_Type == MXL_ANALOG_CABLE) {
2061 /* Analog Cable Mode */
2062 /* state->Mode = MXL_DIGITAL_MODE; */
2063
2064 state->AGC_Mode = 1; /* Single AGC Mode */
2065
2066 /* Disable RSSI */
2067 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2068 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2069 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2070 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2071 /* change for 2.6.3 */
2072 status += MXL_ControlWrite(fe, AGC_IF, 1);
2073 status += MXL_ControlWrite(fe, AGC_RF, 15);
2074 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2075 }
2076
2077 if (state->Mod_Type == MXL_ANALOG_OTA) {
2078 /* Analog OTA Terrestrial mode add for 2.6.7 */
2079 /* state->Mode = MXL_ANALOG_MODE; */
2080
2081 /* Enable RSSI */
2082 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2083 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2084 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2085 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2086
2087 /* RSSI reference point */
2088 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2089 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2090 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2091 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2092 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2093 }
2094
2095 /* RSSI disable */
2096 if (state->EN_RSSI == 0) {
2097 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2098 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2099 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2100 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2101 }
2102
2103 return status;
2104}
2105
2106static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2107{
2108 struct mxl5005s_state *state = fe->tuner_priv;
2109 u16 status = 0 ;
2110 u32 Fref = 0 ;
2111 u32 Kdbl, intModVal ;
2112 u32 fracModVal ;
2113 Kdbl = 2 ;
2114
2115 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2116 Kdbl = 2 ;
2117 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2118 Kdbl = 1 ;
2119
2120 /* IF Synthesizer Control */
2121 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
2122 if (state->IF_LO == 41000000UL) {
2123 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2124 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2125 Fref = 328000000UL ;
2126 }
2127 if (state->IF_LO == 47000000UL) {
2128 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2129 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2130 Fref = 376000000UL ;
2131 }
2132 if (state->IF_LO == 54000000UL) {
2133 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2134 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2135 Fref = 324000000UL ;
2136 }
2137 if (state->IF_LO == 60000000UL) {
2138 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2139 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2140 Fref = 360000000UL ;
2141 }
2142 if (state->IF_LO == 39250000UL) {
2143 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2144 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2145 Fref = 314000000UL ;
2146 }
2147 if (state->IF_LO == 39650000UL) {
2148 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2149 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2150 Fref = 317200000UL ;
2151 }
2152 if (state->IF_LO == 40150000UL) {
2153 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2154 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2155 Fref = 321200000UL ;
2156 }
2157 if (state->IF_LO == 40650000UL) {
2158 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2159 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2160 Fref = 325200000UL ;
2161 }
2162 }
2163
2164 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
2165 if (state->IF_LO == 57000000UL) {
2166 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2167 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2168 Fref = 342000000UL ;
2169 }
2170 if (state->IF_LO == 44000000UL) {
2171 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2172 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2173 Fref = 352000000UL ;
2174 }
2175 if (state->IF_LO == 43750000UL) {
2176 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2177 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2178 Fref = 350000000UL ;
2179 }
2180 if (state->IF_LO == 36650000UL) {
2181 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2182 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2183 Fref = 366500000UL ;
2184 }
2185 if (state->IF_LO == 36150000UL) {
2186 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2187 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2188 Fref = 361500000UL ;
2189 }
2190 if (state->IF_LO == 36000000UL) {
2191 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2192 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2193 Fref = 360000000UL ;
2194 }
2195 if (state->IF_LO == 35250000UL) {
2196 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2197 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2198 Fref = 352500000UL ;
2199 }
2200 if (state->IF_LO == 34750000UL) {
2201 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2202 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2203 Fref = 347500000UL ;
2204 }
2205 if (state->IF_LO == 6280000UL) {
2206 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2207 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2208 Fref = 376800000UL ;
2209 }
2210 if (state->IF_LO == 5000000UL) {
2211 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2212 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2213 Fref = 360000000UL ;
2214 }
2215 if (state->IF_LO == 4500000UL) {
2216 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2217 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2218 Fref = 360000000UL ;
2219 }
2220 if (state->IF_LO == 4570000UL) {
2221 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2222 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2223 Fref = 365600000UL ;
2224 }
2225 if (state->IF_LO == 4000000UL) {
2226 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2227 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2228 Fref = 360000000UL ;
2229 }
2230 if (state->IF_LO == 57400000UL) {
2231 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2232 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2233 Fref = 344400000UL ;
2234 }
2235 if (state->IF_LO == 44400000UL) {
2236 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2237 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2238 Fref = 355200000UL ;
2239 }
2240 if (state->IF_LO == 44150000UL) {
2241 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2242 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2243 Fref = 353200000UL ;
2244 }
2245 if (state->IF_LO == 37050000UL) {
2246 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2247 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2248 Fref = 370500000UL ;
2249 }
2250 if (state->IF_LO == 36550000UL) {
2251 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2252 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2253 Fref = 365500000UL ;
2254 }
2255 if (state->IF_LO == 36125000UL) {
2256 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2257 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2258 Fref = 361250000UL ;
2259 }
2260 if (state->IF_LO == 6000000UL) {
2261 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2262 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2263 Fref = 360000000UL ;
2264 }
2265 if (state->IF_LO == 5400000UL) {
2266 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2267 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2268 Fref = 324000000UL ;
2269 }
2270 if (state->IF_LO == 5380000UL) {
2271 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2272 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2273 Fref = 322800000UL ;
2274 }
2275 if (state->IF_LO == 5200000UL) {
2276 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2277 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2278 Fref = 374400000UL ;
2279 }
2280 if (state->IF_LO == 4900000UL) {
2281 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2282 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2283 Fref = 352800000UL ;
2284 }
2285 if (state->IF_LO == 4400000UL) {
2286 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2287 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2288 Fref = 352000000UL ;
2289 }
2290 if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ {
2291 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2292 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2293 Fref = 365670000UL ;
2294 }
2295 }
2296 /* CHCAL_INT_MOD_IF */
2297 /* CHCAL_FRAC_MOD_IF */
2298 intModVal = Fref / (state->Fxtal * Kdbl/2);
2299 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
2300
2301 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
2302 intModVal);
2303
2304 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
2305 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
2306
2307 return status ;
2308}
2309
2310static u32 MXL_GetXtalInt(u32 Xtal_Freq)
2311{
2312 if ((Xtal_Freq % 1000000) == 0)
2313 return (Xtal_Freq / 10000);
2314 else
2315 return (((Xtal_Freq / 1000000) + 1)*100);
2316}
2317
2318static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2319{
2320 struct mxl5005s_state *state = fe->tuner_priv;
2321 u16 status = 0;
2322 u32 divider_val, E3, E4, E5, E5A;
2323 u32 Fmax, Fmin, FmaxBin, FminBin;
2324 u32 Kdbl_RF = 2;
2325 u32 tg_divval;
2326 u32 tg_lo;
2327 u32 Xtal_Int;
2328
2329 u32 Fref_TG;
2330 u32 Fvco;
2331
2332 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2333
2334 state->RF_IN = RF_Freq;
2335
2336 MXL_SynthRFTGLO_Calc(fe);
2337
2338 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2339 Kdbl_RF = 2;
2340 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2341 Kdbl_RF = 1;
2342
2343 /* Downconverter Controls
2344 * Look-Up Table Implementation for:
2345 * DN_POLY
2346 * DN_RFGAIN
2347 * DN_CAP_RFLPF
2348 * DN_EN_VHFUHFBAR
2349 * DN_GAIN_ADJUST
2350 * Change the boundary reference from RF_IN to RF_LO
2351 */
2352 if (state->RF_LO < 40000000UL)
2353 return -1;
2354
2355 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2356 status += MXL_ControlWrite(fe, DN_POLY, 2);
2357 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2358 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
2359 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2360 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2361 }
2362 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2363 status += MXL_ControlWrite(fe, DN_POLY, 3);
2364 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2365 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
2366 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2367 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2368 }
2369 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2370 status += MXL_ControlWrite(fe, DN_POLY, 3);
2371 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2372 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
2373 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2374 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2375 }
2376 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2377 status += MXL_ControlWrite(fe, DN_POLY, 3);
2378 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2379 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
2380 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2381 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2382 }
2383 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2384 status += MXL_ControlWrite(fe, DN_POLY, 3);
2385 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2386 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2387 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2388 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2389 }
2390 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2391 status += MXL_ControlWrite(fe, DN_POLY, 3);
2392 status += MXL_ControlWrite(fe, DN_RFGAIN, 1);
2393 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2394 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2395 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2396 }
2397 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2398 status += MXL_ControlWrite(fe, DN_POLY, 3);
2399 status += MXL_ControlWrite(fe, DN_RFGAIN, 2);
2400 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2401 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2402 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2403 }
2404 if (state->RF_LO > 900000000UL)
2405 return -1;
2406
2407 /* DN_IQTNBUF_AMP */
2408 /* DN_IQTNGNBFBIAS_BST */
2409 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2410 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2411 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2412 }
2413 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2414 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2415 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2416 }
2417 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2418 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2419 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2420 }
2421 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2422 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2423 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2424 }
2425 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2426 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2427 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2428 }
2429 if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2430 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2431 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2432 }
2433 if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2434 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2435 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2436 }
2437 if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2438 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2439 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2440 }
2441 if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2442 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2443 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2444 }
2445 if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2446 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2447 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2448 }
2449 if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2450 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2451 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2452 }
2453 if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2454 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2455 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2456 }
2457 if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2458 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2459 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2460 }
2461 if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2462 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2463 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2464 }
2465 if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2466 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2467 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2468 }
2469 if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2470 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2471 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2472 }
2473
2474 /*
2475 * Set RF Synth and LO Path Control
2476 *
2477 * Look-Up table implementation for:
2478 * RFSYN_EN_OUTMUX
2479 * RFSYN_SEL_VCO_OUT
2480 * RFSYN_SEL_VCO_HI
2481 * RFSYN_SEL_DIVM
2482 * RFSYN_RF_DIV_BIAS
2483 * DN_SEL_FREQ
2484 *
2485 * Set divider_val, Fmax, Fmix to use in Equations
2486 */
2487 FminBin = 28000000UL ;
2488 FmaxBin = 42500000UL ;
2489 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2490 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2491 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2492 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2493 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2494 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2495 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2496 divider_val = 64 ;
2497 Fmax = FmaxBin ;
2498 Fmin = FminBin ;
2499 }
2500 FminBin = 42500000UL ;
2501 FmaxBin = 56000000UL ;
2502 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2503 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2504 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2505 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2506 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2507 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2508 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2509 divider_val = 64 ;
2510 Fmax = FmaxBin ;
2511 Fmin = FminBin ;
2512 }
2513 FminBin = 56000000UL ;
2514 FmaxBin = 85000000UL ;
2515 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2516 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2517 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2518 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2519 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2520 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2521 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2522 divider_val = 32 ;
2523 Fmax = FmaxBin ;
2524 Fmin = FminBin ;
2525 }
2526 FminBin = 85000000UL ;
2527 FmaxBin = 112000000UL ;
2528 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2529 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2530 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2531 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2532 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2533 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2534 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2535 divider_val = 32 ;
2536 Fmax = FmaxBin ;
2537 Fmin = FminBin ;
2538 }
2539 FminBin = 112000000UL ;
2540 FmaxBin = 170000000UL ;
2541 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2542 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2543 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2544 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2545 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2546 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2547 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2548 divider_val = 16 ;
2549 Fmax = FmaxBin ;
2550 Fmin = FminBin ;
2551 }
2552 FminBin = 170000000UL ;
2553 FmaxBin = 225000000UL ;
2554 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2555 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2556 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2557 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2558 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2559 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2560 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2561 divider_val = 16 ;
2562 Fmax = FmaxBin ;
2563 Fmin = FminBin ;
2564 }
2565 FminBin = 225000000UL ;
2566 FmaxBin = 300000000UL ;
2567 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2568 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2569 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2570 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2571 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2572 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2573 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4);
2574 divider_val = 8 ;
2575 Fmax = 340000000UL ;
2576 Fmin = FminBin ;
2577 }
2578 FminBin = 300000000UL ;
2579 FmaxBin = 340000000UL ;
2580 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2581 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2582 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2583 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2584 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2585 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2586 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2587 divider_val = 8 ;
2588 Fmax = FmaxBin ;
2589 Fmin = 225000000UL ;
2590 }
2591 FminBin = 340000000UL ;
2592 FmaxBin = 450000000UL ;
2593 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2594 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2595 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2596 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2597 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2598 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2);
2599 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2600 divider_val = 8 ;
2601 Fmax = FmaxBin ;
2602 Fmin = FminBin ;
2603 }
2604 FminBin = 450000000UL ;
2605 FmaxBin = 680000000UL ;
2606 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2607 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2608 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2609 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2610 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2611 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2612 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2613 divider_val = 4 ;
2614 Fmax = FmaxBin ;
2615 Fmin = FminBin ;
2616 }
2617 FminBin = 680000000UL ;
2618 FmaxBin = 900000000UL ;
2619 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2620 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2621 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2622 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2623 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2624 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2625 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2626 divider_val = 4 ;
2627 Fmax = FmaxBin ;
2628 Fmin = FminBin ;
2629 }
2630
2631 /* CHCAL_INT_MOD_RF
2632 * CHCAL_FRAC_MOD_RF
2633 * RFSYN_LPF_R
2634 * CHCAL_EN_INT_RF
2635 */
2636 /* Equation E3 RFSYN_VCO_BIAS */
2637 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2638 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
2639
2640 /* Equation E4 CHCAL_INT_MOD_RF */
2641 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
2642 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
2643
2644 /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */
2645 E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
2646 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
2647 (2*state->Fxtal*Kdbl_RF/10000);
2648
2649 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2650
2651 /* Equation E5A RFSYN_LPF_R */
2652 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2653 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
2654
2655 /* Euqation E5B CHCAL_EN_INIT_RF */
2656 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2657 /*if (E5 == 0)
2658 * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2659 *else
2660 * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2661 */
2662
2663 /*
2664 * Set TG Synth
2665 *
2666 * Look-Up table implementation for:
2667 * TG_LO_DIVVAL
2668 * TG_LO_SELVAL
2669 *
2670 * Set divider_val, Fmax, Fmix to use in Equations
2671 */
2672 if (state->TG_LO < 33000000UL)
2673 return -1;
2674
2675 FminBin = 33000000UL ;
2676 FmaxBin = 50000000UL ;
2677 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2678 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6);
2679 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2680 divider_val = 36 ;
2681 Fmax = FmaxBin ;
2682 Fmin = FminBin ;
2683 }
2684 FminBin = 50000000UL ;
2685 FmaxBin = 67000000UL ;
2686 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2687 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1);
2688 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2689 divider_val = 24 ;
2690 Fmax = FmaxBin ;
2691 Fmin = FminBin ;
2692 }
2693 FminBin = 67000000UL ;
2694 FmaxBin = 100000000UL ;
2695 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2696 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC);
2697 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2698 divider_val = 18 ;
2699 Fmax = FmaxBin ;
2700 Fmin = FminBin ;
2701 }
2702 FminBin = 100000000UL ;
2703 FmaxBin = 150000000UL ;
2704 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2705 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2706 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2707 divider_val = 12 ;
2708 Fmax = FmaxBin ;
2709 Fmin = FminBin ;
2710 }
2711 FminBin = 150000000UL ;
2712 FmaxBin = 200000000UL ;
2713 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2714 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2715 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2716 divider_val = 8 ;
2717 Fmax = FmaxBin ;
2718 Fmin = FminBin ;
2719 }
2720 FminBin = 200000000UL ;
2721 FmaxBin = 300000000UL ;
2722 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2723 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2724 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2725 divider_val = 6 ;
2726 Fmax = FmaxBin ;
2727 Fmin = FminBin ;
2728 }
2729 FminBin = 300000000UL ;
2730 FmaxBin = 400000000UL ;
2731 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2732 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2733 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2734 divider_val = 4 ;
2735 Fmax = FmaxBin ;
2736 Fmin = FminBin ;
2737 }
2738 FminBin = 400000000UL ;
2739 FmaxBin = 600000000UL ;
2740 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2741 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2742 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2743 divider_val = 3 ;
2744 Fmax = FmaxBin ;
2745 Fmin = FminBin ;
2746 }
2747 FminBin = 600000000UL ;
2748 FmaxBin = 900000000UL ;
2749 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2750 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2751 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2752 divider_val = 2 ;
2753 Fmax = FmaxBin ;
2754 Fmin = FminBin ;
2755 }
2756
2757 /* TG_DIV_VAL */
2758 tg_divval = (state->TG_LO*divider_val/100000) *
2759 (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
2760 (state->Fxtal/1000);
2761
2762 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
2763
2764 if (state->TG_LO > 600000000UL)
2765 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
2766
2767 Fmax = 1800000000UL ;
2768 Fmin = 1200000000UL ;
2769
2770 /* prevent overflow of 32 bit unsigned integer, use
2771 * following equation. Edit for v2.6.4
2772 */
2773 /* Fref_TF = Fref_TG * 1000 */
2774 Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
2775
2776 /* Fvco = Fvco/10 */
2777 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
2778
2779 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
2780
2781 /* below equation is same as above but much harder to debug.
2782 * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) -
2783 * ((state->TG_LO/10000)*divider_val *
2784 * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
2785 * Xtal_Int/100) + 8;
2786 */
2787
2788 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
2789
2790 /* add for 2.6.5 Special setting for QAM */
2791 if (state->Mod_Type == MXL_QAM) {
2792 if (state->RF_IN < 680000000)
2793 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2794 else
2795 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2796 }
2797
2798 /* Off Chip Tracking Filter Control */
2799 if (state->TF_Type == MXL_TF_OFF) {
2800 /* Tracking Filter Off State; turn off all the banks */
2801 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2802 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2803 status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
2804 status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
2805 status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
2806 }
2807
2808 if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
2809 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2810 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2811
2812 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2813 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2814 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2815 status += MXL_SetGPIO(fe, 3, 0);
2816 status += MXL_SetGPIO(fe, 1, 1);
2817 status += MXL_SetGPIO(fe, 4, 1);
2818 }
2819 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2820 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2821 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2822 status += MXL_SetGPIO(fe, 3, 1);
2823 status += MXL_SetGPIO(fe, 1, 0);
2824 status += MXL_SetGPIO(fe, 4, 1);
2825 }
2826 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2827 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2828 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2829 status += MXL_SetGPIO(fe, 3, 1);
2830 status += MXL_SetGPIO(fe, 1, 0);
2831 status += MXL_SetGPIO(fe, 4, 0);
2832 }
2833 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2834 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2835 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2836 status += MXL_SetGPIO(fe, 3, 1);
2837 status += MXL_SetGPIO(fe, 1, 1);
2838 status += MXL_SetGPIO(fe, 4, 0);
2839 }
2840 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2841 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2842 status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
2843 status += MXL_SetGPIO(fe, 3, 1);
2844 status += MXL_SetGPIO(fe, 1, 1);
2845 status += MXL_SetGPIO(fe, 4, 0);
2846 }
2847 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2848 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2849 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2850 status += MXL_SetGPIO(fe, 3, 1);
2851 status += MXL_SetGPIO(fe, 1, 1);
2852 status += MXL_SetGPIO(fe, 4, 0);
2853 }
2854 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2855 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2856 status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
2857 status += MXL_SetGPIO(fe, 3, 1);
2858 status += MXL_SetGPIO(fe, 1, 1);
2859 status += MXL_SetGPIO(fe, 4, 1);
2860 }
2861 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2862 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2863 status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
2864 status += MXL_SetGPIO(fe, 3, 1);
2865 status += MXL_SetGPIO(fe, 1, 1);
2866 status += MXL_SetGPIO(fe, 4, 1);
2867 }
2868 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2869 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2870 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2871 status += MXL_SetGPIO(fe, 3, 1);
2872 status += MXL_SetGPIO(fe, 1, 1);
2873 status += MXL_SetGPIO(fe, 4, 1);
2874 }
2875 }
2876
2877 if (state->TF_Type == MXL_TF_C_H) {
2878
2879 /* Tracking Filter type C-H for Hauppauge only */
2880 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2881
2882 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2883 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2884 status += MXL_SetGPIO(fe, 4, 0);
2885 status += MXL_SetGPIO(fe, 3, 1);
2886 status += MXL_SetGPIO(fe, 1, 1);
2887 }
2888 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2889 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2890 status += MXL_SetGPIO(fe, 4, 1);
2891 status += MXL_SetGPIO(fe, 3, 0);
2892 status += MXL_SetGPIO(fe, 1, 1);
2893 }
2894 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2895 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2896 status += MXL_SetGPIO(fe, 4, 1);
2897 status += MXL_SetGPIO(fe, 3, 0);
2898 status += MXL_SetGPIO(fe, 1, 0);
2899 }
2900 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2901 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2902 status += MXL_SetGPIO(fe, 4, 1);
2903 status += MXL_SetGPIO(fe, 3, 1);
2904 status += MXL_SetGPIO(fe, 1, 0);
2905 }
2906 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2907 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2908 status += MXL_SetGPIO(fe, 4, 1);
2909 status += MXL_SetGPIO(fe, 3, 1);
2910 status += MXL_SetGPIO(fe, 1, 0);
2911 }
2912 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2913 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2914 status += MXL_SetGPIO(fe, 4, 1);
2915 status += MXL_SetGPIO(fe, 3, 1);
2916 status += MXL_SetGPIO(fe, 1, 0);
2917 }
2918 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2919 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2920 status += MXL_SetGPIO(fe, 4, 1);
2921 status += MXL_SetGPIO(fe, 3, 1);
2922 status += MXL_SetGPIO(fe, 1, 1);
2923 }
2924 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2925 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2926 status += MXL_SetGPIO(fe, 4, 1);
2927 status += MXL_SetGPIO(fe, 3, 1);
2928 status += MXL_SetGPIO(fe, 1, 1);
2929 }
2930 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2931 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2932 status += MXL_SetGPIO(fe, 4, 1);
2933 status += MXL_SetGPIO(fe, 3, 1);
2934 status += MXL_SetGPIO(fe, 1, 1);
2935 }
2936 }
2937
2938 if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
2939
2940 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2941
2942 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
2943 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2944 status += MXL_SetGPIO(fe, 4, 0);
2945 status += MXL_SetGPIO(fe, 1, 1);
2946 status += MXL_SetGPIO(fe, 3, 1);
2947 }
2948 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
2949 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2950 status += MXL_SetGPIO(fe, 4, 0);
2951 status += MXL_SetGPIO(fe, 1, 0);
2952 status += MXL_SetGPIO(fe, 3, 1);
2953 }
2954 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
2955 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2956 status += MXL_SetGPIO(fe, 4, 1);
2957 status += MXL_SetGPIO(fe, 1, 0);
2958 status += MXL_SetGPIO(fe, 3, 1);
2959 }
2960 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
2961 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2962 status += MXL_SetGPIO(fe, 4, 1);
2963 status += MXL_SetGPIO(fe, 1, 0);
2964 status += MXL_SetGPIO(fe, 3, 0);
2965 }
2966 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
2967 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2968 status += MXL_SetGPIO(fe, 4, 1);
2969 status += MXL_SetGPIO(fe, 1, 1);
2970 status += MXL_SetGPIO(fe, 3, 0);
2971 }
2972 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
2973 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2974 status += MXL_SetGPIO(fe, 4, 1);
2975 status += MXL_SetGPIO(fe, 1, 1);
2976 status += MXL_SetGPIO(fe, 3, 0);
2977 }
2978 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
2979 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2980 status += MXL_SetGPIO(fe, 4, 1);
2981 status += MXL_SetGPIO(fe, 1, 1);
2982 status += MXL_SetGPIO(fe, 3, 1);
2983 }
2984 }
2985
2986 if (state->TF_Type == MXL_TF_D_L) {
2987
2988 /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */
2989 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2990
2991 /* if UHF and terrestrial => Turn off Tracking Filter */
2992 if (state->RF_IN >= 471000000 &&
2993 (state->RF_IN - 471000000)%6000000 != 0) {
2994 /* Turn off all the banks */
2995 status += MXL_SetGPIO(fe, 3, 1);
2996 status += MXL_SetGPIO(fe, 1, 1);
2997 status += MXL_SetGPIO(fe, 4, 1);
2998 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2999 status += MXL_ControlWrite(fe, AGC_IF, 10);
3000 } else {
3001 /* if VHF or cable => Turn on Tracking Filter */
3002 if (state->RF_IN >= 43000000 &&
3003 state->RF_IN < 140000000) {
3004
3005 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3006 status += MXL_SetGPIO(fe, 4, 1);
3007 status += MXL_SetGPIO(fe, 1, 1);
3008 status += MXL_SetGPIO(fe, 3, 0);
3009 }
3010 if (state->RF_IN >= 140000000 &&
3011 state->RF_IN < 240000000) {
3012 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3013 status += MXL_SetGPIO(fe, 4, 1);
3014 status += MXL_SetGPIO(fe, 1, 0);
3015 status += MXL_SetGPIO(fe, 3, 0);
3016 }
3017 if (state->RF_IN >= 240000000 &&
3018 state->RF_IN < 340000000) {
3019 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3020 status += MXL_SetGPIO(fe, 4, 0);
3021 status += MXL_SetGPIO(fe, 1, 1);
3022 status += MXL_SetGPIO(fe, 3, 0);
3023 }
3024 if (state->RF_IN >= 340000000 &&
3025 state->RF_IN < 430000000) {
3026 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3027 status += MXL_SetGPIO(fe, 4, 0);
3028 status += MXL_SetGPIO(fe, 1, 0);
3029 status += MXL_SetGPIO(fe, 3, 1);
3030 }
3031 if (state->RF_IN >= 430000000 &&
3032 state->RF_IN < 470000000) {
3033 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3034 status += MXL_SetGPIO(fe, 4, 1);
3035 status += MXL_SetGPIO(fe, 1, 0);
3036 status += MXL_SetGPIO(fe, 3, 1);
3037 }
3038 if (state->RF_IN >= 470000000 &&
3039 state->RF_IN < 570000000) {
3040 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3041 status += MXL_SetGPIO(fe, 4, 0);
3042 status += MXL_SetGPIO(fe, 1, 0);
3043 status += MXL_SetGPIO(fe, 3, 1);
3044 }
3045 if (state->RF_IN >= 570000000 &&
3046 state->RF_IN < 620000000) {
3047 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3048 status += MXL_SetGPIO(fe, 4, 0);
3049 status += MXL_SetGPIO(fe, 1, 1);
3050 status += MXL_SetGPIO(fe, 3, 1);
3051 }
3052 if (state->RF_IN >= 620000000 &&
3053 state->RF_IN < 760000000) {
3054 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3055 status += MXL_SetGPIO(fe, 4, 0);
3056 status += MXL_SetGPIO(fe, 1, 1);
3057 status += MXL_SetGPIO(fe, 3, 1);
3058 }
3059 if (state->RF_IN >= 760000000 &&
3060 state->RF_IN <= 900000000) {
3061 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3062 status += MXL_SetGPIO(fe, 4, 1);
3063 status += MXL_SetGPIO(fe, 1, 1);
3064 status += MXL_SetGPIO(fe, 3, 1);
3065 }
3066 }
3067 }
3068
3069 if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
3070
3071 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3072
3073 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3074 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3075 status += MXL_SetGPIO(fe, 4, 0);
3076 status += MXL_SetGPIO(fe, 1, 1);
3077 status += MXL_SetGPIO(fe, 3, 1);
3078 }
3079 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3080 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3081 status += MXL_SetGPIO(fe, 4, 0);
3082 status += MXL_SetGPIO(fe, 1, 0);
3083 status += MXL_SetGPIO(fe, 3, 1);
3084 }
3085 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3086 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3087 status += MXL_SetGPIO(fe, 4, 1);
3088 status += MXL_SetGPIO(fe, 1, 0);
3089 status += MXL_SetGPIO(fe, 3, 1);
3090 }
3091 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3092 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3093 status += MXL_SetGPIO(fe, 4, 1);
3094 status += MXL_SetGPIO(fe, 1, 0);
3095 status += MXL_SetGPIO(fe, 3, 0);
3096 }
3097 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3098 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3099 status += MXL_SetGPIO(fe, 4, 1);
3100 status += MXL_SetGPIO(fe, 1, 1);
3101 status += MXL_SetGPIO(fe, 3, 0);
3102 }
3103 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3104 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3105 status += MXL_SetGPIO(fe, 4, 1);
3106 status += MXL_SetGPIO(fe, 1, 1);
3107 status += MXL_SetGPIO(fe, 3, 0);
3108 }
3109 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3110 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3111 status += MXL_SetGPIO(fe, 4, 1);
3112 status += MXL_SetGPIO(fe, 1, 1);
3113 status += MXL_SetGPIO(fe, 3, 1);
3114 }
3115 }
3116
3117 if (state->TF_Type == MXL_TF_F) {
3118
3119 /* Tracking Filter type F */
3120 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3121
3122 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
3123 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3124 status += MXL_SetGPIO(fe, 4, 0);
3125 status += MXL_SetGPIO(fe, 1, 1);
3126 status += MXL_SetGPIO(fe, 3, 1);
3127 }
3128 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
3129 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3130 status += MXL_SetGPIO(fe, 4, 0);
3131 status += MXL_SetGPIO(fe, 1, 0);
3132 status += MXL_SetGPIO(fe, 3, 1);
3133 }
3134 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
3135 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3136 status += MXL_SetGPIO(fe, 4, 1);
3137 status += MXL_SetGPIO(fe, 1, 0);
3138 status += MXL_SetGPIO(fe, 3, 1);
3139 }
3140 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
3141 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3142 status += MXL_SetGPIO(fe, 4, 1);
3143 status += MXL_SetGPIO(fe, 1, 0);
3144 status += MXL_SetGPIO(fe, 3, 0);
3145 }
3146 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
3147 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3148 status += MXL_SetGPIO(fe, 4, 1);
3149 status += MXL_SetGPIO(fe, 1, 1);
3150 status += MXL_SetGPIO(fe, 3, 0);
3151 }
3152 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
3153 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3154 status += MXL_SetGPIO(fe, 4, 1);
3155 status += MXL_SetGPIO(fe, 1, 1);
3156 status += MXL_SetGPIO(fe, 3, 0);
3157 }
3158 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
3159 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3160 status += MXL_SetGPIO(fe, 4, 1);
3161 status += MXL_SetGPIO(fe, 1, 1);
3162 status += MXL_SetGPIO(fe, 3, 1);
3163 }
3164 }
3165
3166 if (state->TF_Type == MXL_TF_E_2) {
3167
3168 /* Tracking Filter type E_2 */
3169 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3170
3171 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3172 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3173 status += MXL_SetGPIO(fe, 4, 0);
3174 status += MXL_SetGPIO(fe, 1, 1);
3175 status += MXL_SetGPIO(fe, 3, 1);
3176 }
3177 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3178 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3179 status += MXL_SetGPIO(fe, 4, 0);
3180 status += MXL_SetGPIO(fe, 1, 0);
3181 status += MXL_SetGPIO(fe, 3, 1);
3182 }
3183 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3184 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3185 status += MXL_SetGPIO(fe, 4, 1);
3186 status += MXL_SetGPIO(fe, 1, 0);
3187 status += MXL_SetGPIO(fe, 3, 1);
3188 }
3189 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3190 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3191 status += MXL_SetGPIO(fe, 4, 1);
3192 status += MXL_SetGPIO(fe, 1, 0);
3193 status += MXL_SetGPIO(fe, 3, 0);
3194 }
3195 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3196 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3197 status += MXL_SetGPIO(fe, 4, 1);
3198 status += MXL_SetGPIO(fe, 1, 1);
3199 status += MXL_SetGPIO(fe, 3, 0);
3200 }
3201 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3202 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3203 status += MXL_SetGPIO(fe, 4, 1);
3204 status += MXL_SetGPIO(fe, 1, 1);
3205 status += MXL_SetGPIO(fe, 3, 0);
3206 }
3207 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3208 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3209 status += MXL_SetGPIO(fe, 4, 1);
3210 status += MXL_SetGPIO(fe, 1, 1);
3211 status += MXL_SetGPIO(fe, 3, 1);
3212 }
3213 }
3214
3215 if (state->TF_Type == MXL_TF_G) {
3216
3217 /* Tracking Filter type G add for v2.6.8 */
3218 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3219
3220 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
3221
3222 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3223 status += MXL_SetGPIO(fe, 4, 0);
3224 status += MXL_SetGPIO(fe, 1, 1);
3225 status += MXL_SetGPIO(fe, 3, 1);
3226 }
3227 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
3228 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3229 status += MXL_SetGPIO(fe, 4, 0);
3230 status += MXL_SetGPIO(fe, 1, 0);
3231 status += MXL_SetGPIO(fe, 3, 1);
3232 }
3233 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
3234 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3235 status += MXL_SetGPIO(fe, 4, 1);
3236 status += MXL_SetGPIO(fe, 1, 0);
3237 status += MXL_SetGPIO(fe, 3, 1);
3238 }
3239 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3240 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3241 status += MXL_SetGPIO(fe, 4, 1);
3242 status += MXL_SetGPIO(fe, 1, 0);
3243 status += MXL_SetGPIO(fe, 3, 0);
3244 }
3245 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
3246 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3247 status += MXL_SetGPIO(fe, 4, 1);
3248 status += MXL_SetGPIO(fe, 1, 0);
3249 status += MXL_SetGPIO(fe, 3, 1);
3250 }
3251 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3252 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3253 status += MXL_SetGPIO(fe, 4, 1);
3254 status += MXL_SetGPIO(fe, 1, 1);
3255 status += MXL_SetGPIO(fe, 3, 0);
3256 }
3257 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
3258 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3259 status += MXL_SetGPIO(fe, 4, 1);
3260 status += MXL_SetGPIO(fe, 1, 1);
3261 status += MXL_SetGPIO(fe, 3, 0);
3262 }
3263 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
3264 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3265 status += MXL_SetGPIO(fe, 4, 1);
3266 status += MXL_SetGPIO(fe, 1, 1);
3267 status += MXL_SetGPIO(fe, 3, 1);
3268 }
3269 }
3270
3271 if (state->TF_Type == MXL_TF_E_NA) {
3272
3273 /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */
3274 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3275
3276 /* if UHF and terrestrial=> Turn off Tracking Filter */
3277 if (state->RF_IN >= 471000000 &&
3278 (state->RF_IN - 471000000)%6000000 != 0) {
3279
3280 /* Turn off all the banks */
3281 status += MXL_SetGPIO(fe, 3, 1);
3282 status += MXL_SetGPIO(fe, 1, 1);
3283 status += MXL_SetGPIO(fe, 4, 1);
3284 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3285
3286 /* 2.6.12 Turn on RSSI */
3287 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
3288 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
3289 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
3290 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
3291
3292 /* RSSI reference point */
3293 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
3294 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
3295 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
3296
3297 /* following parameter is from analog OTA mode,
3298 * can be change to seek better performance */
3299 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
3300 } else {
3301 /* if VHF or Cable => Turn on Tracking Filter */
3302
3303 /* 2.6.12 Turn off RSSI */
3304 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
3305
3306 /* change back from above condition */
3307 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
3308
3309
3310 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3311
3312 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3313 status += MXL_SetGPIO(fe, 4, 0);
3314 status += MXL_SetGPIO(fe, 1, 1);
3315 status += MXL_SetGPIO(fe, 3, 1);
3316 }
3317 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3318 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3319 status += MXL_SetGPIO(fe, 4, 0);
3320 status += MXL_SetGPIO(fe, 1, 0);
3321 status += MXL_SetGPIO(fe, 3, 1);
3322 }
3323 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3324 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3325 status += MXL_SetGPIO(fe, 4, 1);
3326 status += MXL_SetGPIO(fe, 1, 0);
3327 status += MXL_SetGPIO(fe, 3, 1);
3328 }
3329 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3330 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3331 status += MXL_SetGPIO(fe, 4, 1);
3332 status += MXL_SetGPIO(fe, 1, 0);
3333 status += MXL_SetGPIO(fe, 3, 0);
3334 }
3335 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3336 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3337 status += MXL_SetGPIO(fe, 4, 1);
3338 status += MXL_SetGPIO(fe, 1, 1);
3339 status += MXL_SetGPIO(fe, 3, 0);
3340 }
3341 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3342 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3343 status += MXL_SetGPIO(fe, 4, 1);
3344 status += MXL_SetGPIO(fe, 1, 1);
3345 status += MXL_SetGPIO(fe, 3, 0);
3346 }
3347 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3348 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3349 status += MXL_SetGPIO(fe, 4, 1);
3350 status += MXL_SetGPIO(fe, 1, 1);
3351 status += MXL_SetGPIO(fe, 3, 1);
3352 }
3353 }
3354 }
3355 return status ;
3356}
3357
3358static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3359{
3360 u16 status = 0;
3361
3362 if (GPIO_Num == 1)
3363 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3364
3365 /* GPIO2 is not available */
3366
3367 if (GPIO_Num == 3) {
3368 if (GPIO_Val == 1) {
3369 status += MXL_ControlWrite(fe, GPIO_3, 0);
3370 status += MXL_ControlWrite(fe, GPIO_3B, 0);
3371 }
3372 if (GPIO_Val == 0) {
3373 status += MXL_ControlWrite(fe, GPIO_3, 1);
3374 status += MXL_ControlWrite(fe, GPIO_3B, 1);
3375 }
3376 if (GPIO_Val == 3) { /* tri-state */
3377 status += MXL_ControlWrite(fe, GPIO_3, 0);
3378 status += MXL_ControlWrite(fe, GPIO_3B, 1);
3379 }
3380 }
3381 if (GPIO_Num == 4) {
3382 if (GPIO_Val == 1) {
3383 status += MXL_ControlWrite(fe, GPIO_4, 0);
3384 status += MXL_ControlWrite(fe, GPIO_4B, 0);
3385 }
3386 if (GPIO_Val == 0) {
3387 status += MXL_ControlWrite(fe, GPIO_4, 1);
3388 status += MXL_ControlWrite(fe, GPIO_4B, 1);
3389 }
3390 if (GPIO_Val == 3) { /* tri-state */
3391 status += MXL_ControlWrite(fe, GPIO_4, 0);
3392 status += MXL_ControlWrite(fe, GPIO_4B, 1);
3393 }
3394 }
3395
3396 return status;
3397}
3398
3399static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3400{
3401 u16 status = 0;
3402
3403 /* Will write ALL Matching Control Name */
3404 /* Write Matching INIT Control */
3405 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
3406 /* Write Matching CH Control */
3407 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
3408#ifdef _MXL_INTERNAL
3409 /* Write Matching MXL Control */
3410 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
3411#endif
3412 return status;
3413}
3414
3415static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
3416 u32 value, u16 controlGroup)
3417{
3418 struct mxl5005s_state *state = fe->tuner_priv;
3419 u16 i, j, k;
3420 u32 highLimit;
3421 u32 ctrlVal;
3422
3423 if (controlGroup == 1) /* Initial Control */ {
3424
3425 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3426
3427 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3428
3429 highLimit = 1 << state->Init_Ctrl[i].size;
3430 if (value < highLimit) {
3431 for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3432 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3433 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3434 (u8)(state->Init_Ctrl[i].bit[j]),
3435 (u8)((value>>j) & 0x01));
3436 }
3437 ctrlVal = 0;
3438 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3439 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3440 } else
3441 return -1;
3442 }
3443 }
3444 }
3445 if (controlGroup == 2) /* Chan change Control */ {
3446
3447 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3448
3449 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3450
3451 highLimit = 1 << state->CH_Ctrl[i].size;
3452 if (value < highLimit) {
3453 for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3454 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3455 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3456 (u8)(state->CH_Ctrl[i].bit[j]),
3457 (u8)((value>>j) & 0x01));
3458 }
3459 ctrlVal = 0;
3460 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3461 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3462 } else
3463 return -1;
3464 }
3465 }
3466 }
3467#ifdef _MXL_INTERNAL
3468 if (controlGroup == 3) /* Maxlinear Control */ {
3469
3470 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3471
3472 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3473
3474 highLimit = (1 << state->MXL_Ctrl[i].size);
3475 if (value < highLimit) {
3476 for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3477 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3478 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3479 (u8)(state->MXL_Ctrl[i].bit[j]),
3480 (u8)((value>>j) & 0x01));
3481 }
3482 ctrlVal = 0;
3483 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3484 ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k);
3485 } else
3486 return -1;
3487 }
3488 }
3489 }
3490#endif
3491 return 0 ; /* successful return */
3492}
3493
3494static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3495{
3496 struct mxl5005s_state *state = fe->tuner_priv;
3497 int i ;
3498
3499 for (i = 0; i < 104; i++) {
3500 if (RegNum == state->TunerRegs[i].Reg_Num) {
3501 *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3502 return 0;
3503 }
3504 }
3505
3506 return 1;
3507}
3508
3509static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3510{
3511 struct mxl5005s_state *state = fe->tuner_priv;
3512 u32 ctrlVal ;
3513 u16 i, k ;
3514
3515 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3516
3517 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3518
3519 ctrlVal = 0;
3520 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3521 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
3522 *value = ctrlVal;
3523 return 0;
3524 }
3525 }
3526
3527 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3528
3529 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3530
3531 ctrlVal = 0;
3532 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3533 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3534 *value = ctrlVal;
3535 return 0;
3536
3537 }
3538 }
3539
3540#ifdef _MXL_INTERNAL
3541 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3542
3543 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3544
3545 ctrlVal = 0;
3546 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3547 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
3548 *value = ctrlVal;
3549 return 0;
3550
3551 }
3552 }
3553#endif
3554 return 1;
3555}
3556
3557static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
3558 u8 bitVal)
3559{
3560 struct mxl5005s_state *state = fe->tuner_priv;
3561 int i ;
3562
3563 const u8 AND_MAP[8] = {
3564 0xFE, 0xFD, 0xFB, 0xF7,
3565 0xEF, 0xDF, 0xBF, 0x7F } ;
3566
3567 const u8 OR_MAP[8] = {
3568 0x01, 0x02, 0x04, 0x08,
3569 0x10, 0x20, 0x40, 0x80 } ;
3570
3571 for (i = 0; i < state->TunerRegs_Num; i++) {
3572 if (state->TunerRegs[i].Reg_Num == address) {
3573 if (bitVal)
3574 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
3575 else
3576 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
3577 break ;
3578 }
3579 }
3580}
3581
3582static u32 MXL_Ceiling(u32 value, u32 resolution)
3583{
3584 return (value/resolution + (value % resolution > 0 ? 1 : 0));
3585}
3586
3587/* Retrieve the Initialzation Registers */
3588static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
3589 u8 *RegVal, int *count)
3590{
3591 u16 status = 0;
3592 int i ;
3593
3594 u8 RegAddr[] = {
3595 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
3596 76, 77, 91, 134, 135, 137, 147,
3597 156, 166, 167, 168, 25 };
3598
3599 *count = sizeof(RegAddr) / sizeof(u8);
3600
3601 status += MXL_BlockInit(fe);
3602
3603 for (i = 0 ; i < *count; i++) {
3604 RegNum[i] = RegAddr[i];
3605 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3606 }
3607
3608 return status;
3609}
3610
3611static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3612 int *count)
3613{
3614 u16 status = 0;
3615 int i ;
3616
3617/* add 77, 166, 167, 168 register for 2.6.12 */
3618#ifdef _MXL_PRODUCTION
3619 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
3620 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3621#else
3622 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
3623 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3624 /*
3625 u8 RegAddr[171];
3626 for (i = 0; i <= 170; i++)
3627 RegAddr[i] = i;
3628 */
3629#endif
3630
3631 *count = sizeof(RegAddr) / sizeof(u8);
3632
3633 for (i = 0 ; i < *count; i++) {
3634 RegNum[i] = RegAddr[i];
3635 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3636 }
3637
3638 return status;
3639}
3640
3641static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
3642 u8 *RegVal, int *count)
3643{
3644 u16 status = 0;
3645 int i;
3646
3647 u8 RegAddr[] = {43, 136};
3648
3649 *count = sizeof(RegAddr) / sizeof(u8);
3650
3651 for (i = 0; i < *count; i++) {
3652 RegNum[i] = RegAddr[i];
3653 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3654 }
3655
3656 return status;
3657}
3658
3659static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
3660{
3661 if (state == 1) /* Load_Start */
3662 *MasterReg = 0xF3;
3663 if (state == 2) /* Power_Down */
3664 *MasterReg = 0x41;
3665 if (state == 3) /* Synth_Reset */
3666 *MasterReg = 0xB1;
3667 if (state == 4) /* Seq_Off */
3668 *MasterReg = 0xF1;
3669
3670 return 0;
3671}
3672
3673#ifdef _MXL_PRODUCTION
3674static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
3675{
3676 struct mxl5005s_state *state = fe->tuner_priv;
3677 u16 status = 0 ;
3678
3679 if (VCO_Range == 1) {
3680 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3681 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3682 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3683 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3684 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3685 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3686 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3687 if (state->Mode == 0 && state->IF_Mode == 1) {
3688 /* Analog Low IF Mode */
3689 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3690 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3691 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3692 status += MXL_ControlWrite(fe,
3693 CHCAL_FRAC_MOD_RF, 180224);
3694 }
3695 if (state->Mode == 0 && state->IF_Mode == 0) {
3696 /* Analog Zero IF Mode */
3697 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3698 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3699 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3700 status += MXL_ControlWrite(fe,
3701 CHCAL_FRAC_MOD_RF, 222822);
3702 }
3703 if (state->Mode == 1) /* Digital Mode */ {
3704 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3705 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3706 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3707 status += MXL_ControlWrite(fe,
3708 CHCAL_FRAC_MOD_RF, 229376);
3709 }
3710 }
3711
3712 if (VCO_Range == 2) {
3713 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3714 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3715 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3716 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3717 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3718 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3719 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3720 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3721 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3722 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3723 if (state->Mode == 0 && state->IF_Mode == 1) {
3724 /* Analog Low IF Mode */
3725 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3726 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3727 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3728 status += MXL_ControlWrite(fe,
3729 CHCAL_FRAC_MOD_RF, 206438);
3730 }
3731 if (state->Mode == 0 && state->IF_Mode == 0) {
3732 /* Analog Zero IF Mode */
3733 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3734 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3735 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3736 status += MXL_ControlWrite(fe,
3737 CHCAL_FRAC_MOD_RF, 206438);
3738 }
3739 if (state->Mode == 1) /* Digital Mode */ {
3740 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3741 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3742 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3743 status += MXL_ControlWrite(fe,
3744 CHCAL_FRAC_MOD_RF, 16384);
3745 }
3746 }
3747
3748 if (VCO_Range == 3) {
3749 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3750 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3751 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3752 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3753 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3754 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3755 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3756 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3757 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3758 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3759 if (state->Mode == 0 && state->IF_Mode == 1) {
3760 /* Analog Low IF Mode */
3761 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3762 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3763 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3764 status += MXL_ControlWrite(fe,
3765 CHCAL_FRAC_MOD_RF, 173670);
3766 }
3767 if (state->Mode == 0 && state->IF_Mode == 0) {
3768 /* Analog Zero IF Mode */
3769 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3770 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3771 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3772 status += MXL_ControlWrite(fe,
3773 CHCAL_FRAC_MOD_RF, 173670);
3774 }
3775 if (state->Mode == 1) /* Digital Mode */ {
3776 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3777 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3778 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3779 status += MXL_ControlWrite(fe,
3780 CHCAL_FRAC_MOD_RF, 245760);
3781 }
3782 }
3783
3784 if (VCO_Range == 4) {
3785 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3786 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3787 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3788 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3789 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3790 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3791 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3792 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3793 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3794 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3795 if (state->Mode == 0 && state->IF_Mode == 1) {
3796 /* Analog Low IF Mode */
3797 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3798 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3799 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3800 status += MXL_ControlWrite(fe,
3801 CHCAL_FRAC_MOD_RF, 206438);
3802 }
3803 if (state->Mode == 0 && state->IF_Mode == 0) {
3804 /* Analog Zero IF Mode */
3805 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3806 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3807 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3808 status += MXL_ControlWrite(fe,
3809 CHCAL_FRAC_MOD_RF, 206438);
3810 }
3811 if (state->Mode == 1) /* Digital Mode */ {
3812 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3813 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3814 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3815 status += MXL_ControlWrite(fe,
3816 CHCAL_FRAC_MOD_RF, 212992);
3817 }
3818 }
3819
3820 return status;
3821}
3822
3823static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
3824{
3825 struct mxl5005s_state *state = fe->tuner_priv;
3826 u16 status = 0;
3827
3828 if (Hystersis == 1)
3829 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
3830
3831 return status;
3832}
3833#endif
3834/* End: Reference driver code found in the Realtek driver that
3835 * is copyright MaxLinear */
3836
3837/* ----------------------------------------------------------------
3838 * Begin: Everything after here is new code to adapt the
3839 * proprietary Realtek driver into a Linux API tuner.
3840 * Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
3841 */
3842static int mxl5005s_reset(struct dvb_frontend *fe)
3843{
3844 struct mxl5005s_state *state = fe->tuner_priv;
3845 int ret = 0;
3846
3847 u8 buf[2] = { 0xff, 0x00 };
3848 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3849 .buf = buf, .len = 2 };
3850
3851 dprintk(2, "%s()\n", __func__);
3852
3853 if (fe->ops.i2c_gate_ctrl)
3854 fe->ops.i2c_gate_ctrl(fe, 1);
3855
3856 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3857 printk(KERN_WARNING "mxl5005s I2C reset failed\n");
3858 ret = -EREMOTEIO;
3859 }
3860
3861 if (fe->ops.i2c_gate_ctrl)
3862 fe->ops.i2c_gate_ctrl(fe, 0);
3863
3864 return ret;
3865}
3866
3867/* Write a single byte to a single reg, latch the value if required by
3868 * following the transaction with the latch byte.
3869 */
3870static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
3871{
3872 struct mxl5005s_state *state = fe->tuner_priv;
3873 u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
3874 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3875 .buf = buf, .len = 3 };
3876
3877 if (latch == 0)
3878 msg.len = 2;
3879
3880 dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr);
3881
3882 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3883 printk(KERN_WARNING "mxl5005s I2C write failed\n");
3884 return -EREMOTEIO;
3885 }
3886 return 0;
3887}
3888
3889static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
3890 u8 *datatable, u8 len)
3891{
3892 int ret = 0, i;
3893
3894 if (fe->ops.i2c_gate_ctrl)
3895 fe->ops.i2c_gate_ctrl(fe, 1);
3896
3897 for (i = 0 ; i < len-1; i++) {
3898 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
3899 if (ret < 0)
3900 break;
3901 }
3902
3903 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
3904
3905 if (fe->ops.i2c_gate_ctrl)
3906 fe->ops.i2c_gate_ctrl(fe, 0);
3907
3908 return ret;
3909}
3910
3911static int mxl5005s_init(struct dvb_frontend *fe)
3912{
3913 dprintk(1, "%s()\n", __func__);
3914 return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
3915}
3916
3917static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
3918 u32 bandwidth)
3919{
3920 struct mxl5005s_state *state = fe->tuner_priv;
3921
3922 u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
3923 u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
3924 int TableLen;
3925
3926 dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
3927
3928 mxl5005s_reset(fe);
3929
3930 /* Tuner initialization stage 0 */
3931 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
3932 AddrTable[0] = MASTER_CONTROL_ADDR;
3933 ByteTable[0] |= state->config->AgcMasterByte;
3934
3935 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
3936
3937 mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
3938
3939 /* Tuner initialization stage 1 */
3940 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
3941
3942 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
3943
3944 return 0;
3945}
3946
3947static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
3948 u32 bandwidth)
3949{
3950 struct mxl5005s_state *state = fe->tuner_priv;
3951 struct mxl5005s_config *c = state->config;
3952
3953 InitTunerControls(fe);
3954
3955 /* Set MxL5005S parameters. */
3956 MXL5005_TunerConfig(
3957 fe,
3958 c->mod_mode,
3959 c->if_mode,
3960 bandwidth,
3961 c->if_freq,
3962 c->xtal_freq,
3963 c->agc_mode,
3964 c->top,
3965 c->output_load,
3966 c->clock_out,
3967 c->div_out,
3968 c->cap_select,
3969 c->rssi_enable,
3970 mod_type,
3971 c->tracking_filter);
3972
3973 return 0;
3974}
3975
3976static int mxl5005s_set_params(struct dvb_frontend *fe,
3977 struct dvb_frontend_parameters *params)
3978{
3979 struct mxl5005s_state *state = fe->tuner_priv;
3980 u32 req_mode, req_bw = 0;
3981 int ret;
3982
3983 dprintk(1, "%s()\n", __func__);
3984
3985 if (fe->ops.info.type == FE_ATSC) {
3986 switch (params->u.vsb.modulation) {
3987 case VSB_8:
3988 req_mode = MXL_ATSC; break;
3989 default:
3990 case QAM_64:
3991 case QAM_256:
3992 case QAM_AUTO:
3993 req_mode = MXL_QAM; break;
3994 }
3995 } else
3996 req_mode = MXL_DVBT;
3997
3998 /* Change tuner for new modulation type if reqd */
3999 if (req_mode != state->current_mode) {
4000 switch (req_mode) {
4001 case VSB_8:
4002 case QAM_64:
4003 case QAM_256:
4004 case QAM_AUTO:
4005 req_bw = MXL5005S_BANDWIDTH_6MHZ;
4006 break;
4007 default:
4008 /* Assume DVB-T */
4009 switch (params->u.ofdm.bandwidth) {
4010 case BANDWIDTH_6_MHZ:
4011 req_bw = MXL5005S_BANDWIDTH_6MHZ;
4012 break;
4013 case BANDWIDTH_7_MHZ:
4014 req_bw = MXL5005S_BANDWIDTH_7MHZ;
4015 break;
4016 case BANDWIDTH_AUTO:
4017 case BANDWIDTH_8_MHZ:
4018 req_bw = MXL5005S_BANDWIDTH_8MHZ;
4019 break;
4020 }
4021 }
4022
4023 state->current_mode = req_mode;
4024 ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4025
4026 } else
4027 ret = 0;
4028
4029 if (ret == 0) {
4030 dprintk(1, "%s() freq=%d\n", __func__, params->frequency);
4031 ret = mxl5005s_SetRfFreqHz(fe, params->frequency);
4032 }
4033
4034 return ret;
4035}
4036
4037static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4038{
4039 struct mxl5005s_state *state = fe->tuner_priv;
4040 dprintk(1, "%s()\n", __func__);
4041
4042 *frequency = state->RF_IN;
4043
4044 return 0;
4045}
4046
4047static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4048{
4049 struct mxl5005s_state *state = fe->tuner_priv;
4050 dprintk(1, "%s()\n", __func__);
4051
4052 *bandwidth = state->Chan_Bandwidth;
4053
4054 return 0;
4055}
4056
4057static int mxl5005s_release(struct dvb_frontend *fe)
4058{
4059 dprintk(1, "%s()\n", __func__);
4060 kfree(fe->tuner_priv);
4061 fe->tuner_priv = NULL;
4062 return 0;
4063}
4064
4065static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4066 .info = {
4067 .name = "MaxLinear MXL5005S",
4068 .frequency_min = 48000000,
4069 .frequency_max = 860000000,
4070 .frequency_step = 50000,
4071 },
4072
4073 .release = mxl5005s_release,
4074 .init = mxl5005s_init,
4075
4076 .set_params = mxl5005s_set_params,
4077 .get_frequency = mxl5005s_get_frequency,
4078 .get_bandwidth = mxl5005s_get_bandwidth,
4079};
4080
4081struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4082 struct i2c_adapter *i2c,
4083 struct mxl5005s_config *config)
4084{
4085 struct mxl5005s_state *state = NULL;
4086 dprintk(1, "%s()\n", __func__);
4087
4088 state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4089 if (state == NULL)
4090 return NULL;
4091
4092 state->frontend = fe;
4093 state->config = config;
4094 state->i2c = i2c;
4095 state->current_mode = MXL_QAM;
4096
4097 printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n",
4098 config->i2c_address);
4099
4100 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
4101 sizeof(struct dvb_tuner_ops));
4102
4103 fe->tuner_priv = state;
4104 return fe;
4105}
4106EXPORT_SYMBOL(mxl5005s_attach);
4107
4108MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
4109MODULE_AUTHOR("Steven Toth");
4110MODULE_LICENSE("GPL");
diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h
new file mode 100644
index 000000000000..396db150bf0c
--- /dev/null
+++ b/drivers/media/common/tuners/mxl5005s.h
@@ -0,0 +1,131 @@
1/*
2 MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
3
4 Copyright (C) 2008 MaxLinear
5 Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21*/
22
23#ifndef __MXL5005S_H
24#define __MXL5005S_H
25
26#include <linux/i2c.h>
27#include "dvb_frontend.h"
28
29struct mxl5005s_config {
30
31 /* 7 bit i2c address */
32 u8 i2c_address;
33
34#define IF_FREQ_4570000HZ 4570000
35#define IF_FREQ_4571429HZ 4571429
36#define IF_FREQ_5380000HZ 5380000
37#define IF_FREQ_36000000HZ 36000000
38#define IF_FREQ_36125000HZ 36125000
39#define IF_FREQ_36166667HZ 36166667
40#define IF_FREQ_44000000HZ 44000000
41 u32 if_freq;
42
43#define CRYSTAL_FREQ_4000000HZ 4000000
44#define CRYSTAL_FREQ_16000000HZ 16000000
45#define CRYSTAL_FREQ_25000000HZ 25000000
46#define CRYSTAL_FREQ_28800000HZ 28800000
47 u32 xtal_freq;
48
49#define MXL_DUAL_AGC 0
50#define MXL_SINGLE_AGC 1
51 u8 agc_mode;
52
53#define MXL_TF_DEFAULT 0
54#define MXL_TF_OFF 1
55#define MXL_TF_C 2
56#define MXL_TF_C_H 3
57#define MXL_TF_D 4
58#define MXL_TF_D_L 5
59#define MXL_TF_E 6
60#define MXL_TF_F 7
61#define MXL_TF_E_2 8
62#define MXL_TF_E_NA 9
63#define MXL_TF_G 10
64 u8 tracking_filter;
65
66#define MXL_RSSI_DISABLE 0
67#define MXL_RSSI_ENABLE 1
68 u8 rssi_enable;
69
70#define MXL_CAP_SEL_DISABLE 0
71#define MXL_CAP_SEL_ENABLE 1
72 u8 cap_select;
73
74#define MXL_DIV_OUT_1 0
75#define MXL_DIV_OUT_4 1
76 u8 div_out;
77
78#define MXL_CLOCK_OUT_DISABLE 0
79#define MXL_CLOCK_OUT_ENABLE 1
80 u8 clock_out;
81
82#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200
83#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300
84 u32 output_load;
85
86#define MXL5005S_TOP_5P5 55
87#define MXL5005S_TOP_7P2 72
88#define MXL5005S_TOP_9P2 92
89#define MXL5005S_TOP_11P0 110
90#define MXL5005S_TOP_12P9 129
91#define MXL5005S_TOP_14P7 147
92#define MXL5005S_TOP_16P8 168
93#define MXL5005S_TOP_19P4 194
94#define MXL5005S_TOP_21P2 212
95#define MXL5005S_TOP_23P2 232
96#define MXL5005S_TOP_25P2 252
97#define MXL5005S_TOP_27P1 271
98#define MXL5005S_TOP_29P2 292
99#define MXL5005S_TOP_31P7 317
100#define MXL5005S_TOP_34P9 349
101 u32 top;
102
103#define MXL_ANALOG_MODE 0
104#define MXL_DIGITAL_MODE 1
105 u8 mod_mode;
106
107#define MXL_ZERO_IF 0
108#define MXL_LOW_IF 1
109 u8 if_mode;
110
111 /* Stuff I don't know what to do with */
112 u8 AgcMasterByte;
113};
114
115#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || \
116 (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE))
117extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
118 struct i2c_adapter *i2c,
119 struct mxl5005s_config *config);
120#else
121static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
122 struct i2c_adapter *i2c,
123 struct mxl5005s_config *config)
124{
125 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
126 return NULL;
127}
128#endif /* CONFIG_DVB_TUNER_MXL5005S */
129
130#endif /* __MXL5005S_H */
131
diff --git a/drivers/media/common/tuners/tda18271-common.c b/drivers/media/common/tuners/tda18271-common.c
index e27a7620a32f..42b5f5d4bfe6 100644
--- a/drivers/media/common/tuners/tda18271-common.c
+++ b/drivers/media/common/tuners/tda18271-common.c
@@ -227,9 +227,8 @@ int tda18271_charge_pump_source(struct dvb_frontend *fe,
227 227
228 regs[r_cp] &= ~0x20; 228 regs[r_cp] &= ~0x20;
229 regs[r_cp] |= ((force & 1) << 5); 229 regs[r_cp] |= ((force & 1) << 5);
230 tda18271_write_regs(fe, r_cp, 1);
231 230
232 return 0; 231 return tda18271_write_regs(fe, r_cp, 1);
233} 232}
234 233
235int tda18271_init_regs(struct dvb_frontend *fe) 234int tda18271_init_regs(struct dvb_frontend *fe)
@@ -487,16 +486,15 @@ int tda18271_set_standby_mode(struct dvb_frontend *fe,
487 struct tda18271_priv *priv = fe->tuner_priv; 486 struct tda18271_priv *priv = fe->tuner_priv;
488 unsigned char *regs = priv->tda18271_regs; 487 unsigned char *regs = priv->tda18271_regs;
489 488
490 tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt); 489 if (tda18271_debug & DBG_ADV)
490 tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt);
491 491
492 regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */ 492 regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
493 regs[R_EP3] |= sm ? (1 << 7) : 0 | 493 regs[R_EP3] |= sm ? (1 << 7) : 0 |
494 sm_lt ? (1 << 6) : 0 | 494 sm_lt ? (1 << 6) : 0 |
495 sm_xt ? (1 << 5) : 0; 495 sm_xt ? (1 << 5) : 0;
496 496
497 tda18271_write_regs(fe, R_EP3, 1); 497 return tda18271_write_regs(fe, R_EP3, 1);
498
499 return 0;
500} 498}
501 499
502/*---------------------------------------------------------------------*/ 500/*---------------------------------------------------------------------*/
@@ -510,7 +508,7 @@ int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
510 u32 div; 508 u32 div;
511 509
512 int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d); 510 int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
513 if (ret < 0) 511 if (tda_fail(ret))
514 goto fail; 512 goto fail;
515 513
516 regs[R_MPD] = (0x77 & pd); 514 regs[R_MPD] = (0x77 & pd);
@@ -542,7 +540,7 @@ int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
542 u32 div; 540 u32 div;
543 541
544 int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d); 542 int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
545 if (ret < 0) 543 if (tda_fail(ret))
546 goto fail; 544 goto fail;
547 545
548 regs[R_CPD] = pd; 546 regs[R_CPD] = pd;
@@ -566,7 +564,7 @@ int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
566 u8 val; 564 u8 val;
567 565
568 int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val); 566 int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
569 if (ret < 0) 567 if (tda_fail(ret))
570 goto fail; 568 goto fail;
571 569
572 regs[R_EP1] &= ~0x07; /* clear bp filter bits */ 570 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
@@ -583,7 +581,7 @@ int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
583 u8 val; 581 u8 val;
584 582
585 int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val); 583 int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
586 if (ret < 0) 584 if (tda_fail(ret))
587 goto fail; 585 goto fail;
588 586
589 regs[R_EB13] &= ~0x7c; /* clear k & m bits */ 587 regs[R_EB13] &= ~0x7c; /* clear k & m bits */
@@ -600,7 +598,7 @@ int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
600 u8 val; 598 u8 val;
601 599
602 int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val); 600 int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
603 if (ret < 0) 601 if (tda_fail(ret))
604 goto fail; 602 goto fail;
605 603
606 regs[R_EP2] &= ~0xe0; /* clear rf band bits */ 604 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
@@ -617,7 +615,7 @@ int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
617 u8 val; 615 u8 val;
618 616
619 int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val); 617 int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
620 if (ret < 0) 618 if (tda_fail(ret))
621 goto fail; 619 goto fail;
622 620
623 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */ 621 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
@@ -634,7 +632,7 @@ int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
634 u8 val; 632 u8 val;
635 633
636 int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val); 634 int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
637 if (ret < 0) 635 if (tda_fail(ret))
638 goto fail; 636 goto fail;
639 637
640 regs[R_EP5] &= ~0x07; 638 regs[R_EP5] &= ~0x07;
diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c
index b262100ae897..89c01fb1f859 100644
--- a/drivers/media/common/tuners/tda18271-fe.c
+++ b/drivers/media/common/tuners/tda18271-fe.c
@@ -51,6 +51,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe,
51{ 51{
52 struct tda18271_priv *priv = fe->tuner_priv; 52 struct tda18271_priv *priv = fe->tuner_priv;
53 unsigned char *regs = priv->tda18271_regs; 53 unsigned char *regs = priv->tda18271_regs;
54 int ret;
54 u32 N; 55 u32 N;
55 56
56 /* update TV broadcast parameters */ 57 /* update TV broadcast parameters */
@@ -85,7 +86,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe,
85 /* update rf top / if top */ 86 /* update rf top / if top */
86 regs[R_EB22] = 0x00; 87 regs[R_EB22] = 0x00;
87 regs[R_EB22] |= map->rfagc_top; 88 regs[R_EB22] |= map->rfagc_top;
88 tda18271_write_regs(fe, R_EB22, 1); 89 ret = tda18271_write_regs(fe, R_EB22, 1);
90 if (tda_fail(ret))
91 goto fail;
89 92
90 /* --------------------------------------------------------------- */ 93 /* --------------------------------------------------------------- */
91 94
@@ -121,7 +124,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe,
121 /* agc1 has priority on agc2 */ 124 /* agc1 has priority on agc2 */
122 regs[R_EB1] &= ~0x01; 125 regs[R_EB1] &= ~0x01;
123 126
124 tda18271_write_regs(fe, R_EB1, 1); 127 ret = tda18271_write_regs(fe, R_EB1, 1);
128 if (tda_fail(ret))
129 goto fail;
125 130
126 /* --------------------------------------------------------------- */ 131 /* --------------------------------------------------------------- */
127 132
@@ -141,7 +146,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe,
141 break; 146 break;
142 } 147 }
143 148
144 tda18271_write_regs(fe, R_TM, 7); 149 ret = tda18271_write_regs(fe, R_TM, 7);
150 if (tda_fail(ret))
151 goto fail;
145 152
146 /* force charge pump source */ 153 /* force charge pump source */
147 charge_pump_source(fe, 1); 154 charge_pump_source(fe, 1);
@@ -158,9 +165,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe,
158 regs[R_EP3] &= ~0x04; 165 regs[R_EP3] &= ~0x04;
159 else 166 else
160 regs[R_EP3] |= 0x04; 167 regs[R_EP3] |= 0x04;
161 tda18271_write_regs(fe, R_EP3, 1); 168 ret = tda18271_write_regs(fe, R_EP3, 1);
162 169fail:
163 return 0; 170 return ret;
164} 171}
165 172
166static int tda18271_read_thermometer(struct dvb_frontend *fe) 173static int tda18271_read_thermometer(struct dvb_frontend *fe)
@@ -213,11 +220,13 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe,
213 struct tda18271_priv *priv = fe->tuner_priv; 220 struct tda18271_priv *priv = fe->tuner_priv;
214 struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state; 221 struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
215 unsigned char *regs = priv->tda18271_regs; 222 unsigned char *regs = priv->tda18271_regs;
216 int tm_current, rfcal_comp, approx, i; 223 int tm_current, rfcal_comp, approx, i, ret;
217 u8 dc_over_dt, rf_tab; 224 u8 dc_over_dt, rf_tab;
218 225
219 /* power up */ 226 /* power up */
220 tda18271_set_standby_mode(fe, 0, 0, 0); 227 ret = tda18271_set_standby_mode(fe, 0, 0, 0);
228 if (tda_fail(ret))
229 goto fail;
221 230
222 /* read die current temperature */ 231 /* read die current temperature */
223 tm_current = tda18271_read_thermometer(fe); 232 tm_current = tda18271_read_thermometer(fe);
@@ -228,8 +237,8 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe,
228 rf_tab = regs[R_EB14]; 237 rf_tab = regs[R_EB14];
229 238
230 i = tda18271_lookup_rf_band(fe, &freq, NULL); 239 i = tda18271_lookup_rf_band(fe, &freq, NULL);
231 if (i < 0) 240 if (tda_fail(i))
232 return -EINVAL; 241 return i;
233 242
234 if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) { 243 if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) {
235 approx = map[i].rf_a1 * 244 approx = map[i].rf_a1 *
@@ -250,35 +259,42 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe,
250 rfcal_comp = dc_over_dt * (tm_current - priv->tm_rfcal); 259 rfcal_comp = dc_over_dt * (tm_current - priv->tm_rfcal);
251 260
252 regs[R_EB14] = approx + rfcal_comp; 261 regs[R_EB14] = approx + rfcal_comp;
253 tda18271_write_regs(fe, R_EB14, 1); 262 ret = tda18271_write_regs(fe, R_EB14, 1);
254 263fail:
255 return 0; 264 return ret;
256} 265}
257 266
258static int tda18271_por(struct dvb_frontend *fe) 267static int tda18271_por(struct dvb_frontend *fe)
259{ 268{
260 struct tda18271_priv *priv = fe->tuner_priv; 269 struct tda18271_priv *priv = fe->tuner_priv;
261 unsigned char *regs = priv->tda18271_regs; 270 unsigned char *regs = priv->tda18271_regs;
271 int ret;
262 272
263 /* power up detector 1 */ 273 /* power up detector 1 */
264 regs[R_EB12] &= ~0x20; 274 regs[R_EB12] &= ~0x20;
265 tda18271_write_regs(fe, R_EB12, 1); 275 ret = tda18271_write_regs(fe, R_EB12, 1);
276 if (tda_fail(ret))
277 goto fail;
266 278
267 regs[R_EB18] &= ~0x80; /* turn agc1 loop on */ 279 regs[R_EB18] &= ~0x80; /* turn agc1 loop on */
268 regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ 280 regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
269 tda18271_write_regs(fe, R_EB18, 1); 281 ret = tda18271_write_regs(fe, R_EB18, 1);
282 if (tda_fail(ret))
283 goto fail;
270 284
271 regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */ 285 regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */
272 286
273 /* POR mode */ 287 /* POR mode */
274 tda18271_set_standby_mode(fe, 1, 0, 0); 288 ret = tda18271_set_standby_mode(fe, 1, 0, 0);
289 if (tda_fail(ret))
290 goto fail;
275 291
276 /* disable 1.5 MHz low pass filter */ 292 /* disable 1.5 MHz low pass filter */
277 regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */ 293 regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */
278 regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */ 294 regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */
279 tda18271_write_regs(fe, R_EB21, 3); 295 ret = tda18271_write_regs(fe, R_EB21, 3);
280 296fail:
281 return 0; 297 return ret;
282} 298}
283 299
284static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq) 300static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq)
@@ -389,7 +405,7 @@ static int tda18271_powerscan(struct dvb_frontend *fe,
389{ 405{
390 struct tda18271_priv *priv = fe->tuner_priv; 406 struct tda18271_priv *priv = fe->tuner_priv;
391 unsigned char *regs = priv->tda18271_regs; 407 unsigned char *regs = priv->tda18271_regs;
392 int sgn, bcal, count, wait; 408 int sgn, bcal, count, wait, ret;
393 u8 cid_target; 409 u8 cid_target;
394 u16 count_limit; 410 u16 count_limit;
395 u32 freq; 411 u32 freq;
@@ -421,7 +437,9 @@ static int tda18271_powerscan(struct dvb_frontend *fe,
421 tda18271_write_regs(fe, R_EP2, 1); 437 tda18271_write_regs(fe, R_EP2, 1);
422 438
423 /* read power detection info, stored in EB10 */ 439 /* read power detection info, stored in EB10 */
424 tda18271_read_extended(fe); 440 ret = tda18271_read_extended(fe);
441 if (tda_fail(ret))
442 return ret;
425 443
426 /* algorithm initialization */ 444 /* algorithm initialization */
427 sgn = 1; 445 sgn = 1;
@@ -447,7 +465,9 @@ static int tda18271_powerscan(struct dvb_frontend *fe,
447 tda18271_write_regs(fe, R_EP2, 1); 465 tda18271_write_regs(fe, R_EP2, 1);
448 466
449 /* read power detection info, stored in EB10 */ 467 /* read power detection info, stored in EB10 */
450 tda18271_read_extended(fe); 468 ret = tda18271_read_extended(fe);
469 if (tda_fail(ret))
470 return ret;
451 471
452 count += 200; 472 count += 200;
453 473
@@ -478,6 +498,7 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe)
478{ 498{
479 struct tda18271_priv *priv = fe->tuner_priv; 499 struct tda18271_priv *priv = fe->tuner_priv;
480 unsigned char *regs = priv->tda18271_regs; 500 unsigned char *regs = priv->tda18271_regs;
501 int ret;
481 502
482 /* set standard to digital */ 503 /* set standard to digital */
483 regs[R_EP3] &= ~0x1f; /* clear std bits */ 504 regs[R_EP3] &= ~0x1f; /* clear std bits */
@@ -489,10 +510,14 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe)
489 /* update IF output level & IF notch frequency */ 510 /* update IF output level & IF notch frequency */
490 regs[R_EP4] &= ~0x1c; /* clear if level bits */ 511 regs[R_EP4] &= ~0x1c; /* clear if level bits */
491 512
492 tda18271_write_regs(fe, R_EP3, 2); 513 ret = tda18271_write_regs(fe, R_EP3, 2);
514 if (tda_fail(ret))
515 goto fail;
493 516
494 regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ 517 regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
495 tda18271_write_regs(fe, R_EB18, 1); 518 ret = tda18271_write_regs(fe, R_EB18, 1);
519 if (tda_fail(ret))
520 goto fail;
496 521
497 regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */ 522 regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */
498 523
@@ -500,9 +525,9 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe)
500 regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */ 525 regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */
501 regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */ 526 regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */
502 527
503 tda18271_write_regs(fe, R_EB21, 3); 528 ret = tda18271_write_regs(fe, R_EB21, 3);
504 529fail:
505 return 0; 530 return ret;
506} 531}
507 532
508static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) 533static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq)
@@ -521,7 +546,7 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq)
521 546
522 i = tda18271_lookup_rf_band(fe, &freq, NULL); 547 i = tda18271_lookup_rf_band(fe, &freq, NULL);
523 548
524 if (i < 0) 549 if (tda_fail(i))
525 return i; 550 return i;
526 551
527 rf_default[RF1] = 1000 * map[i].rf1_def; 552 rf_default[RF1] = 1000 * map[i].rf1_def;
@@ -535,6 +560,8 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq)
535 560
536 /* look for optimized calibration frequency */ 561 /* look for optimized calibration frequency */
537 bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]); 562 bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]);
563 if (tda_fail(bcal))
564 return bcal;
538 565
539 tda18271_calc_rf_cal(fe, &rf_freq[rf]); 566 tda18271_calc_rf_cal(fe, &rf_freq[rf]);
540 prog_tab[rf] = regs[R_EB14]; 567 prog_tab[rf] = regs[R_EB14];
@@ -575,22 +602,29 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe)
575{ 602{
576 struct tda18271_priv *priv = fe->tuner_priv; 603 struct tda18271_priv *priv = fe->tuner_priv;
577 unsigned int i; 604 unsigned int i;
605 int ret;
578 606
579 tda_info("tda18271: performing RF tracking filter calibration\n"); 607 tda_info("tda18271: performing RF tracking filter calibration\n");
580 608
581 /* wait for die temperature stabilization */ 609 /* wait for die temperature stabilization */
582 msleep(200); 610 msleep(200);
583 611
584 tda18271_powerscan_init(fe); 612 ret = tda18271_powerscan_init(fe);
613 if (tda_fail(ret))
614 goto fail;
585 615
586 /* rf band calibration */ 616 /* rf band calibration */
587 for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) 617 for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) {
618 ret =
588 tda18271_rf_tracking_filters_init(fe, 1000 * 619 tda18271_rf_tracking_filters_init(fe, 1000 *
589 priv->rf_cal_state[i].rfmax); 620 priv->rf_cal_state[i].rfmax);
621 if (tda_fail(ret))
622 goto fail;
623 }
590 624
591 priv->tm_rfcal = tda18271_read_thermometer(fe); 625 priv->tm_rfcal = tda18271_read_thermometer(fe);
592 626fail:
593 return 0; 627 return ret;
594} 628}
595 629
596/* ------------------------------------------------------------------ */ 630/* ------------------------------------------------------------------ */
@@ -599,6 +633,7 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe)
599{ 633{
600 struct tda18271_priv *priv = fe->tuner_priv; 634 struct tda18271_priv *priv = fe->tuner_priv;
601 unsigned char *regs = priv->tda18271_regs; 635 unsigned char *regs = priv->tda18271_regs;
636 int ret;
602 637
603 /* test RF_CAL_OK to see if we need init */ 638 /* test RF_CAL_OK to see if we need init */
604 if ((regs[R_EP1] & 0x10) == 0) 639 if ((regs[R_EP1] & 0x10) == 0)
@@ -607,15 +642,22 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe)
607 if (priv->cal_initialized) 642 if (priv->cal_initialized)
608 return 0; 643 return 0;
609 644
610 tda18271_calc_rf_filter_curve(fe); 645 ret = tda18271_calc_rf_filter_curve(fe);
646 if (tda_fail(ret))
647 goto fail;
611 648
612 tda18271_por(fe); 649 ret = tda18271_por(fe);
650 if (tda_fail(ret))
651 goto fail;
613 652
614 tda_info("tda18271: RF tracking filter calibration complete\n"); 653 tda_info("tda18271: RF tracking filter calibration complete\n");
615 654
616 priv->cal_initialized = true; 655 priv->cal_initialized = true;
617 656 goto end;
618 return 0; 657fail:
658 tda_info("tda18271: RF tracking filter calibration failed!\n");
659end:
660 return ret;
619} 661}
620 662
621static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, 663static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe,
@@ -623,6 +665,7 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe,
623{ 665{
624 struct tda18271_priv *priv = fe->tuner_priv; 666 struct tda18271_priv *priv = fe->tuner_priv;
625 unsigned char *regs = priv->tda18271_regs; 667 unsigned char *regs = priv->tda18271_regs;
668 int ret;
626 u32 N = 0; 669 u32 N = 0;
627 670
628 /* calculate bp filter */ 671 /* calculate bp filter */
@@ -671,7 +714,10 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe,
671 714
672 tda18271_calc_main_pll(fe, N); 715 tda18271_calc_main_pll(fe, N);
673 716
674 tda18271_write_regs(fe, R_EP3, 11); 717 ret = tda18271_write_regs(fe, R_EP3, 11);
718 if (tda_fail(ret))
719 return ret;
720
675 msleep(5); /* RF tracking filter calibration initialization */ 721 msleep(5); /* RF tracking filter calibration initialization */
676 722
677 /* search for K,M,CO for RF calibration */ 723 /* search for K,M,CO for RF calibration */
@@ -719,45 +765,56 @@ static int tda18271_ir_cal_init(struct dvb_frontend *fe)
719{ 765{
720 struct tda18271_priv *priv = fe->tuner_priv; 766 struct tda18271_priv *priv = fe->tuner_priv;
721 unsigned char *regs = priv->tda18271_regs; 767 unsigned char *regs = priv->tda18271_regs;
768 int ret;
722 769
723 tda18271_read_regs(fe); 770 ret = tda18271_read_regs(fe);
771 if (tda_fail(ret))
772 goto fail;
724 773
725 /* test IR_CAL_OK to see if we need init */ 774 /* test IR_CAL_OK to see if we need init */
726 if ((regs[R_EP1] & 0x08) == 0) 775 if ((regs[R_EP1] & 0x08) == 0)
727 tda18271_init_regs(fe); 776 ret = tda18271_init_regs(fe);
728 777fail:
729 return 0; 778 return ret;
730} 779}
731 780
732static int tda18271_init(struct dvb_frontend *fe) 781static int tda18271_init(struct dvb_frontend *fe)
733{ 782{
734 struct tda18271_priv *priv = fe->tuner_priv; 783 struct tda18271_priv *priv = fe->tuner_priv;
784 int ret;
735 785
736 mutex_lock(&priv->lock); 786 mutex_lock(&priv->lock);
737 787
738 /* power up */ 788 /* power up */
739 tda18271_set_standby_mode(fe, 0, 0, 0); 789 ret = tda18271_set_standby_mode(fe, 0, 0, 0);
790 if (tda_fail(ret))
791 goto fail;
740 792
741 /* initialization */ 793 /* initialization */
742 tda18271_ir_cal_init(fe); 794 ret = tda18271_ir_cal_init(fe);
795 if (tda_fail(ret))
796 goto fail;
743 797
744 if (priv->id == TDA18271HDC2) 798 if (priv->id == TDA18271HDC2)
745 tda18271c2_rf_cal_init(fe); 799 tda18271c2_rf_cal_init(fe);
746 800fail:
747 mutex_unlock(&priv->lock); 801 mutex_unlock(&priv->lock);
748 802
749 return 0; 803 return ret;
750} 804}
751 805
752static int tda18271_tune(struct dvb_frontend *fe, 806static int tda18271_tune(struct dvb_frontend *fe,
753 struct tda18271_std_map_item *map, u32 freq, u32 bw) 807 struct tda18271_std_map_item *map, u32 freq, u32 bw)
754{ 808{
755 struct tda18271_priv *priv = fe->tuner_priv; 809 struct tda18271_priv *priv = fe->tuner_priv;
810 int ret;
756 811
757 tda_dbg("freq = %d, ifc = %d, bw = %d, agc_mode = %d, std = %d\n", 812 tda_dbg("freq = %d, ifc = %d, bw = %d, agc_mode = %d, std = %d\n",
758 freq, map->if_freq, bw, map->agc_mode, map->std); 813 freq, map->if_freq, bw, map->agc_mode, map->std);
759 814
760 tda18271_init(fe); 815 ret = tda18271_init(fe);
816 if (tda_fail(ret))
817 goto fail;
761 818
762 mutex_lock(&priv->lock); 819 mutex_lock(&priv->lock);
763 820
@@ -769,11 +826,11 @@ static int tda18271_tune(struct dvb_frontend *fe,
769 tda18271c2_rf_tracking_filters_correction(fe, freq); 826 tda18271c2_rf_tracking_filters_correction(fe, freq);
770 break; 827 break;
771 } 828 }
772 tda18271_channel_configuration(fe, map, freq, bw); 829 ret = tda18271_channel_configuration(fe, map, freq, bw);
773 830
774 mutex_unlock(&priv->lock); 831 mutex_unlock(&priv->lock);
775 832fail:
776 return 0; 833 return ret;
777} 834}
778 835
779/* ------------------------------------------------------------------ */ 836/* ------------------------------------------------------------------ */
@@ -837,7 +894,7 @@ static int tda18271_set_params(struct dvb_frontend *fe,
837 894
838 ret = tda18271_tune(fe, map, freq, bw); 895 ret = tda18271_tune(fe, map, freq, bw);
839 896
840 if (ret < 0) 897 if (tda_fail(ret))
841 goto fail; 898 goto fail;
842 899
843 priv->frequency = freq; 900 priv->frequency = freq;
@@ -893,7 +950,7 @@ static int tda18271_set_analog_params(struct dvb_frontend *fe,
893 950
894 ret = tda18271_tune(fe, map, freq, 0); 951 ret = tda18271_tune(fe, map, freq, 0);
895 952
896 if (ret < 0) 953 if (tda_fail(ret))
897 goto fail; 954 goto fail;
898 955
899 priv->frequency = freq; 956 priv->frequency = freq;
@@ -905,16 +962,17 @@ fail:
905static int tda18271_sleep(struct dvb_frontend *fe) 962static int tda18271_sleep(struct dvb_frontend *fe)
906{ 963{
907 struct tda18271_priv *priv = fe->tuner_priv; 964 struct tda18271_priv *priv = fe->tuner_priv;
965 int ret;
908 966
909 mutex_lock(&priv->lock); 967 mutex_lock(&priv->lock);
910 968
911 /* standby mode w/ slave tuner output 969 /* standby mode w/ slave tuner output
912 * & loop thru & xtal oscillator on */ 970 * & loop thru & xtal oscillator on */
913 tda18271_set_standby_mode(fe, 1, 0, 0); 971 ret = tda18271_set_standby_mode(fe, 1, 0, 0);
914 972
915 mutex_unlock(&priv->lock); 973 mutex_unlock(&priv->lock);
916 974
917 return 0; 975 return ret;
918} 976}
919 977
920static int tda18271_release(struct dvb_frontend *fe) 978static int tda18271_release(struct dvb_frontend *fe)
@@ -1095,10 +1153,10 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
1095 if (cfg) 1153 if (cfg)
1096 priv->small_i2c = cfg->small_i2c; 1154 priv->small_i2c = cfg->small_i2c;
1097 1155
1098 if (tda18271_get_id(fe) < 0) 1156 if (tda_fail(tda18271_get_id(fe)))
1099 goto fail; 1157 goto fail;
1100 1158
1101 if (tda18271_assign_map_layout(fe) < 0) 1159 if (tda_fail(tda18271_assign_map_layout(fe)))
1102 goto fail; 1160 goto fail;
1103 1161
1104 mutex_lock(&priv->lock); 1162 mutex_lock(&priv->lock);
diff --git a/drivers/media/common/tuners/tda18271-priv.h b/drivers/media/common/tuners/tda18271-priv.h
index 2bc5eb368ea2..81a739365f8c 100644
--- a/drivers/media/common/tuners/tda18271-priv.h
+++ b/drivers/media/common/tuners/tda18271-priv.h
@@ -153,6 +153,15 @@ extern int tda18271_debug;
153#define tda_reg(fmt, arg...) dprintk(KERN_DEBUG, DBG_REG, fmt, ##arg) 153#define tda_reg(fmt, arg...) dprintk(KERN_DEBUG, DBG_REG, fmt, ##arg)
154#define tda_cal(fmt, arg...) dprintk(KERN_DEBUG, DBG_CAL, fmt, ##arg) 154#define tda_cal(fmt, arg...) dprintk(KERN_DEBUG, DBG_CAL, fmt, ##arg)
155 155
156#define tda_fail(ret) \
157({ \
158 int __ret; \
159 __ret = (ret < 0); \
160 if (__ret) \
161 tda_printk(KERN_ERR, "error %d on line %d\n", ret, __LINE__);\
162 __ret; \
163})
164
156/*---------------------------------------------------------------------*/ 165/*---------------------------------------------------------------------*/
157 166
158enum tda18271_map_type { 167enum tda18271_map_type {
diff --git a/drivers/media/common/tuners/tea5767.c b/drivers/media/common/tuners/tea5767.c
index f6e7d7ad8424..1f5646334a8f 100644
--- a/drivers/media/common/tuners/tea5767.c
+++ b/drivers/media/common/tuners/tea5767.c
@@ -373,14 +373,14 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr)
373 373
374 if ((rc = tuner_i2c_xfer_recv(&i2c, buffer, 7))< 5) { 374 if ((rc = tuner_i2c_xfer_recv(&i2c, buffer, 7))< 5) {
375 printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc); 375 printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc);
376 return EINVAL; 376 return -EINVAL;
377 } 377 }
378 378
379 /* If all bytes are the same then it's a TV tuner and not a tea5767 */ 379 /* If all bytes are the same then it's a TV tuner and not a tea5767 */
380 if (buffer[0] == buffer[1] && buffer[0] == buffer[2] && 380 if (buffer[0] == buffer[1] && buffer[0] == buffer[2] &&
381 buffer[0] == buffer[3] && buffer[0] == buffer[4]) { 381 buffer[0] == buffer[3] && buffer[0] == buffer[4]) {
382 printk(KERN_WARNING "All bytes are equal. It is not a TEA5767\n"); 382 printk(KERN_WARNING "All bytes are equal. It is not a TEA5767\n");
383 return EINVAL; 383 return -EINVAL;
384 } 384 }
385 385
386 /* Status bytes: 386 /* Status bytes:
@@ -390,7 +390,7 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr)
390 */ 390 */
391 if (((buffer[3] & 0x0f) != 0x00) || (buffer[4] != 0x00)) { 391 if (((buffer[3] & 0x0f) != 0x00) || (buffer[4] != 0x00)) {
392 printk(KERN_WARNING "Chip ID is not zero. It is not a TEA5767\n"); 392 printk(KERN_WARNING "Chip ID is not zero. It is not a TEA5767\n");
393 return EINVAL; 393 return -EINVAL;
394 } 394 }
395 395
396 396
diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c
index 43d35bdb221f..ceae6db901ec 100644
--- a/drivers/media/common/tuners/xc5000.c
+++ b/drivers/media/common/tuners/xc5000.c
@@ -212,7 +212,7 @@ static void xc5000_TunerReset(struct dvb_frontend *fe)
212 dprintk(1, "%s()\n", __func__); 212 dprintk(1, "%s()\n", __func__);
213 213
214 if (priv->cfg->tuner_callback) { 214 if (priv->cfg->tuner_callback) {
215 ret = priv->cfg->tuner_callback(priv->cfg->priv, 215 ret = priv->cfg->tuner_callback(priv->devptr,
216 XC5000_TUNER_RESET, 0); 216 XC5000_TUNER_RESET, 0);
217 if (ret) 217 if (ret)
218 printk(KERN_ERR "xc5000: reset failed\n"); 218 printk(KERN_ERR "xc5000: reset failed\n");
@@ -900,9 +900,9 @@ static const struct dvb_tuner_ops xc5000_tuner_ops = {
900 .get_status = xc5000_get_status 900 .get_status = xc5000_get_status
901}; 901};
902 902
903struct dvb_frontend * xc5000_attach(struct dvb_frontend *fe, 903struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe,
904 struct i2c_adapter *i2c, 904 struct i2c_adapter *i2c,
905 struct xc5000_config *cfg) 905 struct xc5000_config *cfg, void *devptr)
906{ 906{
907 struct xc5000_priv *priv = NULL; 907 struct xc5000_priv *priv = NULL;
908 u16 id = 0; 908 u16 id = 0;
@@ -916,6 +916,7 @@ struct dvb_frontend * xc5000_attach(struct dvb_frontend *fe,
916 priv->cfg = cfg; 916 priv->cfg = cfg;
917 priv->bandwidth = BANDWIDTH_6_MHZ; 917 priv->bandwidth = BANDWIDTH_6_MHZ;
918 priv->i2c = i2c; 918 priv->i2c = i2c;
919 priv->devptr = devptr;
919 920
920 /* Check if firmware has been loaded. It is possible that another 921 /* Check if firmware has been loaded. It is possible that another
921 instance of the driver has loaded the firmware. 922 instance of the driver has loaded the firmware.
diff --git a/drivers/media/common/tuners/xc5000.h b/drivers/media/common/tuners/xc5000.h
index 0ee80f9d19b8..c910715addc9 100644
--- a/drivers/media/common/tuners/xc5000.h
+++ b/drivers/media/common/tuners/xc5000.h
@@ -31,29 +31,31 @@ struct xc5000_config {
31 u8 i2c_address; 31 u8 i2c_address;
32 u32 if_khz; 32 u32 if_khz;
33 33
34 /* For each bridge framework, when it attaches either analog or digital,
35 * it has to store a reference back to its _core equivalent structure,
36 * so that it can service the hardware by steering gpio's etc.
37 * Each bridge implementation is different so cast priv accordingly.
38 * The xc5000 driver cares not for this value, other than ensuring
39 * it's passed back to a bridge during tuner_callback().
40 */
41 void *priv;
42 int (*tuner_callback) (void *priv, int command, int arg); 34 int (*tuner_callback) (void *priv, int command, int arg);
43}; 35};
44 36
45/* xc5000 callback command */ 37/* xc5000 callback command */
46#define XC5000_TUNER_RESET 0 38#define XC5000_TUNER_RESET 0
47 39
40/* For each bridge framework, when it attaches either analog or digital,
41 * it has to store a reference back to its _core equivalent structure,
42 * so that it can service the hardware by steering gpio's etc.
43 * Each bridge implementation is different so cast devptr accordingly.
44 * The xc5000 driver cares not for this value, other than ensuring
45 * it's passed back to a bridge during tuner_callback().
46 */
47
48#if defined(CONFIG_MEDIA_TUNER_XC5000) || \ 48#if defined(CONFIG_MEDIA_TUNER_XC5000) || \
49 (defined(CONFIG_MEDIA_TUNER_XC5000_MODULE) && defined(MODULE)) 49 (defined(CONFIG_MEDIA_TUNER_XC5000_MODULE) && defined(MODULE))
50extern struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, 50extern struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe,
51 struct i2c_adapter *i2c, 51 struct i2c_adapter *i2c,
52 struct xc5000_config *cfg); 52 struct xc5000_config *cfg,
53 void *devptr);
53#else 54#else
54static inline struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, 55static inline struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe,
55 struct i2c_adapter *i2c, 56 struct i2c_adapter *i2c,
56 struct xc5000_config *cfg) 57 struct xc5000_config *cfg,
58 void *devptr)
57{ 59{
58 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 60 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
59 return NULL; 61 return NULL;
diff --git a/drivers/media/common/tuners/xc5000_priv.h b/drivers/media/common/tuners/xc5000_priv.h
index 13b2d19341da..ecebfe4745ad 100644
--- a/drivers/media/common/tuners/xc5000_priv.h
+++ b/drivers/media/common/tuners/xc5000_priv.h
@@ -31,6 +31,8 @@ struct xc5000_priv {
31 u8 video_standard; 31 u8 video_standard;
32 u8 rf_mode; 32 u8 rf_mode;
33 u8 fwloaded; 33 u8 fwloaded;
34
35 void *devptr;
34}; 36};
35 37
36#endif 38#endif
diff --git a/drivers/media/dvb/b2c2/flexcop-fe-tuner.c b/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
index 7b0ea3bdfafb..f9d087669d5d 100644
--- a/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
+++ b/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
@@ -634,7 +634,7 @@ int flexcop_frontend_init(struct flexcop_device *fc)
634 } 634 }
635 635
636 /* try the sky v2.3 (vp310/Samsung tbdu18132(tsa5059)) */ 636 /* try the sky v2.3 (vp310/Samsung tbdu18132(tsa5059)) */
637 fc->fe = dvb_attach(vp310_mt312_attach, 637 fc->fe = dvb_attach(mt312_attach,
638 &skystar23_samsung_tbdu18132_config, i2c); 638 &skystar23_samsung_tbdu18132_config, i2c);
639 if (fc->fe != NULL) { 639 if (fc->fe != NULL) {
640 ops = &fc->fe->ops; 640 ops = &fc->fe->ops;
diff --git a/drivers/media/dvb/bt8xx/Kconfig b/drivers/media/dvb/bt8xx/Kconfig
index d1239b8342f8..7588db1319d0 100644
--- a/drivers/media/dvb/bt8xx/Kconfig
+++ b/drivers/media/dvb/bt8xx/Kconfig
@@ -1,6 +1,7 @@
1config DVB_BT8XX 1config DVB_BT8XX
2 tristate "BT8xx based PCI cards" 2 tristate "BT8xx based PCI cards"
3 depends on DVB_CORE && PCI && I2C && VIDEO_BT848 3 depends on DVB_CORE && PCI && I2C && VIDEO_BT848
4 depends on HOTPLUG # due to FW_LOADER
4 select DVB_MT352 if !DVB_FE_CUSTOMISE 5 select DVB_MT352 if !DVB_FE_CUSTOMISE
5 select DVB_SP887X if !DVB_FE_CUSTOMISE 6 select DVB_SP887X if !DVB_FE_CUSTOMISE
6 select DVB_NXT6000 if !DVB_FE_CUSTOMISE 7 select DVB_NXT6000 if !DVB_FE_CUSTOMISE
diff --git a/drivers/media/dvb/cinergyT2/Kconfig b/drivers/media/dvb/cinergyT2/Kconfig
index 3d778c5aba68..c03513b2ccae 100644
--- a/drivers/media/dvb/cinergyT2/Kconfig
+++ b/drivers/media/dvb/cinergyT2/Kconfig
@@ -1,6 +1,6 @@
1config DVB_CINERGYT2 1config DVB_CINERGYT2
2 tristate "Terratec CinergyT2/qanu USB2 DVB-T receiver" 2 tristate "Terratec CinergyT2/qanu USB2 DVB-T receiver"
3 depends on DVB_CORE && USB 3 depends on DVB_CORE && USB && INPUT
4 help 4 help
5 Support for "TerraTec CinergyT2" USB2.0 Highspeed DVB Receivers 5 Support for "TerraTec CinergyT2" USB2.0 Highspeed DVB Receivers
6 6
diff --git a/drivers/media/dvb/dvb-core/dvb_ca_en50221.c b/drivers/media/dvb/dvb-core/dvb_ca_en50221.c
index 8cbdb0ec67e2..588fbe105c27 100644
--- a/drivers/media/dvb/dvb-core/dvb_ca_en50221.c
+++ b/drivers/media/dvb/dvb-core/dvb_ca_en50221.c
@@ -910,15 +910,21 @@ static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca)
910 int curdelay = 100000000; 910 int curdelay = 100000000;
911 int slot; 911 int slot;
912 912
913 /* Beware of too high polling frequency, because one polling
914 * call might take several hundred milliseconds until timeout!
915 */
913 for (slot = 0; slot < ca->slot_count; slot++) { 916 for (slot = 0; slot < ca->slot_count; slot++) {
914 switch (ca->slot_info[slot].slot_state) { 917 switch (ca->slot_info[slot].slot_state) {
915 default: 918 default:
916 case DVB_CA_SLOTSTATE_NONE: 919 case DVB_CA_SLOTSTATE_NONE:
920 delay = HZ * 60; /* 60s */
921 if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE))
922 delay = HZ * 5; /* 5s */
923 break;
917 case DVB_CA_SLOTSTATE_INVALID: 924 case DVB_CA_SLOTSTATE_INVALID:
918 delay = HZ * 60; 925 delay = HZ * 60; /* 60s */
919 if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) { 926 if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE))
920 delay = HZ / 10; 927 delay = HZ / 10; /* 100ms */
921 }
922 break; 928 break;
923 929
924 case DVB_CA_SLOTSTATE_UNINITIALISED: 930 case DVB_CA_SLOTSTATE_UNINITIALISED:
@@ -926,19 +932,17 @@ static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca)
926 case DVB_CA_SLOTSTATE_VALIDATE: 932 case DVB_CA_SLOTSTATE_VALIDATE:
927 case DVB_CA_SLOTSTATE_WAITFR: 933 case DVB_CA_SLOTSTATE_WAITFR:
928 case DVB_CA_SLOTSTATE_LINKINIT: 934 case DVB_CA_SLOTSTATE_LINKINIT:
929 delay = HZ / 10; 935 delay = HZ / 10; /* 100ms */
930 break; 936 break;
931 937
932 case DVB_CA_SLOTSTATE_RUNNING: 938 case DVB_CA_SLOTSTATE_RUNNING:
933 delay = HZ * 60; 939 delay = HZ * 60; /* 60s */
934 if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) { 940 if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE))
935 delay = HZ / 10; 941 delay = HZ / 10; /* 100ms */
936 }
937 if (ca->open) { 942 if (ca->open) {
938 if ((!ca->slot_info[slot].da_irq_supported) || 943 if ((!ca->slot_info[slot].da_irq_supported) ||
939 (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_DA))) { 944 (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_DA)))
940 delay = HZ / 10; 945 delay = HZ / 10; /* 100ms */
941 }
942 } 946 }
943 break; 947 break;
944 } 948 }
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index 4c1cff9feb2e..cf4584e48b6d 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -1,6 +1,7 @@
1config DVB_USB 1config DVB_USB
2 tristate "Support for various USB DVB devices" 2 tristate "Support for various USB DVB devices"
3 depends on DVB_CORE && USB && I2C 3 depends on DVB_CORE && USB && I2C
4 depends on HOTPLUG # due to FW_LOADER
4 select FW_LOADER 5 select FW_LOADER
5 help 6 help
6 By enabling this you will be able to choose the various supported 7 By enabling this you will be able to choose the various supported
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 6d2384605927..c20553c4da1f 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -30,7 +30,7 @@ config DVB_CX24123
30 A DVB-S tuner module. Say Y when you want to support this frontend. 30 A DVB-S tuner module. Say Y when you want to support this frontend.
31 31
32config DVB_MT312 32config DVB_MT312
33 tristate "Zarlink VP310/MT312 based" 33 tristate "Zarlink VP310/MT312/ZL10313 based"
34 depends on DVB_CORE && I2C 34 depends on DVB_CORE && I2C
35 default m if DVB_FE_CUSTOMISE 35 default m if DVB_FE_CUSTOMISE
36 help 36 help
@@ -97,7 +97,7 @@ comment "DVB-T (terrestrial) frontends"
97 97
98config DVB_SP8870 98config DVB_SP8870
99 tristate "Spase sp8870 based" 99 tristate "Spase sp8870 based"
100 depends on DVB_CORE && I2C 100 depends on DVB_CORE && I2C && HOTPLUG
101 default m if DVB_FE_CUSTOMISE 101 default m if DVB_FE_CUSTOMISE
102 select FW_LOADER 102 select FW_LOADER
103 help 103 help
@@ -110,7 +110,7 @@ config DVB_SP8870
110 110
111config DVB_SP887X 111config DVB_SP887X
112 tristate "Spase sp887x based" 112 tristate "Spase sp887x based"
113 depends on DVB_CORE && I2C 113 depends on DVB_CORE && I2C && HOTPLUG
114 default m if DVB_FE_CUSTOMISE 114 default m if DVB_FE_CUSTOMISE
115 select FW_LOADER 115 select FW_LOADER
116 help 116 help
@@ -144,7 +144,7 @@ config DVB_L64781
144 144
145config DVB_TDA1004X 145config DVB_TDA1004X
146 tristate "Philips TDA10045H/TDA10046H based" 146 tristate "Philips TDA10045H/TDA10046H based"
147 depends on DVB_CORE && I2C 147 depends on DVB_CORE && I2C && HOTPLUG
148 default m if DVB_FE_CUSTOMISE 148 default m if DVB_FE_CUSTOMISE
149 select FW_LOADER 149 select FW_LOADER
150 help 150 help
@@ -211,7 +211,7 @@ config DVB_DIB7000P
211 211
212config DVB_TDA10048 212config DVB_TDA10048
213 tristate "Philips TDA10048HN based" 213 tristate "Philips TDA10048HN based"
214 depends on DVB_CORE && I2C 214 depends on DVB_CORE && I2C && HOTPLUG
215 default m if DVB_FE_CUSTOMISE 215 default m if DVB_FE_CUSTOMISE
216 select FW_LOADER 216 select FW_LOADER
217 help 217 help
@@ -253,7 +253,7 @@ comment "ATSC (North American/Korean Terrestrial/Cable DTV) frontends"
253 253
254config DVB_NXT200X 254config DVB_NXT200X
255 tristate "NxtWave Communications NXT2002/NXT2004 based" 255 tristate "NxtWave Communications NXT2002/NXT2004 based"
256 depends on DVB_CORE && I2C 256 depends on DVB_CORE && I2C && HOTPLUG
257 default m if DVB_FE_CUSTOMISE 257 default m if DVB_FE_CUSTOMISE
258 select FW_LOADER 258 select FW_LOADER
259 help 259 help
@@ -268,7 +268,7 @@ config DVB_NXT200X
268 268
269config DVB_OR51211 269config DVB_OR51211
270 tristate "Oren OR51211 based" 270 tristate "Oren OR51211 based"
271 depends on DVB_CORE && I2C 271 depends on DVB_CORE && I2C && HOTPLUG
272 default m if DVB_FE_CUSTOMISE 272 default m if DVB_FE_CUSTOMISE
273 select FW_LOADER 273 select FW_LOADER
274 help 274 help
@@ -281,7 +281,7 @@ config DVB_OR51211
281 281
282config DVB_OR51132 282config DVB_OR51132
283 tristate "Oren OR51132 based" 283 tristate "Oren OR51132 based"
284 depends on DVB_CORE && I2C 284 depends on DVB_CORE && I2C && HOTPLUG
285 default m if DVB_FE_CUSTOMISE 285 default m if DVB_FE_CUSTOMISE
286 select FW_LOADER 286 select FW_LOADER
287 help 287 help
@@ -297,7 +297,7 @@ config DVB_OR51132
297 297
298config DVB_BCM3510 298config DVB_BCM3510
299 tristate "Broadcom BCM3510" 299 tristate "Broadcom BCM3510"
300 depends on DVB_CORE && I2C 300 depends on DVB_CORE && I2C && HOTPLUG
301 default m if DVB_FE_CUSTOMISE 301 default m if DVB_FE_CUSTOMISE
302 select FW_LOADER 302 select FW_LOADER
303 help 303 help
diff --git a/drivers/media/dvb/frontends/itd1000.c b/drivers/media/dvb/frontends/itd1000.c
index 04c562ccf990..600dad6b41ea 100644
--- a/drivers/media/dvb/frontends/itd1000.c
+++ b/drivers/media/dvb/frontends/itd1000.c
@@ -195,7 +195,7 @@ static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
195 } 195 }
196} 196}
197 197
198struct { 198static const struct {
199 u32 freq; 199 u32 freq;
200 u8 values[10]; /* RFTR, RFST1 - RFST9 */ 200 u8 values[10]; /* RFTR, RFST1 - RFST9 */
201} itd1000_fre_values[] = { 201} itd1000_fre_values[] = {
diff --git a/drivers/media/dvb/frontends/mt312.c b/drivers/media/dvb/frontends/mt312.c
index 081ca3398c76..5ac9b15920f8 100644
--- a/drivers/media/dvb/frontends/mt312.c
+++ b/drivers/media/dvb/frontends/mt312.c
@@ -737,7 +737,7 @@ static void mt312_release(struct dvb_frontend *fe)
737} 737}
738 738
739#define MT312_SYS_CLK 90000000UL /* 90 MHz */ 739#define MT312_SYS_CLK 90000000UL /* 90 MHz */
740static struct dvb_frontend_ops vp310_mt312_ops = { 740static struct dvb_frontend_ops mt312_ops = {
741 741
742 .info = { 742 .info = {
743 .name = "Zarlink ???? DVB-S", 743 .name = "Zarlink ???? DVB-S",
@@ -776,7 +776,7 @@ static struct dvb_frontend_ops vp310_mt312_ops = {
776 .set_voltage = mt312_set_voltage, 776 .set_voltage = mt312_set_voltage,
777}; 777};
778 778
779struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config, 779struct dvb_frontend *mt312_attach(const struct mt312_config *config,
780 struct i2c_adapter *i2c) 780 struct i2c_adapter *i2c)
781{ 781{
782 struct mt312_state *state = NULL; 782 struct mt312_state *state = NULL;
@@ -795,7 +795,7 @@ struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config,
795 goto error; 795 goto error;
796 796
797 /* create dvb_frontend */ 797 /* create dvb_frontend */
798 memcpy(&state->frontend.ops, &vp310_mt312_ops, 798 memcpy(&state->frontend.ops, &mt312_ops,
799 sizeof(struct dvb_frontend_ops)); 799 sizeof(struct dvb_frontend_ops));
800 state->frontend.demodulator_priv = state; 800 state->frontend.demodulator_priv = state;
801 801
@@ -827,12 +827,13 @@ error:
827 kfree(state); 827 kfree(state);
828 return NULL; 828 return NULL;
829} 829}
830EXPORT_SYMBOL(vp310_mt312_attach); 830EXPORT_SYMBOL(mt312_attach);
831 831
832module_param(debug, int, 0644); 832module_param(debug, int, 0644);
833MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 833MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
834 834
835MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver"); 835MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
836MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>"); 836MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
837MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
837MODULE_LICENSE("GPL"); 838MODULE_LICENSE("GPL");
838 839
diff --git a/drivers/media/dvb/frontends/mt312.h b/drivers/media/dvb/frontends/mt312.h
index de796eab3911..29e3bb5496b8 100644
--- a/drivers/media/dvb/frontends/mt312.h
+++ b/drivers/media/dvb/frontends/mt312.h
@@ -37,10 +37,10 @@ struct mt312_config {
37}; 37};
38 38
39#if defined(CONFIG_DVB_MT312) || (defined(CONFIG_DVB_MT312_MODULE) && defined(MODULE)) 39#if defined(CONFIG_DVB_MT312) || (defined(CONFIG_DVB_MT312_MODULE) && defined(MODULE))
40struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config, 40struct dvb_frontend *mt312_attach(const struct mt312_config *config,
41 struct i2c_adapter *i2c); 41 struct i2c_adapter *i2c);
42#else 42#else
43static inline struct dvb_frontend *vp310_mt312_attach( 43static inline struct dvb_frontend *mt312_attach(
44 const struct mt312_config *config, struct i2c_adapter *i2c) 44 const struct mt312_config *config, struct i2c_adapter *i2c)
45{ 45{
46 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 46 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
diff --git a/drivers/media/dvb/ttpci/Kconfig b/drivers/media/dvb/ttpci/Kconfig
index ae882432dd3d..d4339b1b3b68 100644
--- a/drivers/media/dvb/ttpci/Kconfig
+++ b/drivers/media/dvb/ttpci/Kconfig
@@ -5,6 +5,7 @@ config TTPCI_EEPROM
5config DVB_AV7110 5config DVB_AV7110
6 tristate "AV7110 cards" 6 tristate "AV7110 cards"
7 depends on DVB_CORE && PCI && I2C 7 depends on DVB_CORE && PCI && I2C
8 depends on HOTPLUG
8 select FW_LOADER if !DVB_AV7110_FIRMWARE 9 select FW_LOADER if !DVB_AV7110_FIRMWARE
9 select TTPCI_EEPROM 10 select TTPCI_EEPROM
10 select VIDEO_SAA7146_VV 11 select VIDEO_SAA7146_VV
@@ -123,6 +124,7 @@ config DVB_BUDGET_AV
123 depends on DVB_BUDGET_CORE && I2C 124 depends on DVB_BUDGET_CORE && I2C
124 select VIDEO_SAA7146_VV 125 select VIDEO_SAA7146_VV
125 depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV 126 depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV
127 depends on HOTPLUG # dependency of FW_LOADER
126 select DVB_PLL if !DVB_FE_CUSTOMISE 128 select DVB_PLL if !DVB_FE_CUSTOMISE
127 select DVB_STV0299 if !DVB_FE_CUSTOMISE 129 select DVB_STV0299 if !DVB_FE_CUSTOMISE
128 select DVB_TDA1004X if !DVB_FE_CUSTOMISE 130 select DVB_TDA1004X if !DVB_FE_CUSTOMISE
diff --git a/drivers/media/dvb/ttusb-dec/Kconfig b/drivers/media/dvb/ttusb-dec/Kconfig
index 83611012ef34..0712899e39a4 100644
--- a/drivers/media/dvb/ttusb-dec/Kconfig
+++ b/drivers/media/dvb/ttusb-dec/Kconfig
@@ -1,6 +1,7 @@
1config DVB_TTUSB_DEC 1config DVB_TTUSB_DEC
2 tristate "Technotrend/Hauppauge USB DEC devices" 2 tristate "Technotrend/Hauppauge USB DEC devices"
3 depends on DVB_CORE && USB 3 depends on DVB_CORE && USB
4 depends on HOTPLUG # due to FW_LOADER
4 select FW_LOADER 5 select FW_LOADER
5 select CRC32 6 select CRC32
6 help 7 help
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index fe743aa7f645..89d8d37838a3 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -44,6 +44,10 @@ config VIDEO_TVEEPROM
44 tristate 44 tristate
45 depends on I2C 45 depends on I2C
46 46
47config VIDEO_TUNER
48 tristate
49 depends on MEDIA_TUNER
50
47# 51#
48# Multimedia Video device configuration 52# Multimedia Video device configuration
49# 53#
@@ -690,7 +694,7 @@ config VIDEO_MXB
690 tristate "Siemens-Nixdorf 'Multimedia eXtension Board'" 694 tristate "Siemens-Nixdorf 'Multimedia eXtension Board'"
691 depends on PCI && VIDEO_V4L1 && I2C 695 depends on PCI && VIDEO_V4L1 && I2C
692 select VIDEO_SAA7146_VV 696 select VIDEO_SAA7146_VV
693 select MEDIA_TUNER 697 select VIDEO_TUNER
694 select VIDEO_SAA7111 if VIDEO_HELPER_CHIPS_AUTO 698 select VIDEO_SAA7111 if VIDEO_HELPER_CHIPS_AUTO
695 select VIDEO_TDA9840 if VIDEO_HELPER_CHIPS_AUTO 699 select VIDEO_TDA9840 if VIDEO_HELPER_CHIPS_AUTO
696 select VIDEO_TEA6415C if VIDEO_HELPER_CHIPS_AUTO 700 select VIDEO_TEA6415C if VIDEO_HELPER_CHIPS_AUTO
@@ -906,7 +910,7 @@ config SOC_CAMERA
906 910
907config SOC_CAMERA_MT9M001 911config SOC_CAMERA_MT9M001
908 tristate "mt9m001 support" 912 tristate "mt9m001 support"
909 depends on SOC_CAMERA 913 depends on SOC_CAMERA && I2C
910 select GPIO_PCA953X if MT9M001_PCA9536_SWITCH 914 select GPIO_PCA953X if MT9M001_PCA9536_SWITCH
911 help 915 help
912 This driver supports MT9M001 cameras from Micron, monochrome 916 This driver supports MT9M001 cameras from Micron, monochrome
@@ -921,7 +925,7 @@ config MT9M001_PCA9536_SWITCH
921 925
922config SOC_CAMERA_MT9V022 926config SOC_CAMERA_MT9V022
923 tristate "mt9v022 support" 927 tristate "mt9v022 support"
924 depends on SOC_CAMERA 928 depends on SOC_CAMERA && I2C
925 select GPIO_PCA953X if MT9V022_PCA9536_SWITCH 929 select GPIO_PCA953X if MT9V022_PCA9536_SWITCH
926 help 930 help
927 This driver supports MT9V022 cameras from Micron 931 This driver supports MT9V022 cameras from Micron
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index a352c6e31f0c..dff0d6abe917 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -84,7 +84,7 @@ obj-$(CONFIG_VIDEO_HEXIUM_GEMINI) += hexium_gemini.o
84obj-$(CONFIG_VIDEO_DPC) += dpc7146.o 84obj-$(CONFIG_VIDEO_DPC) += dpc7146.o
85obj-$(CONFIG_TUNER_3036) += tuner-3036.o 85obj-$(CONFIG_TUNER_3036) += tuner-3036.o
86 86
87obj-$(CONFIG_MEDIA_TUNER) += tuner.o 87obj-$(CONFIG_VIDEO_TUNER) += tuner.o
88 88
89obj-$(CONFIG_VIDEOBUF_GEN) += videobuf-core.o 89obj-$(CONFIG_VIDEOBUF_GEN) += videobuf-core.o
90obj-$(CONFIG_VIDEOBUF_DMA_SG) += videobuf-dma-sg.o 90obj-$(CONFIG_VIDEOBUF_DMA_SG) += videobuf-dma-sg.o
diff --git a/drivers/media/video/au0828/Kconfig b/drivers/media/video/au0828/Kconfig
index cab277fafa63..def10d086373 100644
--- a/drivers/media/video/au0828/Kconfig
+++ b/drivers/media/video/au0828/Kconfig
@@ -1,8 +1,9 @@
1 1
2config VIDEO_AU0828 2config VIDEO_AU0828
3 tristate "Auvitek AU0828 support" 3 tristate "Auvitek AU0828 support"
4 depends on VIDEO_DEV && I2C && INPUT && DVB_CORE 4 depends on VIDEO_DEV && I2C && INPUT && DVB_CORE && USB
5 select I2C_ALGOBIT 5 select I2C_ALGOBIT
6 select VIDEO_TVEEPROM
6 select DVB_AU8522 if !DVB_FE_CUSTOMIZE 7 select DVB_AU8522 if !DVB_FE_CUSTOMIZE
7 select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMIZE 8 select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMIZE
8 ---help--- 9 ---help---
diff --git a/drivers/media/video/au0828/au0828-dvb.c b/drivers/media/video/au0828/au0828-dvb.c
index 1371b4e4b5f1..c86a5f17eca8 100644
--- a/drivers/media/video/au0828/au0828-dvb.c
+++ b/drivers/media/video/au0828/au0828-dvb.c
@@ -337,12 +337,10 @@ int au0828_dvb_register(struct au0828_dev *dev)
337 dvb->frontend = dvb_attach(au8522_attach, 337 dvb->frontend = dvb_attach(au8522_attach,
338 &hauppauge_hvr950q_config, 338 &hauppauge_hvr950q_config,
339 &dev->i2c_adap); 339 &dev->i2c_adap);
340 if (dvb->frontend != NULL) { 340 if (dvb->frontend != NULL)
341 hauppauge_hvr950q_tunerconfig.priv = dev;
342 dvb_attach(xc5000_attach, dvb->frontend, 341 dvb_attach(xc5000_attach, dvb->frontend,
343 &dev->i2c_adap, 342 &dev->i2c_adap,
344 &hauppauge_hvr950q_tunerconfig); 343 &hauppauge_hvr950q_tunerconfig, dev);
345 }
346 break; 344 break;
347 default: 345 default:
348 printk(KERN_WARNING "The frontend of your DVB/ATSC card " 346 printk(KERN_WARNING "The frontend of your DVB/ATSC card "
diff --git a/drivers/media/video/bt8xx/Kconfig b/drivers/media/video/bt8xx/Kconfig
index 7431ef6de9f1..24a34fc1f2b3 100644
--- a/drivers/media/video/bt8xx/Kconfig
+++ b/drivers/media/video/bt8xx/Kconfig
@@ -1,12 +1,13 @@
1config VIDEO_BT848 1config VIDEO_BT848
2 tristate "BT848 Video For Linux" 2 tristate "BT848 Video For Linux"
3 depends on VIDEO_DEV && PCI && I2C && VIDEO_V4L2 && INPUT 3 depends on VIDEO_DEV && PCI && I2C && VIDEO_V4L2 && INPUT
4 depends on HOTPLUG # due to FW_LOADER
4 select I2C_ALGOBIT 5 select I2C_ALGOBIT
5 select FW_LOADER 6 select FW_LOADER
6 select VIDEO_BTCX 7 select VIDEO_BTCX
7 select VIDEOBUF_DMA_SG 8 select VIDEOBUF_DMA_SG
8 select VIDEO_IR 9 select VIDEO_IR
9 select MEDIA_TUNER 10 select VIDEO_TUNER
10 select VIDEO_TVEEPROM 11 select VIDEO_TVEEPROM
11 select VIDEO_MSP3400 if VIDEO_HELPER_CHIPS_AUTO 12 select VIDEO_MSP3400 if VIDEO_HELPER_CHIPS_AUTO
12 select VIDEO_TVAUDIO if VIDEO_HELPER_CHIPS_AUTO 13 select VIDEO_TVAUDIO if VIDEO_HELPER_CHIPS_AUTO
diff --git a/drivers/media/video/cx18/Kconfig b/drivers/media/video/cx18/Kconfig
index acc4b47f1d1d..5f942690570c 100644
--- a/drivers/media/video/cx18/Kconfig
+++ b/drivers/media/video/cx18/Kconfig
@@ -1,14 +1,17 @@
1config VIDEO_CX18 1config VIDEO_CX18
2 tristate "Conexant cx23418 MPEG encoder support" 2 tristate "Conexant cx23418 MPEG encoder support"
3 depends on VIDEO_V4L2 && DVB_CORE && PCI && I2C && EXPERIMENTAL 3 depends on VIDEO_V4L2 && DVB_CORE && PCI && I2C && EXPERIMENTAL
4 depends on INPUT # due to VIDEO_IR
5 depends on HOTPLUG # due to FW_LOADER
4 select I2C_ALGOBIT 6 select I2C_ALGOBIT
5 select FW_LOADER 7 select FW_LOADER
6 select VIDEO_IR 8 select VIDEO_IR
7 select MEDIA_TUNER 9 select VIDEO_TUNER
8 select VIDEO_TVEEPROM 10 select VIDEO_TVEEPROM
9 select VIDEO_CX2341X 11 select VIDEO_CX2341X
10 select VIDEO_CS5345 12 select VIDEO_CS5345
11 select DVB_S5H1409 13 select DVB_S5H1409
14 select MEDIA_TUNER_MXL5005S
12 ---help--- 15 ---help---
13 This is a video4linux driver for Conexant cx23418 based 16 This is a video4linux driver for Conexant cx23418 based
14 PCI combo video recorder devices. 17 PCI combo video recorder devices.
diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c
index f5e3ba1f5354..553adbf2cd44 100644
--- a/drivers/media/video/cx18/cx18-cards.c
+++ b/drivers/media/video/cx18/cx18-cards.c
@@ -47,11 +47,12 @@ static struct cx18_card_tuner_i2c cx18_i2c_std = {
47static const struct cx18_card cx18_card_hvr1600_esmt = { 47static const struct cx18_card cx18_card_hvr1600_esmt = {
48 .type = CX18_CARD_HVR_1600_ESMT, 48 .type = CX18_CARD_HVR_1600_ESMT,
49 .name = "Hauppauge HVR-1600", 49 .name = "Hauppauge HVR-1600",
50 .comment = "DVB & VBI are not yet supported\n", 50 .comment = "VBI is not yet supported\n",
51 .v4l2_capabilities = CX18_CAP_ENCODER, 51 .v4l2_capabilities = CX18_CAP_ENCODER,
52 .hw_audio_ctrl = CX18_HW_CX23418, 52 .hw_audio_ctrl = CX18_HW_CX23418,
53 .hw_muxer = CX18_HW_CS5345, 53 .hw_muxer = CX18_HW_CS5345,
54 .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | CX18_HW_CS5345, 54 .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER |
55 CX18_HW_CS5345 | CX18_HW_DVB,
55 .video_inputs = { 56 .video_inputs = {
56 { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, 57 { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 },
57 { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, 58 { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 },
@@ -86,11 +87,12 @@ static const struct cx18_card cx18_card_hvr1600_esmt = {
86static const struct cx18_card cx18_card_hvr1600_samsung = { 87static const struct cx18_card cx18_card_hvr1600_samsung = {
87 .type = CX18_CARD_HVR_1600_SAMSUNG, 88 .type = CX18_CARD_HVR_1600_SAMSUNG,
88 .name = "Hauppauge HVR-1600 (Preproduction)", 89 .name = "Hauppauge HVR-1600 (Preproduction)",
89 .comment = "DVB & VBI are not yet supported\n", 90 .comment = "VBI is not yet supported\n",
90 .v4l2_capabilities = CX18_CAP_ENCODER, 91 .v4l2_capabilities = CX18_CAP_ENCODER,
91 .hw_audio_ctrl = CX18_HW_CX23418, 92 .hw_audio_ctrl = CX18_HW_CX23418,
92 .hw_muxer = CX18_HW_CS5345, 93 .hw_muxer = CX18_HW_CS5345,
93 .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | CX18_HW_CS5345, 94 .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER |
95 CX18_HW_CS5345 | CX18_HW_DVB,
94 .video_inputs = { 96 .video_inputs = {
95 { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, 97 { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 },
96 { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, 98 { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 },
@@ -134,14 +136,15 @@ static const struct cx18_card_pci_info cx18_pci_h900[] = {
134static const struct cx18_card cx18_card_h900 = { 136static const struct cx18_card cx18_card_h900 = {
135 .type = CX18_CARD_COMPRO_H900, 137 .type = CX18_CARD_COMPRO_H900,
136 .name = "Compro VideoMate H900", 138 .name = "Compro VideoMate H900",
137 .comment = "Not yet supported!\n", 139 .comment = "DVB & VBI are not yet supported\n",
138 .v4l2_capabilities = 0, 140 .v4l2_capabilities = CX18_CAP_ENCODER,
139 .hw_audio_ctrl = CX18_HW_CX23418, 141 .hw_audio_ctrl = CX18_HW_CX23418,
140 .hw_all = CX18_HW_TUNER, 142 .hw_all = CX18_HW_TUNER,
141 .video_inputs = { 143 .video_inputs = {
142 { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, 144 { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE2 },
143 { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, 145 { CX18_CARD_INPUT_SVIDEO1, 1,
144 { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE3 }, 146 CX23418_SVIDEO_LUMA3 | CX23418_SVIDEO_CHROMA4 },
147 { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE1 },
145 }, 148 },
146 .audio_inputs = { 149 .audio_inputs = {
147 { CX18_CARD_INPUT_AUD_TUNER, 150 { CX18_CARD_INPUT_AUD_TUNER,
@@ -163,6 +166,7 @@ static const struct cx18_card cx18_card_h900 = {
163 .tune_lane = 0, 166 .tune_lane = 0,
164 .initial_emrs = 0, 167 .initial_emrs = 0,
165 }, 168 },
169 .xceive_pin = 15,
166 .pci_list = cx18_pci_h900, 170 .pci_list = cx18_pci_h900,
167 .i2c = &cx18_i2c_std, 171 .i2c = &cx18_i2c_std,
168}; 172};
@@ -200,8 +204,6 @@ static const struct cx18_card cx18_card_mpc718 = {
200 /* XC3028 tuner */ 204 /* XC3028 tuner */
201 { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 }, 205 { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
202 }, 206 },
203 /* tuner reset */
204 .gpio_init = { .direction = 0x1000, .initial_value = 0x1000 },
205 .ddr = { 207 .ddr = {
206 /* Probably Samsung K4D263238G-VC33 memory */ 208 /* Probably Samsung K4D263238G-VC33 memory */
207 .chip_config = 0x003, 209 .chip_config = 0x003,
@@ -211,6 +213,7 @@ static const struct cx18_card cx18_card_mpc718 = {
211 .tune_lane = 0, 213 .tune_lane = 0,
212 .initial_emrs = 2, 214 .initial_emrs = 2,
213 }, 215 },
216 .xceive_pin = 15,
214 .pci_list = cx18_pci_mpc718, 217 .pci_list = cx18_pci_mpc718,
215 .i2c = &cx18_i2c_std, 218 .i2c = &cx18_i2c_std,
216}; 219};
diff --git a/drivers/media/video/cx18/cx18-cards.h b/drivers/media/video/cx18/cx18-cards.h
index bca249bdd337..bccb67f0db16 100644
--- a/drivers/media/video/cx18/cx18-cards.h
+++ b/drivers/media/video/cx18/cx18-cards.h
@@ -114,8 +114,8 @@ struct cx18_card_pci_info {
114/* The mask is the set of bits used by the operation */ 114/* The mask is the set of bits used by the operation */
115 115
116struct cx18_gpio_init { /* set initial GPIO DIR and OUT values */ 116struct cx18_gpio_init { /* set initial GPIO DIR and OUT values */
117 u16 direction; /* DIR setting. Leave to 0 if no init is needed */ 117 u32 direction; /* DIR setting. Leave to 0 if no init is needed */
118 u16 initial_value; 118 u32 initial_value;
119}; 119};
120 120
121struct cx18_card_tuner { 121struct cx18_card_tuner {
@@ -153,6 +153,7 @@ struct cx18_card {
153 struct cx18_card_audio_input radio_input; 153 struct cx18_card_audio_input radio_input;
154 154
155 /* GPIO card-specific settings */ 155 /* GPIO card-specific settings */
156 u8 xceive_pin; /* XCeive tuner GPIO reset pin */
156 struct cx18_gpio_init gpio_init; 157 struct cx18_gpio_init gpio_init;
157 158
158 struct cx18_card_tuner tuners[CX18_CARD_MAX_TUNERS]; 159 struct cx18_card_tuner tuners[CX18_CARD_MAX_TUNERS];
diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c
index 3f55d47bc4b9..0dd4e0529970 100644
--- a/drivers/media/video/cx18/cx18-driver.c
+++ b/drivers/media/video/cx18/cx18-driver.c
@@ -164,16 +164,6 @@ MODULE_LICENSE("GPL");
164 164
165MODULE_VERSION(CX18_VERSION); 165MODULE_VERSION(CX18_VERSION);
166 166
167int cx18_waitq(wait_queue_head_t *waitq)
168{
169 DEFINE_WAIT(wait);
170
171 prepare_to_wait(waitq, &wait, TASK_INTERRUPTIBLE);
172 schedule();
173 finish_wait(waitq, &wait);
174 return signal_pending(current) ? -EINTR : 0;
175}
176
177/* Generic utility functions */ 167/* Generic utility functions */
178int cx18_msleep_timeout(unsigned int msecs, int intr) 168int cx18_msleep_timeout(unsigned int msecs, int intr)
179{ 169{
@@ -220,13 +210,13 @@ static void cx18_process_eeprom(struct cx18 *cx)
220 210
221 /* Many thanks to Steven Toth from Hauppauge for providing the 211 /* Many thanks to Steven Toth from Hauppauge for providing the
222 model numbers */ 212 model numbers */
213 /* Note: the Samsung memory models cannot be reliably determined
214 from the model number. Use the cardtype module option if you
215 have one of these preproduction models. */
223 switch (tv.model) { 216 switch (tv.model) {
224 case 74000 ... 74099: 217 case 74000 ... 74999:
225 cx->card = cx18_get_card(CX18_CARD_HVR_1600_ESMT); 218 cx->card = cx18_get_card(CX18_CARD_HVR_1600_ESMT);
226 break; 219 break;
227 case 74700 ... 74799:
228 cx->card = cx18_get_card(CX18_CARD_HVR_1600_SAMSUNG);
229 break;
230 case 0: 220 case 0:
231 CX18_ERR("Invalid EEPROM\n"); 221 CX18_ERR("Invalid EEPROM\n");
232 return; 222 return;
@@ -548,6 +538,7 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *dev,
548 return 0; 538 return 0;
549} 539}
550 540
541#ifdef MODULE
551static u32 cx18_request_module(struct cx18 *cx, u32 hw, 542static u32 cx18_request_module(struct cx18 *cx, u32 hw,
552 const char *name, u32 id) 543 const char *name, u32 id)
553{ 544{
@@ -560,12 +551,14 @@ static u32 cx18_request_module(struct cx18 *cx, u32 hw,
560 CX18_DEBUG_INFO("Loaded module %s\n", name); 551 CX18_DEBUG_INFO("Loaded module %s\n", name);
561 return hw; 552 return hw;
562} 553}
554#endif
563 555
564static void cx18_load_and_init_modules(struct cx18 *cx) 556static void cx18_load_and_init_modules(struct cx18 *cx)
565{ 557{
566 u32 hw = cx->card->hw_all; 558 u32 hw = cx->card->hw_all;
567 int i; 559 int i;
568 560
561#ifdef MODULE
569 /* load modules */ 562 /* load modules */
570#ifndef CONFIG_MEDIA_TUNER 563#ifndef CONFIG_MEDIA_TUNER
571 hw = cx18_request_module(cx, hw, "tuner", CX18_HW_TUNER); 564 hw = cx18_request_module(cx, hw, "tuner", CX18_HW_TUNER);
@@ -573,6 +566,7 @@ static void cx18_load_and_init_modules(struct cx18 *cx)
573#ifndef CONFIG_VIDEO_CS5345 566#ifndef CONFIG_VIDEO_CS5345
574 hw = cx18_request_module(cx, hw, "cs5345", CX18_HW_CS5345); 567 hw = cx18_request_module(cx, hw, "cs5345", CX18_HW_CS5345);
575#endif 568#endif
569#endif
576 570
577 /* check which i2c devices are actually found */ 571 /* check which i2c devices are actually found */
578 for (i = 0; i < 32; i++) { 572 for (i = 0; i < 32; i++) {
@@ -801,7 +795,7 @@ static int __devinit cx18_probe(struct pci_dev *dev,
801 return 0; 795 return 0;
802 796
803free_streams: 797free_streams:
804 cx18_streams_cleanup(cx); 798 cx18_streams_cleanup(cx, 1);
805free_irq: 799free_irq:
806 free_irq(cx->dev->irq, (void *)cx); 800 free_irq(cx->dev->irq, (void *)cx);
807free_i2c: 801free_i2c:
@@ -904,14 +898,13 @@ static void cx18_remove(struct pci_dev *pci_dev)
904 898
905 cx18_halt_firmware(cx); 899 cx18_halt_firmware(cx);
906 900
907 cx18_streams_cleanup(cx); 901 cx18_streams_cleanup(cx, 1);
908 902
909 exit_cx18_i2c(cx); 903 exit_cx18_i2c(cx);
910 904
911 free_irq(cx->dev->irq, (void *)cx); 905 free_irq(cx->dev->irq, (void *)cx);
912 906
913 if (cx->dev) 907 cx18_iounmap(cx);
914 cx18_iounmap(cx);
915 908
916 release_mem_region(cx->base_addr, CX18_MEM_SIZE); 909 release_mem_region(cx->base_addr, CX18_MEM_SIZE);
917 910
diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h
index 2ee939193bb7..a2a6c58d12fe 100644
--- a/drivers/media/video/cx18/cx18-driver.h
+++ b/drivers/media/video/cx18/cx18-driver.h
@@ -444,9 +444,6 @@ extern spinlock_t cx18_cards_lock;
444/* Return non-zero if a signal is pending */ 444/* Return non-zero if a signal is pending */
445int cx18_msleep_timeout(unsigned int msecs, int intr); 445int cx18_msleep_timeout(unsigned int msecs, int intr);
446 446
447/* Wait on queue, returns -EINTR if interrupted */
448int cx18_waitq(wait_queue_head_t *waitq);
449
450/* Read Hauppauge eeprom */ 447/* Read Hauppauge eeprom */
451struct tveeprom; /* forward reference */ 448struct tveeprom; /* forward reference */
452void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv); 449void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv);
diff --git a/drivers/media/video/cx18/cx18-dvb.c b/drivers/media/video/cx18/cx18-dvb.c
index 65efe69d939a..c9744173f969 100644
--- a/drivers/media/video/cx18/cx18-dvb.c
+++ b/drivers/media/video/cx18/cx18-dvb.c
@@ -24,25 +24,27 @@
24#include "cx18-streams.h" 24#include "cx18-streams.h"
25#include "cx18-cards.h" 25#include "cx18-cards.h"
26#include "s5h1409.h" 26#include "s5h1409.h"
27 27#include "mxl5005s.h"
28/* Wait until the MXL500X driver is merged */
29#ifdef HAVE_MXL500X
30#include "mxl500x.h"
31#endif
32 28
33DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 29DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
34 30
35#define CX18_REG_DMUX_NUM_PORT_0_CONTROL 0xd5a000 31#define CX18_REG_DMUX_NUM_PORT_0_CONTROL 0xd5a000
36 32
37#ifdef HAVE_MXL500X 33static struct mxl5005s_config hauppauge_hvr1600_tuner = {
38static struct mxl500x_config hauppauge_hvr1600_tuner = { 34 .i2c_address = 0xC6 >> 1,
39 .delsys = MXL500x_MODE_ATSC, 35 .if_freq = IF_FREQ_5380000HZ,
40 .octf = MXL500x_OCTF_CH, 36 .xtal_freq = CRYSTAL_FREQ_16000000HZ,
41 .xtal_freq = 16000000, 37 .agc_mode = MXL_SINGLE_AGC,
42 .iflo_freq = 5380000, 38 .tracking_filter = MXL_TF_C_H,
43 .ref_freq = 322800000, 39 .rssi_enable = MXL_RSSI_ENABLE,
44 .rssi_ena = MXL_RSSI_ENABLE, 40 .cap_select = MXL_CAP_SEL_ENABLE,
45 .addr = 0xC6 >> 1, 41 .div_out = MXL_DIV_OUT_4,
42 .clock_out = MXL_CLOCK_OUT_DISABLE,
43 .output_load = MXL5005S_IF_OUTPUT_LOAD_200_OHM,
44 .top = MXL5005S_TOP_25P2,
45 .mod_mode = MXL_DIGITAL_MODE,
46 .if_mode = MXL_ZERO_IF,
47 .AgcMasterByte = 0x00,
46}; 48};
47 49
48static struct s5h1409_config hauppauge_hvr1600_config = { 50static struct s5h1409_config hauppauge_hvr1600_config = {
@@ -55,7 +57,6 @@ static struct s5h1409_config hauppauge_hvr1600_config = {
55 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK 57 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK
56 58
57}; 59};
58#endif
59 60
60static int dvb_register(struct cx18_stream *stream); 61static int dvb_register(struct cx18_stream *stream);
61 62
@@ -252,21 +253,18 @@ static int dvb_register(struct cx18_stream *stream)
252 int ret = 0; 253 int ret = 0;
253 254
254 switch (cx->card->type) { 255 switch (cx->card->type) {
255/* Wait until the MXL500X driver is merged */
256#ifdef HAVE_MXL500X
257 case CX18_CARD_HVR_1600_ESMT: 256 case CX18_CARD_HVR_1600_ESMT:
258 case CX18_CARD_HVR_1600_SAMSUNG: 257 case CX18_CARD_HVR_1600_SAMSUNG:
259 dvb->fe = dvb_attach(s5h1409_attach, 258 dvb->fe = dvb_attach(s5h1409_attach,
260 &hauppauge_hvr1600_config, 259 &hauppauge_hvr1600_config,
261 &cx->i2c_adap[0]); 260 &cx->i2c_adap[0]);
262 if (dvb->fe != NULL) { 261 if (dvb->fe != NULL) {
263 dvb_attach(mxl500x_attach, dvb->fe, 262 dvb_attach(mxl5005s_attach, dvb->fe,
264 &hauppauge_hvr1600_tuner, 263 &cx->i2c_adap[0],
265 &cx->i2c_adap[0]); 264 &hauppauge_hvr1600_tuner);
266 ret = 0; 265 ret = 0;
267 } 266 }
268 break; 267 break;
269#endif
270 default: 268 default:
271 /* No Digital Tv Support */ 269 /* No Digital Tv Support */
272 break; 270 break;
diff --git a/drivers/media/video/cx18/cx18-fileops.c b/drivers/media/video/cx18/cx18-fileops.c
index 69303065a294..0b3141db174b 100644
--- a/drivers/media/video/cx18/cx18-fileops.c
+++ b/drivers/media/video/cx18/cx18-fileops.c
@@ -39,7 +39,7 @@
39 associated VBI streams are also automatically claimed. 39 associated VBI streams are also automatically claimed.
40 Possible error returns: -EBUSY if someone else has claimed 40 Possible error returns: -EBUSY if someone else has claimed
41 the stream or 0 on success. */ 41 the stream or 0 on success. */
42int cx18_claim_stream(struct cx18_open_id *id, int type) 42static int cx18_claim_stream(struct cx18_open_id *id, int type)
43{ 43{
44 struct cx18 *cx = id->cx; 44 struct cx18 *cx = id->cx;
45 struct cx18_stream *s = &cx->streams[type]; 45 struct cx18_stream *s = &cx->streams[type];
@@ -87,7 +87,7 @@ int cx18_claim_stream(struct cx18_open_id *id, int type)
87 87
88/* This function releases a previously claimed stream. It will take into 88/* This function releases a previously claimed stream. It will take into
89 account associated VBI streams. */ 89 account associated VBI streams. */
90void cx18_release_stream(struct cx18_stream *s) 90static void cx18_release_stream(struct cx18_stream *s)
91{ 91{
92 struct cx18 *cx = s->cx; 92 struct cx18 *cx = s->cx;
93 struct cx18_stream *s_vbi; 93 struct cx18_stream *s_vbi;
@@ -662,6 +662,8 @@ int cx18_v4l2_open(struct inode *inode, struct file *filp)
662 for (x = 0; cx == NULL && x < cx18_cards_active; x++) { 662 for (x = 0; cx == NULL && x < cx18_cards_active; x++) {
663 /* find out which stream this open was on */ 663 /* find out which stream this open was on */
664 for (y = 0; y < CX18_MAX_STREAMS; y++) { 664 for (y = 0; y < CX18_MAX_STREAMS; y++) {
665 if (cx18_cards[x] == NULL)
666 continue;
665 s = &cx18_cards[x]->streams[y]; 667 s = &cx18_cards[x]->streams[y];
666 if (s->v4l2dev && s->v4l2dev->minor == minor) { 668 if (s->v4l2dev && s->v4l2dev->minor == minor) {
667 cx = cx18_cards[x]; 669 cx = cx18_cards[x];
diff --git a/drivers/media/video/cx18/cx18-fileops.h b/drivers/media/video/cx18/cx18-fileops.h
index 16cdafbd24c5..46da0282fc7d 100644
--- a/drivers/media/video/cx18/cx18-fileops.h
+++ b/drivers/media/video/cx18/cx18-fileops.h
@@ -34,12 +34,3 @@ void cx18_stop_capture(struct cx18_open_id *id, int gop_end);
34void cx18_mute(struct cx18 *cx); 34void cx18_mute(struct cx18 *cx);
35void cx18_unmute(struct cx18 *cx); 35void cx18_unmute(struct cx18 *cx);
36 36
37/* Utilities */
38
39/* Try to claim a stream for the filehandle. Return 0 on success,
40 -EBUSY if stream already claimed. Once a stream is claimed, it
41 remains claimed until the associated filehandle is closed. */
42int cx18_claim_stream(struct cx18_open_id *id, int type);
43
44/* Release a previously claimed stream. */
45void cx18_release_stream(struct cx18_stream *s);
diff --git a/drivers/media/video/cx18/cx18-gpio.c b/drivers/media/video/cx18/cx18-gpio.c
index 19253e6b8673..bb8bc86086d0 100644
--- a/drivers/media/video/cx18/cx18-gpio.c
+++ b/drivers/media/video/cx18/cx18-gpio.c
@@ -35,6 +35,9 @@
35#define CX18_REG_GPIO_OUT2 0xc78104 35#define CX18_REG_GPIO_OUT2 0xc78104
36#define CX18_REG_GPIO_DIR2 0xc7810c 36#define CX18_REG_GPIO_DIR2 0xc7810c
37 37
38static u32 gpio_dir;
39static u32 gpio_val;
40
38/* 41/*
39 * HVR-1600 GPIO pins, courtesy of Hauppauge: 42 * HVR-1600 GPIO pins, courtesy of Hauppauge:
40 * 43 *
@@ -44,31 +47,53 @@
44 * gpio13: cs5345 reset pin 47 * gpio13: cs5345 reset pin
45*/ 48*/
46 49
50static void gpio_write(struct cx18 *cx)
51{
52 write_reg((gpio_dir & 0xffff) << 16, CX18_REG_GPIO_DIR1);
53 write_reg(((gpio_dir & 0xffff) << 16) | (gpio_val & 0xffff),
54 CX18_REG_GPIO_OUT1);
55 write_reg(gpio_dir & 0xffff0000, CX18_REG_GPIO_DIR2);
56 write_reg((gpio_dir & 0xffff0000) | ((gpio_val & 0xffff0000) >> 16),
57 CX18_REG_GPIO_OUT2);
58}
59
47void cx18_gpio_init(struct cx18 *cx) 60void cx18_gpio_init(struct cx18 *cx)
48{ 61{
49 if (cx->card->gpio_init.direction == 0) 62 gpio_dir = cx->card->gpio_init.direction;
63 gpio_val = cx->card->gpio_init.initial_value;
64
65 if (gpio_dir == 0)
50 return; 66 return;
51 67
52 CX18_DEBUG_INFO("GPIO initial dir: %08x out: %08x\n", 68 gpio_dir |= 1 << cx->card->xceive_pin;
53 read_reg(CX18_REG_GPIO_DIR1), read_reg(CX18_REG_GPIO_OUT1)); 69 gpio_val |= 1 << cx->card->xceive_pin;
54 70
55 /* init output data then direction */ 71 CX18_DEBUG_INFO("GPIO initial dir: %08x/%08x out: %08x/%08x\n",
56 write_reg(cx->card->gpio_init.direction << 16, CX18_REG_GPIO_DIR1); 72 read_reg(CX18_REG_GPIO_DIR1), read_reg(CX18_REG_GPIO_DIR2),
57 write_reg(0, CX18_REG_GPIO_DIR2); 73 read_reg(CX18_REG_GPIO_OUT1), read_reg(CX18_REG_GPIO_OUT2));
58 write_reg((cx->card->gpio_init.direction << 16) | 74
59 cx->card->gpio_init.initial_value, CX18_REG_GPIO_OUT1); 75 gpio_write(cx);
60 write_reg(0, CX18_REG_GPIO_OUT2);
61} 76}
62 77
63/* Xceive tuner reset function */ 78/* Xceive tuner reset function */
64int cx18_reset_tuner_gpio(void *dev, int cmd, int value) 79int cx18_reset_tuner_gpio(void *dev, int cmd, int value)
65{ 80{
66 struct i2c_algo_bit_data *algo = dev; 81 struct i2c_algo_bit_data *algo = dev;
67 struct cx18 *cx = algo->data; 82 struct cx18_i2c_algo_callback_data *cb_data = algo->data;
68/* int curdir, curout;*/ 83 struct cx18 *cx = cb_data->cx;
69 84
70 if (cmd != XC2028_TUNER_RESET) 85 if (cmd != XC2028_TUNER_RESET)
71 return 0; 86 return 0;
72 CX18_DEBUG_INFO("Resetting tuner\n"); 87 CX18_DEBUG_INFO("Resetting tuner\n");
88
89 gpio_dir |= 1 << cx->card->xceive_pin;
90 gpio_val &= ~(1 << cx->card->xceive_pin);
91
92 gpio_write(cx);
93 schedule_timeout_interruptible(msecs_to_jiffies(1));
94
95 gpio_val |= 1 << cx->card->xceive_pin;
96 gpio_write(cx);
97 schedule_timeout_interruptible(msecs_to_jiffies(1));
73 return 0; 98 return 0;
74} 99}
diff --git a/drivers/media/video/cx18/cx18-i2c.c b/drivers/media/video/cx18/cx18-i2c.c
index 18c88d1e4833..4f08a4058d1a 100644
--- a/drivers/media/video/cx18/cx18-i2c.c
+++ b/drivers/media/video/cx18/cx18-i2c.c
@@ -25,6 +25,7 @@
25#include "cx18-cards.h" 25#include "cx18-cards.h"
26#include "cx18-gpio.h" 26#include "cx18-gpio.h"
27#include "cx18-av-core.h" 27#include "cx18-av-core.h"
28#include "cx18-i2c.h"
28 29
29#include <media/ir-kbd-i2c.h> 30#include <media/ir-kbd-i2c.h>
30 31
diff --git a/drivers/media/video/cx18/cx18-queue.c b/drivers/media/video/cx18/cx18-queue.c
index 65af1bb507ca..6990b77c6200 100644
--- a/drivers/media/video/cx18/cx18-queue.c
+++ b/drivers/media/video/cx18/cx18-queue.c
@@ -26,17 +26,6 @@
26#include "cx18-queue.h" 26#include "cx18-queue.h"
27#include "cx18-scb.h" 27#include "cx18-scb.h"
28 28
29int cx18_buf_copy_from_user(struct cx18_stream *s, struct cx18_buffer *buf,
30 const char __user *src, int copybytes)
31{
32 if (s->buf_size - buf->bytesused < copybytes)
33 copybytes = s->buf_size - buf->bytesused;
34 if (copy_from_user(buf->buf + buf->bytesused, src, copybytes))
35 return -EFAULT;
36 buf->bytesused += copybytes;
37 return copybytes;
38}
39
40void cx18_buf_swap(struct cx18_buffer *buf) 29void cx18_buf_swap(struct cx18_buffer *buf)
41{ 30{
42 int i; 31 int i;
@@ -159,8 +148,9 @@ static void cx18_queue_move_buf(struct cx18_stream *s, struct cx18_queue *from,
159 -ENOMEM is returned if the buffers could not be obtained, 0 if all 148 -ENOMEM is returned if the buffers could not be obtained, 0 if all
160 buffers where obtained from the 'from' list and if non-zero then 149 buffers where obtained from the 'from' list and if non-zero then
161 the number of stolen buffers is returned. */ 150 the number of stolen buffers is returned. */
162int cx18_queue_move(struct cx18_stream *s, struct cx18_queue *from, 151static int cx18_queue_move(struct cx18_stream *s, struct cx18_queue *from,
163 struct cx18_queue *steal, struct cx18_queue *to, int needed_bytes) 152 struct cx18_queue *steal, struct cx18_queue *to,
153 int needed_bytes)
164{ 154{
165 unsigned long flags; 155 unsigned long flags;
166 int rc = 0; 156 int rc = 0;
@@ -239,12 +229,12 @@ int cx18_stream_alloc(struct cx18_stream *s)
239 229
240 /* allocate stream buffers. Initially all buffers are in q_free. */ 230 /* allocate stream buffers. Initially all buffers are in q_free. */
241 for (i = 0; i < s->buffers; i++) { 231 for (i = 0; i < s->buffers; i++) {
242 struct cx18_buffer *buf = 232 struct cx18_buffer *buf = kzalloc(sizeof(struct cx18_buffer),
243 kzalloc(sizeof(struct cx18_buffer), GFP_KERNEL); 233 GFP_KERNEL|__GFP_NOWARN);
244 234
245 if (buf == NULL) 235 if (buf == NULL)
246 break; 236 break;
247 buf->buf = kmalloc(s->buf_size, GFP_KERNEL); 237 buf->buf = kmalloc(s->buf_size, GFP_KERNEL|__GFP_NOWARN);
248 if (buf->buf == NULL) { 238 if (buf->buf == NULL) {
249 kfree(buf); 239 kfree(buf);
250 break; 240 break;
diff --git a/drivers/media/video/cx18/cx18-queue.h b/drivers/media/video/cx18/cx18-queue.h
index f86c8a6fa6e7..91423b9863a4 100644
--- a/drivers/media/video/cx18/cx18-queue.h
+++ b/drivers/media/video/cx18/cx18-queue.h
@@ -39,8 +39,6 @@ static inline void cx18_buf_sync_for_device(struct cx18_stream *s,
39 s->buf_size, s->dma); 39 s->buf_size, s->dma);
40} 40}
41 41
42int cx18_buf_copy_from_user(struct cx18_stream *s, struct cx18_buffer *buf,
43 const char __user *src, int copybytes);
44void cx18_buf_swap(struct cx18_buffer *buf); 42void cx18_buf_swap(struct cx18_buffer *buf);
45 43
46/* cx18_queue utility functions */ 44/* cx18_queue utility functions */
@@ -48,8 +46,6 @@ void cx18_queue_init(struct cx18_queue *q);
48void cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf, 46void cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf,
49 struct cx18_queue *q); 47 struct cx18_queue *q);
50struct cx18_buffer *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q); 48struct cx18_buffer *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q);
51int cx18_queue_move(struct cx18_stream *s, struct cx18_queue *from,
52 struct cx18_queue *steal, struct cx18_queue *to, int needed_bytes);
53struct cx18_buffer *cx18_queue_find_buf(struct cx18_stream *s, u32 id, 49struct cx18_buffer *cx18_queue_find_buf(struct cx18_stream *s, u32 id,
54 u32 bytesused); 50 u32 bytesused);
55void cx18_flush_queues(struct cx18_stream *s); 51void cx18_flush_queues(struct cx18_stream *s);
diff --git a/drivers/media/video/cx18/cx18-streams.c b/drivers/media/video/cx18/cx18-streams.c
index afb141b2027a..4ca9d847f1b1 100644
--- a/drivers/media/video/cx18/cx18-streams.c
+++ b/drivers/media/video/cx18/cx18-streams.c
@@ -218,7 +218,7 @@ int cx18_streams_setup(struct cx18 *cx)
218 return 0; 218 return 0;
219 219
220 /* One or more streams could not be initialized. Clean 'em all up. */ 220 /* One or more streams could not be initialized. Clean 'em all up. */
221 cx18_streams_cleanup(cx); 221 cx18_streams_cleanup(cx, 0);
222 return -ENOMEM; 222 return -ENOMEM;
223} 223}
224 224
@@ -296,12 +296,12 @@ int cx18_streams_register(struct cx18 *cx)
296 return 0; 296 return 0;
297 297
298 /* One or more streams could not be initialized. Clean 'em all up. */ 298 /* One or more streams could not be initialized. Clean 'em all up. */
299 cx18_streams_cleanup(cx); 299 cx18_streams_cleanup(cx, 1);
300 return -ENOMEM; 300 return -ENOMEM;
301} 301}
302 302
303/* Unregister v4l2 devices */ 303/* Unregister v4l2 devices */
304void cx18_streams_cleanup(struct cx18 *cx) 304void cx18_streams_cleanup(struct cx18 *cx, int unregister)
305{ 305{
306 struct video_device *vdev; 306 struct video_device *vdev;
307 int type; 307 int type;
@@ -319,8 +319,11 @@ void cx18_streams_cleanup(struct cx18 *cx)
319 319
320 cx18_stream_free(&cx->streams[type]); 320 cx18_stream_free(&cx->streams[type]);
321 321
322 /* Unregister device */ 322 /* Unregister or release device */
323 video_unregister_device(vdev); 323 if (unregister)
324 video_unregister_device(vdev);
325 else
326 video_device_release(vdev);
324 } 327 }
325} 328}
326 329
diff --git a/drivers/media/video/cx18/cx18-streams.h b/drivers/media/video/cx18/cx18-streams.h
index 8c7ba7d2fa79..f327e947b24f 100644
--- a/drivers/media/video/cx18/cx18-streams.h
+++ b/drivers/media/video/cx18/cx18-streams.h
@@ -24,7 +24,7 @@
24u32 cx18_find_handle(struct cx18 *cx); 24u32 cx18_find_handle(struct cx18 *cx);
25int cx18_streams_setup(struct cx18 *cx); 25int cx18_streams_setup(struct cx18 *cx);
26int cx18_streams_register(struct cx18 *cx); 26int cx18_streams_register(struct cx18 *cx);
27void cx18_streams_cleanup(struct cx18 *cx); 27void cx18_streams_cleanup(struct cx18 *cx, int unregister);
28 28
29/* Capture related */ 29/* Capture related */
30int cx18_start_v4l2_encode_stream(struct cx18_stream *s); 30int cx18_start_v4l2_encode_stream(struct cx18_stream *s);
diff --git a/drivers/media/video/cx23885/Kconfig b/drivers/media/video/cx23885/Kconfig
index cadf936c3673..7bf14c9a15c7 100644
--- a/drivers/media/video/cx23885/Kconfig
+++ b/drivers/media/video/cx23885/Kconfig
@@ -1,18 +1,20 @@
1config VIDEO_CX23885 1config VIDEO_CX23885
2 tristate "Conexant cx23885 (2388x successor) support" 2 tristate "Conexant cx23885 (2388x successor) support"
3 depends on DVB_CORE && VIDEO_DEV && PCI && I2C && INPUT 3 depends on DVB_CORE && VIDEO_DEV && PCI && I2C && INPUT
4 depends on HOTPLUG # due to FW_LOADER
4 select I2C_ALGOBIT 5 select I2C_ALGOBIT
5 select FW_LOADER 6 select FW_LOADER
6 select VIDEO_BTCX 7 select VIDEO_BTCX
7 select MEDIA_TUNER 8 select VIDEO_TUNER
8 select VIDEO_TVEEPROM 9 select VIDEO_TVEEPROM
9 select VIDEO_IR 10 select VIDEO_IR
10 select VIDEOBUF_DVB 11 select VIDEOBUF_DVB
11 select VIDEO_CX25840 12 select VIDEO_CX25840
13 select VIDEO_CX2341X
14 select DVB_DIB7000P if !DVB_FE_CUSTOMISE
12 select MEDIA_TUNER_MT2131 if !DVB_FE_CUSTOMISE 15 select MEDIA_TUNER_MT2131 if !DVB_FE_CUSTOMISE
13 select DVB_S5H1409 if !DVB_FE_CUSTOMISE 16 select DVB_S5H1409 if !DVB_FE_CUSTOMISE
14 select DVB_LGDT330X if !DVB_FE_CUSTOMISE 17 select DVB_LGDT330X if !DVB_FE_CUSTOMISE
15 select DVB_PLL if !DVB_FE_CUSTOMISE
16 select MEDIA_TUNER_XC2028 if !DVB_FE_CUSTOMIZE 18 select MEDIA_TUNER_XC2028 if !DVB_FE_CUSTOMIZE
17 select MEDIA_TUNER_TDA8290 if !DVB_FE_CUSTOMIZE 19 select MEDIA_TUNER_TDA8290 if !DVB_FE_CUSTOMIZE
18 select MEDIA_TUNER_TDA18271 if !DVB_FE_CUSTOMIZE 20 select MEDIA_TUNER_TDA18271 if !DVB_FE_CUSTOMIZE
diff --git a/drivers/media/video/cx23885/cx23885-cards.c b/drivers/media/video/cx23885/cx23885-cards.c
index 6ebf58724a01..20e05f230546 100644
--- a/drivers/media/video/cx23885/cx23885-cards.c
+++ b/drivers/media/video/cx23885/cx23885-cards.c
@@ -200,6 +200,10 @@ struct cx23885_subid cx23885_subids[] = {
200 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 200 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
201 }, { 201 }, {
202 .subvendor = 0x0070, 202 .subvendor = 0x0070,
203 .subdevice = 0x71d3,
204 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
205 }, {
206 .subvendor = 0x0070,
203 .subdevice = 0x8101, 207 .subdevice = 0x8101,
204 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 208 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
205 }, { 209 }, {
@@ -245,6 +249,33 @@ static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
245 /* Make sure we support the board model */ 249 /* Make sure we support the board model */
246 switch (tv.model) 250 switch (tv.model)
247 { 251 {
252 case 71009:
253 /* WinTV-HVR1200 (PCIe, Retail, full height)
254 * DVB-T and basic analog */
255 case 71359:
256 /* WinTV-HVR1200 (PCIe, OEM, half height)
257 * DVB-T and basic analog */
258 case 71439:
259 /* WinTV-HVR1200 (PCIe, OEM, half height)
260 * DVB-T and basic analog */
261 case 71449:
262 /* WinTV-HVR1200 (PCIe, OEM, full height)
263 * DVB-T and basic analog */
264 case 71939:
265 /* WinTV-HVR1200 (PCIe, OEM, half height)
266 * DVB-T and basic analog */
267 case 71949:
268 /* WinTV-HVR1200 (PCIe, OEM, full height)
269 * DVB-T and basic analog */
270 case 71959:
271 /* WinTV-HVR1200 (PCIe, OEM, full height)
272 * DVB-T and basic analog */
273 case 71979:
274 /* WinTV-HVR1200 (PCIe, OEM, half height)
275 * DVB-T and basic analog */
276 case 71999:
277 /* WinTV-HVR1200 (PCIe, OEM, full height)
278 * DVB-T and basic analog */
248 case 76601: /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual channel ATSC and MPEG2 HW Encoder */ 279 case 76601: /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual channel ATSC and MPEG2 HW Encoder */
249 case 77001: /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC and Basic analog */ 280 case 77001: /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC and Basic analog */
250 case 77011: /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC and Basic analog */ 281 case 77011: /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC and Basic analog */
@@ -263,8 +294,11 @@ static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
263 case 80019: 294 case 80019:
264 /* WinTV-HVR1400 (Express Card, Retail, IR, 295 /* WinTV-HVR1400 (Express Card, Retail, IR,
265 * DVB-T and Basic analog */ 296 * DVB-T and Basic analog */
297 case 81509:
298 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
299 * DVB-T and MPEG2 HW Encoder */
266 case 81519: 300 case 81519:
267 /* WinTV-HVR1700 (PCIe, Retail, No IR, half height, 301 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
268 * DVB-T and MPEG2 HW Encoder */ 302 * DVB-T and MPEG2 HW Encoder */
269 break; 303 break;
270 default: 304 default:
diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c
index f05649727b60..022aa391937a 100644
--- a/drivers/media/video/cx23885/cx23885-dvb.c
+++ b/drivers/media/video/cx23885/cx23885-dvb.c
@@ -37,7 +37,6 @@
37#include "lgdt330x.h" 37#include "lgdt330x.h"
38#include "xc5000.h" 38#include "xc5000.h"
39#include "tda10048.h" 39#include "tda10048.h"
40#include "dvb-pll.h"
41#include "tuner-xc2028.h" 40#include "tuner-xc2028.h"
42#include "tuner-simple.h" 41#include "tuner-simple.h"
43#include "dib7000p.h" 42#include "dib7000p.h"
@@ -385,12 +384,10 @@ static int dvb_register(struct cx23885_tsport *port)
385 port->dvb.frontend = dvb_attach(s5h1409_attach, 384 port->dvb.frontend = dvb_attach(s5h1409_attach,
386 &hauppauge_hvr1500q_config, 385 &hauppauge_hvr1500q_config,
387 &dev->i2c_bus[0].i2c_adap); 386 &dev->i2c_bus[0].i2c_adap);
388 if (port->dvb.frontend != NULL) { 387 if (port->dvb.frontend != NULL)
389 hauppauge_hvr1500q_tunerconfig.priv = i2c_bus;
390 dvb_attach(xc5000_attach, port->dvb.frontend, 388 dvb_attach(xc5000_attach, port->dvb.frontend,
391 &i2c_bus->i2c_adap, 389 &i2c_bus->i2c_adap,
392 &hauppauge_hvr1500q_tunerconfig); 390 &hauppauge_hvr1500q_tunerconfig, i2c_bus);
393 }
394 break; 391 break;
395 case CX23885_BOARD_HAUPPAUGE_HVR1500: 392 case CX23885_BOARD_HAUPPAUGE_HVR1500:
396 i2c_bus = &dev->i2c_bus[1]; 393 i2c_bus = &dev->i2c_bus[1];
diff --git a/drivers/media/video/cx25840/Kconfig b/drivers/media/video/cx25840/Kconfig
index 7cf29a03ed63..448f4cd0ce34 100644
--- a/drivers/media/video/cx25840/Kconfig
+++ b/drivers/media/video/cx25840/Kconfig
@@ -1,6 +1,7 @@
1config VIDEO_CX25840 1config VIDEO_CX25840
2 tristate "Conexant CX2584x audio/video decoders" 2 tristate "Conexant CX2584x audio/video decoders"
3 depends on VIDEO_V4L2 && I2C && EXPERIMENTAL 3 depends on VIDEO_V4L2 && I2C && EXPERIMENTAL
4 depends on HOTPLUG # due to FW_LOADER
4 select FW_LOADER 5 select FW_LOADER
5 ---help--- 6 ---help---
6 Support for the Conexant CX2584x audio/video decoders. 7 Support for the Conexant CX2584x audio/video decoders.
diff --git a/drivers/media/video/cx88/Kconfig b/drivers/media/video/cx88/Kconfig
index b0d7d6a7a4cc..10e20d8196dc 100644
--- a/drivers/media/video/cx88/Kconfig
+++ b/drivers/media/video/cx88/Kconfig
@@ -2,10 +2,9 @@ config VIDEO_CX88
2 tristate "Conexant 2388x (bt878 successor) support" 2 tristate "Conexant 2388x (bt878 successor) support"
3 depends on VIDEO_DEV && PCI && I2C && INPUT 3 depends on VIDEO_DEV && PCI && I2C && INPUT
4 select I2C_ALGOBIT 4 select I2C_ALGOBIT
5 select FW_LOADER
6 select VIDEO_BTCX 5 select VIDEO_BTCX
7 select VIDEOBUF_DMA_SG 6 select VIDEOBUF_DMA_SG
8 select MEDIA_TUNER 7 select VIDEO_TUNER
9 select VIDEO_TVEEPROM 8 select VIDEO_TVEEPROM
10 select VIDEO_IR 9 select VIDEO_IR
11 select VIDEO_WM8775 if VIDEO_HELPER_CHIPS_AUTO 10 select VIDEO_WM8775 if VIDEO_HELPER_CHIPS_AUTO
@@ -34,8 +33,9 @@ config VIDEO_CX88_ALSA
34 33
35config VIDEO_CX88_BLACKBIRD 34config VIDEO_CX88_BLACKBIRD
36 tristate "Blackbird MPEG encoder support (cx2388x + cx23416)" 35 tristate "Blackbird MPEG encoder support (cx2388x + cx23416)"
37 depends on VIDEO_CX88 36 depends on VIDEO_CX88 && HOTPLUG
38 select VIDEO_CX2341X 37 select VIDEO_CX2341X
38 select FW_LOADER
39 ---help--- 39 ---help---
40 This adds support for MPEG encoder cards based on the 40 This adds support for MPEG encoder cards based on the
41 Blackbird reference design, using the Conexant 2388x 41 Blackbird reference design, using the Conexant 2388x
diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c
index 1c7fe6862a60..d96173ff1dba 100644
--- a/drivers/media/video/cx88/cx88-dvb.c
+++ b/drivers/media/video/cx88/cx88-dvb.c
@@ -509,9 +509,6 @@ static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
509 if (!fe) { 509 if (!fe) {
510 printk(KERN_ERR "%s/2: xc3028 attach failed\n", 510 printk(KERN_ERR "%s/2: xc3028 attach failed\n",
511 dev->core->name); 511 dev->core->name);
512 dvb_frontend_detach(dev->dvb.frontend);
513 dvb_unregister_frontend(dev->dvb.frontend);
514 dev->dvb.frontend = NULL;
515 return -EINVAL; 512 return -EINVAL;
516 } 513 }
517 514
@@ -523,20 +520,23 @@ static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
523 520
524static int dvb_register(struct cx8802_dev *dev) 521static int dvb_register(struct cx8802_dev *dev)
525{ 522{
523 struct cx88_core *core = dev->core;
524
526 /* init struct videobuf_dvb */ 525 /* init struct videobuf_dvb */
527 dev->dvb.name = dev->core->name; 526 dev->dvb.name = core->name;
528 dev->ts_gen_cntrl = 0x0c; 527 dev->ts_gen_cntrl = 0x0c;
529 528
530 /* init frontend */ 529 /* init frontend */
531 switch (dev->core->boardnr) { 530 switch (core->boardnr) {
532 case CX88_BOARD_HAUPPAUGE_DVB_T1: 531 case CX88_BOARD_HAUPPAUGE_DVB_T1:
533 dev->dvb.frontend = dvb_attach(cx22702_attach, 532 dev->dvb.frontend = dvb_attach(cx22702_attach,
534 &connexant_refboard_config, 533 &connexant_refboard_config,
535 &dev->core->i2c_adap); 534 &core->i2c_adap);
536 if (dev->dvb.frontend != NULL) { 535 if (dev->dvb.frontend != NULL) {
537 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, 536 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
538 &dev->core->i2c_adap, 537 0x61, &core->i2c_adap,
539 DVB_PLL_THOMSON_DTT759X); 538 DVB_PLL_THOMSON_DTT759X))
539 goto frontend_detach;
540 } 540 }
541 break; 541 break;
542 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1: 542 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
@@ -545,11 +545,12 @@ static int dvb_register(struct cx8802_dev *dev)
545 case CX88_BOARD_WINFAST_DTV1000: 545 case CX88_BOARD_WINFAST_DTV1000:
546 dev->dvb.frontend = dvb_attach(cx22702_attach, 546 dev->dvb.frontend = dvb_attach(cx22702_attach,
547 &connexant_refboard_config, 547 &connexant_refboard_config,
548 &dev->core->i2c_adap); 548 &core->i2c_adap);
549 if (dev->dvb.frontend != NULL) { 549 if (dev->dvb.frontend != NULL) {
550 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, 550 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
551 &dev->core->i2c_adap, 551 0x60, &core->i2c_adap,
552 DVB_PLL_THOMSON_DTT7579); 552 DVB_PLL_THOMSON_DTT7579))
553 goto frontend_detach;
553 } 554 }
554 break; 555 break;
555 case CX88_BOARD_WINFAST_DTV2000H: 556 case CX88_BOARD_WINFAST_DTV2000H:
@@ -559,29 +560,32 @@ static int dvb_register(struct cx8802_dev *dev)
559 case CX88_BOARD_HAUPPAUGE_HVR3000: 560 case CX88_BOARD_HAUPPAUGE_HVR3000:
560 dev->dvb.frontend = dvb_attach(cx22702_attach, 561 dev->dvb.frontend = dvb_attach(cx22702_attach,
561 &hauppauge_hvr_config, 562 &hauppauge_hvr_config,
562 &dev->core->i2c_adap); 563 &core->i2c_adap);
563 if (dev->dvb.frontend != NULL) { 564 if (dev->dvb.frontend != NULL) {
564 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 565 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
565 &dev->core->i2c_adap, 0x61, 566 &core->i2c_adap, 0x61,
566 TUNER_PHILIPS_FMD1216ME_MK3); 567 TUNER_PHILIPS_FMD1216ME_MK3))
568 goto frontend_detach;
567 } 569 }
568 break; 570 break;
569 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS: 571 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
570 dev->dvb.frontend = dvb_attach(mt352_attach, 572 dev->dvb.frontend = dvb_attach(mt352_attach,
571 &dvico_fusionhdtv, 573 &dvico_fusionhdtv,
572 &dev->core->i2c_adap); 574 &core->i2c_adap);
573 if (dev->dvb.frontend != NULL) { 575 if (dev->dvb.frontend != NULL) {
574 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, 576 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
575 NULL, DVB_PLL_THOMSON_DTT7579); 577 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
578 goto frontend_detach;
576 break; 579 break;
577 } 580 }
578 /* ZL10353 replaces MT352 on later cards */ 581 /* ZL10353 replaces MT352 on later cards */
579 dev->dvb.frontend = dvb_attach(zl10353_attach, 582 dev->dvb.frontend = dvb_attach(zl10353_attach,
580 &dvico_fusionhdtv_plus_v1_1, 583 &dvico_fusionhdtv_plus_v1_1,
581 &dev->core->i2c_adap); 584 &core->i2c_adap);
582 if (dev->dvb.frontend != NULL) { 585 if (dev->dvb.frontend != NULL) {
583 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, 586 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
584 NULL, DVB_PLL_THOMSON_DTT7579); 587 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
588 goto frontend_detach;
585 } 589 }
586 break; 590 break;
587 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL: 591 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
@@ -589,28 +593,31 @@ static int dvb_register(struct cx8802_dev *dev)
589 * compatible, with a slightly different MT352 AGC gain. */ 593 * compatible, with a slightly different MT352 AGC gain. */
590 dev->dvb.frontend = dvb_attach(mt352_attach, 594 dev->dvb.frontend = dvb_attach(mt352_attach,
591 &dvico_fusionhdtv_dual, 595 &dvico_fusionhdtv_dual,
592 &dev->core->i2c_adap); 596 &core->i2c_adap);
593 if (dev->dvb.frontend != NULL) { 597 if (dev->dvb.frontend != NULL) {
594 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, 598 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
595 NULL, DVB_PLL_THOMSON_DTT7579); 599 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
600 goto frontend_detach;
596 break; 601 break;
597 } 602 }
598 /* ZL10353 replaces MT352 on later cards */ 603 /* ZL10353 replaces MT352 on later cards */
599 dev->dvb.frontend = dvb_attach(zl10353_attach, 604 dev->dvb.frontend = dvb_attach(zl10353_attach,
600 &dvico_fusionhdtv_plus_v1_1, 605 &dvico_fusionhdtv_plus_v1_1,
601 &dev->core->i2c_adap); 606 &core->i2c_adap);
602 if (dev->dvb.frontend != NULL) { 607 if (dev->dvb.frontend != NULL) {
603 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, 608 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
604 NULL, DVB_PLL_THOMSON_DTT7579); 609 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
610 goto frontend_detach;
605 } 611 }
606 break; 612 break;
607 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1: 613 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
608 dev->dvb.frontend = dvb_attach(mt352_attach, 614 dev->dvb.frontend = dvb_attach(mt352_attach,
609 &dvico_fusionhdtv, 615 &dvico_fusionhdtv,
610 &dev->core->i2c_adap); 616 &core->i2c_adap);
611 if (dev->dvb.frontend != NULL) { 617 if (dev->dvb.frontend != NULL) {
612 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, 618 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
613 NULL, DVB_PLL_LG_Z201); 619 0x61, NULL, DVB_PLL_LG_Z201))
620 goto frontend_detach;
614 } 621 }
615 break; 622 break;
616 case CX88_BOARD_KWORLD_DVB_T: 623 case CX88_BOARD_KWORLD_DVB_T:
@@ -618,10 +625,11 @@ static int dvb_register(struct cx8802_dev *dev)
618 case CX88_BOARD_ADSTECH_DVB_T_PCI: 625 case CX88_BOARD_ADSTECH_DVB_T_PCI:
619 dev->dvb.frontend = dvb_attach(mt352_attach, 626 dev->dvb.frontend = dvb_attach(mt352_attach,
620 &dntv_live_dvbt_config, 627 &dntv_live_dvbt_config,
621 &dev->core->i2c_adap); 628 &core->i2c_adap);
622 if (dev->dvb.frontend != NULL) { 629 if (dev->dvb.frontend != NULL) {
623 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, 630 if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend,
624 NULL, DVB_PLL_UNKNOWN_1); 631 0x61, NULL, DVB_PLL_UNKNOWN_1))
632 goto frontend_detach;
625 } 633 }
626 break; 634 break;
627 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO: 635 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
@@ -630,32 +638,35 @@ static int dvb_register(struct cx8802_dev *dev)
630 dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config, 638 dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
631 &dev->vp3054->adap); 639 &dev->vp3054->adap);
632 if (dev->dvb.frontend != NULL) { 640 if (dev->dvb.frontend != NULL) {
633 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 641 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
634 &dev->core->i2c_adap, 0x61, 642 &core->i2c_adap, 0x61,
635 TUNER_PHILIPS_FMD1216ME_MK3); 643 TUNER_PHILIPS_FMD1216ME_MK3))
644 goto frontend_detach;
636 } 645 }
637#else 646#else
638 printk(KERN_ERR "%s/2: built without vp3054 support\n", dev->core->name); 647 printk(KERN_ERR "%s/2: built without vp3054 support\n",
648 core->name);
639#endif 649#endif
640 break; 650 break;
641 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID: 651 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
642 dev->dvb.frontend = dvb_attach(zl10353_attach, 652 dev->dvb.frontend = dvb_attach(zl10353_attach,
643 &dvico_fusionhdtv_hybrid, 653 &dvico_fusionhdtv_hybrid,
644 &dev->core->i2c_adap); 654 &core->i2c_adap);
645 if (dev->dvb.frontend != NULL) { 655 if (dev->dvb.frontend != NULL) {
646 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 656 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
647 &dev->core->i2c_adap, 0x61, 657 &core->i2c_adap, 0x61,
648 TUNER_THOMSON_FE6600); 658 TUNER_THOMSON_FE6600))
659 goto frontend_detach;
649 } 660 }
650 break; 661 break;
651 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO: 662 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
652 dev->dvb.frontend = dvb_attach(zl10353_attach, 663 dev->dvb.frontend = dvb_attach(zl10353_attach,
653 &dvico_fusionhdtv_xc3028, 664 &dvico_fusionhdtv_xc3028,
654 &dev->core->i2c_adap); 665 &core->i2c_adap);
655 if (dev->dvb.frontend == NULL) 666 if (dev->dvb.frontend == NULL)
656 dev->dvb.frontend = dvb_attach(mt352_attach, 667 dev->dvb.frontend = dvb_attach(mt352_attach,
657 &dvico_fusionhdtv_mt352_xc3028, 668 &dvico_fusionhdtv_mt352_xc3028,
658 &dev->core->i2c_adap); 669 &core->i2c_adap);
659 /* 670 /*
660 * On this board, the demod provides the I2C bus pullup. 671 * On this board, the demod provides the I2C bus pullup.
661 * We must not permit gate_ctrl to be performed, or 672 * We must not permit gate_ctrl to be performed, or
@@ -668,19 +679,18 @@ static int dvb_register(struct cx8802_dev *dev)
668 break; 679 break;
669 case CX88_BOARD_PCHDTV_HD3000: 680 case CX88_BOARD_PCHDTV_HD3000:
670 dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000, 681 dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
671 &dev->core->i2c_adap); 682 &core->i2c_adap);
672 if (dev->dvb.frontend != NULL) { 683 if (dev->dvb.frontend != NULL) {
673 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 684 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
674 &dev->core->i2c_adap, 0x61, 685 &core->i2c_adap, 0x61,
675 TUNER_THOMSON_DTT761X); 686 TUNER_THOMSON_DTT761X))
687 goto frontend_detach;
676 } 688 }
677 break; 689 break;
678 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q: 690 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
679 dev->ts_gen_cntrl = 0x08; 691 dev->ts_gen_cntrl = 0x08;
680 {
681 /* Do a hardware reset of chip before using it. */
682 struct cx88_core *core = dev->core;
683 692
693 /* Do a hardware reset of chip before using it. */
684 cx_clear(MO_GP0_IO, 1); 694 cx_clear(MO_GP0_IO, 1);
685 mdelay(100); 695 mdelay(100);
686 cx_set(MO_GP0_IO, 1); 696 cx_set(MO_GP0_IO, 1);
@@ -690,139 +700,137 @@ static int dvb_register(struct cx8802_dev *dev)
690 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set; 700 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
691 dev->dvb.frontend = dvb_attach(lgdt330x_attach, 701 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
692 &fusionhdtv_3_gold, 702 &fusionhdtv_3_gold,
693 &dev->core->i2c_adap); 703 &core->i2c_adap);
694 if (dev->dvb.frontend != NULL) { 704 if (dev->dvb.frontend != NULL) {
695 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 705 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
696 &dev->core->i2c_adap, 0x61, 706 &core->i2c_adap, 0x61,
697 TUNER_MICROTUNE_4042FI5); 707 TUNER_MICROTUNE_4042FI5))
698 } 708 goto frontend_detach;
699 } 709 }
700 break; 710 break;
701 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T: 711 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
702 dev->ts_gen_cntrl = 0x08; 712 dev->ts_gen_cntrl = 0x08;
703 {
704 /* Do a hardware reset of chip before using it. */
705 struct cx88_core *core = dev->core;
706 713
714 /* Do a hardware reset of chip before using it. */
707 cx_clear(MO_GP0_IO, 1); 715 cx_clear(MO_GP0_IO, 1);
708 mdelay(100); 716 mdelay(100);
709 cx_set(MO_GP0_IO, 9); 717 cx_set(MO_GP0_IO, 9);
710 mdelay(200); 718 mdelay(200);
711 dev->dvb.frontend = dvb_attach(lgdt330x_attach, 719 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
712 &fusionhdtv_3_gold, 720 &fusionhdtv_3_gold,
713 &dev->core->i2c_adap); 721 &core->i2c_adap);
714 if (dev->dvb.frontend != NULL) { 722 if (dev->dvb.frontend != NULL) {
715 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 723 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
716 &dev->core->i2c_adap, 0x61, 724 &core->i2c_adap, 0x61,
717 TUNER_THOMSON_DTT761X); 725 TUNER_THOMSON_DTT761X))
718 } 726 goto frontend_detach;
719 } 727 }
720 break; 728 break;
721 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: 729 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
722 dev->ts_gen_cntrl = 0x08; 730 dev->ts_gen_cntrl = 0x08;
723 {
724 /* Do a hardware reset of chip before using it. */
725 struct cx88_core *core = dev->core;
726 731
732 /* Do a hardware reset of chip before using it. */
727 cx_clear(MO_GP0_IO, 1); 733 cx_clear(MO_GP0_IO, 1);
728 mdelay(100); 734 mdelay(100);
729 cx_set(MO_GP0_IO, 1); 735 cx_set(MO_GP0_IO, 1);
730 mdelay(200); 736 mdelay(200);
731 dev->dvb.frontend = dvb_attach(lgdt330x_attach, 737 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
732 &fusionhdtv_5_gold, 738 &fusionhdtv_5_gold,
733 &dev->core->i2c_adap); 739 &core->i2c_adap);
734 if (dev->dvb.frontend != NULL) { 740 if (dev->dvb.frontend != NULL) {
735 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 741 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
736 &dev->core->i2c_adap, 0x61, 742 &core->i2c_adap, 0x61,
737 TUNER_LG_TDVS_H06XF); 743 TUNER_LG_TDVS_H06XF))
738 dvb_attach(tda9887_attach, dev->dvb.frontend, 744 goto frontend_detach;
739 &dev->core->i2c_adap, 0x43); 745 if (!dvb_attach(tda9887_attach, dev->dvb.frontend,
740 } 746 &core->i2c_adap, 0x43))
747 goto frontend_detach;
741 } 748 }
742 break; 749 break;
743 case CX88_BOARD_PCHDTV_HD5500: 750 case CX88_BOARD_PCHDTV_HD5500:
744 dev->ts_gen_cntrl = 0x08; 751 dev->ts_gen_cntrl = 0x08;
745 {
746 /* Do a hardware reset of chip before using it. */
747 struct cx88_core *core = dev->core;
748 752
753 /* Do a hardware reset of chip before using it. */
749 cx_clear(MO_GP0_IO, 1); 754 cx_clear(MO_GP0_IO, 1);
750 mdelay(100); 755 mdelay(100);
751 cx_set(MO_GP0_IO, 1); 756 cx_set(MO_GP0_IO, 1);
752 mdelay(200); 757 mdelay(200);
753 dev->dvb.frontend = dvb_attach(lgdt330x_attach, 758 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
754 &pchdtv_hd5500, 759 &pchdtv_hd5500,
755 &dev->core->i2c_adap); 760 &core->i2c_adap);
756 if (dev->dvb.frontend != NULL) { 761 if (dev->dvb.frontend != NULL) {
757 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 762 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
758 &dev->core->i2c_adap, 0x61, 763 &core->i2c_adap, 0x61,
759 TUNER_LG_TDVS_H06XF); 764 TUNER_LG_TDVS_H06XF))
760 dvb_attach(tda9887_attach, dev->dvb.frontend, 765 goto frontend_detach;
761 &dev->core->i2c_adap, 0x43); 766 if (!dvb_attach(tda9887_attach, dev->dvb.frontend,
762 } 767 &core->i2c_adap, 0x43))
768 goto frontend_detach;
763 } 769 }
764 break; 770 break;
765 case CX88_BOARD_ATI_HDTVWONDER: 771 case CX88_BOARD_ATI_HDTVWONDER:
766 dev->dvb.frontend = dvb_attach(nxt200x_attach, 772 dev->dvb.frontend = dvb_attach(nxt200x_attach,
767 &ati_hdtvwonder, 773 &ati_hdtvwonder,
768 &dev->core->i2c_adap); 774 &core->i2c_adap);
769 if (dev->dvb.frontend != NULL) { 775 if (dev->dvb.frontend != NULL) {
770 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 776 if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend,
771 &dev->core->i2c_adap, 0x61, 777 &core->i2c_adap, 0x61,
772 TUNER_PHILIPS_TUV1236D); 778 TUNER_PHILIPS_TUV1236D))
779 goto frontend_detach;
773 } 780 }
774 break; 781 break;
775 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1: 782 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
776 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1: 783 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
777 dev->dvb.frontend = dvb_attach(cx24123_attach, 784 dev->dvb.frontend = dvb_attach(cx24123_attach,
778 &hauppauge_novas_config, 785 &hauppauge_novas_config,
779 &dev->core->i2c_adap); 786 &core->i2c_adap);
780 if (dev->dvb.frontend) { 787 if (dev->dvb.frontend) {
781 dvb_attach(isl6421_attach, dev->dvb.frontend, 788 if (!dvb_attach(isl6421_attach, dev->dvb.frontend,
782 &dev->core->i2c_adap, 0x08, 0x00, 0x00); 789 &core->i2c_adap, 0x08, 0x00, 0x00))
790 goto frontend_detach;
783 } 791 }
784 break; 792 break;
785 case CX88_BOARD_KWORLD_DVBS_100: 793 case CX88_BOARD_KWORLD_DVBS_100:
786 dev->dvb.frontend = dvb_attach(cx24123_attach, 794 dev->dvb.frontend = dvb_attach(cx24123_attach,
787 &kworld_dvbs_100_config, 795 &kworld_dvbs_100_config,
788 &dev->core->i2c_adap); 796 &core->i2c_adap);
789 if (dev->dvb.frontend) { 797 if (dev->dvb.frontend) {
790 dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; 798 core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
791 dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage; 799 dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
792 } 800 }
793 break; 801 break;
794 case CX88_BOARD_GENIATECH_DVBS: 802 case CX88_BOARD_GENIATECH_DVBS:
795 dev->dvb.frontend = dvb_attach(cx24123_attach, 803 dev->dvb.frontend = dvb_attach(cx24123_attach,
796 &geniatech_dvbs_config, 804 &geniatech_dvbs_config,
797 &dev->core->i2c_adap); 805 &core->i2c_adap);
798 if (dev->dvb.frontend) { 806 if (dev->dvb.frontend) {
799 dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; 807 core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
800 dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage; 808 dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
801 } 809 }
802 break; 810 break;
803 case CX88_BOARD_PINNACLE_PCTV_HD_800i: 811 case CX88_BOARD_PINNACLE_PCTV_HD_800i:
804 dev->dvb.frontend = dvb_attach(s5h1409_attach, 812 dev->dvb.frontend = dvb_attach(s5h1409_attach,
805 &pinnacle_pctv_hd_800i_config, 813 &pinnacle_pctv_hd_800i_config,
806 &dev->core->i2c_adap); 814 &core->i2c_adap);
807 if (dev->dvb.frontend != NULL) { 815 if (dev->dvb.frontend != NULL) {
808 /* tuner_config.video_dev must point to 816 /* tuner_config.video_dev must point to
809 * i2c_adap.algo_data 817 * i2c_adap.algo_data
810 */ 818 */
811 pinnacle_pctv_hd_800i_tuner_config.priv = 819 if (!dvb_attach(xc5000_attach, dev->dvb.frontend,
812 dev->core->i2c_adap.algo_data; 820 &core->i2c_adap,
813 dvb_attach(xc5000_attach, dev->dvb.frontend, 821 &pinnacle_pctv_hd_800i_tuner_config,
814 &dev->core->i2c_adap, 822 core->i2c_adap.algo_data))
815 &pinnacle_pctv_hd_800i_tuner_config); 823 goto frontend_detach;
816 } 824 }
817 break; 825 break;
818 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO: 826 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
819 dev->dvb.frontend = dvb_attach(s5h1409_attach, 827 dev->dvb.frontend = dvb_attach(s5h1409_attach,
820 &dvico_hdtv5_pci_nano_config, 828 &dvico_hdtv5_pci_nano_config,
821 &dev->core->i2c_adap); 829 &core->i2c_adap);
822 if (dev->dvb.frontend != NULL) { 830 if (dev->dvb.frontend != NULL) {
823 struct dvb_frontend *fe; 831 struct dvb_frontend *fe;
824 struct xc2028_config cfg = { 832 struct xc2028_config cfg = {
825 .i2c_adap = &dev->core->i2c_adap, 833 .i2c_adap = &core->i2c_adap,
826 .i2c_addr = 0x61, 834 .i2c_addr = 0x61,
827 .callback = cx88_pci_nano_callback, 835 .callback = cx88_pci_nano_callback,
828 }; 836 };
@@ -841,50 +849,50 @@ static int dvb_register(struct cx8802_dev *dev)
841 case CX88_BOARD_PINNACLE_HYBRID_PCTV: 849 case CX88_BOARD_PINNACLE_HYBRID_PCTV:
842 dev->dvb.frontend = dvb_attach(zl10353_attach, 850 dev->dvb.frontend = dvb_attach(zl10353_attach,
843 &cx88_geniatech_x8000_mt, 851 &cx88_geniatech_x8000_mt,
844 &dev->core->i2c_adap); 852 &core->i2c_adap);
845 if (attach_xc3028(0x61, dev) < 0) 853 if (attach_xc3028(0x61, dev) < 0)
846 return -EINVAL; 854 goto frontend_detach;
847 break; 855 break;
848 case CX88_BOARD_GENIATECH_X8000_MT: 856 case CX88_BOARD_GENIATECH_X8000_MT:
849 dev->ts_gen_cntrl = 0x00; 857 dev->ts_gen_cntrl = 0x00;
850 858
851 dev->dvb.frontend = dvb_attach(zl10353_attach, 859 dev->dvb.frontend = dvb_attach(zl10353_attach,
852 &cx88_geniatech_x8000_mt, 860 &cx88_geniatech_x8000_mt,
853 &dev->core->i2c_adap); 861 &core->i2c_adap);
854 if (attach_xc3028(0x61, dev) < 0) 862 if (attach_xc3028(0x61, dev) < 0)
855 return -EINVAL; 863 goto frontend_detach;
856 break; 864 break;
857 case CX88_BOARD_KWORLD_ATSC_120: 865 case CX88_BOARD_KWORLD_ATSC_120:
858 dev->dvb.frontend = dvb_attach(s5h1409_attach, 866 dev->dvb.frontend = dvb_attach(s5h1409_attach,
859 &kworld_atsc_120_config, 867 &kworld_atsc_120_config,
860 &dev->core->i2c_adap); 868 &core->i2c_adap);
861 if (attach_xc3028(0x61, dev) < 0) 869 if (attach_xc3028(0x61, dev) < 0)
862 return -EINVAL; 870 goto frontend_detach;
863 break; 871 break;
864 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: 872 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
865 dev->dvb.frontend = dvb_attach(s5h1411_attach, 873 dev->dvb.frontend = dvb_attach(s5h1411_attach,
866 &dvico_fusionhdtv7_config, 874 &dvico_fusionhdtv7_config,
867 &dev->core->i2c_adap); 875 &core->i2c_adap);
868 if (dev->dvb.frontend != NULL) { 876 if (dev->dvb.frontend != NULL) {
869 /* tuner_config.video_dev must point to 877 /* tuner_config.video_dev must point to
870 * i2c_adap.algo_data 878 * i2c_adap.algo_data
871 */ 879 */
872 dvico_fusionhdtv7_tuner_config.priv = 880 if (!dvb_attach(xc5000_attach, dev->dvb.frontend,
873 dev->core->i2c_adap.algo_data; 881 &core->i2c_adap,
874 dvb_attach(xc5000_attach, dev->dvb.frontend, 882 &dvico_fusionhdtv7_tuner_config,
875 &dev->core->i2c_adap, 883 core->i2c_adap.algo_data))
876 &dvico_fusionhdtv7_tuner_config); 884 goto frontend_detach;
877 } 885 }
878 break; 886 break;
879 default: 887 default:
880 printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n", 888 printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
881 dev->core->name); 889 core->name);
882 break; 890 break;
883 } 891 }
884 if (NULL == dev->dvb.frontend) { 892 if (NULL == dev->dvb.frontend) {
885 printk(KERN_ERR 893 printk(KERN_ERR
886 "%s/2: frontend initialization failed\n", 894 "%s/2: frontend initialization failed\n",
887 dev->core->name); 895 core->name);
888 return -EINVAL; 896 return -EINVAL;
889 } 897 }
890 898
@@ -892,11 +900,18 @@ static int dvb_register(struct cx8802_dev *dev)
892 dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl; 900 dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
893 901
894 /* Put the analog decoder in standby to keep it quiet */ 902 /* Put the analog decoder in standby to keep it quiet */
895 cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL); 903 cx88_call_i2c_clients(core, TUNER_SET_STANDBY, NULL);
896 904
897 /* register everything */ 905 /* register everything */
898 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, 906 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev,
899 &dev->pci->dev, adapter_nr); 907 &dev->pci->dev, adapter_nr);
908
909frontend_detach:
910 if (dev->dvb.frontend) {
911 dvb_frontend_detach(dev->dvb.frontend);
912 dev->dvb.frontend = NULL;
913 }
914 return -EINVAL;
900} 915}
901 916
902/* ----------------------------------------------------------- */ 917/* ----------------------------------------------------------- */
diff --git a/drivers/media/video/em28xx/Kconfig b/drivers/media/video/em28xx/Kconfig
index c7c2896bbd8b..16a5af30e9d1 100644
--- a/drivers/media/video/em28xx/Kconfig
+++ b/drivers/media/video/em28xx/Kconfig
@@ -1,7 +1,7 @@
1config VIDEO_EM28XX 1config VIDEO_EM28XX
2 tristate "Empia EM28xx USB video capture support" 2 tristate "Empia EM28xx USB video capture support"
3 depends on VIDEO_DEV && I2C && INPUT 3 depends on VIDEO_DEV && I2C && INPUT
4 select MEDIA_TUNER 4 select VIDEO_TUNER
5 select VIDEO_TVEEPROM 5 select VIDEO_TVEEPROM
6 select VIDEO_IR 6 select VIDEO_IR
7 select VIDEOBUF_VMALLOC 7 select VIDEOBUF_VMALLOC
@@ -35,7 +35,6 @@ config VIDEO_EM28XX_DVB
35 select DVB_LGDT330X if !DVB_FE_CUSTOMISE 35 select DVB_LGDT330X if !DVB_FE_CUSTOMISE
36 select DVB_ZL10353 if !DVB_FE_CUSTOMISE 36 select DVB_ZL10353 if !DVB_FE_CUSTOMISE
37 select VIDEOBUF_DVB 37 select VIDEOBUF_DVB
38 select FW_LOADER
39 ---help--- 38 ---help---
40 This adds support for DVB cards based on the 39 This adds support for DVB cards based on the
41 Empiatech em28xx chips. 40 Empiatech em28xx chips.
diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c
index 50ccf3771204..3e4f3c7e92e7 100644
--- a/drivers/media/video/em28xx/em28xx-cards.c
+++ b/drivers/media/video/em28xx/em28xx-cards.c
@@ -420,7 +420,13 @@ struct usb_device_id em28xx_id_table [] = {
420 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 }, 420 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 },
421 { USB_DEVICE(0x2040, 0x6502), 421 { USB_DEVICE(0x2040, 0x6502),
422 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 }, 422 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 },
423 { USB_DEVICE(0x2040, 0x6513), 423 { USB_DEVICE(0x2040, 0x6513), /* HCW HVR-980 */
424 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
425 { USB_DEVICE(0x2040, 0x6517), /* HP HVR-950 */
426 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
427 { USB_DEVICE(0x2040, 0x651b), /* RP HVR-950 */
428 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
429 { USB_DEVICE(0x2040, 0x651f), /* HCW HVR-850 */
424 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 }, 430 .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
425 { USB_DEVICE(0x0ccd, 0x0042), 431 { USB_DEVICE(0x0ccd, 0x0042),
426 .driver_info = EM2880_BOARD_TERRATEC_HYBRID_XS }, 432 .driver_info = EM2880_BOARD_TERRATEC_HYBRID_XS },
diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c
index 7df81575b7f2..8cf4983f0039 100644
--- a/drivers/media/video/em28xx/em28xx-dvb.c
+++ b/drivers/media/video/em28xx/em28xx-dvb.c
@@ -251,7 +251,6 @@ static int attach_xc3028(u8 addr, struct em28xx *dev)
251 printk(KERN_ERR "%s/2: xc3028 attach failed\n", 251 printk(KERN_ERR "%s/2: xc3028 attach failed\n",
252 dev->name); 252 dev->name);
253 dvb_frontend_detach(dev->dvb->frontend); 253 dvb_frontend_detach(dev->dvb->frontend);
254 dvb_unregister_frontend(dev->dvb->frontend);
255 dev->dvb->frontend = NULL; 254 dev->dvb->frontend = NULL;
256 return -EINVAL; 255 return -EINVAL;
257 } 256 }
diff --git a/drivers/media/video/ivtv/Kconfig b/drivers/media/video/ivtv/Kconfig
index eec115bf9517..5d7ee8fcdd50 100644
--- a/drivers/media/video/ivtv/Kconfig
+++ b/drivers/media/video/ivtv/Kconfig
@@ -1,10 +1,12 @@
1config VIDEO_IVTV 1config VIDEO_IVTV
2 tristate "Conexant cx23416/cx23415 MPEG encoder/decoder support" 2 tristate "Conexant cx23416/cx23415 MPEG encoder/decoder support"
3 depends on VIDEO_V4L1 && VIDEO_V4L2 && PCI && I2C && EXPERIMENTAL 3 depends on VIDEO_V4L1 && VIDEO_V4L2 && PCI && I2C && EXPERIMENTAL
4 depends on INPUT # due to VIDEO_IR
5 depends on HOTPLUG # due to FW_LOADER
4 select I2C_ALGOBIT 6 select I2C_ALGOBIT
5 select FW_LOADER 7 select FW_LOADER
6 select VIDEO_IR 8 select VIDEO_IR
7 select MEDIA_TUNER 9 select VIDEO_TUNER
8 select VIDEO_TVEEPROM 10 select VIDEO_TVEEPROM
9 select VIDEO_CX2341X 11 select VIDEO_CX2341X
10 select VIDEO_CX25840 12 select VIDEO_CX25840
diff --git a/drivers/media/video/ivtv/ivtv-controls.c b/drivers/media/video/ivtv/ivtv-controls.c
index 8c02fa661591..c7e449f6397b 100644
--- a/drivers/media/video/ivtv/ivtv-controls.c
+++ b/drivers/media/video/ivtv/ivtv-controls.c
@@ -181,12 +181,12 @@ static int ivtv_setup_vbi_fmt(struct ivtv *itv, enum v4l2_mpeg_stream_vbi_fmt fm
181 return 0; 181 return 0;
182 } 182 }
183 /* Need sliced data for mpeg insertion */ 183 /* Need sliced data for mpeg insertion */
184 if (get_service_set(itv->vbi.sliced_in) == 0) { 184 if (ivtv_get_service_set(itv->vbi.sliced_in) == 0) {
185 if (itv->is_60hz) 185 if (itv->is_60hz)
186 itv->vbi.sliced_in->service_set = V4L2_SLICED_CAPTION_525; 186 itv->vbi.sliced_in->service_set = V4L2_SLICED_CAPTION_525;
187 else 187 else
188 itv->vbi.sliced_in->service_set = V4L2_SLICED_WSS_625; 188 itv->vbi.sliced_in->service_set = V4L2_SLICED_WSS_625;
189 expand_service_set(itv->vbi.sliced_in, itv->is_50hz); 189 ivtv_expand_service_set(itv->vbi.sliced_in, itv->is_50hz);
190 } 190 }
191 return 0; 191 return 0;
192} 192}
diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c
index ed020f722b05..797e636771da 100644
--- a/drivers/media/video/ivtv/ivtv-driver.c
+++ b/drivers/media/video/ivtv/ivtv-driver.c
@@ -853,6 +853,7 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *dev,
853 return 0; 853 return 0;
854} 854}
855 855
856#ifdef MODULE
856static u32 ivtv_request_module(struct ivtv *itv, u32 hw, 857static u32 ivtv_request_module(struct ivtv *itv, u32 hw,
857 const char *name, u32 id) 858 const char *name, u32 id)
858{ 859{
@@ -865,12 +866,14 @@ static u32 ivtv_request_module(struct ivtv *itv, u32 hw,
865 IVTV_DEBUG_INFO("Loaded module %s\n", name); 866 IVTV_DEBUG_INFO("Loaded module %s\n", name);
866 return hw; 867 return hw;
867} 868}
869#endif
868 870
869static void ivtv_load_and_init_modules(struct ivtv *itv) 871static void ivtv_load_and_init_modules(struct ivtv *itv)
870{ 872{
871 u32 hw = itv->card->hw_all; 873 u32 hw = itv->card->hw_all;
872 unsigned i; 874 unsigned i;
873 875
876#ifdef MODULE
874 /* load modules */ 877 /* load modules */
875#ifndef CONFIG_MEDIA_TUNER 878#ifndef CONFIG_MEDIA_TUNER
876 hw = ivtv_request_module(itv, hw, "tuner", IVTV_HW_TUNER); 879 hw = ivtv_request_module(itv, hw, "tuner", IVTV_HW_TUNER);
@@ -911,6 +914,7 @@ static void ivtv_load_and_init_modules(struct ivtv *itv)
911#ifndef CONFIG_VIDEO_M52790 914#ifndef CONFIG_VIDEO_M52790
912 hw = ivtv_request_module(itv, hw, "m52790", IVTV_HW_M52790); 915 hw = ivtv_request_module(itv, hw, "m52790", IVTV_HW_M52790);
913#endif 916#endif
917#endif
914 918
915 /* check which i2c devices are actually found */ 919 /* check which i2c devices are actually found */
916 for (i = 0; i < 32; i++) { 920 for (i = 0; i < 32; i++) {
@@ -1228,7 +1232,7 @@ static int __devinit ivtv_probe(struct pci_dev *dev,
1228 return 0; 1232 return 0;
1229 1233
1230free_streams: 1234free_streams:
1231 ivtv_streams_cleanup(itv); 1235 ivtv_streams_cleanup(itv, 1);
1232free_irq: 1236free_irq:
1233 free_irq(itv->dev->irq, (void *)itv); 1237 free_irq(itv->dev->irq, (void *)itv);
1234free_i2c: 1238free_i2c:
@@ -1373,7 +1377,7 @@ static void ivtv_remove(struct pci_dev *pci_dev)
1373 flush_workqueue(itv->irq_work_queues); 1377 flush_workqueue(itv->irq_work_queues);
1374 destroy_workqueue(itv->irq_work_queues); 1378 destroy_workqueue(itv->irq_work_queues);
1375 1379
1376 ivtv_streams_cleanup(itv); 1380 ivtv_streams_cleanup(itv, 1);
1377 ivtv_udma_free(itv); 1381 ivtv_udma_free(itv);
1378 1382
1379 exit_ivtv_i2c(itv); 1383 exit_ivtv_i2c(itv);
diff --git a/drivers/media/video/ivtv/ivtv-fileops.c b/drivers/media/video/ivtv/ivtv-fileops.c
index 2b74b0ab1477..f2fa434b677b 100644
--- a/drivers/media/video/ivtv/ivtv-fileops.c
+++ b/drivers/media/video/ivtv/ivtv-fileops.c
@@ -987,6 +987,8 @@ int ivtv_v4l2_open(struct inode *inode, struct file *filp)
987 /* Find which card this open was on */ 987 /* Find which card this open was on */
988 spin_lock(&ivtv_cards_lock); 988 spin_lock(&ivtv_cards_lock);
989 for (x = 0; itv == NULL && x < ivtv_cards_active; x++) { 989 for (x = 0; itv == NULL && x < ivtv_cards_active; x++) {
990 if (ivtv_cards[x] == NULL)
991 continue;
990 /* find out which stream this open was on */ 992 /* find out which stream this open was on */
991 for (y = 0; y < IVTV_MAX_STREAMS; y++) { 993 for (y = 0; y < IVTV_MAX_STREAMS; y++) {
992 s = &ivtv_cards[x]->streams[y]; 994 s = &ivtv_cards[x]->streams[y];
diff --git a/drivers/media/video/ivtv/ivtv-ioctl.c b/drivers/media/video/ivtv/ivtv-ioctl.c
index d508b5d0538c..26cc0f6699fd 100644
--- a/drivers/media/video/ivtv/ivtv-ioctl.c
+++ b/drivers/media/video/ivtv/ivtv-ioctl.c
@@ -38,7 +38,7 @@
38#include <linux/dvb/audio.h> 38#include <linux/dvb/audio.h>
39#include <linux/i2c-id.h> 39#include <linux/i2c-id.h>
40 40
41u16 service2vbi(int type) 41u16 ivtv_service2vbi(int type)
42{ 42{
43 switch (type) { 43 switch (type) {
44 case V4L2_SLICED_TELETEXT_B: 44 case V4L2_SLICED_TELETEXT_B:
@@ -88,7 +88,7 @@ static u16 select_service_from_set(int field, int line, u16 set, int is_pal)
88 return 0; 88 return 0;
89} 89}
90 90
91void expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal) 91void ivtv_expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal)
92{ 92{
93 u16 set = fmt->service_set; 93 u16 set = fmt->service_set;
94 int f, l; 94 int f, l;
@@ -115,7 +115,7 @@ static int check_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal)
115 return set != 0; 115 return set != 0;
116} 116}
117 117
118u16 get_service_set(struct v4l2_sliced_vbi_format *fmt) 118u16 ivtv_get_service_set(struct v4l2_sliced_vbi_format *fmt)
119{ 119{
120 int f, l; 120 int f, l;
121 u16 set = 0; 121 u16 set = 0;
@@ -466,7 +466,7 @@ static int ivtv_get_fmt(struct ivtv *itv, int streamtype, struct v4l2_format *fm
466 vbifmt->service_lines[0][23] = V4L2_SLICED_WSS_625; 466 vbifmt->service_lines[0][23] = V4L2_SLICED_WSS_625;
467 vbifmt->service_lines[0][16] = V4L2_SLICED_VPS; 467 vbifmt->service_lines[0][16] = V4L2_SLICED_VPS;
468 } 468 }
469 vbifmt->service_set = get_service_set(vbifmt); 469 vbifmt->service_set = ivtv_get_service_set(vbifmt);
470 break; 470 break;
471 } 471 }
472 472
@@ -481,12 +481,12 @@ static int ivtv_get_fmt(struct ivtv *itv, int streamtype, struct v4l2_format *fm
481 if (streamtype == IVTV_DEC_STREAM_TYPE_VBI) { 481 if (streamtype == IVTV_DEC_STREAM_TYPE_VBI) {
482 vbifmt->service_set = itv->is_50hz ? V4L2_SLICED_VBI_625 : 482 vbifmt->service_set = itv->is_50hz ? V4L2_SLICED_VBI_625 :
483 V4L2_SLICED_VBI_525; 483 V4L2_SLICED_VBI_525;
484 expand_service_set(vbifmt, itv->is_50hz); 484 ivtv_expand_service_set(vbifmt, itv->is_50hz);
485 break; 485 break;
486 } 486 }
487 487
488 itv->video_dec_func(itv, VIDIOC_G_FMT, fmt); 488 itv->video_dec_func(itv, VIDIOC_G_FMT, fmt);
489 vbifmt->service_set = get_service_set(vbifmt); 489 vbifmt->service_set = ivtv_get_service_set(vbifmt);
490 break; 490 break;
491 } 491 }
492 case V4L2_BUF_TYPE_VBI_OUTPUT: 492 case V4L2_BUF_TYPE_VBI_OUTPUT:
@@ -640,9 +640,9 @@ static int ivtv_try_or_set_fmt(struct ivtv *itv, int streamtype,
640 memset(vbifmt->reserved, 0, sizeof(vbifmt->reserved)); 640 memset(vbifmt->reserved, 0, sizeof(vbifmt->reserved));
641 641
642 if (vbifmt->service_set) 642 if (vbifmt->service_set)
643 expand_service_set(vbifmt, itv->is_50hz); 643 ivtv_expand_service_set(vbifmt, itv->is_50hz);
644 set = check_service_set(vbifmt, itv->is_50hz); 644 set = check_service_set(vbifmt, itv->is_50hz);
645 vbifmt->service_set = get_service_set(vbifmt); 645 vbifmt->service_set = ivtv_get_service_set(vbifmt);
646 646
647 if (!set_fmt) 647 if (!set_fmt)
648 return 0; 648 return 0;
diff --git a/drivers/media/video/ivtv/ivtv-ioctl.h b/drivers/media/video/ivtv/ivtv-ioctl.h
index a03351b6853d..4e67f0ed1fc0 100644
--- a/drivers/media/video/ivtv/ivtv-ioctl.h
+++ b/drivers/media/video/ivtv/ivtv-ioctl.h
@@ -21,9 +21,9 @@
21#ifndef IVTV_IOCTL_H 21#ifndef IVTV_IOCTL_H
22#define IVTV_IOCTL_H 22#define IVTV_IOCTL_H
23 23
24u16 service2vbi(int type); 24u16 ivtv_service2vbi(int type);
25void expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal); 25void ivtv_expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal);
26u16 get_service_set(struct v4l2_sliced_vbi_format *fmt); 26u16 ivtv_get_service_set(struct v4l2_sliced_vbi_format *fmt);
27int ivtv_v4l2_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, 27int ivtv_v4l2_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
28 unsigned long arg); 28 unsigned long arg);
29int ivtv_v4l2_ioctls(struct ivtv *itv, struct file *filp, unsigned int cmd, void *arg); 29int ivtv_v4l2_ioctls(struct ivtv *itv, struct file *filp, unsigned int cmd, void *arg);
diff --git a/drivers/media/video/ivtv/ivtv-queue.c b/drivers/media/video/ivtv/ivtv-queue.c
index 3e1deec67a5e..fc8b1eaa333b 100644
--- a/drivers/media/video/ivtv/ivtv-queue.c
+++ b/drivers/media/video/ivtv/ivtv-queue.c
@@ -203,14 +203,14 @@ int ivtv_stream_alloc(struct ivtv_stream *s)
203 s->dma != PCI_DMA_NONE ? "DMA " : "", 203 s->dma != PCI_DMA_NONE ? "DMA " : "",
204 s->name, s->buffers, s->buf_size, s->buffers * s->buf_size / 1024); 204 s->name, s->buffers, s->buf_size, s->buffers * s->buf_size / 1024);
205 205
206 s->sg_pending = kzalloc(SGsize, GFP_KERNEL); 206 s->sg_pending = kzalloc(SGsize, GFP_KERNEL|__GFP_NOWARN);
207 if (s->sg_pending == NULL) { 207 if (s->sg_pending == NULL) {
208 IVTV_ERR("Could not allocate sg_pending for %s stream\n", s->name); 208 IVTV_ERR("Could not allocate sg_pending for %s stream\n", s->name);
209 return -ENOMEM; 209 return -ENOMEM;
210 } 210 }
211 s->sg_pending_size = 0; 211 s->sg_pending_size = 0;
212 212
213 s->sg_processing = kzalloc(SGsize, GFP_KERNEL); 213 s->sg_processing = kzalloc(SGsize, GFP_KERNEL|__GFP_NOWARN);
214 if (s->sg_processing == NULL) { 214 if (s->sg_processing == NULL) {
215 IVTV_ERR("Could not allocate sg_processing for %s stream\n", s->name); 215 IVTV_ERR("Could not allocate sg_processing for %s stream\n", s->name);
216 kfree(s->sg_pending); 216 kfree(s->sg_pending);
@@ -219,7 +219,8 @@ int ivtv_stream_alloc(struct ivtv_stream *s)
219 } 219 }
220 s->sg_processing_size = 0; 220 s->sg_processing_size = 0;
221 221
222 s->sg_dma = kzalloc(sizeof(struct ivtv_sg_element), GFP_KERNEL); 222 s->sg_dma = kzalloc(sizeof(struct ivtv_sg_element),
223 GFP_KERNEL|__GFP_NOWARN);
223 if (s->sg_dma == NULL) { 224 if (s->sg_dma == NULL) {
224 IVTV_ERR("Could not allocate sg_dma for %s stream\n", s->name); 225 IVTV_ERR("Could not allocate sg_dma for %s stream\n", s->name);
225 kfree(s->sg_pending); 226 kfree(s->sg_pending);
@@ -235,11 +236,12 @@ int ivtv_stream_alloc(struct ivtv_stream *s)
235 236
236 /* allocate stream buffers. Initially all buffers are in q_free. */ 237 /* allocate stream buffers. Initially all buffers are in q_free. */
237 for (i = 0; i < s->buffers; i++) { 238 for (i = 0; i < s->buffers; i++) {
238 struct ivtv_buffer *buf = kzalloc(sizeof(struct ivtv_buffer), GFP_KERNEL); 239 struct ivtv_buffer *buf = kzalloc(sizeof(struct ivtv_buffer),
240 GFP_KERNEL|__GFP_NOWARN);
239 241
240 if (buf == NULL) 242 if (buf == NULL)
241 break; 243 break;
242 buf->buf = kmalloc(s->buf_size + 256, GFP_KERNEL); 244 buf->buf = kmalloc(s->buf_size + 256, GFP_KERNEL|__GFP_NOWARN);
243 if (buf->buf == NULL) { 245 if (buf->buf == NULL) {
244 kfree(buf); 246 kfree(buf);
245 break; 247 break;
diff --git a/drivers/media/video/ivtv/ivtv-streams.c b/drivers/media/video/ivtv/ivtv-streams.c
index 4ab8d36831ba..c47c2b945147 100644
--- a/drivers/media/video/ivtv/ivtv-streams.c
+++ b/drivers/media/video/ivtv/ivtv-streams.c
@@ -244,7 +244,7 @@ int ivtv_streams_setup(struct ivtv *itv)
244 return 0; 244 return 0;
245 245
246 /* One or more streams could not be initialized. Clean 'em all up. */ 246 /* One or more streams could not be initialized. Clean 'em all up. */
247 ivtv_streams_cleanup(itv); 247 ivtv_streams_cleanup(itv, 0);
248 return -ENOMEM; 248 return -ENOMEM;
249} 249}
250 250
@@ -304,12 +304,12 @@ int ivtv_streams_register(struct ivtv *itv)
304 return 0; 304 return 0;
305 305
306 /* One or more streams could not be initialized. Clean 'em all up. */ 306 /* One or more streams could not be initialized. Clean 'em all up. */
307 ivtv_streams_cleanup(itv); 307 ivtv_streams_cleanup(itv, 1);
308 return -ENOMEM; 308 return -ENOMEM;
309} 309}
310 310
311/* Unregister v4l2 devices */ 311/* Unregister v4l2 devices */
312void ivtv_streams_cleanup(struct ivtv *itv) 312void ivtv_streams_cleanup(struct ivtv *itv, int unregister)
313{ 313{
314 int type; 314 int type;
315 315
@@ -322,8 +322,11 @@ void ivtv_streams_cleanup(struct ivtv *itv)
322 continue; 322 continue;
323 323
324 ivtv_stream_free(&itv->streams[type]); 324 ivtv_stream_free(&itv->streams[type]);
325 /* Unregister device */ 325 /* Unregister or release device */
326 video_unregister_device(vdev); 326 if (unregister)
327 video_unregister_device(vdev);
328 else
329 video_device_release(vdev);
327 } 330 }
328} 331}
329 332
diff --git a/drivers/media/video/ivtv/ivtv-streams.h b/drivers/media/video/ivtv/ivtv-streams.h
index 3d76a415fbd8..a653a5136417 100644
--- a/drivers/media/video/ivtv/ivtv-streams.h
+++ b/drivers/media/video/ivtv/ivtv-streams.h
@@ -23,7 +23,7 @@
23 23
24int ivtv_streams_setup(struct ivtv *itv); 24int ivtv_streams_setup(struct ivtv *itv);
25int ivtv_streams_register(struct ivtv *itv); 25int ivtv_streams_register(struct ivtv *itv);
26void ivtv_streams_cleanup(struct ivtv *itv); 26void ivtv_streams_cleanup(struct ivtv *itv, int unregister);
27 27
28/* Capture related */ 28/* Capture related */
29int ivtv_start_v4l2_encode_stream(struct ivtv_stream *s); 29int ivtv_start_v4l2_encode_stream(struct ivtv_stream *s);
diff --git a/drivers/media/video/ivtv/ivtv-vbi.c b/drivers/media/video/ivtv/ivtv-vbi.c
index c151bcf5519a..71798f0da27f 100644
--- a/drivers/media/video/ivtv/ivtv-vbi.c
+++ b/drivers/media/video/ivtv/ivtv-vbi.c
@@ -169,7 +169,8 @@ static void copy_vbi_data(struct ivtv *itv, int lines, u32 pts_stamp)
169 linemask[0] |= (1 << l); 169 linemask[0] |= (1 << l);
170 else 170 else
171 linemask[1] |= (1 << (l - 32)); 171 linemask[1] |= (1 << (l - 32));
172 dst[sd + 12 + line * 43] = service2vbi(itv->vbi.sliced_data[i].id); 172 dst[sd + 12 + line * 43] =
173 ivtv_service2vbi(itv->vbi.sliced_data[i].id);
173 memcpy(dst + sd + 12 + line * 43 + 1, itv->vbi.sliced_data[i].data, 42); 174 memcpy(dst + sd + 12 + line * 43 + 1, itv->vbi.sliced_data[i].data, 42);
174 line++; 175 line++;
175 } 176 }
diff --git a/drivers/media/video/ivtv/ivtv-yuv.c b/drivers/media/video/ivtv/ivtv-yuv.c
index 62f70bd5e3cb..a9417f6e4087 100644
--- a/drivers/media/video/ivtv/ivtv-yuv.c
+++ b/drivers/media/video/ivtv/ivtv-yuv.c
@@ -908,7 +908,7 @@ static void ivtv_yuv_init(struct ivtv *itv)
908 } 908 }
909 909
910 /* We need a buffer for blanking when Y plane is offset - non-fatal if we can't get one */ 910 /* We need a buffer for blanking when Y plane is offset - non-fatal if we can't get one */
911 yi->blanking_ptr = kzalloc(720 * 16, GFP_KERNEL); 911 yi->blanking_ptr = kzalloc(720 * 16, GFP_KERNEL|__GFP_NOWARN);
912 if (yi->blanking_ptr) { 912 if (yi->blanking_ptr) {
913 yi->blanking_dmaptr = pci_map_single(itv->dev, yi->blanking_ptr, 720*16, PCI_DMA_TODEVICE); 913 yi->blanking_dmaptr = pci_map_single(itv->dev, yi->blanking_ptr, 720*16, PCI_DMA_TODEVICE);
914 } else { 914 } else {
diff --git a/drivers/media/video/ivtv/ivtvfb.c b/drivers/media/video/ivtv/ivtvfb.c
index df789f683e63..73be154f7f05 100644
--- a/drivers/media/video/ivtv/ivtvfb.c
+++ b/drivers/media/video/ivtv/ivtvfb.c
@@ -948,7 +948,8 @@ static int ivtvfb_init_vidmode(struct ivtv *itv)
948 } 948 }
949 949
950 /* Allocate the pseudo palette */ 950 /* Allocate the pseudo palette */
951 oi->ivtvfb_info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); 951 oi->ivtvfb_info.pseudo_palette =
952 kmalloc(sizeof(u32) * 16, GFP_KERNEL|__GFP_NOWARN);
952 953
953 if (!oi->ivtvfb_info.pseudo_palette) { 954 if (!oi->ivtvfb_info.pseudo_palette) {
954 IVTVFB_ERR("abort, unable to alloc pseudo pallete\n"); 955 IVTVFB_ERR("abort, unable to alloc pseudo pallete\n");
@@ -1056,7 +1057,8 @@ static int ivtvfb_init_card(struct ivtv *itv)
1056 return -EBUSY; 1057 return -EBUSY;
1057 } 1058 }
1058 1059
1059 itv->osd_info = kzalloc(sizeof(struct osd_info), GFP_ATOMIC); 1060 itv->osd_info = kzalloc(sizeof(struct osd_info),
1061 GFP_ATOMIC|__GFP_NOWARN);
1060 if (itv->osd_info == NULL) { 1062 if (itv->osd_info == NULL) {
1061 IVTVFB_ERR("Failed to allocate memory for osd_info\n"); 1063 IVTVFB_ERR("Failed to allocate memory for osd_info\n");
1062 return -ENOMEM; 1064 return -ENOMEM;
diff --git a/drivers/media/video/mt9m001.c b/drivers/media/video/mt9m001.c
index 179e47049a45..ee43499544c1 100644
--- a/drivers/media/video/mt9m001.c
+++ b/drivers/media/video/mt9m001.c
@@ -12,15 +12,12 @@
12#include <linux/slab.h> 12#include <linux/slab.h>
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/log2.h> 14#include <linux/log2.h>
15#include <linux/gpio.h>
15 16
16#include <media/v4l2-common.h> 17#include <media/v4l2-common.h>
17#include <media/v4l2-chip-ident.h> 18#include <media/v4l2-chip-ident.h>
18#include <media/soc_camera.h> 19#include <media/soc_camera.h>
19 20
20#ifdef CONFIG_MT9M001_PCA9536_SWITCH
21#include <asm/gpio.h>
22#endif
23
24/* mt9m001 i2c address 0x5d 21/* mt9m001 i2c address 0x5d
25 * The platform has to define i2c_board_info 22 * The platform has to define i2c_board_info
26 * and call i2c_register_board_info() */ 23 * and call i2c_register_board_info() */
diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c
index d1391ac55096..1658fe590392 100644
--- a/drivers/media/video/mt9v022.c
+++ b/drivers/media/video/mt9v022.c
@@ -13,15 +13,12 @@
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/delay.h> 14#include <linux/delay.h>
15#include <linux/log2.h> 15#include <linux/log2.h>
16#include <linux/gpio.h>
16 17
17#include <media/v4l2-common.h> 18#include <media/v4l2-common.h>
18#include <media/v4l2-chip-ident.h> 19#include <media/v4l2-chip-ident.h>
19#include <media/soc_camera.h> 20#include <media/soc_camera.h>
20 21
21#ifdef CONFIG_MT9M001_PCA9536_SWITCH
22#include <asm/gpio.h>
23#endif
24
25/* mt9v022 i2c address 0x48, 0x4c, 0x58, 0x5c 22/* mt9v022 i2c address 0x48, 0x4c, 0x58, 0x5c
26 * The platform has to define i2c_board_info 23 * The platform has to define i2c_board_info
27 * and call i2c_register_board_info() */ 24 * and call i2c_register_board_info() */
@@ -91,7 +88,7 @@ static const struct soc_camera_data_format mt9v022_monochrome_formats[] = {
91struct mt9v022 { 88struct mt9v022 {
92 struct i2c_client *client; 89 struct i2c_client *client;
93 struct soc_camera_device icd; 90 struct soc_camera_device icd;
94 int model; /* V4L2_IDENT_MT9M001* codes from v4l2-chip-ident.h */ 91 int model; /* V4L2_IDENT_MT9V022* codes from v4l2-chip-ident.h */
95 int switch_gpio; 92 int switch_gpio;
96 u16 chip_control; 93 u16 chip_control;
97 unsigned char datawidth; 94 unsigned char datawidth;
diff --git a/drivers/media/video/pvrusb2/Kconfig b/drivers/media/video/pvrusb2/Kconfig
index 9620c67fae77..4482b2c72ced 100644
--- a/drivers/media/video/pvrusb2/Kconfig
+++ b/drivers/media/video/pvrusb2/Kconfig
@@ -1,8 +1,10 @@
1config VIDEO_PVRUSB2 1config VIDEO_PVRUSB2
2 tristate "Hauppauge WinTV-PVR USB2 support" 2 tristate "Hauppauge WinTV-PVR USB2 support"
3 depends on VIDEO_V4L2 && I2C 3 depends on VIDEO_V4L2 && I2C
4 depends on VIDEO_MEDIA # Avoids pvrusb = Y / DVB = M
5 depends on HOTPLUG # due to FW_LOADER
4 select FW_LOADER 6 select FW_LOADER
5 select MEDIA_TUNER 7 select VIDEO_TUNER
6 select VIDEO_TVEEPROM 8 select VIDEO_TVEEPROM
7 select VIDEO_CX2341X 9 select VIDEO_CX2341X
8 select VIDEO_SAA711X 10 select VIDEO_SAA711X
diff --git a/drivers/media/video/saa7134/Kconfig b/drivers/media/video/saa7134/Kconfig
index 40e4c3bd2cb9..83f076abce35 100644
--- a/drivers/media/video/saa7134/Kconfig
+++ b/drivers/media/video/saa7134/Kconfig
@@ -3,7 +3,7 @@ config VIDEO_SAA7134
3 depends on VIDEO_DEV && PCI && I2C && INPUT 3 depends on VIDEO_DEV && PCI && I2C && INPUT
4 select VIDEOBUF_DMA_SG 4 select VIDEOBUF_DMA_SG
5 select VIDEO_IR 5 select VIDEO_IR
6 select MEDIA_TUNER 6 select VIDEO_TUNER
7 select VIDEO_TVEEPROM 7 select VIDEO_TVEEPROM
8 select CRC32 8 select CRC32
9 ---help--- 9 ---help---
@@ -27,6 +27,7 @@ config VIDEO_SAA7134_ALSA
27config VIDEO_SAA7134_DVB 27config VIDEO_SAA7134_DVB
28 tristate "DVB/ATSC Support for saa7134 based TV cards" 28 tristate "DVB/ATSC Support for saa7134 based TV cards"
29 depends on VIDEO_SAA7134 && DVB_CORE 29 depends on VIDEO_SAA7134 && DVB_CORE
30 depends on HOTPLUG # due to FW_LOADER
30 select VIDEOBUF_DVB 31 select VIDEOBUF_DVB
31 select FW_LOADER 32 select FW_LOADER
32 select DVB_PLL if !DVB_FE_CUSTOMISE 33 select DVB_PLL if !DVB_FE_CUSTOMISE
diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c
index eec127864fe3..2c19cd0113c8 100644
--- a/drivers/media/video/saa7134/saa7134-core.c
+++ b/drivers/media/video/saa7134/saa7134-core.c
@@ -864,7 +864,6 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev,
864 struct saa7134_dev *dev; 864 struct saa7134_dev *dev;
865 struct saa7134_mpeg_ops *mops; 865 struct saa7134_mpeg_ops *mops;
866 int err; 866 int err;
867 int mask;
868 867
869 if (saa7134_devcount == SAA7134_MAXBOARDS) 868 if (saa7134_devcount == SAA7134_MAXBOARDS)
870 return -ENOMEM; 869 return -ENOMEM;
@@ -1065,11 +1064,6 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev,
1065 if (TUNER_ABSENT != dev->tuner_type) 1064 if (TUNER_ABSENT != dev->tuner_type)
1066 saa7134_i2c_call_clients(dev, TUNER_SET_STANDBY, NULL); 1065 saa7134_i2c_call_clients(dev, TUNER_SET_STANDBY, NULL);
1067 1066
1068 if (card(dev).gpiomask != 0) {
1069 mask = card(dev).gpiomask;
1070 saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, mask, mask);
1071 saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, mask, 0);
1072 }
1073 return 0; 1067 return 0;
1074 1068
1075 fail4: 1069 fail4:
diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c
index 2d16be2259db..469f93aac008 100644
--- a/drivers/media/video/saa7134/saa7134-dvb.c
+++ b/drivers/media/video/saa7134/saa7134-dvb.c
@@ -538,19 +538,23 @@ static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe)
538 return 0; 538 return 0;
539} 539}
540 540
541static void configure_tda827x_fe(struct saa7134_dev *dev, struct tda1004x_config *cdec_conf, 541static int configure_tda827x_fe(struct saa7134_dev *dev,
542 struct tda827x_config *tuner_conf) 542 struct tda1004x_config *cdec_conf,
543 struct tda827x_config *tuner_conf)
543{ 544{
544 dev->dvb.frontend = dvb_attach(tda10046_attach, cdec_conf, &dev->i2c_adap); 545 dev->dvb.frontend = dvb_attach(tda10046_attach, cdec_conf, &dev->i2c_adap);
545 if (dev->dvb.frontend) { 546 if (dev->dvb.frontend) {
546 if (cdec_conf->i2c_gate) 547 if (cdec_conf->i2c_gate)
547 dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl; 548 dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl;
548 if (dvb_attach(tda827x_attach, dev->dvb.frontend, cdec_conf->tuner_address, 549 if (dvb_attach(tda827x_attach, dev->dvb.frontend,
549 &dev->i2c_adap, tuner_conf) == NULL) { 550 cdec_conf->tuner_address,
550 wprintk("no tda827x tuner found at addr: %02x\n", 551 &dev->i2c_adap, tuner_conf))
552 return 0;
553
554 wprintk("no tda827x tuner found at addr: %02x\n",
551 cdec_conf->tuner_address); 555 cdec_conf->tuner_address);
552 }
553 } 556 }
557 return -EINVAL;
554} 558}
555 559
556/* ------------------------------------------------------------------ */ 560/* ------------------------------------------------------------------ */
@@ -997,7 +1001,9 @@ static int dvb_init(struct saa7134_dev *dev)
997 break; 1001 break;
998 case SAA7134_BOARD_FLYDVBTDUO: 1002 case SAA7134_BOARD_FLYDVBTDUO:
999 case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS: 1003 case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS:
1000 configure_tda827x_fe(dev, &tda827x_lifeview_config, &tda827x_cfg_0); 1004 if (configure_tda827x_fe(dev, &tda827x_lifeview_config,
1005 &tda827x_cfg_0) < 0)
1006 goto dettach_frontend;
1001 break; 1007 break;
1002 case SAA7134_BOARD_PHILIPS_EUROPA: 1008 case SAA7134_BOARD_PHILIPS_EUROPA:
1003 case SAA7134_BOARD_VIDEOMATE_DVBT_300: 1009 case SAA7134_BOARD_VIDEOMATE_DVBT_300:
@@ -1022,36 +1028,52 @@ static int dvb_init(struct saa7134_dev *dev)
1022 } 1028 }
1023 break; 1029 break;
1024 case SAA7134_BOARD_KWORLD_DVBT_210: 1030 case SAA7134_BOARD_KWORLD_DVBT_210:
1025 configure_tda827x_fe(dev, &kworld_dvb_t_210_config, &tda827x_cfg_2); 1031 if (configure_tda827x_fe(dev, &kworld_dvb_t_210_config,
1032 &tda827x_cfg_2) < 0)
1033 goto dettach_frontend;
1026 break; 1034 break;
1027 case SAA7134_BOARD_PHILIPS_TIGER: 1035 case SAA7134_BOARD_PHILIPS_TIGER:
1028 configure_tda827x_fe(dev, &philips_tiger_config, &tda827x_cfg_0); 1036 if (configure_tda827x_fe(dev, &philips_tiger_config,
1037 &tda827x_cfg_0) < 0)
1038 goto dettach_frontend;
1029 break; 1039 break;
1030 case SAA7134_BOARD_PINNACLE_PCTV_310i: 1040 case SAA7134_BOARD_PINNACLE_PCTV_310i:
1031 configure_tda827x_fe(dev, &pinnacle_pctv_310i_config, &tda827x_cfg_1); 1041 if (configure_tda827x_fe(dev, &pinnacle_pctv_310i_config,
1042 &tda827x_cfg_1) < 0)
1043 goto dettach_frontend;
1032 break; 1044 break;
1033 case SAA7134_BOARD_HAUPPAUGE_HVR1110: 1045 case SAA7134_BOARD_HAUPPAUGE_HVR1110:
1034 configure_tda827x_fe(dev, &hauppauge_hvr_1110_config, &tda827x_cfg_1); 1046 if (configure_tda827x_fe(dev, &hauppauge_hvr_1110_config,
1047 &tda827x_cfg_1) < 0)
1048 goto dettach_frontend;
1035 break; 1049 break;
1036 case SAA7134_BOARD_ASUSTeK_P7131_DUAL: 1050 case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
1037 configure_tda827x_fe(dev, &asus_p7131_dual_config, &tda827x_cfg_0); 1051 if (configure_tda827x_fe(dev, &asus_p7131_dual_config,
1052 &tda827x_cfg_0) < 0)
1053 goto dettach_frontend;
1038 break; 1054 break;
1039 case SAA7134_BOARD_FLYDVBT_LR301: 1055 case SAA7134_BOARD_FLYDVBT_LR301:
1040 configure_tda827x_fe(dev, &tda827x_lifeview_config, &tda827x_cfg_0); 1056 if (configure_tda827x_fe(dev, &tda827x_lifeview_config,
1057 &tda827x_cfg_0) < 0)
1058 goto dettach_frontend;
1041 break; 1059 break;
1042 case SAA7134_BOARD_FLYDVB_TRIO: 1060 case SAA7134_BOARD_FLYDVB_TRIO:
1043 if(! use_frontend) { /* terrestrial */ 1061 if (!use_frontend) { /* terrestrial */
1044 configure_tda827x_fe(dev, &lifeview_trio_config, &tda827x_cfg_0); 1062 if (configure_tda827x_fe(dev, &lifeview_trio_config,
1063 &tda827x_cfg_0) < 0)
1064 goto dettach_frontend;
1045 } else { /* satellite */ 1065 } else { /* satellite */
1046 dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap); 1066 dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap);
1047 if (dev->dvb.frontend) { 1067 if (dev->dvb.frontend) {
1048 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x63, 1068 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x63,
1049 &dev->i2c_adap, 0) == NULL) { 1069 &dev->i2c_adap, 0) == NULL) {
1050 wprintk("%s: Lifeview Trio, No tda826x found!\n", __func__); 1070 wprintk("%s: Lifeview Trio, No tda826x found!\n", __func__);
1071 goto dettach_frontend;
1051 } 1072 }
1052 if (dvb_attach(isl6421_attach, dev->dvb.frontend, &dev->i2c_adap, 1073 if (dvb_attach(isl6421_attach, dev->dvb.frontend, &dev->i2c_adap,
1053 0x08, 0, 0) == NULL) { 1074 0x08, 0, 0) == NULL) {
1054 wprintk("%s: Lifeview Trio, No ISL6421 found!\n", __func__); 1075 wprintk("%s: Lifeview Trio, No ISL6421 found!\n", __func__);
1076 goto dettach_frontend;
1055 } 1077 }
1056 } 1078 }
1057 } 1079 }
@@ -1067,15 +1089,20 @@ static int dvb_init(struct saa7134_dev *dev)
1067 &ads_duo_cfg) == NULL) { 1089 &ads_duo_cfg) == NULL) {
1068 wprintk("no tda827x tuner found at addr: %02x\n", 1090 wprintk("no tda827x tuner found at addr: %02x\n",
1069 ads_tech_duo_config.tuner_address); 1091 ads_tech_duo_config.tuner_address);
1092 goto dettach_frontend;
1070 } 1093 }
1071 } 1094 }
1072 break; 1095 break;
1073 case SAA7134_BOARD_TEVION_DVBT_220RF: 1096 case SAA7134_BOARD_TEVION_DVBT_220RF:
1074 configure_tda827x_fe(dev, &tevion_dvbt220rf_config, &tda827x_cfg_0); 1097 if (configure_tda827x_fe(dev, &tevion_dvbt220rf_config,
1098 &tda827x_cfg_0) < 0)
1099 goto dettach_frontend;
1075 break; 1100 break;
1076 case SAA7134_BOARD_MEDION_MD8800_QUADRO: 1101 case SAA7134_BOARD_MEDION_MD8800_QUADRO:
1077 if (!use_frontend) { /* terrestrial */ 1102 if (!use_frontend) { /* terrestrial */
1078 configure_tda827x_fe(dev, &md8800_dvbt_config, &tda827x_cfg_0); 1103 if (configure_tda827x_fe(dev, &md8800_dvbt_config,
1104 &tda827x_cfg_0) < 0)
1105 goto dettach_frontend;
1079 } else { /* satellite */ 1106 } else { /* satellite */
1080 dev->dvb.frontend = dvb_attach(tda10086_attach, 1107 dev->dvb.frontend = dvb_attach(tda10086_attach,
1081 &flydvbs, &dev->i2c_adap); 1108 &flydvbs, &dev->i2c_adap);
@@ -1086,16 +1113,20 @@ static int dvb_init(struct saa7134_dev *dev)
1086 struct i2c_msg msg = {.addr = 0x08, .flags = 0, .len = 1}; 1113 struct i2c_msg msg = {.addr = 0x08, .flags = 0, .len = 1};
1087 1114
1088 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 1115 if (dvb_attach(tda826x_attach, dev->dvb.frontend,
1089 0x60, &dev->i2c_adap, 0) == NULL) 1116 0x60, &dev->i2c_adap, 0) == NULL) {
1090 wprintk("%s: Medion Quadro, no tda826x " 1117 wprintk("%s: Medion Quadro, no tda826x "
1091 "found !\n", __func__); 1118 "found !\n", __func__);
1119 goto dettach_frontend;
1120 }
1092 if (dev_id != 0x08) { 1121 if (dev_id != 0x08) {
1093 /* we need to open the i2c gate (we know it exists) */ 1122 /* we need to open the i2c gate (we know it exists) */
1094 fe->ops.i2c_gate_ctrl(fe, 1); 1123 fe->ops.i2c_gate_ctrl(fe, 1);
1095 if (dvb_attach(isl6405_attach, fe, 1124 if (dvb_attach(isl6405_attach, fe,
1096 &dev->i2c_adap, 0x08, 0, 0) == NULL) 1125 &dev->i2c_adap, 0x08, 0, 0) == NULL) {
1097 wprintk("%s: Medion Quadro, no ISL6405 " 1126 wprintk("%s: Medion Quadro, no ISL6405 "
1098 "found !\n", __func__); 1127 "found !\n", __func__);
1128 goto dettach_frontend;
1129 }
1099 if (dev_id == 0x07) { 1130 if (dev_id == 0x07) {
1100 /* fire up the 2nd section of the LNB supply since 1131 /* fire up the 2nd section of the LNB supply since
1101 we can't do this from the other section */ 1132 we can't do this from the other section */
@@ -1117,19 +1148,17 @@ static int dvb_init(struct saa7134_dev *dev)
1117 case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180: 1148 case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180:
1118 dev->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180, 1149 dev->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180,
1119 &dev->i2c_adap); 1150 &dev->i2c_adap);
1120 if (dev->dvb.frontend) { 1151 if (dev->dvb.frontend)
1121 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, 1152 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
1122 NULL, DVB_PLL_TDHU2); 1153 NULL, DVB_PLL_TDHU2);
1123 }
1124 break; 1154 break;
1125 case SAA7134_BOARD_KWORLD_ATSC110: 1155 case SAA7134_BOARD_KWORLD_ATSC110:
1126 dev->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110, 1156 dev->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110,
1127 &dev->i2c_adap); 1157 &dev->i2c_adap);
1128 if (dev->dvb.frontend) { 1158 if (dev->dvb.frontend)
1129 dvb_attach(simple_tuner_attach, dev->dvb.frontend, 1159 dvb_attach(simple_tuner_attach, dev->dvb.frontend,
1130 &dev->i2c_adap, 0x61, 1160 &dev->i2c_adap, 0x61,
1131 TUNER_PHILIPS_TUV1236D); 1161 TUNER_PHILIPS_TUV1236D);
1132 }
1133 break; 1162 break;
1134 case SAA7134_BOARD_FLYDVBS_LR300: 1163 case SAA7134_BOARD_FLYDVBS_LR300:
1135 dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, 1164 dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs,
@@ -1138,10 +1167,12 @@ static int dvb_init(struct saa7134_dev *dev)
1138 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60, 1167 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60,
1139 &dev->i2c_adap, 0) == NULL) { 1168 &dev->i2c_adap, 0) == NULL) {
1140 wprintk("%s: No tda826x found!\n", __func__); 1169 wprintk("%s: No tda826x found!\n", __func__);
1170 goto dettach_frontend;
1141 } 1171 }
1142 if (dvb_attach(isl6421_attach, dev->dvb.frontend, 1172 if (dvb_attach(isl6421_attach, dev->dvb.frontend,
1143 &dev->i2c_adap, 0x08, 0, 0) == NULL) { 1173 &dev->i2c_adap, 0x08, 0, 0) == NULL) {
1144 wprintk("%s: No ISL6421 found!\n", __func__); 1174 wprintk("%s: No ISL6421 found!\n", __func__);
1175 goto dettach_frontend;
1145 } 1176 }
1146 } 1177 }
1147 break; 1178 break;
@@ -1168,43 +1199,65 @@ static int dvb_init(struct saa7134_dev *dev)
1168 } 1199 }
1169 break; 1200 break;
1170 case SAA7134_BOARD_CINERGY_HT_PCMCIA: 1201 case SAA7134_BOARD_CINERGY_HT_PCMCIA:
1171 configure_tda827x_fe(dev, &cinergy_ht_config, &tda827x_cfg_0); 1202 if (configure_tda827x_fe(dev, &cinergy_ht_config,
1203 &tda827x_cfg_0) < 0)
1204 goto dettach_frontend;
1172 break; 1205 break;
1173 case SAA7134_BOARD_CINERGY_HT_PCI: 1206 case SAA7134_BOARD_CINERGY_HT_PCI:
1174 configure_tda827x_fe(dev, &cinergy_ht_pci_config, &tda827x_cfg_0); 1207 if (configure_tda827x_fe(dev, &cinergy_ht_pci_config,
1208 &tda827x_cfg_0) < 0)
1209 goto dettach_frontend;
1175 break; 1210 break;
1176 case SAA7134_BOARD_PHILIPS_TIGER_S: 1211 case SAA7134_BOARD_PHILIPS_TIGER_S:
1177 configure_tda827x_fe(dev, &philips_tiger_s_config, &tda827x_cfg_2); 1212 if (configure_tda827x_fe(dev, &philips_tiger_s_config,
1213 &tda827x_cfg_2) < 0)
1214 goto dettach_frontend;
1178 break; 1215 break;
1179 case SAA7134_BOARD_ASUS_P7131_4871: 1216 case SAA7134_BOARD_ASUS_P7131_4871:
1180 configure_tda827x_fe(dev, &asus_p7131_4871_config, &tda827x_cfg_2); 1217 if (configure_tda827x_fe(dev, &asus_p7131_4871_config,
1218 &tda827x_cfg_2) < 0)
1219 goto dettach_frontend;
1181 break; 1220 break;
1182 case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA: 1221 case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA:
1183 configure_tda827x_fe(dev, &asus_p7131_hybrid_lna_config, &tda827x_cfg_2); 1222 if (configure_tda827x_fe(dev, &asus_p7131_hybrid_lna_config,
1223 &tda827x_cfg_2) < 0)
1224 goto dettach_frontend;
1184 break; 1225 break;
1185 case SAA7134_BOARD_AVERMEDIA_SUPER_007: 1226 case SAA7134_BOARD_AVERMEDIA_SUPER_007:
1186 configure_tda827x_fe(dev, &avermedia_super_007_config, &tda827x_cfg_0); 1227 if (configure_tda827x_fe(dev, &avermedia_super_007_config,
1228 &tda827x_cfg_0) < 0)
1229 goto dettach_frontend;
1187 break; 1230 break;
1188 case SAA7134_BOARD_TWINHAN_DTV_DVB_3056: 1231 case SAA7134_BOARD_TWINHAN_DTV_DVB_3056:
1189 configure_tda827x_fe(dev, &twinhan_dtv_dvb_3056_config, &tda827x_cfg_2_sw42); 1232 if (configure_tda827x_fe(dev, &twinhan_dtv_dvb_3056_config,
1233 &tda827x_cfg_2_sw42) < 0)
1234 goto dettach_frontend;
1190 break; 1235 break;
1191 case SAA7134_BOARD_PHILIPS_SNAKE: 1236 case SAA7134_BOARD_PHILIPS_SNAKE:
1192 dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, 1237 dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs,
1193 &dev->i2c_adap); 1238 &dev->i2c_adap);
1194 if (dev->dvb.frontend) { 1239 if (dev->dvb.frontend) {
1195 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60, 1240 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60,
1196 &dev->i2c_adap, 0) == NULL) 1241 &dev->i2c_adap, 0) == NULL) {
1197 wprintk("%s: No tda826x found!\n", __func__); 1242 wprintk("%s: No tda826x found!\n", __func__);
1243 goto dettach_frontend;
1244 }
1198 if (dvb_attach(lnbp21_attach, dev->dvb.frontend, 1245 if (dvb_attach(lnbp21_attach, dev->dvb.frontend,
1199 &dev->i2c_adap, 0, 0) == NULL) 1246 &dev->i2c_adap, 0, 0) == NULL) {
1200 wprintk("%s: No lnbp21 found!\n", __func__); 1247 wprintk("%s: No lnbp21 found!\n", __func__);
1248 goto dettach_frontend;
1249 }
1201 } 1250 }
1202 break; 1251 break;
1203 case SAA7134_BOARD_CREATIX_CTX953: 1252 case SAA7134_BOARD_CREATIX_CTX953:
1204 configure_tda827x_fe(dev, &md8800_dvbt_config, &tda827x_cfg_0); 1253 if (configure_tda827x_fe(dev, &md8800_dvbt_config,
1254 &tda827x_cfg_0) < 0)
1255 goto dettach_frontend;
1205 break; 1256 break;
1206 case SAA7134_BOARD_MSI_TVANYWHERE_AD11: 1257 case SAA7134_BOARD_MSI_TVANYWHERE_AD11:
1207 configure_tda827x_fe(dev, &philips_tiger_s_config, &tda827x_cfg_2); 1258 if (configure_tda827x_fe(dev, &philips_tiger_s_config,
1259 &tda827x_cfg_2) < 0)
1260 goto dettach_frontend;
1208 break; 1261 break;
1209 case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: 1262 case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
1210 dev->dvb.frontend = dvb_attach(mt352_attach, 1263 dev->dvb.frontend = dvb_attach(mt352_attach,
@@ -1218,16 +1271,20 @@ static int dvb_init(struct saa7134_dev *dev)
1218 if (dev->dvb.frontend) { 1271 if (dev->dvb.frontend) {
1219 struct dvb_frontend *fe; 1272 struct dvb_frontend *fe;
1220 if (dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, 1273 if (dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
1221 &dev->i2c_adap, DVB_PLL_PHILIPS_SD1878_TDA8261) == NULL) 1274 &dev->i2c_adap, DVB_PLL_PHILIPS_SD1878_TDA8261) == NULL) {
1222 wprintk("%s: MD7134 DVB-S, no SD1878 " 1275 wprintk("%s: MD7134 DVB-S, no SD1878 "
1223 "found !\n", __func__); 1276 "found !\n", __func__);
1277 goto dettach_frontend;
1278 }
1224 /* we need to open the i2c gate (we know it exists) */ 1279 /* we need to open the i2c gate (we know it exists) */
1225 fe = dev->dvb.frontend; 1280 fe = dev->dvb.frontend;
1226 fe->ops.i2c_gate_ctrl(fe, 1); 1281 fe->ops.i2c_gate_ctrl(fe, 1);
1227 if (dvb_attach(isl6405_attach, fe, 1282 if (dvb_attach(isl6405_attach, fe,
1228 &dev->i2c_adap, 0x08, 0, 0) == NULL) 1283 &dev->i2c_adap, 0x08, 0, 0) == NULL) {
1229 wprintk("%s: MD7134 DVB-S, no ISL6405 " 1284 wprintk("%s: MD7134 DVB-S, no ISL6405 "
1230 "found !\n", __func__); 1285 "found !\n", __func__);
1286 goto dettach_frontend;
1287 }
1231 fe->ops.i2c_gate_ctrl(fe, 0); 1288 fe->ops.i2c_gate_ctrl(fe, 0);
1232 dev->original_set_voltage = fe->ops.set_voltage; 1289 dev->original_set_voltage = fe->ops.set_voltage;
1233 fe->ops.set_voltage = md8800_set_voltage; 1290 fe->ops.set_voltage = md8800_set_voltage;
@@ -1254,10 +1311,7 @@ static int dvb_init(struct saa7134_dev *dev)
1254 if (!fe) { 1311 if (!fe) {
1255 printk(KERN_ERR "%s/2: xc3028 attach failed\n", 1312 printk(KERN_ERR "%s/2: xc3028 attach failed\n",
1256 dev->name); 1313 dev->name);
1257 dvb_frontend_detach(dev->dvb.frontend); 1314 goto dettach_frontend;
1258 dvb_unregister_frontend(dev->dvb.frontend);
1259 dev->dvb.frontend = NULL;
1260 return -1;
1261 } 1315 }
1262 } 1316 }
1263 1317
@@ -1282,6 +1336,12 @@ static int dvb_init(struct saa7134_dev *dev)
1282 dev->dvb.frontend->ops.tuner_ops.sleep(dev->dvb.frontend); 1336 dev->dvb.frontend->ops.tuner_ops.sleep(dev->dvb.frontend);
1283 } 1337 }
1284 return ret; 1338 return ret;
1339
1340dettach_frontend:
1341 dvb_frontend_detach(dev->dvb.frontend);
1342 dev->dvb.frontend = NULL;
1343
1344 return -1;
1285} 1345}
1286 1346
1287static int dvb_fini(struct saa7134_dev *dev) 1347static int dvb_fini(struct saa7134_dev *dev)
diff --git a/drivers/media/video/stk-webcam.c b/drivers/media/video/stk-webcam.c
index 9276ed997388..b12c60cf5a09 100644
--- a/drivers/media/video/stk-webcam.c
+++ b/drivers/media/video/stk-webcam.c
@@ -30,6 +30,7 @@
30#include <linux/kref.h> 30#include <linux/kref.h>
31 31
32#include <linux/usb.h> 32#include <linux/usb.h>
33#include <linux/mm.h>
33#include <linux/vmalloc.h> 34#include <linux/vmalloc.h>
34#include <linux/videodev2.h> 35#include <linux/videodev2.h>
35#include <media/v4l2-common.h> 36#include <media/v4l2-common.h>
@@ -245,6 +246,8 @@ static int stk_initialise(struct stk_camera *dev)
245 return -1; 246 return -1;
246} 247}
247 248
249#ifdef CONFIG_VIDEO_V4L1_COMPAT
250
248/* sysfs functions */ 251/* sysfs functions */
249/*FIXME cleanup this */ 252/*FIXME cleanup this */
250 253
@@ -350,6 +353,10 @@ static void stk_remove_sysfs_files(struct video_device *vdev)
350 video_device_remove_file(vdev, &dev_attr_vflip); 353 video_device_remove_file(vdev, &dev_attr_vflip);
351} 354}
352 355
356#else
357#define stk_create_sysfs_files(a)
358#define stk_remove_sysfs_files(a)
359#endif
353 360
354/* *********************************************** */ 361/* *********************************************** */
355/* 362/*
diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c
index 6bf104ea051d..5a75788b92ae 100644
--- a/drivers/media/video/tuner-core.c
+++ b/drivers/media/video/tuner-core.c
@@ -40,11 +40,11 @@
40 typeof(&FUNCTION) __a = symbol_request(FUNCTION); \ 40 typeof(&FUNCTION) __a = symbol_request(FUNCTION); \
41 if (__a) { \ 41 if (__a) { \
42 __r = (int) __a(ARGS); \ 42 __r = (int) __a(ARGS); \
43 symbol_put(FUNCTION); \
43 } else { \ 44 } else { \
44 printk(KERN_ERR "TUNER: Unable to find " \ 45 printk(KERN_ERR "TUNER: Unable to find " \
45 "symbol "#FUNCTION"()\n"); \ 46 "symbol "#FUNCTION"()\n"); \
46 } \ 47 } \
47 symbol_put(FUNCTION); \
48 __r; \ 48 __r; \
49}) 49})
50 50
@@ -340,16 +340,6 @@ static void tuner_i2c_address_check(struct tuner *t)
340 tuner_warn("====================== WARNING! ======================\n"); 340 tuner_warn("====================== WARNING! ======================\n");
341} 341}
342 342
343static void attach_tda829x(struct tuner *t)
344{
345 struct tda829x_config cfg = {
346 .lna_cfg = t->config,
347 .tuner_callback = t->tuner_callback,
348 };
349 dvb_attach(tda829x_attach,
350 &t->fe, t->i2c->adapter, t->i2c->addr, &cfg);
351}
352
353static struct xc5000_config xc5000_cfg; 343static struct xc5000_config xc5000_cfg;
354 344
355static void set_type(struct i2c_client *c, unsigned int type, 345static void set_type(struct i2c_client *c, unsigned int type,
@@ -385,12 +375,19 @@ static void set_type(struct i2c_client *c, unsigned int type,
385 375
386 switch (t->type) { 376 switch (t->type) {
387 case TUNER_MT2032: 377 case TUNER_MT2032:
388 dvb_attach(microtune_attach, 378 if (!dvb_attach(microtune_attach,
389 &t->fe, t->i2c->adapter, t->i2c->addr); 379 &t->fe, t->i2c->adapter, t->i2c->addr))
380 goto attach_failed;
390 break; 381 break;
391 case TUNER_PHILIPS_TDA8290: 382 case TUNER_PHILIPS_TDA8290:
392 { 383 {
393 attach_tda829x(t); 384 struct tda829x_config cfg = {
385 .lna_cfg = t->config,
386 .tuner_callback = t->tuner_callback,
387 };
388 if (!dvb_attach(tda829x_attach, &t->fe, t->i2c->adapter,
389 t->i2c->addr, &cfg))
390 goto attach_failed;
394 break; 391 break;
395 } 392 }
396 case TUNER_TEA5767: 393 case TUNER_TEA5767:
@@ -441,8 +438,9 @@ static void set_type(struct i2c_client *c, unsigned int type,
441 break; 438 break;
442 } 439 }
443 case TUNER_TDA9887: 440 case TUNER_TDA9887:
444 dvb_attach(tda9887_attach, 441 if (!dvb_attach(tda9887_attach,
445 &t->fe, t->i2c->adapter, t->i2c->addr); 442 &t->fe, t->i2c->adapter, t->i2c->addr))
443 goto attach_failed;
446 break; 444 break;
447 case TUNER_XC5000: 445 case TUNER_XC5000:
448 { 446 {
@@ -450,10 +448,10 @@ static void set_type(struct i2c_client *c, unsigned int type,
450 448
451 xc5000_cfg.i2c_address = t->i2c->addr; 449 xc5000_cfg.i2c_address = t->i2c->addr;
452 xc5000_cfg.if_khz = 5380; 450 xc5000_cfg.if_khz = 5380;
453 xc5000_cfg.priv = c->adapter->algo_data;
454 xc5000_cfg.tuner_callback = t->tuner_callback; 451 xc5000_cfg.tuner_callback = t->tuner_callback;
455 if (!dvb_attach(xc5000_attach, 452 if (!dvb_attach(xc5000_attach,
456 &t->fe, t->i2c->adapter, &xc5000_cfg)) 453 &t->fe, t->i2c->adapter, &xc5000_cfg,
454 c->adapter->algo_data))
457 goto attach_failed; 455 goto attach_failed;
458 456
459 xc_tuner_ops = &t->fe.ops.tuner_ops; 457 xc_tuner_ops = &t->fe.ops.tuner_ops;
@@ -1167,7 +1165,7 @@ static int tuner_probe(struct i2c_client *client,
1167 /* If chip is not tda8290, don't register. 1165 /* If chip is not tda8290, don't register.
1168 since it can be tda9887*/ 1166 since it can be tda9887*/
1169 if (tuner_symbol_probe(tda829x_probe, t->i2c->adapter, 1167 if (tuner_symbol_probe(tda829x_probe, t->i2c->adapter,
1170 t->i2c->addr) == 0) { 1168 t->i2c->addr) >= 0) {
1171 tuner_dbg("tda829x detected\n"); 1169 tuner_dbg("tda829x detected\n");
1172 } else { 1170 } else {
1173 /* Default is being tda9887 */ 1171 /* Default is being tda9887 */
@@ -1181,7 +1179,7 @@ static int tuner_probe(struct i2c_client *client,
1181 case 0x60: 1179 case 0x60:
1182 if (tuner_symbol_probe(tea5767_autodetection, 1180 if (tuner_symbol_probe(tea5767_autodetection,
1183 t->i2c->adapter, t->i2c->addr) 1181 t->i2c->adapter, t->i2c->addr)
1184 != EINVAL) { 1182 >= 0) {
1185 t->type = TUNER_TEA5767; 1183 t->type = TUNER_TEA5767;
1186 t->mode_mask = T_RADIO; 1184 t->mode_mask = T_RADIO;
1187 t->mode = T_STANDBY; 1185 t->mode = T_STANDBY;
diff --git a/drivers/media/video/tveeprom.c b/drivers/media/video/tveeprom.c
index 3cf8a8e801e5..9da0e1807ffb 100644
--- a/drivers/media/video/tveeprom.c
+++ b/drivers/media/video/tveeprom.c
@@ -319,10 +319,12 @@ audioIC[] =
319 {AUDIO_CHIP_INTERNAL, "CX25843"}, 319 {AUDIO_CHIP_INTERNAL, "CX25843"},
320 {AUDIO_CHIP_INTERNAL, "CX23418"}, 320 {AUDIO_CHIP_INTERNAL, "CX23418"},
321 {AUDIO_CHIP_INTERNAL, "CX23885"}, 321 {AUDIO_CHIP_INTERNAL, "CX23885"},
322 /* 40-42 */ 322 /* 40-44 */
323 {AUDIO_CHIP_INTERNAL, "CX23888"}, 323 {AUDIO_CHIP_INTERNAL, "CX23888"},
324 {AUDIO_CHIP_INTERNAL, "SAA7131"}, 324 {AUDIO_CHIP_INTERNAL, "SAA7131"},
325 {AUDIO_CHIP_INTERNAL, "CX23887"}, 325 {AUDIO_CHIP_INTERNAL, "CX23887"},
326 {AUDIO_CHIP_INTERNAL, "SAA7164"},
327 {AUDIO_CHIP_INTERNAL, "AU8522"},
326}; 328};
327 329
328/* This list is supplied by Hauppauge. Thanks! */ 330/* This list is supplied by Hauppauge. Thanks! */
@@ -341,8 +343,10 @@ static const char *decoderIC[] = {
341 "CX882", "TVP5150A", "CX25840", "CX25841", "CX25842", 343 "CX882", "TVP5150A", "CX25840", "CX25841", "CX25842",
342 /* 30-34 */ 344 /* 30-34 */
343 "CX25843", "CX23418", "NEC61153", "CX23885", "CX23888", 345 "CX25843", "CX23418", "NEC61153", "CX23885", "CX23888",
344 /* 35-37 */ 346 /* 35-39 */
345 "SAA7131", "CX25837", "CX23887" 347 "SAA7131", "CX25837", "CX23887", "CX23885A", "CX23887A",
348 /* 40-42 */
349 "SAA7164", "CX23885B", "AU8522"
346}; 350};
347 351
348static int hasRadioTuner(int tunerType) 352static int hasRadioTuner(int tunerType)
diff --git a/drivers/media/video/usbvision/Kconfig b/drivers/media/video/usbvision/Kconfig
index 74e1d3075a20..fc24ef05b3f3 100644
--- a/drivers/media/video/usbvision/Kconfig
+++ b/drivers/media/video/usbvision/Kconfig
@@ -1,7 +1,7 @@
1config VIDEO_USBVISION 1config VIDEO_USBVISION
2 tristate "USB video devices based on Nogatech NT1003/1004/1005" 2 tristate "USB video devices based on Nogatech NT1003/1004/1005"
3 depends on I2C && VIDEO_V4L2 3 depends on I2C && VIDEO_V4L2
4 select MEDIA_TUNER 4 select VIDEO_TUNER
5 select VIDEO_SAA711X if VIDEO_HELPER_CHIPS_AUTO 5 select VIDEO_SAA711X if VIDEO_HELPER_CHIPS_AUTO
6 ---help--- 6 ---help---
7 There are more than 50 different USB video devices based on 7 There are more than 50 different USB video devices based on
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 06:20:56 -0500