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authorAlex Deucher <alexdeucher@gmail.com>2009-08-04 11:24:24 -0400
committerDave Airlie <airlied@redhat.com>2009-08-04 22:07:09 -0400
commit6502fbfaf81b09b3f474bb7b3796257e9450273e (patch)
treef8b61e7d368d2251977ce36ecbda299bcf98e3b2 /drivers
parent90bc1a658a53f8832ee799685703977a450e5af9 (diff)
drm/radeon: Add support for RS880 chips
These are new AMD IGP chips Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c22
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h1
2 files changed, 16 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 146f3570af8e..20f17908b036 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -384,8 +384,9 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
384 DRM_INFO("Loading RV670 PFP Microcode\n"); 384 DRM_INFO("Loading RV670 PFP Microcode\n");
385 for (i = 0; i < PFP_UCODE_SIZE; i++) 385 for (i = 0; i < PFP_UCODE_SIZE; i++)
386 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); 386 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
388 DRM_INFO("Loading RS780 CP Microcode\n"); 388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
389 DRM_INFO("Loading RS780/RS880 CP Microcode\n");
389 for (i = 0; i < PM4_UCODE_SIZE; i++) { 390 for (i = 0; i < PM4_UCODE_SIZE; i++) {
390 RADEON_WRITE(R600_CP_ME_RAM_DATA, 391 RADEON_WRITE(R600_CP_ME_RAM_DATA,
391 RS780_cp_microcode[i][0]); 392 RS780_cp_microcode[i][0]);
@@ -396,7 +397,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
396 } 397 }
397 398
398 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 399 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
399 DRM_INFO("Loading RS780 PFP Microcode\n"); 400 DRM_INFO("Loading RS780/RS880 PFP Microcode\n");
400 for (i = 0; i < PFP_UCODE_SIZE; i++) 401 for (i = 0; i < PFP_UCODE_SIZE; i++)
401 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]); 402 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
402 } 403 }
@@ -783,6 +784,7 @@ static void r600_gfx_init(struct drm_device *dev,
783 break; 784 break;
784 case CHIP_RV610: 785 case CHIP_RV610:
785 case CHIP_RS780: 786 case CHIP_RS780:
787 case CHIP_RS880:
786 case CHIP_RV620: 788 case CHIP_RV620:
787 dev_priv->r600_max_pipes = 1; 789 dev_priv->r600_max_pipes = 1;
788 dev_priv->r600_max_tile_pipes = 1; 790 dev_priv->r600_max_tile_pipes = 1;
@@ -917,7 +919,8 @@ static void r600_gfx_init(struct drm_device *dev,
917 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
918 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 922 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
921 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 924 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
922 else 925 else
923 RADEON_WRITE(R600_DB_DEBUG, 0); 926 RADEON_WRITE(R600_DB_DEBUG, 0);
@@ -935,7 +938,8 @@ static void r600_gfx_init(struct drm_device *dev,
935 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 938 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
936 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 939 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
937 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 940 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
938 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 941 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
942 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
939 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 943 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
940 R600_FETCH_FIFO_HIWATER(0xa) | 944 R600_FETCH_FIFO_HIWATER(0xa) |
941 R600_DONE_FIFO_HIWATER(0xe0) | 945 R600_DONE_FIFO_HIWATER(0xe0) |
@@ -978,7 +982,8 @@ static void r600_gfx_init(struct drm_device *dev,
978 R600_NUM_ES_STACK_ENTRIES(0)); 982 R600_NUM_ES_STACK_ENTRIES(0));
979 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 983 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
980 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 984 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
981 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 985 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
986 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
982 /* no vertex cache */ 987 /* no vertex cache */
983 sq_config &= ~R600_VC_ENABLE; 988 sq_config &= ~R600_VC_ENABLE;
984 989
@@ -1035,7 +1040,8 @@ static void r600_gfx_init(struct drm_device *dev,
1035 1040
1036 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1041 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1037 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1042 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1038 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 1043 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1044 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1039 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1045 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1040 else 1046 else
1041 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1047 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
@@ -1078,6 +1084,7 @@ static void r600_gfx_init(struct drm_device *dev,
1078 break; 1084 break;
1079 case CHIP_RV610: 1085 case CHIP_RV610:
1080 case CHIP_RS780: 1086 case CHIP_RS780:
1087 case CHIP_RS880:
1081 case CHIP_RV620: 1088 case CHIP_RV620:
1082 gs_prim_buffer_depth = 32; 1089 gs_prim_buffer_depth = 32;
1083 break; 1090 break;
@@ -1123,6 +1130,7 @@ static void r600_gfx_init(struct drm_device *dev,
1123 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1130 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1124 case CHIP_RV610: 1131 case CHIP_RV610:
1125 case CHIP_RS780: 1132 case CHIP_RS780:
1133 case CHIP_RS880:
1126 case CHIP_RV620: 1134 case CHIP_RV620:
1127 tc_cntl = R600_TC_L2_SIZE(8); 1135 tc_cntl = R600_TC_L2_SIZE(8);
1128 break; 1136 break;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 127d0456f628..3933f8216a34 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -143,6 +143,7 @@ enum radeon_family {
143 CHIP_RV635, 143 CHIP_RV635,
144 CHIP_RV670, 144 CHIP_RV670,
145 CHIP_RS780, 145 CHIP_RS780,
146 CHIP_RS880,
146 CHIP_RV770, 147 CHIP_RV770,
147 CHIP_RV730, 148 CHIP_RV730,
148 CHIP_RV710, 149 CHIP_RV710,