diff options
author | Paul Mundt <lethal@linux-sh.org> | 2007-11-06 21:05:32 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2007-11-06 21:13:55 -0500 |
commit | f96691872439ab2071171d4531c4a95b5d493ae5 (patch) | |
tree | 340a0a5faa7429e9cb579417f8da78b0d6f6aaa2 /drivers | |
parent | 07782cec9b444746859855fc310f20f254e995a0 (diff) |
sh: Kill off the remaining ST40 cruft.
The ST40 stuff in-tree hasn't built for some time, and hasn't been
updated for over 3 years. ST maintains their own out-of-tree changes
and rebases occasionally, and that's ultimately where all of the ST40
users go anyways.
In order for the ST40 code to be brought up to date most of the stuff
removed in this changeset would have to be rewritten anyways, so there's
very little benefit in keeping the remnants around either.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/serial/sh-sci.h | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index e89ae29645d6..207aeb50db65 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -102,12 +102,6 @@ | |||
102 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 102 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
103 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 103 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
104 | # define SCIF_ONLY | 104 | # define SCIF_ONLY |
105 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | ||
106 | # define SCSPTR1 0xffe00020 /* 16 bit SCIF */ | ||
107 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | ||
108 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
109 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
110 | # define SCIF_ONLY | ||
111 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 105 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
112 | # include <asm/hardware.h> | 106 | # include <asm/hardware.h> |
113 | # define SCIF_BASE_ADDR 0x01030000 | 107 | # define SCIF_BASE_ADDR 0x01030000 |
@@ -116,8 +110,7 @@ | |||
116 | # define SCIF_LSR2_OFFS 0x0000024 | 110 | # define SCIF_LSR2_OFFS 0x0000024 |
117 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ | 111 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
118 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | 112 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ |
119 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, | 113 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
120 | TE=1,RE=1,REIE=1 */ | ||
121 | # define SCIF_ONLY | 114 | # define SCIF_ONLY |
122 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | 115 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
123 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 116 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
@@ -577,15 +570,6 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
577 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | 570 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ |
578 | return 1; | 571 | return 1; |
579 | } | 572 | } |
580 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | ||
581 | static inline int sci_rxd_in(struct uart_port *port) | ||
582 | { | ||
583 | if (port->mapbase == 0xffe00000) | ||
584 | return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */ | ||
585 | else | ||
586 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | ||
587 | |||
588 | } | ||
589 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 573 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
590 | static inline int sci_rxd_in(struct uart_port *port) | 574 | static inline int sci_rxd_in(struct uart_port *port) |
591 | { | 575 | { |