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authorEliezer Tamir <eliezert@broadcom.com>2008-02-28 14:49:42 -0500
committerDavid S. Miller <davem@davemloft.net>2008-02-28 14:49:42 -0500
commitc14423fe585a5937db6e2eece4b79486521103be (patch)
treee1a158f10f92def85b1992706d167d5a4bc730af /drivers
parent21e43188f272c7fd9efc84b8244c0b1dfccaa105 (diff)
[BNX2X]: Spelling fixes
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x.c119
-rw-r--r--drivers/net/bnx2x.h2
2 files changed, 56 insertions, 65 deletions
diff --git a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c
index afc7f34b1dcf..7b2d7898f06d 100644
--- a/drivers/net/bnx2x.c
+++ b/drivers/net/bnx2x.c
@@ -10,13 +10,13 @@
10 * Based on code from Michael Chan's bnx2 driver 10 * Based on code from Michael Chan's bnx2 driver
11 * UDP CSUM errata workaround by Arik Gendelman 11 * UDP CSUM errata workaround by Arik Gendelman
12 * Slowpath rework by Vladislav Zolotarov 12 * Slowpath rework by Vladislav Zolotarov
13 * Statistics and Link managment by Yitchak Gertner 13 * Statistics and Link management by Yitchak Gertner
14 * 14 *
15 */ 15 */
16 16
17/* define this to make the driver freeze on error 17/* define this to make the driver freeze on error
18 * to allow getting debug info 18 * to allow getting debug info
19 * (you will need to reboot afterwords) 19 * (you will need to reboot afterwards)
20 */ 20 */
21/*#define BNX2X_STOP_ON_ERROR*/ 21/*#define BNX2X_STOP_ON_ERROR*/
22 22
@@ -71,7 +71,7 @@
71#define TX_TIMEOUT (5*HZ) 71#define TX_TIMEOUT (5*HZ)
72 72
73static char version[] __devinitdata = 73static char version[] __devinitdata =
74 "Broadcom NetXtreme II 577xx 10Gigabit Ethernet Driver " 74 "Broadcom NetXtreme II 5771X 10Gigabit Ethernet Driver "
75 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 75 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76 76
77MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com>"); 77MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com>");
@@ -94,8 +94,8 @@ module_param(debug, int, 0);
94MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); 94MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
95MODULE_PARM_DESC(poll, "use polling (for debug)"); 95MODULE_PARM_DESC(poll, "use polling (for debug)");
96MODULE_PARM_DESC(onefunc, "enable only first function"); 96MODULE_PARM_DESC(onefunc, "enable only first function");
97MODULE_PARM_DESC(nomcp, "ignore managment CPU (Implies onefunc)"); 97MODULE_PARM_DESC(nomcp, "ignore management CPU (Implies onefunc)");
98MODULE_PARM_DESC(debug, "defualt debug msglevel"); 98MODULE_PARM_DESC(debug, "default debug msglevel");
99 99
100#ifdef BNX2X_MULTI 100#ifdef BNX2X_MULTI
101module_param(use_multi, int, 0); 101module_param(use_multi, int, 0);
@@ -341,6 +341,7 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
341 } 341 }
342 return rc; 342 return rc;
343} 343}
344
344static void bnx2x_fw_dump(struct bnx2x *bp) 345static void bnx2x_fw_dump(struct bnx2x *bp)
345{ 346{
346 u32 mark, offset; 347 u32 mark, offset;
@@ -491,7 +492,7 @@ static void bnx2x_disable_int_sync(struct bnx2x *bp)
491 int i; 492 int i;
492 493
493 atomic_inc(&bp->intr_sem); 494 atomic_inc(&bp->intr_sem);
494 /* prevent the HW from sending interrupts*/ 495 /* prevent the HW from sending interrupts */
495 bnx2x_disable_int(bp); 496 bnx2x_disable_int(bp);
496 497
497 /* make sure all ISRs are done */ 498 /* make sure all ISRs are done */
@@ -775,6 +776,7 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
775 mb(); /* force bnx2x_wait_ramrod to see the change */ 776 mb(); /* force bnx2x_wait_ramrod to see the change */
776 return; 777 return;
777 } 778 }
779
778 switch (command | bp->state) { 780 switch (command | bp->state) {
779 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT): 781 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
780 DP(NETIF_MSG_IFUP, "got setup ramrod\n"); 782 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
@@ -1471,7 +1473,7 @@ static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 reg, u32 addr, u32 val)
1471} 1473}
1472 1474
1473/* 1475/*
1474 * link managment 1476 * link management
1475 */ 1477 */
1476 1478
1477static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status) 1479static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
@@ -1482,7 +1484,7 @@ static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
1482 1484
1483 bp->flow_ctrl = 0; 1485 bp->flow_ctrl = 0;
1484 1486
1485 /* reolve from gp_status in case of AN complete and not sgmii */ 1487 /* resolve from gp_status in case of AN complete and not sgmii */
1486 if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) && 1488 if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
1487 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 1489 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1488 (!(bp->phy_flags & PHY_SGMII_FLAG)) && 1490 (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
@@ -1680,7 +1682,7 @@ static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
1680 int port = bp->port; 1682 int port = bp->port;
1681 1683
1682 /* first reset all status 1684 /* first reset all status
1683 * we asume only one line will be change at a time */ 1685 * we assume only one line will be change at a time */
1684 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 1686 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1685 (NIG_XGXS0_LINK_STATUS | 1687 (NIG_XGXS0_LINK_STATUS |
1686 NIG_SERDES0_LINK_STATUS | 1688 NIG_SERDES0_LINK_STATUS |
@@ -1819,7 +1821,7 @@ static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb)
1819 u32 wb_write[2]; 1821 u32 wb_write[2];
1820 u32 val; 1822 u32 val;
1821 1823
1822 DP(NETIF_MSG_LINK, "enableing BigMAC\n"); 1824 DP(NETIF_MSG_LINK, "enabling BigMAC\n");
1823 /* reset and unreset the BigMac */ 1825 /* reset and unreset the BigMac */
1824 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1826 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1825 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1827 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
@@ -1940,7 +1942,7 @@ static void bnx2x_emac_enable(struct bnx2x *bp)
1940 u32 val; 1942 u32 val;
1941 int timeout; 1943 int timeout;
1942 1944
1943 DP(NETIF_MSG_LINK, "enableing EMAC\n"); 1945 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1944 /* reset and unreset the emac core */ 1946 /* reset and unreset the emac core */
1945 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1947 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1946 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1948 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
@@ -2033,7 +2035,7 @@ static void bnx2x_emac_enable(struct bnx2x *bp)
2033 EMAC_TX_MODE_EXT_PAUSE_EN); 2035 EMAC_TX_MODE_EXT_PAUSE_EN);
2034 } 2036 }
2035 2037
2036 /* KEEP_VLAN_TAG, promiscous */ 2038 /* KEEP_VLAN_TAG, promiscuous */
2037 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 2039 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
2038 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 2040 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2039 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val); 2041 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
@@ -2161,7 +2163,6 @@ static void bnx2x_pbf_update(struct bnx2x *bp)
2161 u32 count = 1000; 2163 u32 count = 1000;
2162 u32 pause = 0; 2164 u32 pause = 0;
2163 2165
2164
2165 /* disable port */ 2166 /* disable port */
2166 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2167 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2167 2168
@@ -2803,7 +2804,7 @@ static void bnx2x_ext_phy_init(struct bnx2x *bp)
2803 bnx2x_bits_en(bp, 2804 bnx2x_bits_en(bp,
2804 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 2805 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2805 NIG_MASK_MI_INT); 2806 NIG_MASK_MI_INT);
2806 DP(NETIF_MSG_LINK, "enabled extenal phy int\n"); 2807 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2807 2808
2808 bp->phy_addr = ext_phy_type; 2809 bp->phy_addr = ext_phy_type;
2809 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, 2810 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
@@ -2824,7 +2825,7 @@ static void bnx2x_ext_phy_init(struct bnx2x *bp)
2824 bnx2x_bits_en(bp, 2825 bnx2x_bits_en(bp,
2825 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 2826 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2826 NIG_MASK_MI_INT); 2827 NIG_MASK_MI_INT);
2827 DP(NETIF_MSG_LINK, "enabled extenal phy int\n"); 2828 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2828 2829
2829 bp->phy_addr = ext_phy_type; 2830 bp->phy_addr = ext_phy_type;
2830 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, 2831 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
@@ -2857,7 +2858,7 @@ static void bnx2x_ext_phy_init(struct bnx2x *bp)
2857 bnx2x_bits_en(bp, 2858 bnx2x_bits_en(bp,
2858 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 2859 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2859 NIG_MASK_MI_INT); 2860 NIG_MASK_MI_INT);
2860 DP(NETIF_MSG_LINK, "enabled extenal phy int\n"); 2861 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2861 break; 2862 break;
2862 2863
2863 default: 2864 default:
@@ -2994,13 +2995,13 @@ static void bnx2x_link_initialize(struct bnx2x *bp)
2994 /* AN enabled */ 2995 /* AN enabled */
2995 bnx2x_set_brcm_cl37_advertisment(bp); 2996 bnx2x_set_brcm_cl37_advertisment(bp);
2996 2997
2997 /* program duplex & pause advertisment (for aneg) */ 2998 /* program duplex & pause advertisement (for aneg) */
2998 bnx2x_set_ieee_aneg_advertisment(bp); 2999 bnx2x_set_ieee_aneg_advertisment(bp);
2999 3000
3000 /* enable autoneg */ 3001 /* enable autoneg */
3001 bnx2x_set_autoneg(bp); 3002 bnx2x_set_autoneg(bp);
3002 3003
3003 /* enalbe and restart AN */ 3004 /* enable and restart AN */
3004 bnx2x_restart_autoneg(bp); 3005 bnx2x_restart_autoneg(bp);
3005 } 3006 }
3006 3007
@@ -3158,7 +3159,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3158 int port = bp->port; 3159 int port = bp->port;
3159 3160
3160 DP(NETIF_MSG_TIMER, 3161 DP(NETIF_MSG_TIMER,
3161 "spe (%x:%x) command %x hw_cid %x data (%x:%x) left %x\n", 3162 "spe (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n",
3162 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) + 3163 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
3163 (void *)bp->spq_prod_bd - (void *)bp->spq), command, 3164 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
3164 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left); 3165 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
@@ -3464,7 +3465,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3464 HW_PRTY_ASSERT_SET_1) || 3465 HW_PRTY_ASSERT_SET_1) ||
3465 (attn.sig[2] & group_mask.sig[2] & 3466 (attn.sig[2] & group_mask.sig[2] &
3466 HW_PRTY_ASSERT_SET_2)) 3467 HW_PRTY_ASSERT_SET_2))
3467 BNX2X_ERR("FATAL HW block parity atention\n"); 3468 BNX2X_ERR("FATAL HW block parity attention\n");
3468 } 3469 }
3469 } 3470 }
3470 3471
@@ -3906,7 +3907,7 @@ static void bnx2x_stop_stats(struct bnx2x *bp)
3906 3907
3907 while (bp->stats_state != STATS_STATE_DISABLE) { 3908 while (bp->stats_state != STATS_STATE_DISABLE) {
3908 if (!timeout) { 3909 if (!timeout) {
3909 BNX2X_ERR("timeout wating for stats stop\n"); 3910 BNX2X_ERR("timeout waiting for stats stop\n");
3910 break; 3911 break;
3911 } 3912 }
3912 timeout--; 3913 timeout--;
@@ -4626,7 +4627,7 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
4626 fp->rx_bd_prod = fp->rx_comp_prod = ring_prod; 4627 fp->rx_bd_prod = fp->rx_comp_prod = ring_prod;
4627 fp->rx_pkt = fp->rx_calls = 0; 4628 fp->rx_pkt = fp->rx_calls = 0;
4628 4629
4629 /* Warning! this will genrate an interrupt (to the TSTORM) */ 4630 /* Warning! this will generate an interrupt (to the TSTORM) */
4630 /* must only be done when chip is initialized */ 4631 /* must only be done when chip is initialized */
4631 REG_WR(bp, BAR_TSTRORM_INTMEM + 4632 REG_WR(bp, BAR_TSTRORM_INTMEM +
4632 TSTORM_RCQ_PROD_OFFSET(port, j), ring_prod); 4633 TSTORM_RCQ_PROD_OFFSET(port, j), ring_prod);
@@ -4850,7 +4851,7 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4850/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n", 4851/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n",
4851 (*(u32 *)&tstorm_config)); */ 4852 (*(u32 *)&tstorm_config)); */
4852 4853
4853 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx untill link is up */ 4854 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4854 bnx2x_set_storm_rx_mode(bp); 4855 bnx2x_set_storm_rx_mode(bp);
4855 4856
4856 for_each_queue(bp, i) 4857 for_each_queue(bp, i)
@@ -5359,7 +5360,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
5359 REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 8); 5360 REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 8);
5360#endif 5361#endif
5361 bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END); 5362 bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5362 /* softrest pulse */ 5363 /* soft reset pulse */
5363 REG_WR(bp, QM_REG_SOFT_RESET, 1); 5364 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5364 REG_WR(bp, QM_REG_SOFT_RESET, 0); 5365 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5365 5366
@@ -5413,7 +5414,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
5413 REG_WR(bp, SRC_REG_SOFT_RST, 1); 5414 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5414 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) { 5415 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5415 REG_WR(bp, i, 0xc0cac01a); 5416 REG_WR(bp, i, 0xc0cac01a);
5416 /* TODO: repleace with something meaningfull */ 5417 /* TODO: replace with something meaningful */
5417 } 5418 }
5418 /* SRCH COMMON comes here */ 5419 /* SRCH COMMON comes here */
5419 REG_WR(bp, SRC_REG_SOFT_RST, 0); 5420 REG_WR(bp, SRC_REG_SOFT_RST, 0);
@@ -5647,7 +5648,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
5647 5648
5648 bnx2x_link_reset(bp); 5649 bnx2x_link_reset(bp);
5649 5650
5650 /* Reset pciex errors for debug */ 5651 /* Reset PCIE errors for debug */
5651 REG_WR(bp, 0x2114, 0xffffffff); 5652 REG_WR(bp, 0x2114, 0xffffffff);
5652 REG_WR(bp, 0x2120, 0xffffffff); 5653 REG_WR(bp, 0x2120, 0xffffffff);
5653 REG_WR(bp, 0x2814, 0xffffffff); 5654 REG_WR(bp, 0x2814, 0xffffffff);
@@ -5681,8 +5682,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
5681 return 0; 5682 return 0;
5682} 5683}
5683 5684
5684 5685/* send the MCP a request, block until there is a reply */
5685/* send the MCP a request, block untill there is a reply */
5686static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) 5686static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5687{ 5687{
5688 u32 rc = 0; 5688 u32 rc = 0;
@@ -5869,7 +5869,7 @@ static int bnx2x_alloc_mem(struct bnx2x *bp)
5869 for (i = 0; i < 16*1024; i += 64) 5869 for (i = 0; i < 16*1024; i += 64)
5870 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64; 5870 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
5871 5871
5872 /* now sixup the last line in the block to point to the next block */ 5872 /* now fixup the last line in the block to point to the next block */
5873 *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping; 5873 *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
5874 5874
5875 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */ 5875 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
@@ -5950,11 +5950,11 @@ static void bnx2x_free_msix_irqs(struct bnx2x *bp)
5950 int i; 5950 int i;
5951 5951
5952 free_irq(bp->msix_table[0].vector, bp->dev); 5952 free_irq(bp->msix_table[0].vector, bp->dev);
5953 DP(NETIF_MSG_IFDOWN, "rleased sp irq (%d)\n", 5953 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
5954 bp->msix_table[0].vector); 5954 bp->msix_table[0].vector);
5955 5955
5956 for_each_queue(bp, i) { 5956 for_each_queue(bp, i) {
5957 DP(NETIF_MSG_IFDOWN, "about to rlease fp #%d->%d irq " 5957 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq "
5958 "state(%x)\n", i, bp->msix_table[i + 1].vector, 5958 "state(%x)\n", i, bp->msix_table[i + 1].vector,
5959 bnx2x_fp(bp, i, state)); 5959 bnx2x_fp(bp, i, state));
5960 5960
@@ -6010,7 +6010,6 @@ static int bnx2x_enable_msix(struct bnx2x *bp)
6010static int bnx2x_req_msix_irqs(struct bnx2x *bp) 6010static int bnx2x_req_msix_irqs(struct bnx2x *bp)
6011{ 6011{
6012 6012
6013
6014 int i, rc; 6013 int i, rc;
6015 6014
6016 DP(NETIF_MSG_IFUP, "about to request sp irq\n"); 6015 DP(NETIF_MSG_IFUP, "about to request sp irq\n");
@@ -6109,8 +6108,8 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6109 /* can take a while if any port is running */ 6108 /* can take a while if any port is running */
6110 int timeout = 500; 6109 int timeout = 500;
6111 6110
6112 /* DP("waiting for state to become %d on IDX [%d]\n", 6111 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6113 state, sb_idx); */ 6112 poll ? "polling" : "waiting", state, idx);
6114 6113
6115 might_sleep(); 6114 might_sleep();
6116 6115
@@ -6136,7 +6135,6 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6136 6135
6137 } 6136 }
6138 6137
6139
6140 /* timeout! */ 6138 /* timeout! */
6141 BNX2X_ERR("timeout waiting for ramrod %d on %d\n", state, idx); 6139 BNX2X_ERR("timeout waiting for ramrod %d on %d\n", state, idx);
6142 return -EBUSY; 6140 return -EBUSY;
@@ -6146,7 +6144,7 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6146static int bnx2x_setup_leading(struct bnx2x *bp) 6144static int bnx2x_setup_leading(struct bnx2x *bp)
6147{ 6145{
6148 6146
6149 /* reset IGU staae */ 6147 /* reset IGU state */
6150 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, 0, IGU_INT_ENABLE, 0); 6148 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6151 6149
6152 /* SETUP ramrod */ 6150 /* SETUP ramrod */
@@ -6196,18 +6194,15 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
6196 rc = FW_MSG_CODE_DRV_LOAD_COMMON; 6194 rc = FW_MSG_CODE_DRV_LOAD_COMMON;
6197 } 6195 }
6198 6196
6199 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", bp->num_queues);
6200
6201 /* if we can't use msix we only need one fp, 6197 /* if we can't use msix we only need one fp,
6202 * so try to enable msix with the requested number of fp's 6198 * so try to enable msix with the requested number of fp's
6203 * and fallback to inta with one fp 6199 * and fallback to inta with one fp
6204 */ 6200 */
6205 if (req_irq) { 6201 if (req_irq) {
6206
6207 if (use_inta) { 6202 if (use_inta) {
6208 bp->num_queues = 1; 6203 bp->num_queues = 1;
6209 } else { 6204 } else {
6210 if (use_multi > 1 && use_multi <= 16) 6205 if ((use_multi > 1) && (use_multi <= 16))
6211 /* user requested number */ 6206 /* user requested number */
6212 bp->num_queues = use_multi; 6207 bp->num_queues = use_multi;
6213 else if (use_multi == 1) 6208 else if (use_multi == 1)
@@ -6216,15 +6211,17 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
6216 bp->num_queues = 1; 6211 bp->num_queues = 1;
6217 6212
6218 if (bnx2x_enable_msix(bp)) { 6213 if (bnx2x_enable_msix(bp)) {
6219 /* faild to enable msix */ 6214 /* failed to enable msix */
6220 bp->num_queues = 1; 6215 bp->num_queues = 1;
6221 if (use_multi) 6216 if (use_multi)
6222 BNX2X_ERR("Muti requested but failed" 6217 BNX2X_ERR("Multi requested but failed"
6223 " to enable MSI-X\n"); 6218 " to enable MSI-X\n");
6224 } 6219 }
6225 } 6220 }
6226 } 6221 }
6227 6222
6223 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", bp->num_queues);
6224
6228 if (bnx2x_alloc_mem(bp)) 6225 if (bnx2x_alloc_mem(bp))
6229 return -ENOMEM; 6226 return -ENOMEM;
6230 6227
@@ -6257,12 +6254,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
6257 6254
6258 atomic_set(&bp->intr_sem, 0); 6255 atomic_set(&bp->intr_sem, 0);
6259 6256
6260 /* Reenable SP tasklet */
6261 /*if (bp->sp_task_en) { */
6262 /* tasklet_enable(&bp->sp_task);*/
6263 /*} else { */
6264 /* bp->sp_task_en = 1; */
6265 /*} */
6266 6257
6267 /* Setup NIC internals and enable interrupts */ 6258 /* Setup NIC internals and enable interrupts */
6268 bnx2x_nic_init(bp); 6259 bnx2x_nic_init(bp);
@@ -6401,14 +6392,14 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6401 6392
6402 int rc; 6393 int rc;
6403 6394
6404 /* halt the connnection */ 6395 /* halt the connection */
6405 bp->fp[index].state = BNX2X_FP_STATE_HALTING; 6396 bp->fp[index].state = BNX2X_FP_STATE_HALTING;
6406 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0); 6397 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0);
6407 6398
6408 6399
6409 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index, 6400 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
6410 &(bp->fp[index].state), 1); 6401 &(bp->fp[index].state), 1);
6411 if (rc) /* timout */ 6402 if (rc) /* timeout */
6412 return rc; 6403 return rc;
6413 6404
6414 /* delete cfc entry */ 6405 /* delete cfc entry */
@@ -6423,7 +6414,7 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6423static void bnx2x_stop_leading(struct bnx2x *bp) 6414static void bnx2x_stop_leading(struct bnx2x *bp)
6424{ 6415{
6425 6416
6426 /* if the other port is hadling traffic, 6417 /* if the other port is handling traffic,
6427 this can take a lot of time */ 6418 this can take a lot of time */
6428 int timeout = 500; 6419 int timeout = 500;
6429 6420
@@ -6471,7 +6462,7 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int fre_irq)
6471 msleep(1); 6462 msleep(1);
6472 6463
6473 /* Delete the timer: do it before disabling interrupts, as it 6464 /* Delete the timer: do it before disabling interrupts, as it
6474 may be stil STAT_QUERY ramrod pending after stopping the timer */ 6465 may be still STAT_QUERY ramrod pending after stopping the timer */
6475 del_timer_sync(&bp->timer); 6466 del_timer_sync(&bp->timer);
6476 6467
6477 /* Wait until stat ramrod returns and all SP tasks complete */ 6468 /* Wait until stat ramrod returns and all SP tasks complete */
@@ -6932,7 +6923,7 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp)
6932 6923
6933 val = SHMEM_RD(bp, validity_map[port]); 6924 val = SHMEM_RD(bp, validity_map[port]);
6934 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 6925 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6935 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 6926 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6936 BNX2X_ERR("MCP validity signature bad\n"); 6927 BNX2X_ERR("MCP validity signature bad\n");
6937 6928
6938 bp->fw_seq = (SHMEM_RD(bp, drv_fw_mb[port].drv_mb_header) & 6929 bp->fw_seq = (SHMEM_RD(bp, drv_fw_mb[port].drv_mb_header) &
@@ -7452,13 +7443,13 @@ static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
7452 7443
7453 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 7444 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
7454 DP(NETIF_MSG_NVM, 7445 DP(NETIF_MSG_NVM,
7455 "Invalid paramter: offset 0x%x buf_size 0x%x\n", 7446 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
7456 offset, buf_size); 7447 offset, buf_size);
7457 return -EINVAL; 7448 return -EINVAL;
7458 } 7449 }
7459 7450
7460 if (offset + buf_size > bp->flash_size) { 7451 if (offset + buf_size > bp->flash_size) {
7461 DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +" 7452 DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +"
7462 " buf_size (0x%x) > flash_size (0x%x)\n", 7453 " buf_size (0x%x) > flash_size (0x%x)\n",
7463 offset, buf_size, bp->flash_size); 7454 offset, buf_size, bp->flash_size);
7464 return -EINVAL; 7455 return -EINVAL;
@@ -7568,7 +7559,7 @@ static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
7568 u32 val; 7559 u32 val;
7569 7560
7570 if (offset + buf_size > bp->flash_size) { 7561 if (offset + buf_size > bp->flash_size) {
7571 DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +" 7562 DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +"
7572 " buf_size (0x%x) > flash_size (0x%x)\n", 7563 " buf_size (0x%x) > flash_size (0x%x)\n",
7573 offset, buf_size, bp->flash_size); 7564 offset, buf_size, bp->flash_size);
7574 return -EINVAL; 7565 return -EINVAL;
@@ -7621,13 +7612,13 @@ static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
7621 7612
7622 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 7613 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
7623 DP(NETIF_MSG_NVM, 7614 DP(NETIF_MSG_NVM,
7624 "Invalid paramter: offset 0x%x buf_size 0x%x\n", 7615 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
7625 offset, buf_size); 7616 offset, buf_size);
7626 return -EINVAL; 7617 return -EINVAL;
7627 } 7618 }
7628 7619
7629 if (offset + buf_size > bp->flash_size) { 7620 if (offset + buf_size > bp->flash_size) {
7630 DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +" 7621 DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +"
7631 " buf_size (0x%x) > flash_size (0x%x)\n", 7622 " buf_size (0x%x) > flash_size (0x%x)\n",
7632 offset, buf_size, bp->flash_size); 7623 offset, buf_size, bp->flash_size);
7633 return -EINVAL; 7624 return -EINVAL;
@@ -8314,7 +8305,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
8314 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT); 8305 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
8315 tx_bd->general_data |= 1; /* header nbd */ 8306 tx_bd->general_data |= 1; /* header nbd */
8316 8307
8317 /* remeber the first bd of the packet */ 8308 /* remember the first bd of the packet */
8318 tx_buf->first_bd = bd_prod; 8309 tx_buf->first_bd = bd_prod;
8319 8310
8320 DP(NETIF_MSG_TX_QUEUED, 8311 DP(NETIF_MSG_TX_QUEUED,
@@ -8427,7 +8418,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
8427 tx_bd->vlan = cpu_to_le16(pkt_prod); 8418 tx_bd->vlan = cpu_to_le16(pkt_prod);
8428 /* this marks the bd 8419 /* this marks the bd
8429 * as one that has no individual mapping 8420 * as one that has no individual mapping
8430 * the FW ignors this flag in a bd not maked start 8421 * the FW ignores this flag in a bd not marked start
8431 */ 8422 */
8432 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO; 8423 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
8433 DP(NETIF_MSG_TX_QUEUED, 8424 DP(NETIF_MSG_TX_QUEUED,
@@ -8584,7 +8575,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8584 case SIOCGMIIPHY: 8575 case SIOCGMIIPHY:
8585 data->phy_id = bp->phy_addr; 8576 data->phy_id = bp->phy_addr;
8586 8577
8587 /* fallthru */ 8578 /* fallthrough */
8588 case SIOCGMIIREG: { 8579 case SIOCGMIIREG: {
8589 u32 mii_regval; 8580 u32 mii_regval;
8590 8581
@@ -8633,7 +8624,7 @@ static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
8633 return -EINVAL; 8624 return -EINVAL;
8634 8625
8635 /* This does not race with packet allocation 8626 /* This does not race with packet allocation
8636 * because the actuall alloc size is 8627 * because the actual alloc size is
8637 * only updated as part of load 8628 * only updated as part of load
8638 */ 8629 */
8639 dev->mtu = new_mtu; 8630 dev->mtu = new_mtu;
@@ -8813,7 +8804,7 @@ static int __devinit bnx2x_init_board(struct pci_dev *pdev,
8813 bnx2x_get_hwinfo(bp); 8804 bnx2x_get_hwinfo(bp);
8814 8805
8815 if (CHIP_REV(bp) == CHIP_REV_FPGA) { 8806 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
8816 printk(KERN_ERR PFX "FPGA detacted. MCP disabled," 8807 printk(KERN_ERR PFX "FPGA detected. MCP disabled,"
8817 " will only init first device\n"); 8808 " will only init first device\n");
8818 onefunc = 1; 8809 onefunc = 1;
8819 nomcp = 1; 8810 nomcp = 1;
@@ -8944,7 +8935,7 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
8944 8935
8945 rc = register_netdev(dev); 8936 rc = register_netdev(dev);
8946 if (rc) { 8937 if (rc) {
8947 printk(KERN_ERR PFX "Cannot register net device\n"); 8938 dev_err(&pdev->dev, "Cannot register net device\n");
8948 if (bp->regview) 8939 if (bp->regview)
8949 iounmap(bp->regview); 8940 iounmap(bp->regview);
8950 if (bp->doorbells) 8941 if (bp->doorbells)
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 4f7ae6f77452..7a01668e3978 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -517,7 +517,7 @@ struct bnx2x {
517 */ 517 */
518 u8 stat_pending; 518 u8 stat_pending;
519 519
520 /* End of fileds used in the performance code paths */ 520 /* End of fields used in the performance code paths */
521 521
522 int panic; 522 int panic;
523 int msglevel; 523 int msglevel;