diff options
| author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2011-03-25 08:42:26 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2011-05-20 06:26:24 -0400 |
| commit | be9297d130835082587ef95cc83825871146e840 (patch) | |
| tree | 6099710faefc9330932e6a2bff6489f406eed23d /drivers | |
| parent | 6cacdd46e23826c0591238f5f11b1bfa6490797d (diff) | |
[media] drxd_map_firm.h: make checkpatch.pl happier
s/(define\s+[^\s]+)\s........../\1/
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/media/dvb/frontends/drxd_map_firm.h | 25322 |
1 files changed, 12661 insertions, 12661 deletions
diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h index c9fbb459b20f..160323a4f932 100644 --- a/drivers/media/dvb/frontends/drxd_map_firm.h +++ b/drivers/media/dvb/frontends/drxd_map_firm.h | |||
| @@ -24,12671 +24,12671 @@ | |||
| 24 | #ifndef __DRX3973D_MAP__H__ | 24 | #ifndef __DRX3973D_MAP__H__ |
| 25 | #define __DRX3973D_MAP__H__ | 25 | #define __DRX3973D_MAP__H__ |
| 26 | 26 | ||
| 27 | #define HI_SID 0x10 | 27 | #define HI_SID 0x10 |
| 28 | 28 | ||
| 29 | #define HI_COMM_EXEC__A 0x400000 | 29 | #define HI_COMM_EXEC__A 0x400000 |
| 30 | #define HI_COMM_EXEC__W 3 | 30 | #define HI_COMM_EXEC__W 3 |
| 31 | #define HI_COMM_EXEC__M 0x7 | 31 | #define HI_COMM_EXEC__M 0x7 |
| 32 | #define HI_COMM_EXEC_CTL__B 0 | 32 | #define HI_COMM_EXEC_CTL__B 0 |
| 33 | #define HI_COMM_EXEC_CTL__W 3 | 33 | #define HI_COMM_EXEC_CTL__W 3 |
| 34 | #define HI_COMM_EXEC_CTL__M 0x7 | 34 | #define HI_COMM_EXEC_CTL__M 0x7 |
| 35 | #define HI_COMM_EXEC_CTL_STOP 0x0 | 35 | #define HI_COMM_EXEC_CTL_STOP 0x0 |
| 36 | #define HI_COMM_EXEC_CTL_ACTIVE 0x1 | 36 | #define HI_COMM_EXEC_CTL_ACTIVE 0x1 |
| 37 | #define HI_COMM_EXEC_CTL_HOLD 0x2 | 37 | #define HI_COMM_EXEC_CTL_HOLD 0x2 |
| 38 | #define HI_COMM_EXEC_CTL_STEP 0x3 | 38 | #define HI_COMM_EXEC_CTL_STEP 0x3 |
| 39 | #define HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 39 | #define HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 40 | #define HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 40 | #define HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 41 | 41 | ||
| 42 | #define HI_COMM_STATE__A 0x400001 | 42 | #define HI_COMM_STATE__A 0x400001 |
| 43 | #define HI_COMM_STATE__W 16 | 43 | #define HI_COMM_STATE__W 16 |
| 44 | #define HI_COMM_STATE__M 0xFFFF | 44 | #define HI_COMM_STATE__M 0xFFFF |
| 45 | #define HI_COMM_MB__A 0x400002 | 45 | #define HI_COMM_MB__A 0x400002 |
| 46 | #define HI_COMM_MB__W 16 | 46 | #define HI_COMM_MB__W 16 |
| 47 | #define HI_COMM_MB__M 0xFFFF | 47 | #define HI_COMM_MB__M 0xFFFF |
| 48 | #define HI_COMM_SERVICE0__A 0x400003 | 48 | #define HI_COMM_SERVICE0__A 0x400003 |
| 49 | #define HI_COMM_SERVICE0__W 16 | 49 | #define HI_COMM_SERVICE0__W 16 |
| 50 | #define HI_COMM_SERVICE0__M 0xFFFF | 50 | #define HI_COMM_SERVICE0__M 0xFFFF |
| 51 | #define HI_COMM_SERVICE1__A 0x400004 | 51 | #define HI_COMM_SERVICE1__A 0x400004 |
| 52 | #define HI_COMM_SERVICE1__W 16 | 52 | #define HI_COMM_SERVICE1__W 16 |
| 53 | #define HI_COMM_SERVICE1__M 0xFFFF | 53 | #define HI_COMM_SERVICE1__M 0xFFFF |
| 54 | #define HI_COMM_INT_STA__A 0x400007 | 54 | #define HI_COMM_INT_STA__A 0x400007 |
| 55 | #define HI_COMM_INT_STA__W 16 | 55 | #define HI_COMM_INT_STA__W 16 |
| 56 | #define HI_COMM_INT_STA__M 0xFFFF | 56 | #define HI_COMM_INT_STA__M 0xFFFF |
| 57 | #define HI_COMM_INT_MSK__A 0x400008 | 57 | #define HI_COMM_INT_MSK__A 0x400008 |
| 58 | #define HI_COMM_INT_MSK__W 16 | 58 | #define HI_COMM_INT_MSK__W 16 |
| 59 | #define HI_COMM_INT_MSK__M 0xFFFF | 59 | #define HI_COMM_INT_MSK__M 0xFFFF |
| 60 | 60 | ||
| 61 | #define HI_CT_REG_COMM_EXEC__A 0x410000 | 61 | #define HI_CT_REG_COMM_EXEC__A 0x410000 |
| 62 | #define HI_CT_REG_COMM_EXEC__W 3 | 62 | #define HI_CT_REG_COMM_EXEC__W 3 |
| 63 | #define HI_CT_REG_COMM_EXEC__M 0x7 | 63 | #define HI_CT_REG_COMM_EXEC__M 0x7 |
| 64 | #define HI_CT_REG_COMM_EXEC_CTL__B 0 | 64 | #define HI_CT_REG_COMM_EXEC_CTL__B 0 |
| 65 | #define HI_CT_REG_COMM_EXEC_CTL__W 3 | 65 | #define HI_CT_REG_COMM_EXEC_CTL__W 3 |
| 66 | #define HI_CT_REG_COMM_EXEC_CTL__M 0x7 | 66 | #define HI_CT_REG_COMM_EXEC_CTL__M 0x7 |
| 67 | #define HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 | 67 | #define HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 68 | #define HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 68 | #define HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 69 | #define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 | 69 | #define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 70 | #define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 | 70 | #define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 71 | 71 | ||
| 72 | #define HI_CT_REG_COMM_STATE__A 0x410001 | 72 | #define HI_CT_REG_COMM_STATE__A 0x410001 |
| 73 | #define HI_CT_REG_COMM_STATE__W 10 | 73 | #define HI_CT_REG_COMM_STATE__W 10 |
| 74 | #define HI_CT_REG_COMM_STATE__M 0x3FF | 74 | #define HI_CT_REG_COMM_STATE__M 0x3FF |
| 75 | #define HI_CT_REG_COMM_SERVICE0__A 0x410003 | 75 | #define HI_CT_REG_COMM_SERVICE0__A 0x410003 |
| 76 | #define HI_CT_REG_COMM_SERVICE0__W 16 | 76 | #define HI_CT_REG_COMM_SERVICE0__W 16 |
| 77 | #define HI_CT_REG_COMM_SERVICE0__M 0xFFFF | 77 | #define HI_CT_REG_COMM_SERVICE0__M 0xFFFF |
| 78 | #define HI_CT_REG_COMM_SERVICE1__A 0x410004 | 78 | #define HI_CT_REG_COMM_SERVICE1__A 0x410004 |
| 79 | #define HI_CT_REG_COMM_SERVICE1__W 16 | 79 | #define HI_CT_REG_COMM_SERVICE1__W 16 |
| 80 | #define HI_CT_REG_COMM_SERVICE1__M 0xFFFF | 80 | #define HI_CT_REG_COMM_SERVICE1__M 0xFFFF |
| 81 | #define HI_CT_REG_COMM_SERVICE1_HI__B 0 | 81 | #define HI_CT_REG_COMM_SERVICE1_HI__B 0 |
| 82 | #define HI_CT_REG_COMM_SERVICE1_HI__W 1 | 82 | #define HI_CT_REG_COMM_SERVICE1_HI__W 1 |
| 83 | #define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 | 83 | #define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 |
| 84 | 84 | ||
| 85 | #define HI_CT_REG_COMM_INT_STA__A 0x410007 | 85 | #define HI_CT_REG_COMM_INT_STA__A 0x410007 |
| 86 | #define HI_CT_REG_COMM_INT_STA__W 1 | 86 | #define HI_CT_REG_COMM_INT_STA__W 1 |
| 87 | #define HI_CT_REG_COMM_INT_STA__M 0x1 | 87 | #define HI_CT_REG_COMM_INT_STA__M 0x1 |
| 88 | #define HI_CT_REG_COMM_INT_STA_REQUEST__B 0 | 88 | #define HI_CT_REG_COMM_INT_STA_REQUEST__B 0 |
| 89 | #define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 | 89 | #define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 |
| 90 | #define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 | 90 | #define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 |
| 91 | 91 | ||
| 92 | #define HI_CT_REG_COMM_INT_MSK__A 0x410008 | 92 | #define HI_CT_REG_COMM_INT_MSK__A 0x410008 |
| 93 | #define HI_CT_REG_COMM_INT_MSK__W 1 | 93 | #define HI_CT_REG_COMM_INT_MSK__W 1 |
| 94 | #define HI_CT_REG_COMM_INT_MSK__M 0x1 | 94 | #define HI_CT_REG_COMM_INT_MSK__M 0x1 |
| 95 | #define HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 | 95 | #define HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 |
| 96 | #define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 | 96 | #define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 |
| 97 | #define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 | 97 | #define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 |
| 98 | 98 | ||
| 99 | #define HI_CT_REG_CTL_STK__AX 0x410010 | 99 | #define HI_CT_REG_CTL_STK__AX 0x410010 |
| 100 | #define HI_CT_REG_CTL_STK__XSZ 4 | 100 | #define HI_CT_REG_CTL_STK__XSZ 4 |
| 101 | #define HI_CT_REG_CTL_STK__W 10 | 101 | #define HI_CT_REG_CTL_STK__W 10 |
| 102 | #define HI_CT_REG_CTL_STK__M 0x3FF | 102 | #define HI_CT_REG_CTL_STK__M 0x3FF |
| 103 | 103 | ||
| 104 | #define HI_CT_REG_CTL_BPT_IDX__A 0x41001F | 104 | #define HI_CT_REG_CTL_BPT_IDX__A 0x41001F |
| 105 | #define HI_CT_REG_CTL_BPT_IDX__W 1 | 105 | #define HI_CT_REG_CTL_BPT_IDX__W 1 |
| 106 | #define HI_CT_REG_CTL_BPT_IDX__M 0x1 | 106 | #define HI_CT_REG_CTL_BPT_IDX__M 0x1 |
| 107 | 107 | ||
| 108 | #define HI_CT_REG_CTL_BPT__A 0x410020 | 108 | #define HI_CT_REG_CTL_BPT__A 0x410020 |
| 109 | #define HI_CT_REG_CTL_BPT__W 10 | 109 | #define HI_CT_REG_CTL_BPT__W 10 |
| 110 | #define HI_CT_REG_CTL_BPT__M 0x3FF | 110 | #define HI_CT_REG_CTL_BPT__M 0x3FF |
| 111 | 111 | ||
| 112 | #define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 | 112 | #define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 |
| 113 | #define HI_RA_RAM_SLV0_FLG_SMM__W 1 | 113 | #define HI_RA_RAM_SLV0_FLG_SMM__W 1 |
| 114 | #define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 | 114 | #define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 |
| 115 | #define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 | 115 | #define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 |
| 116 | #define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 | 116 | #define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 |
| 117 | 117 | ||
| 118 | #define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 | 118 | #define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 |
| 119 | #define HI_RA_RAM_SLV0_DEV_ID__W 7 | 119 | #define HI_RA_RAM_SLV0_DEV_ID__W 7 |
| 120 | #define HI_RA_RAM_SLV0_DEV_ID__M 0x7F | 120 | #define HI_RA_RAM_SLV0_DEV_ID__M 0x7F |
| 121 | 121 | ||
| 122 | #define HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 | 122 | #define HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 |
| 123 | #define HI_RA_RAM_SLV0_FLG_CRC__W 1 | 123 | #define HI_RA_RAM_SLV0_FLG_CRC__W 1 |
| 124 | #define HI_RA_RAM_SLV0_FLG_CRC__M 0x1 | 124 | #define HI_RA_RAM_SLV0_FLG_CRC__M 0x1 |
| 125 | #define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 | 125 | #define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 |
| 126 | #define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 | 126 | #define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 |
| 127 | 127 | ||
| 128 | #define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 | 128 | #define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 |
| 129 | #define HI_RA_RAM_SLV0_FLG_ACC__W 3 | 129 | #define HI_RA_RAM_SLV0_FLG_ACC__W 3 |
| 130 | #define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 | 130 | #define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 |
| 131 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 | 131 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 |
| 132 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 | 132 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 |
| 133 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 | 133 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 |
| 134 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 | 134 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 |
| 135 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 | 135 | #define HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 |
| 136 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 | 136 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 |
| 137 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 | 137 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 |
| 138 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 | 138 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 |
| 139 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 | 139 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 |
| 140 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 | 140 | #define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 |
| 141 | 141 | ||
| 142 | #define HI_RA_RAM_SLV0_STATE__A 0x420014 | 142 | #define HI_RA_RAM_SLV0_STATE__A 0x420014 |
| 143 | #define HI_RA_RAM_SLV0_STATE__W 1 | 143 | #define HI_RA_RAM_SLV0_STATE__W 1 |
| 144 | #define HI_RA_RAM_SLV0_STATE__M 0x1 | 144 | #define HI_RA_RAM_SLV0_STATE__M 0x1 |
| 145 | #define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 | 145 | #define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 |
| 146 | #define HI_RA_RAM_SLV0_STATE_DATA 0x1 | 146 | #define HI_RA_RAM_SLV0_STATE_DATA 0x1 |
| 147 | 147 | ||
| 148 | #define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 | 148 | #define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 |
| 149 | #define HI_RA_RAM_SLV0_BLK_BNK__W 12 | 149 | #define HI_RA_RAM_SLV0_BLK_BNK__W 12 |
| 150 | #define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF | 150 | #define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF |
| 151 | #define HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 | 151 | #define HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 |
| 152 | #define HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 | 152 | #define HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 |
| 153 | #define HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F | 153 | #define HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F |
| 154 | #define HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 | 154 | #define HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 |
| 155 | #define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 | 155 | #define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 |
| 156 | #define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 | 156 | #define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 |
| 157 | 157 | ||
| 158 | #define HI_RA_RAM_SLV0_ADDR__A 0x420016 | 158 | #define HI_RA_RAM_SLV0_ADDR__A 0x420016 |
| 159 | #define HI_RA_RAM_SLV0_ADDR__W 16 | 159 | #define HI_RA_RAM_SLV0_ADDR__W 16 |
| 160 | #define HI_RA_RAM_SLV0_ADDR__M 0xFFFF | 160 | #define HI_RA_RAM_SLV0_ADDR__M 0xFFFF |
| 161 | 161 | ||
| 162 | #define HI_RA_RAM_SLV0_CRC__A 0x420017 | 162 | #define HI_RA_RAM_SLV0_CRC__A 0x420017 |
| 163 | #define HI_RA_RAM_SLV0_CRC__W 16 | 163 | #define HI_RA_RAM_SLV0_CRC__W 16 |
| 164 | #define HI_RA_RAM_SLV0_CRC__M 0xFFFF | 164 | #define HI_RA_RAM_SLV0_CRC__M 0xFFFF |
| 165 | 165 | ||
| 166 | #define HI_RA_RAM_SLV0_READBACK__A 0x420018 | 166 | #define HI_RA_RAM_SLV0_READBACK__A 0x420018 |
| 167 | #define HI_RA_RAM_SLV0_READBACK__W 16 | 167 | #define HI_RA_RAM_SLV0_READBACK__W 16 |
| 168 | #define HI_RA_RAM_SLV0_READBACK__M 0xFFFF | 168 | #define HI_RA_RAM_SLV0_READBACK__M 0xFFFF |
| 169 | 169 | ||
| 170 | #define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 | 170 | #define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 |
| 171 | #define HI_RA_RAM_SLV1_FLG_SMM__W 1 | 171 | #define HI_RA_RAM_SLV1_FLG_SMM__W 1 |
| 172 | #define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 | 172 | #define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 |
| 173 | #define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 | 173 | #define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 |
| 174 | #define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 | 174 | #define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 |
| 175 | 175 | ||
| 176 | #define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 | 176 | #define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 |
| 177 | #define HI_RA_RAM_SLV1_DEV_ID__W 7 | 177 | #define HI_RA_RAM_SLV1_DEV_ID__W 7 |
| 178 | #define HI_RA_RAM_SLV1_DEV_ID__M 0x7F | 178 | #define HI_RA_RAM_SLV1_DEV_ID__M 0x7F |
| 179 | 179 | ||
| 180 | #define HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 | 180 | #define HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 |
| 181 | #define HI_RA_RAM_SLV1_FLG_CRC__W 1 | 181 | #define HI_RA_RAM_SLV1_FLG_CRC__W 1 |
| 182 | #define HI_RA_RAM_SLV1_FLG_CRC__M 0x1 | 182 | #define HI_RA_RAM_SLV1_FLG_CRC__M 0x1 |
| 183 | #define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 | 183 | #define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 |
| 184 | #define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 | 184 | #define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 |
| 185 | 185 | ||
| 186 | #define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 | 186 | #define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 |
| 187 | #define HI_RA_RAM_SLV1_FLG_ACC__W 3 | 187 | #define HI_RA_RAM_SLV1_FLG_ACC__W 3 |
| 188 | #define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 | 188 | #define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 |
| 189 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 | 189 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 |
| 190 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 | 190 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 |
| 191 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 | 191 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 |
| 192 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 | 192 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 |
| 193 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 | 193 | #define HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 |
| 194 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 | 194 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 |
| 195 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 | 195 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 |
| 196 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 | 196 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 |
| 197 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 | 197 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 |
| 198 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 | 198 | #define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 |
| 199 | 199 | ||
| 200 | #define HI_RA_RAM_SLV1_STATE__A 0x420024 | 200 | #define HI_RA_RAM_SLV1_STATE__A 0x420024 |
| 201 | #define HI_RA_RAM_SLV1_STATE__W 1 | 201 | #define HI_RA_RAM_SLV1_STATE__W 1 |
| 202 | #define HI_RA_RAM_SLV1_STATE__M 0x1 | 202 | #define HI_RA_RAM_SLV1_STATE__M 0x1 |
| 203 | #define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 | 203 | #define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 |
| 204 | #define HI_RA_RAM_SLV1_STATE_DATA 0x1 | 204 | #define HI_RA_RAM_SLV1_STATE_DATA 0x1 |
| 205 | 205 | ||
| 206 | #define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 | 206 | #define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 |
| 207 | #define HI_RA_RAM_SLV1_BLK_BNK__W 12 | 207 | #define HI_RA_RAM_SLV1_BLK_BNK__W 12 |
| 208 | #define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF | 208 | #define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF |
| 209 | #define HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 | 209 | #define HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 |
| 210 | #define HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 | 210 | #define HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 |
| 211 | #define HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F | 211 | #define HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F |
| 212 | #define HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 | 212 | #define HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 |
| 213 | #define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 | 213 | #define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 |
| 214 | #define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 | 214 | #define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 |
| 215 | 215 | ||
| 216 | #define HI_RA_RAM_SLV1_ADDR__A 0x420026 | 216 | #define HI_RA_RAM_SLV1_ADDR__A 0x420026 |
| 217 | #define HI_RA_RAM_SLV1_ADDR__W 16 | 217 | #define HI_RA_RAM_SLV1_ADDR__W 16 |
| 218 | #define HI_RA_RAM_SLV1_ADDR__M 0xFFFF | 218 | #define HI_RA_RAM_SLV1_ADDR__M 0xFFFF |
| 219 | 219 | ||
| 220 | #define HI_RA_RAM_SLV1_CRC__A 0x420027 | 220 | #define HI_RA_RAM_SLV1_CRC__A 0x420027 |
| 221 | #define HI_RA_RAM_SLV1_CRC__W 16 | 221 | #define HI_RA_RAM_SLV1_CRC__W 16 |
| 222 | #define HI_RA_RAM_SLV1_CRC__M 0xFFFF | 222 | #define HI_RA_RAM_SLV1_CRC__M 0xFFFF |
| 223 | 223 | ||
| 224 | #define HI_RA_RAM_SLV1_READBACK__A 0x420028 | 224 | #define HI_RA_RAM_SLV1_READBACK__A 0x420028 |
| 225 | #define HI_RA_RAM_SLV1_READBACK__W 16 | 225 | #define HI_RA_RAM_SLV1_READBACK__W 16 |
| 226 | #define HI_RA_RAM_SLV1_READBACK__M 0xFFFF | 226 | #define HI_RA_RAM_SLV1_READBACK__M 0xFFFF |
| 227 | 227 | ||
| 228 | #define HI_RA_RAM_SRV_SEM__A 0x420030 | 228 | #define HI_RA_RAM_SRV_SEM__A 0x420030 |
| 229 | #define HI_RA_RAM_SRV_SEM__W 1 | 229 | #define HI_RA_RAM_SRV_SEM__W 1 |
| 230 | #define HI_RA_RAM_SRV_SEM__M 0x1 | 230 | #define HI_RA_RAM_SRV_SEM__M 0x1 |
| 231 | #define HI_RA_RAM_SRV_SEM_FREE 0x0 | 231 | #define HI_RA_RAM_SRV_SEM_FREE 0x0 |
| 232 | #define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 | 232 | #define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 |
| 233 | 233 | ||
| 234 | #define HI_RA_RAM_SRV_RES__A 0x420031 | 234 | #define HI_RA_RAM_SRV_RES__A 0x420031 |
| 235 | #define HI_RA_RAM_SRV_RES__W 3 | 235 | #define HI_RA_RAM_SRV_RES__W 3 |
| 236 | #define HI_RA_RAM_SRV_RES__M 0x7 | 236 | #define HI_RA_RAM_SRV_RES__M 0x7 |
| 237 | #define HI_RA_RAM_SRV_RES_OK 0x0 | 237 | #define HI_RA_RAM_SRV_RES_OK 0x0 |
| 238 | #define HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 | 238 | #define HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 |
| 239 | #define HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 | 239 | #define HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 |
| 240 | #define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 | 240 | #define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 |
| 241 | #define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 | 241 | #define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 |
| 242 | 242 | ||
| 243 | #define HI_RA_RAM_SRV_CMD__A 0x420032 | 243 | #define HI_RA_RAM_SRV_CMD__A 0x420032 |
| 244 | #define HI_RA_RAM_SRV_CMD__W 3 | 244 | #define HI_RA_RAM_SRV_CMD__W 3 |
| 245 | #define HI_RA_RAM_SRV_CMD__M 0x7 | 245 | #define HI_RA_RAM_SRV_CMD__M 0x7 |
| 246 | #define HI_RA_RAM_SRV_CMD_NULL 0x0 | 246 | #define HI_RA_RAM_SRV_CMD_NULL 0x0 |
| 247 | #define HI_RA_RAM_SRV_CMD_UIO 0x1 | 247 | #define HI_RA_RAM_SRV_CMD_UIO 0x1 |
| 248 | #define HI_RA_RAM_SRV_CMD_RESET 0x2 | 248 | #define HI_RA_RAM_SRV_CMD_RESET 0x2 |
| 249 | #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 | 249 | #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 |
| 250 | #define HI_RA_RAM_SRV_CMD_COPY 0x4 | 250 | #define HI_RA_RAM_SRV_CMD_COPY 0x4 |
| 251 | #define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 | 251 | #define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 |
| 252 | #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 | 252 | #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 |
| 253 | 253 | ||
| 254 | #define HI_RA_RAM_SRV_PAR__AX 0x420033 | 254 | #define HI_RA_RAM_SRV_PAR__AX 0x420033 |
| 255 | #define HI_RA_RAM_SRV_PAR__XSZ 5 | 255 | #define HI_RA_RAM_SRV_PAR__XSZ 5 |
| 256 | #define HI_RA_RAM_SRV_PAR__W 16 | 256 | #define HI_RA_RAM_SRV_PAR__W 16 |
| 257 | #define HI_RA_RAM_SRV_PAR__M 0xFFFF | 257 | #define HI_RA_RAM_SRV_PAR__M 0xFFFF |
| 258 | 258 | ||
| 259 | #define HI_RA_RAM_SRV_NOP_RES__A 0x420031 | 259 | #define HI_RA_RAM_SRV_NOP_RES__A 0x420031 |
| 260 | #define HI_RA_RAM_SRV_NOP_RES__W 3 | 260 | #define HI_RA_RAM_SRV_NOP_RES__W 3 |
| 261 | #define HI_RA_RAM_SRV_NOP_RES__M 0x7 | 261 | #define HI_RA_RAM_SRV_NOP_RES__M 0x7 |
| 262 | #define HI_RA_RAM_SRV_NOP_RES_OK 0x0 | 262 | #define HI_RA_RAM_SRV_NOP_RES_OK 0x0 |
| 263 | #define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 | 263 | #define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 |
| 264 | 264 | ||
| 265 | #define HI_RA_RAM_SRV_UIO_RES__A 0x420031 | 265 | #define HI_RA_RAM_SRV_UIO_RES__A 0x420031 |
| 266 | #define HI_RA_RAM_SRV_UIO_RES__W 3 | 266 | #define HI_RA_RAM_SRV_UIO_RES__W 3 |
| 267 | #define HI_RA_RAM_SRV_UIO_RES__M 0x7 | 267 | #define HI_RA_RAM_SRV_UIO_RES__M 0x7 |
| 268 | #define HI_RA_RAM_SRV_UIO_RES_LO 0x0 | 268 | #define HI_RA_RAM_SRV_UIO_RES_LO 0x0 |
| 269 | #define HI_RA_RAM_SRV_UIO_RES_HI 0x1 | 269 | #define HI_RA_RAM_SRV_UIO_RES_HI 0x1 |
| 270 | 270 | ||
| 271 | #define HI_RA_RAM_SRV_UIO_KEY__A 0x420033 | 271 | #define HI_RA_RAM_SRV_UIO_KEY__A 0x420033 |
| 272 | #define HI_RA_RAM_SRV_UIO_KEY__W 16 | 272 | #define HI_RA_RAM_SRV_UIO_KEY__W 16 |
| 273 | #define HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF | 273 | #define HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF |
| 274 | #define HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 | 274 | #define HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 |
| 275 | 275 | ||
| 276 | #define HI_RA_RAM_SRV_UIO_SEL__A 0x420034 | 276 | #define HI_RA_RAM_SRV_UIO_SEL__A 0x420034 |
| 277 | #define HI_RA_RAM_SRV_UIO_SEL__W 2 | 277 | #define HI_RA_RAM_SRV_UIO_SEL__W 2 |
| 278 | #define HI_RA_RAM_SRV_UIO_SEL__M 0x3 | 278 | #define HI_RA_RAM_SRV_UIO_SEL__M 0x3 |
| 279 | #define HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 | 279 | #define HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 |
| 280 | #define HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 | 280 | #define HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 |
| 281 | 281 | ||
| 282 | #define HI_RA_RAM_SRV_UIO_SET__A 0x420035 | 282 | #define HI_RA_RAM_SRV_UIO_SET__A 0x420035 |
| 283 | #define HI_RA_RAM_SRV_UIO_SET__W 2 | 283 | #define HI_RA_RAM_SRV_UIO_SET__W 2 |
| 284 | #define HI_RA_RAM_SRV_UIO_SET__M 0x3 | 284 | #define HI_RA_RAM_SRV_UIO_SET__M 0x3 |
| 285 | #define HI_RA_RAM_SRV_UIO_SET_OUT__B 0 | 285 | #define HI_RA_RAM_SRV_UIO_SET_OUT__B 0 |
| 286 | #define HI_RA_RAM_SRV_UIO_SET_OUT__W 1 | 286 | #define HI_RA_RAM_SRV_UIO_SET_OUT__W 1 |
| 287 | #define HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 | 287 | #define HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 |
| 288 | #define HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 | 288 | #define HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 |
| 289 | #define HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 | 289 | #define HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 |
| 290 | #define HI_RA_RAM_SRV_UIO_SET_DIR__B 1 | 290 | #define HI_RA_RAM_SRV_UIO_SET_DIR__B 1 |
| 291 | #define HI_RA_RAM_SRV_UIO_SET_DIR__W 1 | 291 | #define HI_RA_RAM_SRV_UIO_SET_DIR__W 1 |
| 292 | #define HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 | 292 | #define HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 |
| 293 | #define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 | 293 | #define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 |
| 294 | #define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 | 294 | #define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 |
| 295 | 295 | ||
| 296 | #define HI_RA_RAM_SRV_RST_RES__A 0x420031 | 296 | #define HI_RA_RAM_SRV_RST_RES__A 0x420031 |
| 297 | #define HI_RA_RAM_SRV_RST_RES__W 1 | 297 | #define HI_RA_RAM_SRV_RST_RES__W 1 |
| 298 | #define HI_RA_RAM_SRV_RST_RES__M 0x1 | 298 | #define HI_RA_RAM_SRV_RST_RES__M 0x1 |
| 299 | #define HI_RA_RAM_SRV_RST_RES_OK 0x0 | 299 | #define HI_RA_RAM_SRV_RST_RES_OK 0x0 |
| 300 | #define HI_RA_RAM_SRV_RST_RES_ERROR 0x1 | 300 | #define HI_RA_RAM_SRV_RST_RES_ERROR 0x1 |
| 301 | 301 | ||
| 302 | #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 | 302 | #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 |
| 303 | #define HI_RA_RAM_SRV_RST_KEY__W 16 | 303 | #define HI_RA_RAM_SRV_RST_KEY__W 16 |
| 304 | #define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF | 304 | #define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF |
| 305 | #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 | 305 | #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 |
| 306 | 306 | ||
| 307 | #define HI_RA_RAM_SRV_CFG_RES__A 0x420031 | 307 | #define HI_RA_RAM_SRV_CFG_RES__A 0x420031 |
| 308 | #define HI_RA_RAM_SRV_CFG_RES__W 1 | 308 | #define HI_RA_RAM_SRV_CFG_RES__W 1 |
| 309 | #define HI_RA_RAM_SRV_CFG_RES__M 0x1 | 309 | #define HI_RA_RAM_SRV_CFG_RES__M 0x1 |
| 310 | #define HI_RA_RAM_SRV_CFG_RES_OK 0x0 | 310 | #define HI_RA_RAM_SRV_CFG_RES_OK 0x0 |
| 311 | #define HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 | 311 | #define HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 |
| 312 | 312 | ||
| 313 | #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 | 313 | #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 |
| 314 | #define HI_RA_RAM_SRV_CFG_KEY__W 16 | 314 | #define HI_RA_RAM_SRV_CFG_KEY__W 16 |
| 315 | #define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF | 315 | #define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF |
| 316 | #define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 | 316 | #define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 |
| 317 | 317 | ||
| 318 | #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 | 318 | #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 |
| 319 | #define HI_RA_RAM_SRV_CFG_DIV__W 5 | 319 | #define HI_RA_RAM_SRV_CFG_DIV__W 5 |
| 320 | #define HI_RA_RAM_SRV_CFG_DIV__M 0x1F | 320 | #define HI_RA_RAM_SRV_CFG_DIV__M 0x1F |
| 321 | 321 | ||
| 322 | #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 | 322 | #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 |
| 323 | #define HI_RA_RAM_SRV_CFG_BDL__W 6 | 323 | #define HI_RA_RAM_SRV_CFG_BDL__W 6 |
| 324 | #define HI_RA_RAM_SRV_CFG_BDL__M 0x3F | 324 | #define HI_RA_RAM_SRV_CFG_BDL__M 0x3F |
| 325 | 325 | ||
| 326 | #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 | 326 | #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 |
| 327 | #define HI_RA_RAM_SRV_CFG_WUP__W 8 | 327 | #define HI_RA_RAM_SRV_CFG_WUP__W 8 |
| 328 | #define HI_RA_RAM_SRV_CFG_WUP__M 0xFF | 328 | #define HI_RA_RAM_SRV_CFG_WUP__M 0xFF |
| 329 | 329 | ||
| 330 | #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 | 330 | #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 |
| 331 | #define HI_RA_RAM_SRV_CFG_ACT__W 4 | 331 | #define HI_RA_RAM_SRV_CFG_ACT__W 4 |
| 332 | #define HI_RA_RAM_SRV_CFG_ACT__M 0xF | 332 | #define HI_RA_RAM_SRV_CFG_ACT__M 0xF |
| 333 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 | 333 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 |
| 334 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 | 334 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 |
| 335 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 | 335 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 |
| 336 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 | 336 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 |
| 337 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 | 337 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 |
| 338 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 | 338 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 |
| 339 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 | 339 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 |
| 340 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 | 340 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 |
| 341 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 | 341 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 |
| 342 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 | 342 | #define HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 |
| 343 | #define HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 | 343 | #define HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 |
| 344 | #define HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 | 344 | #define HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 |
| 345 | #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 | 345 | #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 |
| 346 | #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 | 346 | #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 |
| 347 | #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 | 347 | #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 |
| 348 | #define HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 | 348 | #define HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 |
| 349 | #define HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 | 349 | #define HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 |
| 350 | #define HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 | 350 | #define HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 |
| 351 | #define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 | 351 | #define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 |
| 352 | #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 | 352 | #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 |
| 353 | 353 | ||
| 354 | #define HI_RA_RAM_SRV_CPY_RES__A 0x420031 | 354 | #define HI_RA_RAM_SRV_CPY_RES__A 0x420031 |
| 355 | #define HI_RA_RAM_SRV_CPY_RES__W 1 | 355 | #define HI_RA_RAM_SRV_CPY_RES__W 1 |
| 356 | #define HI_RA_RAM_SRV_CPY_RES__M 0x1 | 356 | #define HI_RA_RAM_SRV_CPY_RES__M 0x1 |
| 357 | #define HI_RA_RAM_SRV_CPY_RES_OK 0x0 | 357 | #define HI_RA_RAM_SRV_CPY_RES_OK 0x0 |
| 358 | #define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 | 358 | #define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 |
| 359 | 359 | ||
| 360 | #define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 | 360 | #define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 |
| 361 | #define HI_RA_RAM_SRV_CPY_SBB__W 12 | 361 | #define HI_RA_RAM_SRV_CPY_SBB__W 12 |
| 362 | #define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF | 362 | #define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF |
| 363 | #define HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 | 363 | #define HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 |
| 364 | #define HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 | 364 | #define HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 |
| 365 | #define HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F | 365 | #define HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F |
| 366 | #define HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 | 366 | #define HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 |
| 367 | #define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 | 367 | #define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 |
| 368 | #define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 | 368 | #define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 |
| 369 | 369 | ||
| 370 | #define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 | 370 | #define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 |
| 371 | #define HI_RA_RAM_SRV_CPY_SAD__W 16 | 371 | #define HI_RA_RAM_SRV_CPY_SAD__W 16 |
| 372 | #define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF | 372 | #define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF |
| 373 | 373 | ||
| 374 | #define HI_RA_RAM_SRV_CPY_LEN__A 0x420035 | 374 | #define HI_RA_RAM_SRV_CPY_LEN__A 0x420035 |
| 375 | #define HI_RA_RAM_SRV_CPY_LEN__W 16 | 375 | #define HI_RA_RAM_SRV_CPY_LEN__W 16 |
| 376 | #define HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF | 376 | #define HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF |
| 377 | 377 | ||
| 378 | #define HI_RA_RAM_SRV_CPY_DBB__A 0x420033 | 378 | #define HI_RA_RAM_SRV_CPY_DBB__A 0x420033 |
| 379 | #define HI_RA_RAM_SRV_CPY_DBB__W 12 | 379 | #define HI_RA_RAM_SRV_CPY_DBB__W 12 |
| 380 | #define HI_RA_RAM_SRV_CPY_DBB__M 0xFFF | 380 | #define HI_RA_RAM_SRV_CPY_DBB__M 0xFFF |
| 381 | #define HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 | 381 | #define HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 |
| 382 | #define HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 | 382 | #define HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 |
| 383 | #define HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F | 383 | #define HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F |
| 384 | #define HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 | 384 | #define HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 |
| 385 | #define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 | 385 | #define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 |
| 386 | #define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 | 386 | #define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 |
| 387 | 387 | ||
| 388 | #define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 | 388 | #define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 |
| 389 | #define HI_RA_RAM_SRV_CPY_DAD__W 16 | 389 | #define HI_RA_RAM_SRV_CPY_DAD__W 16 |
| 390 | #define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF | 390 | #define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF |
| 391 | 391 | ||
| 392 | #define HI_RA_RAM_SRV_TRM_RES__A 0x420031 | 392 | #define HI_RA_RAM_SRV_TRM_RES__A 0x420031 |
| 393 | #define HI_RA_RAM_SRV_TRM_RES__W 2 | 393 | #define HI_RA_RAM_SRV_TRM_RES__W 2 |
| 394 | #define HI_RA_RAM_SRV_TRM_RES__M 0x3 | 394 | #define HI_RA_RAM_SRV_TRM_RES__M 0x3 |
| 395 | #define HI_RA_RAM_SRV_TRM_RES_OK 0x0 | 395 | #define HI_RA_RAM_SRV_TRM_RES_OK 0x0 |
| 396 | #define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 | 396 | #define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 |
| 397 | #define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 | 397 | #define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 |
| 398 | 398 | ||
| 399 | #define HI_RA_RAM_SRV_TRM_MST__A 0x420033 | 399 | #define HI_RA_RAM_SRV_TRM_MST__A 0x420033 |
| 400 | #define HI_RA_RAM_SRV_TRM_MST__W 12 | 400 | #define HI_RA_RAM_SRV_TRM_MST__W 12 |
| 401 | #define HI_RA_RAM_SRV_TRM_MST__M 0xFFF | 401 | #define HI_RA_RAM_SRV_TRM_MST__M 0xFFF |
| 402 | 402 | ||
| 403 | #define HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 | 403 | #define HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 |
| 404 | #define HI_RA_RAM_SRV_TRM_SEQ__W 7 | 404 | #define HI_RA_RAM_SRV_TRM_SEQ__W 7 |
| 405 | #define HI_RA_RAM_SRV_TRM_SEQ__M 0x7F | 405 | #define HI_RA_RAM_SRV_TRM_SEQ__M 0x7F |
| 406 | 406 | ||
| 407 | #define HI_RA_RAM_SRV_TRM_TRM__A 0x420035 | 407 | #define HI_RA_RAM_SRV_TRM_TRM__A 0x420035 |
| 408 | #define HI_RA_RAM_SRV_TRM_TRM__W 15 | 408 | #define HI_RA_RAM_SRV_TRM_TRM__W 15 |
| 409 | #define HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF | 409 | #define HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF |
| 410 | #define HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 | 410 | #define HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 |
| 411 | #define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 | 411 | #define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 |
| 412 | #define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF | 412 | #define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF |
| 413 | 413 | ||
| 414 | #define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 | 414 | #define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 |
| 415 | #define HI_RA_RAM_SRV_TRM_DBB__W 12 | 415 | #define HI_RA_RAM_SRV_TRM_DBB__W 12 |
| 416 | #define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF | 416 | #define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF |
| 417 | #define HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 | 417 | #define HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 |
| 418 | #define HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 | 418 | #define HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 |
| 419 | #define HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F | 419 | #define HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F |
| 420 | #define HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 | 420 | #define HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 |
| 421 | #define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 | 421 | #define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 |
| 422 | #define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 | 422 | #define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 |
| 423 | 423 | ||
| 424 | #define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 | 424 | #define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 |
| 425 | #define HI_RA_RAM_SRV_TRM_DAD__W 16 | 425 | #define HI_RA_RAM_SRV_TRM_DAD__W 16 |
| 426 | #define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF | 426 | #define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF |
| 427 | 427 | ||
| 428 | #define HI_RA_RAM_USR_BEGIN__A 0x420040 | 428 | #define HI_RA_RAM_USR_BEGIN__A 0x420040 |
| 429 | #define HI_RA_RAM_USR_BEGIN__W 16 | 429 | #define HI_RA_RAM_USR_BEGIN__W 16 |
| 430 | #define HI_RA_RAM_USR_BEGIN__M 0xFFFF | 430 | #define HI_RA_RAM_USR_BEGIN__M 0xFFFF |
| 431 | 431 | ||
| 432 | #define HI_RA_RAM_USR_END__A 0x42007F | 432 | #define HI_RA_RAM_USR_END__A 0x42007F |
| 433 | #define HI_RA_RAM_USR_END__W 16 | 433 | #define HI_RA_RAM_USR_END__W 16 |
| 434 | #define HI_RA_RAM_USR_END__M 0xFFFF | 434 | #define HI_RA_RAM_USR_END__M 0xFFFF |
| 435 | 435 | ||
| 436 | #define HI_IF_RAM_TRP_BPT0__AX 0x430000 | 436 | #define HI_IF_RAM_TRP_BPT0__AX 0x430000 |
| 437 | #define HI_IF_RAM_TRP_BPT0__XSZ 2 | 437 | #define HI_IF_RAM_TRP_BPT0__XSZ 2 |
| 438 | #define HI_IF_RAM_TRP_BPT0__W 12 | 438 | #define HI_IF_RAM_TRP_BPT0__W 12 |
| 439 | #define HI_IF_RAM_TRP_BPT0__M 0xFFF | 439 | #define HI_IF_RAM_TRP_BPT0__M 0xFFF |
| 440 | 440 | ||
| 441 | #define HI_IF_RAM_TRP_STKU__AX 0x430002 | 441 | #define HI_IF_RAM_TRP_STKU__AX 0x430002 |
| 442 | #define HI_IF_RAM_TRP_STKU__XSZ 2 | 442 | #define HI_IF_RAM_TRP_STKU__XSZ 2 |
| 443 | #define HI_IF_RAM_TRP_STKU__W 12 | 443 | #define HI_IF_RAM_TRP_STKU__W 12 |
| 444 | #define HI_IF_RAM_TRP_STKU__M 0xFFF | 444 | #define HI_IF_RAM_TRP_STKU__M 0xFFF |
| 445 | 445 | ||
| 446 | #define HI_IF_RAM_USR_BEGIN__A 0x430200 | 446 | #define HI_IF_RAM_USR_BEGIN__A 0x430200 |
| 447 | #define HI_IF_RAM_USR_BEGIN__W 12 | 447 | #define HI_IF_RAM_USR_BEGIN__W 12 |
| 448 | #define HI_IF_RAM_USR_BEGIN__M 0xFFF | 448 | #define HI_IF_RAM_USR_BEGIN__M 0xFFF |
| 449 | 449 | ||
| 450 | #define HI_IF_RAM_USR_END__A 0x4303FF | 450 | #define HI_IF_RAM_USR_END__A 0x4303FF |
| 451 | #define HI_IF_RAM_USR_END__W 12 | 451 | #define HI_IF_RAM_USR_END__W 12 |
| 452 | #define HI_IF_RAM_USR_END__M 0xFFF | 452 | #define HI_IF_RAM_USR_END__M 0xFFF |
| 453 | 453 | ||
| 454 | #define SC_SID 0x11 | 454 | #define SC_SID 0x11 |
| 455 | 455 | ||
| 456 | #define SC_COMM_EXEC__A 0x800000 | 456 | #define SC_COMM_EXEC__A 0x800000 |
| 457 | #define SC_COMM_EXEC__W 3 | 457 | #define SC_COMM_EXEC__W 3 |
| 458 | #define SC_COMM_EXEC__M 0x7 | 458 | #define SC_COMM_EXEC__M 0x7 |
| 459 | #define SC_COMM_EXEC_CTL__B 0 | 459 | #define SC_COMM_EXEC_CTL__B 0 |
| 460 | #define SC_COMM_EXEC_CTL__W 3 | 460 | #define SC_COMM_EXEC_CTL__W 3 |
| 461 | #define SC_COMM_EXEC_CTL__M 0x7 | 461 | #define SC_COMM_EXEC_CTL__M 0x7 |
| 462 | #define SC_COMM_EXEC_CTL_STOP 0x0 | 462 | #define SC_COMM_EXEC_CTL_STOP 0x0 |
| 463 | #define SC_COMM_EXEC_CTL_ACTIVE 0x1 | 463 | #define SC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 464 | #define SC_COMM_EXEC_CTL_HOLD 0x2 | 464 | #define SC_COMM_EXEC_CTL_HOLD 0x2 |
| 465 | #define SC_COMM_EXEC_CTL_STEP 0x3 | 465 | #define SC_COMM_EXEC_CTL_STEP 0x3 |
| 466 | #define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 466 | #define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 467 | #define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 467 | #define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 468 | 468 | ||
| 469 | #define SC_COMM_STATE__A 0x800001 | 469 | #define SC_COMM_STATE__A 0x800001 |
| 470 | #define SC_COMM_STATE__W 16 | 470 | #define SC_COMM_STATE__W 16 |
| 471 | #define SC_COMM_STATE__M 0xFFFF | 471 | #define SC_COMM_STATE__M 0xFFFF |
| 472 | #define SC_COMM_MB__A 0x800002 | 472 | #define SC_COMM_MB__A 0x800002 |
| 473 | #define SC_COMM_MB__W 16 | 473 | #define SC_COMM_MB__W 16 |
| 474 | #define SC_COMM_MB__M 0xFFFF | 474 | #define SC_COMM_MB__M 0xFFFF |
| 475 | #define SC_COMM_SERVICE0__A 0x800003 | 475 | #define SC_COMM_SERVICE0__A 0x800003 |
| 476 | #define SC_COMM_SERVICE0__W 16 | 476 | #define SC_COMM_SERVICE0__W 16 |
| 477 | #define SC_COMM_SERVICE0__M 0xFFFF | 477 | #define SC_COMM_SERVICE0__M 0xFFFF |
| 478 | #define SC_COMM_SERVICE1__A 0x800004 | 478 | #define SC_COMM_SERVICE1__A 0x800004 |
| 479 | #define SC_COMM_SERVICE1__W 16 | 479 | #define SC_COMM_SERVICE1__W 16 |
| 480 | #define SC_COMM_SERVICE1__M 0xFFFF | 480 | #define SC_COMM_SERVICE1__M 0xFFFF |
| 481 | #define SC_COMM_INT_STA__A 0x800007 | 481 | #define SC_COMM_INT_STA__A 0x800007 |
| 482 | #define SC_COMM_INT_STA__W 16 | 482 | #define SC_COMM_INT_STA__W 16 |
| 483 | #define SC_COMM_INT_STA__M 0xFFFF | 483 | #define SC_COMM_INT_STA__M 0xFFFF |
| 484 | #define SC_COMM_INT_MSK__A 0x800008 | 484 | #define SC_COMM_INT_MSK__A 0x800008 |
| 485 | #define SC_COMM_INT_MSK__W 16 | 485 | #define SC_COMM_INT_MSK__W 16 |
| 486 | #define SC_COMM_INT_MSK__M 0xFFFF | 486 | #define SC_COMM_INT_MSK__M 0xFFFF |
| 487 | 487 | ||
| 488 | #define SC_CT_REG_COMM_EXEC__A 0x810000 | 488 | #define SC_CT_REG_COMM_EXEC__A 0x810000 |
| 489 | #define SC_CT_REG_COMM_EXEC__W 3 | 489 | #define SC_CT_REG_COMM_EXEC__W 3 |
| 490 | #define SC_CT_REG_COMM_EXEC__M 0x7 | 490 | #define SC_CT_REG_COMM_EXEC__M 0x7 |
| 491 | #define SC_CT_REG_COMM_EXEC_CTL__B 0 | 491 | #define SC_CT_REG_COMM_EXEC_CTL__B 0 |
| 492 | #define SC_CT_REG_COMM_EXEC_CTL__W 3 | 492 | #define SC_CT_REG_COMM_EXEC_CTL__W 3 |
| 493 | #define SC_CT_REG_COMM_EXEC_CTL__M 0x7 | 493 | #define SC_CT_REG_COMM_EXEC_CTL__M 0x7 |
| 494 | #define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 | 494 | #define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 495 | #define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 495 | #define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 496 | #define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 | 496 | #define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 497 | #define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 | 497 | #define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 498 | 498 | ||
| 499 | #define SC_CT_REG_COMM_STATE__A 0x810001 | 499 | #define SC_CT_REG_COMM_STATE__A 0x810001 |
| 500 | #define SC_CT_REG_COMM_STATE__W 10 | 500 | #define SC_CT_REG_COMM_STATE__W 10 |
| 501 | #define SC_CT_REG_COMM_STATE__M 0x3FF | 501 | #define SC_CT_REG_COMM_STATE__M 0x3FF |
| 502 | #define SC_CT_REG_COMM_SERVICE0__A 0x810003 | 502 | #define SC_CT_REG_COMM_SERVICE0__A 0x810003 |
| 503 | #define SC_CT_REG_COMM_SERVICE0__W 16 | 503 | #define SC_CT_REG_COMM_SERVICE0__W 16 |
| 504 | #define SC_CT_REG_COMM_SERVICE0__M 0xFFFF | 504 | #define SC_CT_REG_COMM_SERVICE0__M 0xFFFF |
| 505 | #define SC_CT_REG_COMM_SERVICE1__A 0x810004 | 505 | #define SC_CT_REG_COMM_SERVICE1__A 0x810004 |
| 506 | #define SC_CT_REG_COMM_SERVICE1__W 16 | 506 | #define SC_CT_REG_COMM_SERVICE1__W 16 |
| 507 | #define SC_CT_REG_COMM_SERVICE1__M 0xFFFF | 507 | #define SC_CT_REG_COMM_SERVICE1__M 0xFFFF |
| 508 | #define SC_CT_REG_COMM_SERVICE1_SC__B 1 | 508 | #define SC_CT_REG_COMM_SERVICE1_SC__B 1 |
| 509 | #define SC_CT_REG_COMM_SERVICE1_SC__W 1 | 509 | #define SC_CT_REG_COMM_SERVICE1_SC__W 1 |
| 510 | #define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 | 510 | #define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 |
| 511 | 511 | ||
| 512 | #define SC_CT_REG_COMM_INT_STA__A 0x810007 | 512 | #define SC_CT_REG_COMM_INT_STA__A 0x810007 |
| 513 | #define SC_CT_REG_COMM_INT_STA__W 1 | 513 | #define SC_CT_REG_COMM_INT_STA__W 1 |
| 514 | #define SC_CT_REG_COMM_INT_STA__M 0x1 | 514 | #define SC_CT_REG_COMM_INT_STA__M 0x1 |
| 515 | #define SC_CT_REG_COMM_INT_STA_REQUEST__B 0 | 515 | #define SC_CT_REG_COMM_INT_STA_REQUEST__B 0 |
| 516 | #define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 | 516 | #define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 |
| 517 | #define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 | 517 | #define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 |
| 518 | 518 | ||
| 519 | #define SC_CT_REG_COMM_INT_MSK__A 0x810008 | 519 | #define SC_CT_REG_COMM_INT_MSK__A 0x810008 |
| 520 | #define SC_CT_REG_COMM_INT_MSK__W 1 | 520 | #define SC_CT_REG_COMM_INT_MSK__W 1 |
| 521 | #define SC_CT_REG_COMM_INT_MSK__M 0x1 | 521 | #define SC_CT_REG_COMM_INT_MSK__M 0x1 |
| 522 | #define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 | 522 | #define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 |
| 523 | #define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 | 523 | #define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 |
| 524 | #define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 | 524 | #define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 |
| 525 | 525 | ||
| 526 | #define SC_CT_REG_CTL_STK__AX 0x810010 | 526 | #define SC_CT_REG_CTL_STK__AX 0x810010 |
| 527 | #define SC_CT_REG_CTL_STK__XSZ 4 | 527 | #define SC_CT_REG_CTL_STK__XSZ 4 |
| 528 | #define SC_CT_REG_CTL_STK__W 10 | 528 | #define SC_CT_REG_CTL_STK__W 10 |
| 529 | #define SC_CT_REG_CTL_STK__M 0x3FF | 529 | #define SC_CT_REG_CTL_STK__M 0x3FF |
| 530 | 530 | ||
| 531 | #define SC_CT_REG_CTL_BPT_IDX__A 0x81001F | 531 | #define SC_CT_REG_CTL_BPT_IDX__A 0x81001F |
| 532 | #define SC_CT_REG_CTL_BPT_IDX__W 1 | 532 | #define SC_CT_REG_CTL_BPT_IDX__W 1 |
| 533 | #define SC_CT_REG_CTL_BPT_IDX__M 0x1 | 533 | #define SC_CT_REG_CTL_BPT_IDX__M 0x1 |
| 534 | 534 | ||
| 535 | #define SC_CT_REG_CTL_BPT__A 0x810020 | 535 | #define SC_CT_REG_CTL_BPT__A 0x810020 |
| 536 | #define SC_CT_REG_CTL_BPT__W 10 | 536 | #define SC_CT_REG_CTL_BPT__W 10 |
| 537 | #define SC_CT_REG_CTL_BPT__M 0x3FF | 537 | #define SC_CT_REG_CTL_BPT__M 0x3FF |
| 538 | 538 | ||
| 539 | #define SC_RA_RAM_PARAM0__A 0x820040 | 539 | #define SC_RA_RAM_PARAM0__A 0x820040 |
| 540 | #define SC_RA_RAM_PARAM0__W 16 | 540 | #define SC_RA_RAM_PARAM0__W 16 |
| 541 | #define SC_RA_RAM_PARAM0__M 0xFFFF | 541 | #define SC_RA_RAM_PARAM0__M 0xFFFF |
| 542 | #define SC_RA_RAM_PARAM1__A 0x820041 | 542 | #define SC_RA_RAM_PARAM1__A 0x820041 |
| 543 | #define SC_RA_RAM_PARAM1__W 16 | 543 | #define SC_RA_RAM_PARAM1__W 16 |
| 544 | #define SC_RA_RAM_PARAM1__M 0xFFFF | 544 | #define SC_RA_RAM_PARAM1__M 0xFFFF |
| 545 | #define SC_RA_RAM_CMD_ADDR__A 0x820042 | 545 | #define SC_RA_RAM_CMD_ADDR__A 0x820042 |
| 546 | #define SC_RA_RAM_CMD_ADDR__W 16 | 546 | #define SC_RA_RAM_CMD_ADDR__W 16 |
| 547 | #define SC_RA_RAM_CMD_ADDR__M 0xFFFF | 547 | #define SC_RA_RAM_CMD_ADDR__M 0xFFFF |
| 548 | #define SC_RA_RAM_CMD__A 0x820043 | 548 | #define SC_RA_RAM_CMD__A 0x820043 |
| 549 | #define SC_RA_RAM_CMD__W 16 | 549 | #define SC_RA_RAM_CMD__W 16 |
| 550 | #define SC_RA_RAM_CMD__M 0xFFFF | 550 | #define SC_RA_RAM_CMD__M 0xFFFF |
| 551 | #define SC_RA_RAM_CMD_NULL 0x0 | 551 | #define SC_RA_RAM_CMD_NULL 0x0 |
| 552 | #define SC_RA_RAM_CMD_PROC_START 0x1 | 552 | #define SC_RA_RAM_CMD_PROC_START 0x1 |
| 553 | #define SC_RA_RAM_CMD_PROC_TRIGGER 0x2 | 553 | #define SC_RA_RAM_CMD_PROC_TRIGGER 0x2 |
| 554 | #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 | 554 | #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 |
| 555 | #define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 | 555 | #define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 |
| 556 | #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 | 556 | #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 |
| 557 | #define SC_RA_RAM_CMD_USER_IO 0x6 | 557 | #define SC_RA_RAM_CMD_USER_IO 0x6 |
| 558 | #define SC_RA_RAM_CMD_SET_TIMER 0x7 | 558 | #define SC_RA_RAM_CMD_SET_TIMER 0x7 |
| 559 | #define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 | 559 | #define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 |
| 560 | #define SC_RA_RAM_CMD_MAX 0x8 | 560 | #define SC_RA_RAM_CMD_MAX 0x8 |
| 561 | #define SC_RA_RAM_CMDBLOCK__C 0x4 | 561 | #define SC_RA_RAM_CMDBLOCK__C 0x4 |
| 562 | 562 | ||
| 563 | #define SC_RA_RAM_PROC_ACTIVATE__A 0x820044 | 563 | #define SC_RA_RAM_PROC_ACTIVATE__A 0x820044 |
| 564 | #define SC_RA_RAM_PROC_ACTIVATE__W 16 | 564 | #define SC_RA_RAM_PROC_ACTIVATE__W 16 |
| 565 | #define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF | 565 | #define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF |
| 566 | #define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF | 566 | #define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF |
| 567 | #define SC_RA_RAM_PROC_TERMINATED__A 0x820045 | 567 | #define SC_RA_RAM_PROC_TERMINATED__A 0x820045 |
| 568 | #define SC_RA_RAM_PROC_TERMINATED__W 16 | 568 | #define SC_RA_RAM_PROC_TERMINATED__W 16 |
| 569 | #define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF | 569 | #define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF |
| 570 | #define SC_RA_RAM_SW_EVENT__A 0x820046 | 570 | #define SC_RA_RAM_SW_EVENT__A 0x820046 |
| 571 | #define SC_RA_RAM_SW_EVENT__W 14 | 571 | #define SC_RA_RAM_SW_EVENT__W 14 |
| 572 | #define SC_RA_RAM_SW_EVENT__M 0x3FFF | 572 | #define SC_RA_RAM_SW_EVENT__M 0x3FFF |
| 573 | #define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 | 573 | #define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 |
| 574 | #define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 | 574 | #define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 |
| 575 | #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 | 575 | #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 |
| 576 | #define SC_RA_RAM_SW_EVENT_RUN__B 1 | 576 | #define SC_RA_RAM_SW_EVENT_RUN__B 1 |
| 577 | #define SC_RA_RAM_SW_EVENT_RUN__W 1 | 577 | #define SC_RA_RAM_SW_EVENT_RUN__W 1 |
| 578 | #define SC_RA_RAM_SW_EVENT_RUN__M 0x2 | 578 | #define SC_RA_RAM_SW_EVENT_RUN__M 0x2 |
| 579 | #define SC_RA_RAM_SW_EVENT_TERMINATE__B 2 | 579 | #define SC_RA_RAM_SW_EVENT_TERMINATE__B 2 |
| 580 | #define SC_RA_RAM_SW_EVENT_TERMINATE__W 1 | 580 | #define SC_RA_RAM_SW_EVENT_TERMINATE__W 1 |
| 581 | #define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 | 581 | #define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 |
| 582 | #define SC_RA_RAM_SW_EVENT_FT_START__B 3 | 582 | #define SC_RA_RAM_SW_EVENT_FT_START__B 3 |
| 583 | #define SC_RA_RAM_SW_EVENT_FT_START__W 1 | 583 | #define SC_RA_RAM_SW_EVENT_FT_START__W 1 |
| 584 | #define SC_RA_RAM_SW_EVENT_FT_START__M 0x8 | 584 | #define SC_RA_RAM_SW_EVENT_FT_START__M 0x8 |
| 585 | #define SC_RA_RAM_SW_EVENT_FI_START__B 4 | 585 | #define SC_RA_RAM_SW_EVENT_FI_START__B 4 |
| 586 | #define SC_RA_RAM_SW_EVENT_FI_START__W 1 | 586 | #define SC_RA_RAM_SW_EVENT_FI_START__W 1 |
| 587 | #define SC_RA_RAM_SW_EVENT_FI_START__M 0x10 | 587 | #define SC_RA_RAM_SW_EVENT_FI_START__M 0x10 |
| 588 | #define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 | 588 | #define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 |
| 589 | #define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 | 589 | #define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 |
| 590 | #define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 | 590 | #define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 |
| 591 | #define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 | 591 | #define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 |
| 592 | #define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 | 592 | #define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 |
| 593 | #define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 | 593 | #define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 |
| 594 | #define SC_RA_RAM_SW_EVENT_CE_IR__B 7 | 594 | #define SC_RA_RAM_SW_EVENT_CE_IR__B 7 |
| 595 | #define SC_RA_RAM_SW_EVENT_CE_IR__W 1 | 595 | #define SC_RA_RAM_SW_EVENT_CE_IR__W 1 |
| 596 | #define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 | 596 | #define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 |
| 597 | #define SC_RA_RAM_SW_EVENT_FE_FD__B 8 | 597 | #define SC_RA_RAM_SW_EVENT_FE_FD__B 8 |
| 598 | #define SC_RA_RAM_SW_EVENT_FE_FD__W 1 | 598 | #define SC_RA_RAM_SW_EVENT_FE_FD__W 1 |
| 599 | #define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 | 599 | #define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 |
| 600 | #define SC_RA_RAM_SW_EVENT_FE_CF__B 9 | 600 | #define SC_RA_RAM_SW_EVENT_FE_CF__B 9 |
| 601 | #define SC_RA_RAM_SW_EVENT_FE_CF__W 1 | 601 | #define SC_RA_RAM_SW_EVENT_FE_CF__W 1 |
| 602 | #define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 | 602 | #define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 |
| 603 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10 | 603 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10 |
| 604 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1 | 604 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1 |
| 605 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400 | 605 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400 |
| 606 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11 | 606 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11 |
| 607 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1 | 607 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1 |
| 608 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800 | 608 | #define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800 |
| 609 | 609 | ||
| 610 | #define SC_RA_RAM_LOCKTRACK__A 0x820047 | 610 | #define SC_RA_RAM_LOCKTRACK__A 0x820047 |
| 611 | #define SC_RA_RAM_LOCKTRACK__W 16 | 611 | #define SC_RA_RAM_LOCKTRACK__W 16 |
| 612 | #define SC_RA_RAM_LOCKTRACK__M 0xFFFF | 612 | #define SC_RA_RAM_LOCKTRACK__M 0xFFFF |
| 613 | #define SC_RA_RAM_LOCKTRACK_NULL 0x0 | 613 | #define SC_RA_RAM_LOCKTRACK_NULL 0x0 |
| 614 | #define SC_RA_RAM_LOCKTRACK_MIN 0x1 | 614 | #define SC_RA_RAM_LOCKTRACK_MIN 0x1 |
| 615 | #define SC_RA_RAM_LOCKTRACK_RESET 0x1 | 615 | #define SC_RA_RAM_LOCKTRACK_RESET 0x1 |
| 616 | #define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 | 616 | #define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 |
| 617 | #define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 | 617 | #define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 |
| 618 | #define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 | 618 | #define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 |
| 619 | #define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5 | 619 | #define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5 |
| 620 | #define SC_RA_RAM_LOCKTRACK_LC 0x6 | 620 | #define SC_RA_RAM_LOCKTRACK_LC 0x6 |
| 621 | #define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7 | 621 | #define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7 |
| 622 | #define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8 | 622 | #define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8 |
| 623 | #define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9 | 623 | #define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9 |
| 624 | #define SC_RA_RAM_LOCKTRACK_TRACK 0xA | 624 | #define SC_RA_RAM_LOCKTRACK_TRACK 0xA |
| 625 | #define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB | 625 | #define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB |
| 626 | #define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC | 626 | #define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC |
| 627 | #define SC_RA_RAM_LOCKTRACK_MAX 0xD | 627 | #define SC_RA_RAM_LOCKTRACK_MAX 0xD |
| 628 | 628 | ||
| 629 | #define SC_RA_RAM_OP_PARAM__A 0x820048 | 629 | #define SC_RA_RAM_OP_PARAM__A 0x820048 |
| 630 | #define SC_RA_RAM_OP_PARAM__W 13 | 630 | #define SC_RA_RAM_OP_PARAM__W 13 |
| 631 | #define SC_RA_RAM_OP_PARAM__M 0x1FFF | 631 | #define SC_RA_RAM_OP_PARAM__M 0x1FFF |
| 632 | #define SC_RA_RAM_OP_PARAM_MODE__B 0 | 632 | #define SC_RA_RAM_OP_PARAM_MODE__B 0 |
| 633 | #define SC_RA_RAM_OP_PARAM_MODE__W 2 | 633 | #define SC_RA_RAM_OP_PARAM_MODE__W 2 |
| 634 | #define SC_RA_RAM_OP_PARAM_MODE__M 0x3 | 634 | #define SC_RA_RAM_OP_PARAM_MODE__M 0x3 |
| 635 | #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 | 635 | #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 |
| 636 | #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 | 636 | #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 |
| 637 | #define SC_RA_RAM_OP_PARAM_GUARD__B 2 | 637 | #define SC_RA_RAM_OP_PARAM_GUARD__B 2 |
| 638 | #define SC_RA_RAM_OP_PARAM_GUARD__W 2 | 638 | #define SC_RA_RAM_OP_PARAM_GUARD__W 2 |
| 639 | #define SC_RA_RAM_OP_PARAM_GUARD__M 0xC | 639 | #define SC_RA_RAM_OP_PARAM_GUARD__M 0xC |
| 640 | #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 | 640 | #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 |
| 641 | #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 | 641 | #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 |
| 642 | #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 | 642 | #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 |
| 643 | #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC | 643 | #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC |
| 644 | #define SC_RA_RAM_OP_PARAM_CONST__B 4 | 644 | #define SC_RA_RAM_OP_PARAM_CONST__B 4 |
| 645 | #define SC_RA_RAM_OP_PARAM_CONST__W 2 | 645 | #define SC_RA_RAM_OP_PARAM_CONST__W 2 |
| 646 | #define SC_RA_RAM_OP_PARAM_CONST__M 0x30 | 646 | #define SC_RA_RAM_OP_PARAM_CONST__M 0x30 |
| 647 | #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 | 647 | #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 |
| 648 | #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 | 648 | #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 |
| 649 | #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 | 649 | #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 |
| 650 | #define SC_RA_RAM_OP_PARAM_HIER__B 6 | 650 | #define SC_RA_RAM_OP_PARAM_HIER__B 6 |
| 651 | #define SC_RA_RAM_OP_PARAM_HIER__W 3 | 651 | #define SC_RA_RAM_OP_PARAM_HIER__W 3 |
| 652 | #define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 | 652 | #define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 |
| 653 | #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 | 653 | #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 |
| 654 | #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 | 654 | #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 |
| 655 | #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 | 655 | #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 |
| 656 | #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 | 656 | #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 |
| 657 | #define SC_RA_RAM_OP_PARAM_RATE__B 9 | 657 | #define SC_RA_RAM_OP_PARAM_RATE__B 9 |
| 658 | #define SC_RA_RAM_OP_PARAM_RATE__W 3 | 658 | #define SC_RA_RAM_OP_PARAM_RATE__W 3 |
| 659 | #define SC_RA_RAM_OP_PARAM_RATE__M 0xE00 | 659 | #define SC_RA_RAM_OP_PARAM_RATE__M 0xE00 |
| 660 | #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 | 660 | #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 |
| 661 | #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 | 661 | #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 |
| 662 | #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 | 662 | #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 |
| 663 | #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 | 663 | #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 |
| 664 | #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 | 664 | #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 |
| 665 | #define SC_RA_RAM_OP_PARAM_PRIO__B 12 | 665 | #define SC_RA_RAM_OP_PARAM_PRIO__B 12 |
| 666 | #define SC_RA_RAM_OP_PARAM_PRIO__W 1 | 666 | #define SC_RA_RAM_OP_PARAM_PRIO__W 1 |
| 667 | #define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 | 667 | #define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 |
| 668 | #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 | 668 | #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 |
| 669 | #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 | 669 | #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 |
| 670 | 670 | ||
| 671 | #define SC_RA_RAM_OP_AUTO__A 0x820049 | 671 | #define SC_RA_RAM_OP_AUTO__A 0x820049 |
| 672 | #define SC_RA_RAM_OP_AUTO__W 6 | 672 | #define SC_RA_RAM_OP_AUTO__W 6 |
| 673 | #define SC_RA_RAM_OP_AUTO__M 0x3F | 673 | #define SC_RA_RAM_OP_AUTO__M 0x3F |
| 674 | #define SC_RA_RAM_OP_AUTO__PRE 0x1F | 674 | #define SC_RA_RAM_OP_AUTO__PRE 0x1F |
| 675 | #define SC_RA_RAM_OP_AUTO_MODE__B 0 | 675 | #define SC_RA_RAM_OP_AUTO_MODE__B 0 |
| 676 | #define SC_RA_RAM_OP_AUTO_MODE__W 1 | 676 | #define SC_RA_RAM_OP_AUTO_MODE__W 1 |
| 677 | #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 | 677 | #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 |
| 678 | #define SC_RA_RAM_OP_AUTO_GUARD__B 1 | 678 | #define SC_RA_RAM_OP_AUTO_GUARD__B 1 |
| 679 | #define SC_RA_RAM_OP_AUTO_GUARD__W 1 | 679 | #define SC_RA_RAM_OP_AUTO_GUARD__W 1 |
| 680 | #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 | 680 | #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 |
| 681 | #define SC_RA_RAM_OP_AUTO_CONST__B 2 | 681 | #define SC_RA_RAM_OP_AUTO_CONST__B 2 |
| 682 | #define SC_RA_RAM_OP_AUTO_CONST__W 1 | 682 | #define SC_RA_RAM_OP_AUTO_CONST__W 1 |
| 683 | #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 | 683 | #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 |
| 684 | #define SC_RA_RAM_OP_AUTO_HIER__B 3 | 684 | #define SC_RA_RAM_OP_AUTO_HIER__B 3 |
| 685 | #define SC_RA_RAM_OP_AUTO_HIER__W 1 | 685 | #define SC_RA_RAM_OP_AUTO_HIER__W 1 |
| 686 | #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 | 686 | #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 |
| 687 | #define SC_RA_RAM_OP_AUTO_RATE__B 4 | 687 | #define SC_RA_RAM_OP_AUTO_RATE__B 4 |
| 688 | #define SC_RA_RAM_OP_AUTO_RATE__W 1 | 688 | #define SC_RA_RAM_OP_AUTO_RATE__W 1 |
| 689 | #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 | 689 | #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 |
| 690 | #define SC_RA_RAM_OP_AUTO_PRIO__B 5 | 690 | #define SC_RA_RAM_OP_AUTO_PRIO__B 5 |
| 691 | #define SC_RA_RAM_OP_AUTO_PRIO__W 1 | 691 | #define SC_RA_RAM_OP_AUTO_PRIO__W 1 |
| 692 | #define SC_RA_RAM_OP_AUTO_PRIO__M 0x20 | 692 | #define SC_RA_RAM_OP_AUTO_PRIO__M 0x20 |
| 693 | 693 | ||
| 694 | #define SC_RA_RAM_PILOT_STATUS__A 0x82004A | 694 | #define SC_RA_RAM_PILOT_STATUS__A 0x82004A |
| 695 | #define SC_RA_RAM_PILOT_STATUS__W 16 | 695 | #define SC_RA_RAM_PILOT_STATUS__W 16 |
| 696 | #define SC_RA_RAM_PILOT_STATUS__M 0xFFFF | 696 | #define SC_RA_RAM_PILOT_STATUS__M 0xFFFF |
| 697 | #define SC_RA_RAM_PILOT_STATUS_OK 0x0 | 697 | #define SC_RA_RAM_PILOT_STATUS_OK 0x0 |
| 698 | #define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 | 698 | #define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 |
| 699 | #define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 | 699 | #define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 |
| 700 | 700 | ||
| 701 | #define SC_RA_RAM_LOCK__A 0x82004B | 701 | #define SC_RA_RAM_LOCK__A 0x82004B |
| 702 | #define SC_RA_RAM_LOCK__W 4 | 702 | #define SC_RA_RAM_LOCK__W 4 |
| 703 | #define SC_RA_RAM_LOCK__M 0xF | 703 | #define SC_RA_RAM_LOCK__M 0xF |
| 704 | #define SC_RA_RAM_LOCK_DEMOD__B 0 | 704 | #define SC_RA_RAM_LOCK_DEMOD__B 0 |
| 705 | #define SC_RA_RAM_LOCK_DEMOD__W 1 | 705 | #define SC_RA_RAM_LOCK_DEMOD__W 1 |
| 706 | #define SC_RA_RAM_LOCK_DEMOD__M 0x1 | 706 | #define SC_RA_RAM_LOCK_DEMOD__M 0x1 |
| 707 | #define SC_RA_RAM_LOCK_FEC__B 1 | 707 | #define SC_RA_RAM_LOCK_FEC__B 1 |
| 708 | #define SC_RA_RAM_LOCK_FEC__W 1 | 708 | #define SC_RA_RAM_LOCK_FEC__W 1 |
| 709 | #define SC_RA_RAM_LOCK_FEC__M 0x2 | 709 | #define SC_RA_RAM_LOCK_FEC__M 0x2 |
| 710 | #define SC_RA_RAM_LOCK_MPEG__B 2 | 710 | #define SC_RA_RAM_LOCK_MPEG__B 2 |
| 711 | #define SC_RA_RAM_LOCK_MPEG__W 1 | 711 | #define SC_RA_RAM_LOCK_MPEG__W 1 |
| 712 | #define SC_RA_RAM_LOCK_MPEG__M 0x4 | 712 | #define SC_RA_RAM_LOCK_MPEG__M 0x4 |
| 713 | #define SC_RA_RAM_LOCK_NODVBT__B 3 | 713 | #define SC_RA_RAM_LOCK_NODVBT__B 3 |
| 714 | #define SC_RA_RAM_LOCK_NODVBT__W 1 | 714 | #define SC_RA_RAM_LOCK_NODVBT__W 1 |
| 715 | #define SC_RA_RAM_LOCK_NODVBT__M 0x8 | 715 | #define SC_RA_RAM_LOCK_NODVBT__M 0x8 |
| 716 | 716 | ||
| 717 | #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C | 717 | #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C |
| 718 | #define SC_RA_RAM_BE_OPT_ENA__W 5 | 718 | #define SC_RA_RAM_BE_OPT_ENA__W 5 |
| 719 | #define SC_RA_RAM_BE_OPT_ENA__M 0x1F | 719 | #define SC_RA_RAM_BE_OPT_ENA__M 0x1F |
| 720 | #define SC_RA_RAM_BE_OPT_ENA__PRE 0x14 | 720 | #define SC_RA_RAM_BE_OPT_ENA__PRE 0x14 |
| 721 | #define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 | 721 | #define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 |
| 722 | #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 | 722 | #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 |
| 723 | #define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2 | 723 | #define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2 |
| 724 | #define SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 | 724 | #define SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 |
| 725 | #define SC_RA_RAM_BE_OPT_ENA_MAX 0x5 | 725 | #define SC_RA_RAM_BE_OPT_ENA_MAX 0x5 |
| 726 | 726 | ||
| 727 | #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D | 727 | #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D |
| 728 | #define SC_RA_RAM_BE_OPT_DELAY__W 16 | 728 | #define SC_RA_RAM_BE_OPT_DELAY__W 16 |
| 729 | #define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF | 729 | #define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF |
| 730 | #define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 | 730 | #define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 |
| 731 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E | 731 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E |
| 732 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 | 732 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 |
| 733 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF | 733 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF |
| 734 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 | 734 | #define SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 |
| 735 | #define SC_RA_RAM_ECHO_THRES__A 0x82004F | 735 | #define SC_RA_RAM_ECHO_THRES__A 0x82004F |
| 736 | #define SC_RA_RAM_ECHO_THRES__W 16 | 736 | #define SC_RA_RAM_ECHO_THRES__W 16 |
| 737 | #define SC_RA_RAM_ECHO_THRES__M 0xFFFF | 737 | #define SC_RA_RAM_ECHO_THRES__M 0xFFFF |
| 738 | #define SC_RA_RAM_ECHO_THRES__PRE 0x2A | 738 | #define SC_RA_RAM_ECHO_THRES__PRE 0x2A |
| 739 | #define SC_RA_RAM_CONFIG__A 0x820050 | 739 | #define SC_RA_RAM_CONFIG__A 0x820050 |
| 740 | #define SC_RA_RAM_CONFIG__W 16 | 740 | #define SC_RA_RAM_CONFIG__W 16 |
| 741 | #define SC_RA_RAM_CONFIG__M 0xFFFF | 741 | #define SC_RA_RAM_CONFIG__M 0xFFFF |
| 742 | #define SC_RA_RAM_CONFIG__PRE 0x54 | 742 | #define SC_RA_RAM_CONFIG__PRE 0x54 |
| 743 | #define SC_RA_RAM_CONFIG_ID__B 0 | 743 | #define SC_RA_RAM_CONFIG_ID__B 0 |
| 744 | #define SC_RA_RAM_CONFIG_ID__W 1 | 744 | #define SC_RA_RAM_CONFIG_ID__W 1 |
| 745 | #define SC_RA_RAM_CONFIG_ID__M 0x1 | 745 | #define SC_RA_RAM_CONFIG_ID__M 0x1 |
| 746 | #define SC_RA_RAM_CONFIG_ID_PRO 0x0 | 746 | #define SC_RA_RAM_CONFIG_ID_PRO 0x0 |
| 747 | #define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 | 747 | #define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 |
| 748 | #define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 | 748 | #define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 |
| 749 | #define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 | 749 | #define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 |
| 750 | #define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 | 750 | #define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 |
| 751 | #define SC_RA_RAM_CONFIG_FR_ENABLE__B 2 | 751 | #define SC_RA_RAM_CONFIG_FR_ENABLE__B 2 |
| 752 | #define SC_RA_RAM_CONFIG_FR_ENABLE__W 1 | 752 | #define SC_RA_RAM_CONFIG_FR_ENABLE__W 1 |
| 753 | #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 | 753 | #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 |
| 754 | #define SC_RA_RAM_CONFIG_MIXMODE__B 3 | 754 | #define SC_RA_RAM_CONFIG_MIXMODE__B 3 |
| 755 | #define SC_RA_RAM_CONFIG_MIXMODE__W 1 | 755 | #define SC_RA_RAM_CONFIG_MIXMODE__W 1 |
| 756 | #define SC_RA_RAM_CONFIG_MIXMODE__M 0x8 | 756 | #define SC_RA_RAM_CONFIG_MIXMODE__M 0x8 |
| 757 | #define SC_RA_RAM_CONFIG_FREQSCAN__B 4 | 757 | #define SC_RA_RAM_CONFIG_FREQSCAN__B 4 |
| 758 | #define SC_RA_RAM_CONFIG_FREQSCAN__W 1 | 758 | #define SC_RA_RAM_CONFIG_FREQSCAN__W 1 |
| 759 | #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 | 759 | #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 |
| 760 | #define SC_RA_RAM_CONFIG_SLAVE__B 5 | 760 | #define SC_RA_RAM_CONFIG_SLAVE__B 5 |
| 761 | #define SC_RA_RAM_CONFIG_SLAVE__W 1 | 761 | #define SC_RA_RAM_CONFIG_SLAVE__W 1 |
| 762 | #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 | 762 | #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 |
| 763 | #define SC_RA_RAM_CONFIG_FAR_OFF__B 6 | 763 | #define SC_RA_RAM_CONFIG_FAR_OFF__B 6 |
| 764 | #define SC_RA_RAM_CONFIG_FAR_OFF__W 1 | 764 | #define SC_RA_RAM_CONFIG_FAR_OFF__W 1 |
| 765 | #define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 | 765 | #define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 |
| 766 | #define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 | 766 | #define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 |
| 767 | #define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 | 767 | #define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 |
| 768 | #define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 | 768 | #define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 |
| 769 | #define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 | 769 | #define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 |
| 770 | #define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 | 770 | #define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 |
| 771 | #define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 | 771 | #define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 |
| 772 | #define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 | 772 | #define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 |
| 773 | #define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 | 773 | #define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 |
| 774 | #define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 | 774 | #define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 |
| 775 | 775 | ||
| 776 | #define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 | 776 | #define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 |
| 777 | #define SC_RA_RAM_PILOT_THRES_SPD__W 16 | 777 | #define SC_RA_RAM_PILOT_THRES_SPD__W 16 |
| 778 | #define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF | 778 | #define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF |
| 779 | #define SC_RA_RAM_PILOT_THRES_SPD__PRE 0x4 | 779 | #define SC_RA_RAM_PILOT_THRES_SPD__PRE 0x4 |
| 780 | #define SC_RA_RAM_PILOT_THRES_CPD__A 0x820052 | 780 | #define SC_RA_RAM_PILOT_THRES_CPD__A 0x820052 |
| 781 | #define SC_RA_RAM_PILOT_THRES_CPD__W 16 | 781 | #define SC_RA_RAM_PILOT_THRES_CPD__W 16 |
| 782 | #define SC_RA_RAM_PILOT_THRES_CPD__M 0xFFFF | 782 | #define SC_RA_RAM_PILOT_THRES_CPD__M 0xFFFF |
| 783 | #define SC_RA_RAM_PILOT_THRES_CPD__PRE 0x4 | 783 | #define SC_RA_RAM_PILOT_THRES_CPD__PRE 0x4 |
| 784 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__A 0x820053 | 784 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__A 0x820053 |
| 785 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__W 16 | 785 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__W 16 |
| 786 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF | 786 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF |
| 787 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 | 787 | #define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 |
| 788 | 788 | ||
| 789 | #define SC_RA_RAM_CO_THRES_8K__A 0x820055 | 789 | #define SC_RA_RAM_CO_THRES_8K__A 0x820055 |
| 790 | #define SC_RA_RAM_CO_THRES_8K__W 16 | 790 | #define SC_RA_RAM_CO_THRES_8K__W 16 |
| 791 | #define SC_RA_RAM_CO_THRES_8K__M 0xFFFF | 791 | #define SC_RA_RAM_CO_THRES_8K__M 0xFFFF |
| 792 | #define SC_RA_RAM_CO_THRES_8K__PRE 0x10E | 792 | #define SC_RA_RAM_CO_THRES_8K__PRE 0x10E |
| 793 | #define SC_RA_RAM_CO_THRES_2K__A 0x820056 | 793 | #define SC_RA_RAM_CO_THRES_2K__A 0x820056 |
| 794 | #define SC_RA_RAM_CO_THRES_2K__W 16 | 794 | #define SC_RA_RAM_CO_THRES_2K__W 16 |
| 795 | #define SC_RA_RAM_CO_THRES_2K__M 0xFFFF | 795 | #define SC_RA_RAM_CO_THRES_2K__M 0xFFFF |
| 796 | #define SC_RA_RAM_CO_THRES_2K__PRE 0x208 | 796 | #define SC_RA_RAM_CO_THRES_2K__PRE 0x208 |
| 797 | #define SC_RA_RAM_CO_LEVEL__A 0x820057 | 797 | #define SC_RA_RAM_CO_LEVEL__A 0x820057 |
| 798 | #define SC_RA_RAM_CO_LEVEL__W 16 | 798 | #define SC_RA_RAM_CO_LEVEL__W 16 |
| 799 | #define SC_RA_RAM_CO_LEVEL__M 0xFFFF | 799 | #define SC_RA_RAM_CO_LEVEL__M 0xFFFF |
| 800 | #define SC_RA_RAM_CO_DETECT__A 0x820058 | 800 | #define SC_RA_RAM_CO_DETECT__A 0x820058 |
| 801 | #define SC_RA_RAM_CO_DETECT__W 16 | 801 | #define SC_RA_RAM_CO_DETECT__W 16 |
| 802 | #define SC_RA_RAM_CO_DETECT__M 0xFFFF | 802 | #define SC_RA_RAM_CO_DETECT__M 0xFFFF |
| 803 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059 | 803 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059 |
| 804 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16 | 804 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16 |
| 805 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF | 805 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF |
| 806 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB | 806 | #define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB |
| 807 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A | 807 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A |
| 808 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16 | 808 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16 |
| 809 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF | 809 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF |
| 810 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB | 810 | #define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB |
| 811 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B | 811 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B |
| 812 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16 | 812 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16 |
| 813 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF | 813 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF |
| 814 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB | 814 | #define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB |
| 815 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C | 815 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C |
| 816 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16 | 816 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16 |
| 817 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF | 817 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF |
| 818 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD | 818 | #define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD |
| 819 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D | 819 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D |
| 820 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16 | 820 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16 |
| 821 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF | 821 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF |
| 822 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED | 822 | #define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED |
| 823 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E | 823 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E |
| 824 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16 | 824 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16 |
| 825 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF | 825 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF |
| 826 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD | 826 | #define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD |
| 827 | #define SC_RA_RAM_MOTION_OFFSET__A 0x82005F | 827 | #define SC_RA_RAM_MOTION_OFFSET__A 0x82005F |
| 828 | #define SC_RA_RAM_MOTION_OFFSET__W 16 | 828 | #define SC_RA_RAM_MOTION_OFFSET__W 16 |
| 829 | #define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF | 829 | #define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF |
| 830 | #define SC_RA_RAM_MOTION_OFFSET__PRE 0x2 | 830 | #define SC_RA_RAM_MOTION_OFFSET__PRE 0x2 |
| 831 | #define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 | 831 | #define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 |
| 832 | #define SC_RA_RAM_STATE_PROC_STOP__XSZ 12 | 832 | #define SC_RA_RAM_STATE_PROC_STOP__XSZ 12 |
| 833 | #define SC_RA_RAM_STATE_PROC_STOP__W 16 | 833 | #define SC_RA_RAM_STATE_PROC_STOP__W 16 |
| 834 | #define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF | 834 | #define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF |
| 835 | #define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE | 835 | #define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE |
| 836 | #define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 | 836 | #define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 |
| 837 | #define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 | 837 | #define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 |
| 838 | #define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 | 838 | #define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 |
| 839 | #define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 | 839 | #define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 |
| 840 | #define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 | 840 | #define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 |
| 841 | #define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 | 841 | #define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 |
| 842 | #define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 | 842 | #define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 |
| 843 | #define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 | 843 | #define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 |
| 844 | #define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0 | 844 | #define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0 |
| 845 | #define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE | 845 | #define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE |
| 846 | #define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE | 846 | #define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE |
| 847 | #define SC_RA_RAM_STATE_PROC_START__AX 0x820070 | 847 | #define SC_RA_RAM_STATE_PROC_START__AX 0x820070 |
| 848 | #define SC_RA_RAM_STATE_PROC_START__XSZ 12 | 848 | #define SC_RA_RAM_STATE_PROC_START__XSZ 12 |
| 849 | #define SC_RA_RAM_STATE_PROC_START__W 16 | 849 | #define SC_RA_RAM_STATE_PROC_START__W 16 |
| 850 | #define SC_RA_RAM_STATE_PROC_START__M 0xFFFF | 850 | #define SC_RA_RAM_STATE_PROC_START__M 0xFFFF |
| 851 | #define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 | 851 | #define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 |
| 852 | #define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 | 852 | #define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 |
| 853 | #define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 | 853 | #define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 |
| 854 | #define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 | 854 | #define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 |
| 855 | #define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 | 855 | #define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 |
| 856 | #define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 | 856 | #define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 |
| 857 | #define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10 | 857 | #define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10 |
| 858 | #define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 | 858 | #define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 |
| 859 | #define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0 | 859 | #define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0 |
| 860 | #define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30 | 860 | #define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30 |
| 861 | #define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0 | 861 | #define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0 |
| 862 | #define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0 | 862 | #define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0 |
| 863 | #define SC_RA_RAM_IF_SAVE__AX 0x82008E | 863 | #define SC_RA_RAM_IF_SAVE__AX 0x82008E |
| 864 | #define SC_RA_RAM_IF_SAVE__XSZ 2 | 864 | #define SC_RA_RAM_IF_SAVE__XSZ 2 |
| 865 | #define SC_RA_RAM_IF_SAVE__W 16 | 865 | #define SC_RA_RAM_IF_SAVE__W 16 |
| 866 | #define SC_RA_RAM_IF_SAVE__M 0xFFFF | 866 | #define SC_RA_RAM_IF_SAVE__M 0xFFFF |
| 867 | #define SC_RA_RAM_FR_THRES__A 0x82007D | 867 | #define SC_RA_RAM_FR_THRES__A 0x82007D |
| 868 | #define SC_RA_RAM_FR_THRES__W 16 | 868 | #define SC_RA_RAM_FR_THRES__W 16 |
| 869 | #define SC_RA_RAM_FR_THRES__M 0xFFFF | 869 | #define SC_RA_RAM_FR_THRES__M 0xFFFF |
| 870 | #define SC_RA_RAM_FR_THRES__PRE 0x1A2C | 870 | #define SC_RA_RAM_FR_THRES__PRE 0x1A2C |
| 871 | #define SC_RA_RAM_STATUS__A 0x82007E | 871 | #define SC_RA_RAM_STATUS__A 0x82007E |
| 872 | #define SC_RA_RAM_STATUS__W 16 | 872 | #define SC_RA_RAM_STATUS__W 16 |
| 873 | #define SC_RA_RAM_STATUS__M 0xFFFF | 873 | #define SC_RA_RAM_STATUS__M 0xFFFF |
| 874 | #define SC_RA_RAM_NF_BORDER_INIT__A 0x82007F | 874 | #define SC_RA_RAM_NF_BORDER_INIT__A 0x82007F |
| 875 | #define SC_RA_RAM_NF_BORDER_INIT__W 16 | 875 | #define SC_RA_RAM_NF_BORDER_INIT__W 16 |
| 876 | #define SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF | 876 | #define SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF |
| 877 | #define SC_RA_RAM_NF_BORDER_INIT__PRE 0x500 | 877 | #define SC_RA_RAM_NF_BORDER_INIT__PRE 0x500 |
| 878 | #define SC_RA_RAM_TIMER__A 0x820080 | 878 | #define SC_RA_RAM_TIMER__A 0x820080 |
| 879 | #define SC_RA_RAM_TIMER__W 16 | 879 | #define SC_RA_RAM_TIMER__W 16 |
| 880 | #define SC_RA_RAM_TIMER__M 0xFFFF | 880 | #define SC_RA_RAM_TIMER__M 0xFFFF |
| 881 | #define SC_RA_RAM_FI_OFFSET__A 0x820081 | 881 | #define SC_RA_RAM_FI_OFFSET__A 0x820081 |
| 882 | #define SC_RA_RAM_FI_OFFSET__W 16 | 882 | #define SC_RA_RAM_FI_OFFSET__W 16 |
| 883 | #define SC_RA_RAM_FI_OFFSET__M 0xFFFF | 883 | #define SC_RA_RAM_FI_OFFSET__M 0xFFFF |
| 884 | #define SC_RA_RAM_FI_OFFSET__PRE 0x382 | 884 | #define SC_RA_RAM_FI_OFFSET__PRE 0x382 |
| 885 | #define SC_RA_RAM_ECHO_GUARD__A 0x820082 | 885 | #define SC_RA_RAM_ECHO_GUARD__A 0x820082 |
| 886 | #define SC_RA_RAM_ECHO_GUARD__W 16 | 886 | #define SC_RA_RAM_ECHO_GUARD__W 16 |
| 887 | #define SC_RA_RAM_ECHO_GUARD__M 0xFFFF | 887 | #define SC_RA_RAM_ECHO_GUARD__M 0xFFFF |
| 888 | #define SC_RA_RAM_ECHO_GUARD__PRE 0x18 | 888 | #define SC_RA_RAM_ECHO_GUARD__PRE 0x18 |
| 889 | 889 | ||
| 890 | #define SC_RA_RAM_IR_FREQ__A 0x8200D0 | 890 | #define SC_RA_RAM_IR_FREQ__A 0x8200D0 |
| 891 | #define SC_RA_RAM_IR_FREQ__W 16 | 891 | #define SC_RA_RAM_IR_FREQ__W 16 |
| 892 | #define SC_RA_RAM_IR_FREQ__M 0xFFFF | 892 | #define SC_RA_RAM_IR_FREQ__M 0xFFFF |
| 893 | #define SC_RA_RAM_IR_FREQ__PRE 0x0 | 893 | #define SC_RA_RAM_IR_FREQ__PRE 0x0 |
| 894 | 894 | ||
| 895 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 | 895 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 |
| 896 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 | 896 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 |
| 897 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF | 897 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF |
| 898 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 | 898 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 |
| 899 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 | 899 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 |
| 900 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 | 900 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 |
| 901 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF | 901 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF |
| 902 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 | 902 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 |
| 903 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 | 903 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 |
| 904 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 | 904 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 |
| 905 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF | 905 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF |
| 906 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 | 906 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 |
| 907 | 907 | ||
| 908 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 | 908 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 |
| 909 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 | 909 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 |
| 910 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF | 910 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF |
| 911 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 | 911 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 |
| 912 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 | 912 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 |
| 913 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 | 913 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 |
| 914 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF | 914 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF |
| 915 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 | 915 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 |
| 916 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 | 916 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 |
| 917 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 | 917 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 |
| 918 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF | 918 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF |
| 919 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 | 919 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 |
| 920 | 920 | ||
| 921 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 | 921 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 |
| 922 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 | 922 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 |
| 923 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF | 923 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF |
| 924 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 | 924 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 |
| 925 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 | 925 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 |
| 926 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 | 926 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 |
| 927 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF | 927 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF |
| 928 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 | 928 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 |
| 929 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 | 929 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 |
| 930 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 | 930 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 |
| 931 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF | 931 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF |
| 932 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 | 932 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 |
| 933 | 933 | ||
| 934 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA | 934 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA |
| 935 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 | 935 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 |
| 936 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF | 936 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF |
| 937 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB | 937 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB |
| 938 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB | 938 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB |
| 939 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 | 939 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 |
| 940 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF | 940 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF |
| 941 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 | 941 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 |
| 942 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC | 942 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC |
| 943 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 | 943 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 |
| 944 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF | 944 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF |
| 945 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 | 945 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 |
| 946 | 946 | ||
| 947 | #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD | 947 | #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD |
| 948 | #define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 | 948 | #define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 |
| 949 | #define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF | 949 | #define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF |
| 950 | #define SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0xFFFF | 950 | #define SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0xFFFF |
| 951 | #define SC_RA_RAM_ECHO_AGE__A 0x8200DE | 951 | #define SC_RA_RAM_ECHO_AGE__A 0x8200DE |
| 952 | #define SC_RA_RAM_ECHO_AGE__W 16 | 952 | #define SC_RA_RAM_ECHO_AGE__W 16 |
| 953 | #define SC_RA_RAM_ECHO_AGE__M 0xFFFF | 953 | #define SC_RA_RAM_ECHO_AGE__M 0xFFFF |
| 954 | #define SC_RA_RAM_ECHO_AGE__PRE 0xFFFF | 954 | #define SC_RA_RAM_ECHO_AGE__PRE 0xFFFF |
| 955 | #define SC_RA_RAM_ECHO_FILTER__A 0x8200DF | 955 | #define SC_RA_RAM_ECHO_FILTER__A 0x8200DF |
| 956 | #define SC_RA_RAM_ECHO_FILTER__W 16 | 956 | #define SC_RA_RAM_ECHO_FILTER__W 16 |
| 957 | #define SC_RA_RAM_ECHO_FILTER__M 0xFFFF | 957 | #define SC_RA_RAM_ECHO_FILTER__M 0xFFFF |
| 958 | #define SC_RA_RAM_ECHO_FILTER__PRE 0x2 | 958 | #define SC_RA_RAM_ECHO_FILTER__PRE 0x2 |
| 959 | 959 | ||
| 960 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 | 960 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 |
| 961 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 | 961 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 |
| 962 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF | 962 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF |
| 963 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 | 963 | #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 |
| 964 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 | 964 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 |
| 965 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 | 965 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 |
| 966 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF | 966 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF |
| 967 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 | 967 | #define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 |
| 968 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 | 968 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 |
| 969 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 | 969 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 |
| 970 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF | 970 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF |
| 971 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 | 971 | #define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 |
| 972 | 972 | ||
| 973 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 | 973 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 |
| 974 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 | 974 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 |
| 975 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF | 975 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF |
| 976 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE | 976 | #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE |
| 977 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 | 977 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 |
| 978 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 | 978 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 |
| 979 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF | 979 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF |
| 980 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 | 980 | #define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 |
| 981 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 | 981 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 |
| 982 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 | 982 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 |
| 983 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF | 983 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF |
| 984 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 | 984 | #define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 |
| 985 | 985 | ||
| 986 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 | 986 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 |
| 987 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 | 987 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 |
| 988 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF | 988 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF |
| 989 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x10 | 989 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x10 |
| 990 | #define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 | 990 | #define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 |
| 991 | #define SC_RA_RAM_SAMPLE_RATE_STEP__W 16 | 991 | #define SC_RA_RAM_SAMPLE_RATE_STEP__W 16 |
| 992 | #define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF | 992 | #define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF |
| 993 | #define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 | 993 | #define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 |
| 994 | 994 | ||
| 995 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA | 995 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA |
| 996 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 | 996 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 |
| 997 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF | 997 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF |
| 998 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 | 998 | #define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 |
| 999 | #define SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB | 999 | #define SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB |
| 1000 | #define SC_RA_RAM_TPS_TIMEOUT__W 16 | 1000 | #define SC_RA_RAM_TPS_TIMEOUT__W 16 |
| 1001 | #define SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF | 1001 | #define SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF |
| 1002 | #define SC_RA_RAM_BAND__A 0x8200EC | 1002 | #define SC_RA_RAM_BAND__A 0x8200EC |
| 1003 | #define SC_RA_RAM_BAND__W 16 | 1003 | #define SC_RA_RAM_BAND__W 16 |
| 1004 | #define SC_RA_RAM_BAND__M 0xFFFF | 1004 | #define SC_RA_RAM_BAND__M 0xFFFF |
| 1005 | #define SC_RA_RAM_BAND__PRE 0x0 | 1005 | #define SC_RA_RAM_BAND__PRE 0x0 |
| 1006 | #define SC_RA_RAM_BAND_INTERVAL__B 0 | 1006 | #define SC_RA_RAM_BAND_INTERVAL__B 0 |
| 1007 | #define SC_RA_RAM_BAND_INTERVAL__W 4 | 1007 | #define SC_RA_RAM_BAND_INTERVAL__W 4 |
| 1008 | #define SC_RA_RAM_BAND_INTERVAL__M 0xF | 1008 | #define SC_RA_RAM_BAND_INTERVAL__M 0xF |
| 1009 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 | 1009 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 |
| 1010 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 | 1010 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 |
| 1011 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 | 1011 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 |
| 1012 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 | 1012 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 |
| 1013 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 | 1013 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 |
| 1014 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 | 1014 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 |
| 1015 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 | 1015 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 |
| 1016 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 | 1016 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 |
| 1017 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 | 1017 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 |
| 1018 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 | 1018 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 |
| 1019 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 | 1019 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 |
| 1020 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 | 1020 | #define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 |
| 1021 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 | 1021 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 |
| 1022 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 | 1022 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 |
| 1023 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 | 1023 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 |
| 1024 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 | 1024 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 |
| 1025 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 | 1025 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 |
| 1026 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 | 1026 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 |
| 1027 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 | 1027 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 |
| 1028 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 | 1028 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 |
| 1029 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 | 1029 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 |
| 1030 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 | 1030 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 |
| 1031 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 | 1031 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 |
| 1032 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 | 1032 | #define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 |
| 1033 | 1033 | ||
| 1034 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED | 1034 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED |
| 1035 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 | 1035 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 |
| 1036 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF | 1036 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF |
| 1037 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 | 1037 | #define SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 |
| 1038 | #define SC_RA_RAM_REG__AX 0x8200F0 | 1038 | #define SC_RA_RAM_REG__AX 0x8200F0 |
| 1039 | #define SC_RA_RAM_REG__XSZ 2 | 1039 | #define SC_RA_RAM_REG__XSZ 2 |
| 1040 | #define SC_RA_RAM_REG__W 16 | 1040 | #define SC_RA_RAM_REG__W 16 |
| 1041 | #define SC_RA_RAM_REG__M 0xFFFF | 1041 | #define SC_RA_RAM_REG__M 0xFFFF |
| 1042 | #define SC_RA_RAM_BREAK__A 0x8200F2 | 1042 | #define SC_RA_RAM_BREAK__A 0x8200F2 |
| 1043 | #define SC_RA_RAM_BREAK__W 16 | 1043 | #define SC_RA_RAM_BREAK__W 16 |
| 1044 | #define SC_RA_RAM_BREAK__M 0xFFFF | 1044 | #define SC_RA_RAM_BREAK__M 0xFFFF |
| 1045 | #define SC_RA_RAM_BOOTCOUNT__A 0x8200F3 | 1045 | #define SC_RA_RAM_BOOTCOUNT__A 0x8200F3 |
| 1046 | #define SC_RA_RAM_BOOTCOUNT__W 16 | 1046 | #define SC_RA_RAM_BOOTCOUNT__W 16 |
| 1047 | #define SC_RA_RAM_BOOTCOUNT__M 0xFFFF | 1047 | #define SC_RA_RAM_BOOTCOUNT__M 0xFFFF |
| 1048 | 1048 | ||
| 1049 | #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 | 1049 | #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 |
| 1050 | #define SC_RA_RAM_LC_ABS_2K__W 16 | 1050 | #define SC_RA_RAM_LC_ABS_2K__W 16 |
| 1051 | #define SC_RA_RAM_LC_ABS_2K__M 0xFFFF | 1051 | #define SC_RA_RAM_LC_ABS_2K__M 0xFFFF |
| 1052 | #define SC_RA_RAM_LC_ABS_2K__PRE 0x1F | 1052 | #define SC_RA_RAM_LC_ABS_2K__PRE 0x1F |
| 1053 | #define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 | 1053 | #define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 |
| 1054 | #define SC_RA_RAM_LC_ABS_8K__W 16 | 1054 | #define SC_RA_RAM_LC_ABS_8K__W 16 |
| 1055 | #define SC_RA_RAM_LC_ABS_8K__M 0xFFFF | 1055 | #define SC_RA_RAM_LC_ABS_8K__M 0xFFFF |
| 1056 | #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F | 1056 | #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F |
| 1057 | 1057 | ||
| 1058 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 | 1058 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 |
| 1059 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 | 1059 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 |
| 1060 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF | 1060 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF |
| 1061 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE 0x1 | 1061 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE 0x1 |
| 1062 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A 0x8200F7 | 1062 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A 0x8200F7 |
| 1063 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W 16 | 1063 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W 16 |
| 1064 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF | 1064 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF |
| 1065 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 | 1065 | #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 |
| 1066 | 1066 | ||
| 1067 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 | 1067 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 |
| 1068 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 | 1068 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 |
| 1069 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF | 1069 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF |
| 1070 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE 0x3 | 1070 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE 0x3 |
| 1071 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A 0x8200F9 | 1071 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A 0x8200F9 |
| 1072 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W 16 | 1072 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W 16 |
| 1073 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M 0xFFFF | 1073 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M 0xFFFF |
| 1074 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE 0x2 | 1074 | #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE 0x2 |
| 1075 | #define SC_RA_RAM_RELOCK__A 0x8200FE | 1075 | #define SC_RA_RAM_RELOCK__A 0x8200FE |
| 1076 | #define SC_RA_RAM_RELOCK__W 16 | 1076 | #define SC_RA_RAM_RELOCK__W 16 |
| 1077 | #define SC_RA_RAM_RELOCK__M 0xFFFF | 1077 | #define SC_RA_RAM_RELOCK__M 0xFFFF |
| 1078 | #define SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF | 1078 | #define SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF |
| 1079 | #define SC_RA_RAM_STACKUNDERFLOW__W 16 | 1079 | #define SC_RA_RAM_STACKUNDERFLOW__W 16 |
| 1080 | #define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF | 1080 | #define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF |
| 1081 | 1081 | ||
| 1082 | #define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 | 1082 | #define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 |
| 1083 | #define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 | 1083 | #define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 |
| 1084 | #define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF | 1084 | #define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF |
| 1085 | #define SC_RA_RAM_NF_PREPOST__A 0x820149 | 1085 | #define SC_RA_RAM_NF_PREPOST__A 0x820149 |
| 1086 | #define SC_RA_RAM_NF_PREPOST__W 16 | 1086 | #define SC_RA_RAM_NF_PREPOST__W 16 |
| 1087 | #define SC_RA_RAM_NF_PREPOST__M 0xFFFF | 1087 | #define SC_RA_RAM_NF_PREPOST__M 0xFFFF |
| 1088 | #define SC_RA_RAM_NF_PREBORDER__A 0x82014A | 1088 | #define SC_RA_RAM_NF_PREBORDER__A 0x82014A |
| 1089 | #define SC_RA_RAM_NF_PREBORDER__W 16 | 1089 | #define SC_RA_RAM_NF_PREBORDER__W 16 |
| 1090 | #define SC_RA_RAM_NF_PREBORDER__M 0xFFFF | 1090 | #define SC_RA_RAM_NF_PREBORDER__M 0xFFFF |
| 1091 | #define SC_RA_RAM_NF_START__A 0x82014B | 1091 | #define SC_RA_RAM_NF_START__A 0x82014B |
| 1092 | #define SC_RA_RAM_NF_START__W 16 | 1092 | #define SC_RA_RAM_NF_START__W 16 |
| 1093 | #define SC_RA_RAM_NF_START__M 0xFFFF | 1093 | #define SC_RA_RAM_NF_START__M 0xFFFF |
| 1094 | #define SC_RA_RAM_NF_MINISI__AX 0x82014C | 1094 | #define SC_RA_RAM_NF_MINISI__AX 0x82014C |
| 1095 | #define SC_RA_RAM_NF_MINISI__XSZ 2 | 1095 | #define SC_RA_RAM_NF_MINISI__XSZ 2 |
| 1096 | #define SC_RA_RAM_NF_MINISI__W 16 | 1096 | #define SC_RA_RAM_NF_MINISI__W 16 |
| 1097 | #define SC_RA_RAM_NF_MINISI__M 0xFFFF | 1097 | #define SC_RA_RAM_NF_MINISI__M 0xFFFF |
| 1098 | #define SC_RA_RAM_NF_MAXECHO__A 0x82014E | 1098 | #define SC_RA_RAM_NF_MAXECHO__A 0x82014E |
| 1099 | #define SC_RA_RAM_NF_MAXECHO__W 16 | 1099 | #define SC_RA_RAM_NF_MAXECHO__W 16 |
| 1100 | #define SC_RA_RAM_NF_MAXECHO__M 0xFFFF | 1100 | #define SC_RA_RAM_NF_MAXECHO__M 0xFFFF |
| 1101 | #define SC_RA_RAM_NF_NRECHOES__A 0x82014F | 1101 | #define SC_RA_RAM_NF_NRECHOES__A 0x82014F |
| 1102 | #define SC_RA_RAM_NF_NRECHOES__W 16 | 1102 | #define SC_RA_RAM_NF_NRECHOES__W 16 |
| 1103 | #define SC_RA_RAM_NF_NRECHOES__M 0xFFFF | 1103 | #define SC_RA_RAM_NF_NRECHOES__M 0xFFFF |
| 1104 | #define SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 | 1104 | #define SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 |
| 1105 | #define SC_RA_RAM_NF_ECHOTABLE__XSZ 16 | 1105 | #define SC_RA_RAM_NF_ECHOTABLE__XSZ 16 |
| 1106 | #define SC_RA_RAM_NF_ECHOTABLE__W 16 | 1106 | #define SC_RA_RAM_NF_ECHOTABLE__W 16 |
| 1107 | #define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF | 1107 | #define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF |
| 1108 | 1108 | ||
| 1109 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 | 1109 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 |
| 1110 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 | 1110 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 |
| 1111 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF | 1111 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF |
| 1112 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 | 1112 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 |
| 1113 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 | 1113 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 |
| 1114 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 | 1114 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 |
| 1115 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF | 1115 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF |
| 1116 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 | 1116 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 |
| 1117 | 1117 | ||
| 1118 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 | 1118 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 |
| 1119 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 | 1119 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 |
| 1120 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF | 1120 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF |
| 1121 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB | 1121 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB |
| 1122 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 | 1122 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 |
| 1123 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 | 1123 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 |
| 1124 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF | 1124 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF |
| 1125 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 | 1125 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 |
| 1126 | 1126 | ||
| 1127 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 | 1127 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 |
| 1128 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 | 1128 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 |
| 1129 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF | 1129 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF |
| 1130 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF | 1130 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF |
| 1131 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 | 1131 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 |
| 1132 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 | 1132 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 |
| 1133 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF | 1133 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF |
| 1134 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 | 1134 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 |
| 1135 | 1135 | ||
| 1136 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 | 1136 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 |
| 1137 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 | 1137 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 |
| 1138 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF | 1138 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF |
| 1139 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E | 1139 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E |
| 1140 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 | 1140 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 |
| 1141 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 | 1141 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 |
| 1142 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF | 1142 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF |
| 1143 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 | 1143 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 |
| 1144 | 1144 | ||
| 1145 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 | 1145 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 |
| 1146 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 | 1146 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 |
| 1147 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF | 1147 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF |
| 1148 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A | 1148 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A |
| 1149 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 | 1149 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 |
| 1150 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 | 1150 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 |
| 1151 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF | 1151 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF |
| 1152 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 | 1152 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 |
| 1153 | 1153 | ||
| 1154 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA | 1154 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA |
| 1155 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 | 1155 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 |
| 1156 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF | 1156 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF |
| 1157 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB | 1157 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB |
| 1158 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB | 1158 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB |
| 1159 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 | 1159 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 |
| 1160 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF | 1160 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF |
| 1161 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 | 1161 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 |
| 1162 | 1162 | ||
| 1163 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC | 1163 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC |
| 1164 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 | 1164 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 |
| 1165 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF | 1165 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF |
| 1166 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F | 1166 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F |
| 1167 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD | 1167 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD |
| 1168 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 | 1168 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 |
| 1169 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF | 1169 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF |
| 1170 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 | 1170 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 |
| 1171 | 1171 | ||
| 1172 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE | 1172 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE |
| 1173 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 | 1173 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 |
| 1174 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF | 1174 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF |
| 1175 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 | 1175 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 |
| 1176 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF | 1176 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF |
| 1177 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 | 1177 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 |
| 1178 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF | 1178 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF |
| 1179 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 | 1179 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 |
| 1180 | #define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE | 1180 | #define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE |
| 1181 | #define SC_RA_RAM_DRIVER_VERSION__XSZ 2 | 1181 | #define SC_RA_RAM_DRIVER_VERSION__XSZ 2 |
| 1182 | #define SC_RA_RAM_DRIVER_VERSION__W 16 | 1182 | #define SC_RA_RAM_DRIVER_VERSION__W 16 |
| 1183 | #define SC_RA_RAM_DRIVER_VERSION__M 0xFFFF | 1183 | #define SC_RA_RAM_DRIVER_VERSION__M 0xFFFF |
| 1184 | #define SC_RA_RAM_EVENT0_MIN 0x7 | 1184 | #define SC_RA_RAM_EVENT0_MIN 0x7 |
| 1185 | #define SC_RA_RAM_EVENT0_FE_CU 0x7 | 1185 | #define SC_RA_RAM_EVENT0_FE_CU 0x7 |
| 1186 | #define SC_RA_RAM_EVENT0_CE 0xA | 1186 | #define SC_RA_RAM_EVENT0_CE 0xA |
| 1187 | #define SC_RA_RAM_EVENT0_EQ 0xE | 1187 | #define SC_RA_RAM_EVENT0_EQ 0xE |
| 1188 | #define SC_RA_RAM_EVENT0_MAX 0xF | 1188 | #define SC_RA_RAM_EVENT0_MAX 0xF |
| 1189 | #define SC_RA_RAM_EVENT1_MIN 0x8 | 1189 | #define SC_RA_RAM_EVENT1_MIN 0x8 |
| 1190 | #define SC_RA_RAM_EVENT1_EC_OD 0x8 | 1190 | #define SC_RA_RAM_EVENT1_EC_OD 0x8 |
| 1191 | #define SC_RA_RAM_EVENT1_LC 0xC | 1191 | #define SC_RA_RAM_EVENT1_LC 0xC |
| 1192 | #define SC_RA_RAM_EVENT1_MAX 0xD | 1192 | #define SC_RA_RAM_EVENT1_MAX 0xD |
| 1193 | #define SC_RA_RAM_PROC_LOCKTRACK 0x0 | 1193 | #define SC_RA_RAM_PROC_LOCKTRACK 0x0 |
| 1194 | #define SC_RA_RAM_PROC_MODE_GUARD 0x1 | 1194 | #define SC_RA_RAM_PROC_MODE_GUARD 0x1 |
| 1195 | #define SC_RA_RAM_PROC_PILOTS 0x2 | 1195 | #define SC_RA_RAM_PROC_PILOTS 0x2 |
| 1196 | #define SC_RA_RAM_PROC_FESTART_ADJUST 0x3 | 1196 | #define SC_RA_RAM_PROC_FESTART_ADJUST 0x3 |
| 1197 | #define SC_RA_RAM_PROC_ECHO 0x4 | 1197 | #define SC_RA_RAM_PROC_ECHO 0x4 |
| 1198 | #define SC_RA_RAM_PROC_BE_OPT 0x5 | 1198 | #define SC_RA_RAM_PROC_BE_OPT 0x5 |
| 1199 | #define SC_RA_RAM_PROC_EQ 0x7 | 1199 | #define SC_RA_RAM_PROC_EQ 0x7 |
| 1200 | #define SC_RA_RAM_PROC_MAX 0x8 | 1200 | #define SC_RA_RAM_PROC_MAX 0x8 |
| 1201 | 1201 | ||
| 1202 | #define SC_IF_RAM_TRP_RST__AX 0x830000 | 1202 | #define SC_IF_RAM_TRP_RST__AX 0x830000 |
| 1203 | #define SC_IF_RAM_TRP_RST__XSZ 2 | 1203 | #define SC_IF_RAM_TRP_RST__XSZ 2 |
| 1204 | #define SC_IF_RAM_TRP_RST__W 12 | 1204 | #define SC_IF_RAM_TRP_RST__W 12 |
| 1205 | #define SC_IF_RAM_TRP_RST__M 0xFFF | 1205 | #define SC_IF_RAM_TRP_RST__M 0xFFF |
| 1206 | 1206 | ||
| 1207 | #define SC_IF_RAM_TRP_BPT0__AX 0x830002 | 1207 | #define SC_IF_RAM_TRP_BPT0__AX 0x830002 |
| 1208 | #define SC_IF_RAM_TRP_BPT0__XSZ 2 | 1208 | #define SC_IF_RAM_TRP_BPT0__XSZ 2 |
| 1209 | #define SC_IF_RAM_TRP_BPT0__W 12 | 1209 | #define SC_IF_RAM_TRP_BPT0__W 12 |
| 1210 | #define SC_IF_RAM_TRP_BPT0__M 0xFFF | 1210 | #define SC_IF_RAM_TRP_BPT0__M 0xFFF |
| 1211 | 1211 | ||
| 1212 | #define SC_IF_RAM_TRP_STKU__AX 0x830004 | 1212 | #define SC_IF_RAM_TRP_STKU__AX 0x830004 |
| 1213 | #define SC_IF_RAM_TRP_STKU__XSZ 2 | 1213 | #define SC_IF_RAM_TRP_STKU__XSZ 2 |
| 1214 | #define SC_IF_RAM_TRP_STKU__W 12 | 1214 | #define SC_IF_RAM_TRP_STKU__W 12 |
| 1215 | #define SC_IF_RAM_TRP_STKU__M 0xFFF | 1215 | #define SC_IF_RAM_TRP_STKU__M 0xFFF |
| 1216 | 1216 | ||
| 1217 | #define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE | 1217 | #define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE |
| 1218 | #define SC_IF_RAM_VERSION_MA_MI__W 12 | 1218 | #define SC_IF_RAM_VERSION_MA_MI__W 12 |
| 1219 | #define SC_IF_RAM_VERSION_MA_MI__M 0xFFF | 1219 | #define SC_IF_RAM_VERSION_MA_MI__M 0xFFF |
| 1220 | 1220 | ||
| 1221 | #define SC_IF_RAM_VERSION_PATCH__A 0x830FFF | 1221 | #define SC_IF_RAM_VERSION_PATCH__A 0x830FFF |
| 1222 | #define SC_IF_RAM_VERSION_PATCH__W 12 | 1222 | #define SC_IF_RAM_VERSION_PATCH__W 12 |
| 1223 | #define SC_IF_RAM_VERSION_PATCH__M 0xFFF | 1223 | #define SC_IF_RAM_VERSION_PATCH__M 0xFFF |
| 1224 | 1224 | ||
| 1225 | #define FE_COMM_EXEC__A 0xC00000 | 1225 | #define FE_COMM_EXEC__A 0xC00000 |
| 1226 | #define FE_COMM_EXEC__W 3 | 1226 | #define FE_COMM_EXEC__W 3 |
| 1227 | #define FE_COMM_EXEC__M 0x7 | 1227 | #define FE_COMM_EXEC__M 0x7 |
| 1228 | #define FE_COMM_EXEC_CTL__B 0 | 1228 | #define FE_COMM_EXEC_CTL__B 0 |
| 1229 | #define FE_COMM_EXEC_CTL__W 3 | 1229 | #define FE_COMM_EXEC_CTL__W 3 |
| 1230 | #define FE_COMM_EXEC_CTL__M 0x7 | 1230 | #define FE_COMM_EXEC_CTL__M 0x7 |
| 1231 | #define FE_COMM_EXEC_CTL_STOP 0x0 | 1231 | #define FE_COMM_EXEC_CTL_STOP 0x0 |
| 1232 | #define FE_COMM_EXEC_CTL_ACTIVE 0x1 | 1232 | #define FE_COMM_EXEC_CTL_ACTIVE 0x1 |
| 1233 | #define FE_COMM_EXEC_CTL_HOLD 0x2 | 1233 | #define FE_COMM_EXEC_CTL_HOLD 0x2 |
| 1234 | #define FE_COMM_EXEC_CTL_STEP 0x3 | 1234 | #define FE_COMM_EXEC_CTL_STEP 0x3 |
| 1235 | #define FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 1235 | #define FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 1236 | #define FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 1236 | #define FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 1237 | 1237 | ||
| 1238 | #define FE_COMM_STATE__A 0xC00001 | 1238 | #define FE_COMM_STATE__A 0xC00001 |
| 1239 | #define FE_COMM_STATE__W 16 | 1239 | #define FE_COMM_STATE__W 16 |
| 1240 | #define FE_COMM_STATE__M 0xFFFF | 1240 | #define FE_COMM_STATE__M 0xFFFF |
| 1241 | #define FE_COMM_MB__A 0xC00002 | 1241 | #define FE_COMM_MB__A 0xC00002 |
| 1242 | #define FE_COMM_MB__W 16 | 1242 | #define FE_COMM_MB__W 16 |
| 1243 | #define FE_COMM_MB__M 0xFFFF | 1243 | #define FE_COMM_MB__M 0xFFFF |
| 1244 | #define FE_COMM_SERVICE0__A 0xC00003 | 1244 | #define FE_COMM_SERVICE0__A 0xC00003 |
| 1245 | #define FE_COMM_SERVICE0__W 16 | 1245 | #define FE_COMM_SERVICE0__W 16 |
| 1246 | #define FE_COMM_SERVICE0__M 0xFFFF | 1246 | #define FE_COMM_SERVICE0__M 0xFFFF |
| 1247 | #define FE_COMM_SERVICE1__A 0xC00004 | 1247 | #define FE_COMM_SERVICE1__A 0xC00004 |
| 1248 | #define FE_COMM_SERVICE1__W 16 | 1248 | #define FE_COMM_SERVICE1__W 16 |
| 1249 | #define FE_COMM_SERVICE1__M 0xFFFF | 1249 | #define FE_COMM_SERVICE1__M 0xFFFF |
| 1250 | #define FE_COMM_INT_STA__A 0xC00007 | 1250 | #define FE_COMM_INT_STA__A 0xC00007 |
| 1251 | #define FE_COMM_INT_STA__W 16 | 1251 | #define FE_COMM_INT_STA__W 16 |
| 1252 | #define FE_COMM_INT_STA__M 0xFFFF | 1252 | #define FE_COMM_INT_STA__M 0xFFFF |
| 1253 | #define FE_COMM_INT_MSK__A 0xC00008 | 1253 | #define FE_COMM_INT_MSK__A 0xC00008 |
| 1254 | #define FE_COMM_INT_MSK__W 16 | 1254 | #define FE_COMM_INT_MSK__W 16 |
| 1255 | #define FE_COMM_INT_MSK__M 0xFFFF | 1255 | #define FE_COMM_INT_MSK__M 0xFFFF |
| 1256 | 1256 | ||
| 1257 | #define FE_AD_SID 0x1 | 1257 | #define FE_AD_SID 0x1 |
| 1258 | 1258 | ||
| 1259 | #define FE_AD_REG_COMM_EXEC__A 0xC10000 | 1259 | #define FE_AD_REG_COMM_EXEC__A 0xC10000 |
| 1260 | #define FE_AD_REG_COMM_EXEC__W 3 | 1260 | #define FE_AD_REG_COMM_EXEC__W 3 |
| 1261 | #define FE_AD_REG_COMM_EXEC__M 0x7 | 1261 | #define FE_AD_REG_COMM_EXEC__M 0x7 |
| 1262 | #define FE_AD_REG_COMM_EXEC_CTL__B 0 | 1262 | #define FE_AD_REG_COMM_EXEC_CTL__B 0 |
| 1263 | #define FE_AD_REG_COMM_EXEC_CTL__W 3 | 1263 | #define FE_AD_REG_COMM_EXEC_CTL__W 3 |
| 1264 | #define FE_AD_REG_COMM_EXEC_CTL__M 0x7 | 1264 | #define FE_AD_REG_COMM_EXEC_CTL__M 0x7 |
| 1265 | #define FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 | 1265 | #define FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 1266 | #define FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 1266 | #define FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 1267 | #define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 | 1267 | #define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 1268 | #define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 | 1268 | #define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 |
| 1269 | 1269 | ||
| 1270 | #define FE_AD_REG_COMM_MB__A 0xC10002 | 1270 | #define FE_AD_REG_COMM_MB__A 0xC10002 |
| 1271 | #define FE_AD_REG_COMM_MB__W 2 | 1271 | #define FE_AD_REG_COMM_MB__W 2 |
| 1272 | #define FE_AD_REG_COMM_MB__M 0x3 | 1272 | #define FE_AD_REG_COMM_MB__M 0x3 |
| 1273 | #define FE_AD_REG_COMM_MB_CTR__B 0 | 1273 | #define FE_AD_REG_COMM_MB_CTR__B 0 |
| 1274 | #define FE_AD_REG_COMM_MB_CTR__W 1 | 1274 | #define FE_AD_REG_COMM_MB_CTR__W 1 |
| 1275 | #define FE_AD_REG_COMM_MB_CTR__M 0x1 | 1275 | #define FE_AD_REG_COMM_MB_CTR__M 0x1 |
| 1276 | #define FE_AD_REG_COMM_MB_CTR_OFF 0x0 | 1276 | #define FE_AD_REG_COMM_MB_CTR_OFF 0x0 |
| 1277 | #define FE_AD_REG_COMM_MB_CTR_ON 0x1 | 1277 | #define FE_AD_REG_COMM_MB_CTR_ON 0x1 |
| 1278 | #define FE_AD_REG_COMM_MB_OBS__B 1 | 1278 | #define FE_AD_REG_COMM_MB_OBS__B 1 |
| 1279 | #define FE_AD_REG_COMM_MB_OBS__W 1 | 1279 | #define FE_AD_REG_COMM_MB_OBS__W 1 |
| 1280 | #define FE_AD_REG_COMM_MB_OBS__M 0x2 | 1280 | #define FE_AD_REG_COMM_MB_OBS__M 0x2 |
| 1281 | #define FE_AD_REG_COMM_MB_OBS_OFF 0x0 | 1281 | #define FE_AD_REG_COMM_MB_OBS_OFF 0x0 |
| 1282 | #define FE_AD_REG_COMM_MB_OBS_ON 0x2 | 1282 | #define FE_AD_REG_COMM_MB_OBS_ON 0x2 |
| 1283 | 1283 | ||
| 1284 | #define FE_AD_REG_COMM_SERVICE0__A 0xC10003 | 1284 | #define FE_AD_REG_COMM_SERVICE0__A 0xC10003 |
| 1285 | #define FE_AD_REG_COMM_SERVICE0__W 10 | 1285 | #define FE_AD_REG_COMM_SERVICE0__W 10 |
| 1286 | #define FE_AD_REG_COMM_SERVICE0__M 0x3FF | 1286 | #define FE_AD_REG_COMM_SERVICE0__M 0x3FF |
| 1287 | #define FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 | 1287 | #define FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 |
| 1288 | #define FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 | 1288 | #define FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 |
| 1289 | #define FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 | 1289 | #define FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 |
| 1290 | 1290 | ||
| 1291 | #define FE_AD_REG_COMM_SERVICE1__A 0xC10004 | 1291 | #define FE_AD_REG_COMM_SERVICE1__A 0xC10004 |
| 1292 | #define FE_AD_REG_COMM_SERVICE1__W 11 | 1292 | #define FE_AD_REG_COMM_SERVICE1__W 11 |
| 1293 | #define FE_AD_REG_COMM_SERVICE1__M 0x7FF | 1293 | #define FE_AD_REG_COMM_SERVICE1__M 0x7FF |
| 1294 | 1294 | ||
| 1295 | #define FE_AD_REG_COMM_INT_STA__A 0xC10007 | 1295 | #define FE_AD_REG_COMM_INT_STA__A 0xC10007 |
| 1296 | #define FE_AD_REG_COMM_INT_STA__W 2 | 1296 | #define FE_AD_REG_COMM_INT_STA__W 2 |
| 1297 | #define FE_AD_REG_COMM_INT_STA__M 0x3 | 1297 | #define FE_AD_REG_COMM_INT_STA__M 0x3 |
| 1298 | #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 | 1298 | #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 |
| 1299 | #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 | 1299 | #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 |
| 1300 | #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 | 1300 | #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 |
| 1301 | 1301 | ||
| 1302 | #define FE_AD_REG_COMM_INT_MSK__A 0xC10008 | 1302 | #define FE_AD_REG_COMM_INT_MSK__A 0xC10008 |
| 1303 | #define FE_AD_REG_COMM_INT_MSK__W 2 | 1303 | #define FE_AD_REG_COMM_INT_MSK__W 2 |
| 1304 | #define FE_AD_REG_COMM_INT_MSK__M 0x3 | 1304 | #define FE_AD_REG_COMM_INT_MSK__M 0x3 |
| 1305 | #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 | 1305 | #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 |
| 1306 | #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 | 1306 | #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 |
| 1307 | #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 | 1307 | #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 |
| 1308 | 1308 | ||
| 1309 | #define FE_AD_REG_CUR_SEL__A 0xC10010 | 1309 | #define FE_AD_REG_CUR_SEL__A 0xC10010 |
| 1310 | #define FE_AD_REG_CUR_SEL__W 2 | 1310 | #define FE_AD_REG_CUR_SEL__W 2 |
| 1311 | #define FE_AD_REG_CUR_SEL__M 0x3 | 1311 | #define FE_AD_REG_CUR_SEL__M 0x3 |
| 1312 | #define FE_AD_REG_CUR_SEL_INIT 0x2 | 1312 | #define FE_AD_REG_CUR_SEL_INIT 0x2 |
| 1313 | 1313 | ||
| 1314 | #define FE_AD_REG_OVERFLOW__A 0xC10011 | 1314 | #define FE_AD_REG_OVERFLOW__A 0xC10011 |
| 1315 | #define FE_AD_REG_OVERFLOW__W 1 | 1315 | #define FE_AD_REG_OVERFLOW__W 1 |
| 1316 | #define FE_AD_REG_OVERFLOW__M 0x1 | 1316 | #define FE_AD_REG_OVERFLOW__M 0x1 |
| 1317 | #define FE_AD_REG_OVERFLOW_INIT 0x0 | 1317 | #define FE_AD_REG_OVERFLOW_INIT 0x0 |
| 1318 | 1318 | ||
| 1319 | #define FE_AD_REG_FDB_IN__A 0xC10012 | 1319 | #define FE_AD_REG_FDB_IN__A 0xC10012 |
| 1320 | #define FE_AD_REG_FDB_IN__W 1 | 1320 | #define FE_AD_REG_FDB_IN__W 1 |
| 1321 | #define FE_AD_REG_FDB_IN__M 0x1 | 1321 | #define FE_AD_REG_FDB_IN__M 0x1 |
| 1322 | #define FE_AD_REG_FDB_IN_INIT 0x0 | 1322 | #define FE_AD_REG_FDB_IN_INIT 0x0 |
| 1323 | 1323 | ||
| 1324 | #define FE_AD_REG_PD__A 0xC10013 | 1324 | #define FE_AD_REG_PD__A 0xC10013 |
| 1325 | #define FE_AD_REG_PD__W 1 | 1325 | #define FE_AD_REG_PD__W 1 |
| 1326 | #define FE_AD_REG_PD__M 0x1 | 1326 | #define FE_AD_REG_PD__M 0x1 |
| 1327 | #define FE_AD_REG_PD_INIT 0x1 | 1327 | #define FE_AD_REG_PD_INIT 0x1 |
| 1328 | 1328 | ||
| 1329 | #define FE_AD_REG_INVEXT__A 0xC10014 | 1329 | #define FE_AD_REG_INVEXT__A 0xC10014 |
| 1330 | #define FE_AD_REG_INVEXT__W 1 | 1330 | #define FE_AD_REG_INVEXT__W 1 |
| 1331 | #define FE_AD_REG_INVEXT__M 0x1 | 1331 | #define FE_AD_REG_INVEXT__M 0x1 |
| 1332 | #define FE_AD_REG_INVEXT_INIT 0x0 | 1332 | #define FE_AD_REG_INVEXT_INIT 0x0 |
| 1333 | 1333 | ||
| 1334 | #define FE_AD_REG_CLKNEG__A 0xC10015 | 1334 | #define FE_AD_REG_CLKNEG__A 0xC10015 |
| 1335 | #define FE_AD_REG_CLKNEG__W 1 | 1335 | #define FE_AD_REG_CLKNEG__W 1 |
| 1336 | #define FE_AD_REG_CLKNEG__M 0x1 | 1336 | #define FE_AD_REG_CLKNEG__M 0x1 |
| 1337 | #define FE_AD_REG_CLKNEG_INIT 0x0 | 1337 | #define FE_AD_REG_CLKNEG_INIT 0x0 |
| 1338 | 1338 | ||
| 1339 | #define FE_AD_REG_MON_IN_MUX__A 0xC10016 | 1339 | #define FE_AD_REG_MON_IN_MUX__A 0xC10016 |
| 1340 | #define FE_AD_REG_MON_IN_MUX__W 2 | 1340 | #define FE_AD_REG_MON_IN_MUX__W 2 |
| 1341 | #define FE_AD_REG_MON_IN_MUX__M 0x3 | 1341 | #define FE_AD_REG_MON_IN_MUX__M 0x3 |
| 1342 | #define FE_AD_REG_MON_IN_MUX_INIT 0x0 | 1342 | #define FE_AD_REG_MON_IN_MUX_INIT 0x0 |
| 1343 | 1343 | ||
| 1344 | #define FE_AD_REG_MON_IN5__A 0xC10017 | 1344 | #define FE_AD_REG_MON_IN5__A 0xC10017 |
| 1345 | #define FE_AD_REG_MON_IN5__W 10 | 1345 | #define FE_AD_REG_MON_IN5__W 10 |
| 1346 | #define FE_AD_REG_MON_IN5__M 0x3FF | 1346 | #define FE_AD_REG_MON_IN5__M 0x3FF |
| 1347 | #define FE_AD_REG_MON_IN5_INIT 0x0 | 1347 | #define FE_AD_REG_MON_IN5_INIT 0x0 |
| 1348 | 1348 | ||
| 1349 | #define FE_AD_REG_MON_IN4__A 0xC10018 | 1349 | #define FE_AD_REG_MON_IN4__A 0xC10018 |
| 1350 | #define FE_AD_REG_MON_IN4__W 10 | 1350 | #define FE_AD_REG_MON_IN4__W 10 |
| 1351 | #define FE_AD_REG_MON_IN4__M 0x3FF | 1351 | #define FE_AD_REG_MON_IN4__M 0x3FF |
| 1352 | #define FE_AD_REG_MON_IN4_INIT 0x0 | 1352 | #define FE_AD_REG_MON_IN4_INIT 0x0 |
| 1353 | 1353 | ||
| 1354 | #define FE_AD_REG_MON_IN3__A 0xC10019 | 1354 | #define FE_AD_REG_MON_IN3__A 0xC10019 |
| 1355 | #define FE_AD_REG_MON_IN3__W 10 | 1355 | #define FE_AD_REG_MON_IN3__W 10 |
| 1356 | #define FE_AD_REG_MON_IN3__M 0x3FF | 1356 | #define FE_AD_REG_MON_IN3__M 0x3FF |
| 1357 | #define FE_AD_REG_MON_IN3_INIT 0x0 | 1357 | #define FE_AD_REG_MON_IN3_INIT 0x0 |
| 1358 | 1358 | ||
| 1359 | #define FE_AD_REG_MON_IN2__A 0xC1001A | 1359 | #define FE_AD_REG_MON_IN2__A 0xC1001A |
| 1360 | #define FE_AD_REG_MON_IN2__W 10 | 1360 | #define FE_AD_REG_MON_IN2__W 10 |
| 1361 | #define FE_AD_REG_MON_IN2__M 0x3FF | 1361 | #define FE_AD_REG_MON_IN2__M 0x3FF |
| 1362 | #define FE_AD_REG_MON_IN2_INIT 0x0 | 1362 | #define FE_AD_REG_MON_IN2_INIT 0x0 |
| 1363 | 1363 | ||
| 1364 | #define FE_AD_REG_MON_IN1__A 0xC1001B | 1364 | #define FE_AD_REG_MON_IN1__A 0xC1001B |
| 1365 | #define FE_AD_REG_MON_IN1__W 10 | 1365 | #define FE_AD_REG_MON_IN1__W 10 |
| 1366 | #define FE_AD_REG_MON_IN1__M 0x3FF | 1366 | #define FE_AD_REG_MON_IN1__M 0x3FF |
| 1367 | #define FE_AD_REG_MON_IN1_INIT 0x0 | 1367 | #define FE_AD_REG_MON_IN1_INIT 0x0 |
| 1368 | 1368 | ||
| 1369 | #define FE_AD_REG_MON_IN0__A 0xC1001C | 1369 | #define FE_AD_REG_MON_IN0__A 0xC1001C |
| 1370 | #define FE_AD_REG_MON_IN0__W 10 | 1370 | #define FE_AD_REG_MON_IN0__W 10 |
| 1371 | #define FE_AD_REG_MON_IN0__M 0x3FF | 1371 | #define FE_AD_REG_MON_IN0__M 0x3FF |
| 1372 | #define FE_AD_REG_MON_IN0_INIT 0x0 | 1372 | #define FE_AD_REG_MON_IN0_INIT 0x0 |
| 1373 | 1373 | ||
| 1374 | #define FE_AD_REG_MON_IN_VAL__A 0xC1001D | 1374 | #define FE_AD_REG_MON_IN_VAL__A 0xC1001D |
| 1375 | #define FE_AD_REG_MON_IN_VAL__W 1 | 1375 | #define FE_AD_REG_MON_IN_VAL__W 1 |
| 1376 | #define FE_AD_REG_MON_IN_VAL__M 0x1 | 1376 | #define FE_AD_REG_MON_IN_VAL__M 0x1 |
| 1377 | #define FE_AD_REG_MON_IN_VAL_INIT 0x0 | 1377 | #define FE_AD_REG_MON_IN_VAL_INIT 0x0 |
| 1378 | 1378 | ||
| 1379 | #define FE_AD_REG_CTR_CLK_O__A 0xC1001E | 1379 | #define FE_AD_REG_CTR_CLK_O__A 0xC1001E |
| 1380 | #define FE_AD_REG_CTR_CLK_O__W 1 | 1380 | #define FE_AD_REG_CTR_CLK_O__W 1 |
| 1381 | #define FE_AD_REG_CTR_CLK_O__M 0x1 | 1381 | #define FE_AD_REG_CTR_CLK_O__M 0x1 |
| 1382 | #define FE_AD_REG_CTR_CLK_O_INIT 0x0 | 1382 | #define FE_AD_REG_CTR_CLK_O_INIT 0x0 |
| 1383 | 1383 | ||
| 1384 | #define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F | 1384 | #define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F |
| 1385 | #define FE_AD_REG_CTR_CLK_E_O__W 1 | 1385 | #define FE_AD_REG_CTR_CLK_E_O__W 1 |
| 1386 | #define FE_AD_REG_CTR_CLK_E_O__M 0x1 | 1386 | #define FE_AD_REG_CTR_CLK_E_O__M 0x1 |
| 1387 | #define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 | 1387 | #define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 |
| 1388 | 1388 | ||
| 1389 | #define FE_AD_REG_CTR_VAL_O__A 0xC10020 | 1389 | #define FE_AD_REG_CTR_VAL_O__A 0xC10020 |
| 1390 | #define FE_AD_REG_CTR_VAL_O__W 1 | 1390 | #define FE_AD_REG_CTR_VAL_O__W 1 |
| 1391 | #define FE_AD_REG_CTR_VAL_O__M 0x1 | 1391 | #define FE_AD_REG_CTR_VAL_O__M 0x1 |
| 1392 | #define FE_AD_REG_CTR_VAL_O_INIT 0x0 | 1392 | #define FE_AD_REG_CTR_VAL_O_INIT 0x0 |
| 1393 | 1393 | ||
| 1394 | #define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 | 1394 | #define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 |
| 1395 | #define FE_AD_REG_CTR_VAL_E_O__W 1 | 1395 | #define FE_AD_REG_CTR_VAL_E_O__W 1 |
| 1396 | #define FE_AD_REG_CTR_VAL_E_O__M 0x1 | 1396 | #define FE_AD_REG_CTR_VAL_E_O__M 0x1 |
| 1397 | #define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 | 1397 | #define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 |
| 1398 | 1398 | ||
| 1399 | #define FE_AD_REG_CTR_DATA_O__A 0xC10022 | 1399 | #define FE_AD_REG_CTR_DATA_O__A 0xC10022 |
| 1400 | #define FE_AD_REG_CTR_DATA_O__W 10 | 1400 | #define FE_AD_REG_CTR_DATA_O__W 10 |
| 1401 | #define FE_AD_REG_CTR_DATA_O__M 0x3FF | 1401 | #define FE_AD_REG_CTR_DATA_O__M 0x3FF |
| 1402 | #define FE_AD_REG_CTR_DATA_O_INIT 0x0 | 1402 | #define FE_AD_REG_CTR_DATA_O_INIT 0x0 |
| 1403 | 1403 | ||
| 1404 | #define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 | 1404 | #define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 |
| 1405 | #define FE_AD_REG_CTR_DATA_E_O__W 10 | 1405 | #define FE_AD_REG_CTR_DATA_E_O__W 10 |
| 1406 | #define FE_AD_REG_CTR_DATA_E_O__M 0x3FF | 1406 | #define FE_AD_REG_CTR_DATA_E_O__M 0x3FF |
| 1407 | #define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF | 1407 | #define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF |
| 1408 | 1408 | ||
| 1409 | #define FE_AG_SID 0x2 | 1409 | #define FE_AG_SID 0x2 |
| 1410 | 1410 | ||
| 1411 | #define FE_AG_REG_COMM_EXEC__A 0xC20000 | 1411 | #define FE_AG_REG_COMM_EXEC__A 0xC20000 |
| 1412 | #define FE_AG_REG_COMM_EXEC__W 3 | 1412 | #define FE_AG_REG_COMM_EXEC__W 3 |
| 1413 | #define FE_AG_REG_COMM_EXEC__M 0x7 | 1413 | #define FE_AG_REG_COMM_EXEC__M 0x7 |
| 1414 | #define FE_AG_REG_COMM_EXEC_CTL__B 0 | 1414 | #define FE_AG_REG_COMM_EXEC_CTL__B 0 |
| 1415 | #define FE_AG_REG_COMM_EXEC_CTL__W 3 | 1415 | #define FE_AG_REG_COMM_EXEC_CTL__W 3 |
| 1416 | #define FE_AG_REG_COMM_EXEC_CTL__M 0x7 | 1416 | #define FE_AG_REG_COMM_EXEC_CTL__M 0x7 |
| 1417 | #define FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 | 1417 | #define FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 |
| 1418 | #define FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 1418 | #define FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 1419 | #define FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 | 1419 | #define FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 1420 | #define FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 | 1420 | #define FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 |
| 1421 | 1421 | ||
| 1422 | #define FE_AG_REG_COMM_STATE__A 0xC20001 | 1422 | #define FE_AG_REG_COMM_STATE__A 0xC20001 |
| 1423 | #define FE_AG_REG_COMM_STATE__W 4 | 1423 | #define FE_AG_REG_COMM_STATE__W 4 |
| 1424 | #define FE_AG_REG_COMM_STATE__M 0xF | 1424 | #define FE_AG_REG_COMM_STATE__M 0xF |
| 1425 | 1425 | ||
| 1426 | #define FE_AG_REG_COMM_MB__A 0xC20002 | 1426 | #define FE_AG_REG_COMM_MB__A 0xC20002 |
| 1427 | #define FE_AG_REG_COMM_MB__W 2 | 1427 | #define FE_AG_REG_COMM_MB__W 2 |
| 1428 | #define FE_AG_REG_COMM_MB__M 0x3 | 1428 | #define FE_AG_REG_COMM_MB__M 0x3 |
| 1429 | #define FE_AG_REG_COMM_MB_CTR__B 0 | 1429 | #define FE_AG_REG_COMM_MB_CTR__B 0 |
| 1430 | #define FE_AG_REG_COMM_MB_CTR__W 1 | 1430 | #define FE_AG_REG_COMM_MB_CTR__W 1 |
| 1431 | #define FE_AG_REG_COMM_MB_CTR__M 0x1 | 1431 | #define FE_AG_REG_COMM_MB_CTR__M 0x1 |
| 1432 | #define FE_AG_REG_COMM_MB_CTR_OFF 0x0 | 1432 | #define FE_AG_REG_COMM_MB_CTR_OFF 0x0 |
| 1433 | #define FE_AG_REG_COMM_MB_CTR_ON 0x1 | 1433 | #define FE_AG_REG_COMM_MB_CTR_ON 0x1 |
| 1434 | #define FE_AG_REG_COMM_MB_OBS__B 1 | 1434 | #define FE_AG_REG_COMM_MB_OBS__B 1 |
| 1435 | #define FE_AG_REG_COMM_MB_OBS__W 1 | 1435 | #define FE_AG_REG_COMM_MB_OBS__W 1 |
| 1436 | #define FE_AG_REG_COMM_MB_OBS__M 0x2 | 1436 | #define FE_AG_REG_COMM_MB_OBS__M 0x2 |
| 1437 | #define FE_AG_REG_COMM_MB_OBS_OFF 0x0 | 1437 | #define FE_AG_REG_COMM_MB_OBS_OFF 0x0 |
| 1438 | #define FE_AG_REG_COMM_MB_OBS_ON 0x2 | 1438 | #define FE_AG_REG_COMM_MB_OBS_ON 0x2 |
| 1439 | 1439 | ||
| 1440 | #define FE_AG_REG_COMM_SERVICE0__A 0xC20003 | 1440 | #define FE_AG_REG_COMM_SERVICE0__A 0xC20003 |
| 1441 | #define FE_AG_REG_COMM_SERVICE0__W 10 | 1441 | #define FE_AG_REG_COMM_SERVICE0__W 10 |
| 1442 | #define FE_AG_REG_COMM_SERVICE0__M 0x3FF | 1442 | #define FE_AG_REG_COMM_SERVICE0__M 0x3FF |
| 1443 | 1443 | ||
| 1444 | #define FE_AG_REG_COMM_SERVICE1__A 0xC20004 | 1444 | #define FE_AG_REG_COMM_SERVICE1__A 0xC20004 |
| 1445 | #define FE_AG_REG_COMM_SERVICE1__W 11 | 1445 | #define FE_AG_REG_COMM_SERVICE1__W 11 |
| 1446 | #define FE_AG_REG_COMM_SERVICE1__M 0x7FF | 1446 | #define FE_AG_REG_COMM_SERVICE1__M 0x7FF |
| 1447 | 1447 | ||
| 1448 | #define FE_AG_REG_COMM_INT_STA__A 0xC20007 | 1448 | #define FE_AG_REG_COMM_INT_STA__A 0xC20007 |
| 1449 | #define FE_AG_REG_COMM_INT_STA__W 8 | 1449 | #define FE_AG_REG_COMM_INT_STA__W 8 |
| 1450 | #define FE_AG_REG_COMM_INT_STA__M 0xFF | 1450 | #define FE_AG_REG_COMM_INT_STA__M 0xFF |
| 1451 | #define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 | 1451 | #define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 |
| 1452 | #define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 | 1452 | #define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 |
| 1453 | #define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 | 1453 | #define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 |
| 1454 | #define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 | 1454 | #define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 |
| 1455 | #define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 | 1455 | #define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 |
| 1456 | #define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 | 1456 | #define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 |
| 1457 | #define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 | 1457 | #define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 |
| 1458 | #define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 | 1458 | #define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 |
| 1459 | #define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 | 1459 | #define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 |
| 1460 | #define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 | 1460 | #define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 |
| 1461 | #define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 | 1461 | #define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 |
| 1462 | #define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 | 1462 | #define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 |
| 1463 | #define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 | 1463 | #define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 |
| 1464 | #define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 | 1464 | #define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 |
| 1465 | #define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 | 1465 | #define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 |
| 1466 | #define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 | 1466 | #define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 |
| 1467 | #define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 | 1467 | #define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 |
| 1468 | #define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 | 1468 | #define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 |
| 1469 | #define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__B 6 | 1469 | #define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__B 6 |
| 1470 | #define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__W 1 | 1470 | #define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__W 1 |
| 1471 | #define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__M 0x40 | 1471 | #define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__M 0x40 |
| 1472 | #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 | 1472 | #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 |
| 1473 | #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 | 1473 | #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 |
| 1474 | #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 | 1474 | #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 |
| 1475 | 1475 | ||
| 1476 | #define FE_AG_REG_COMM_INT_MSK__A 0xC20008 | 1476 | #define FE_AG_REG_COMM_INT_MSK__A 0xC20008 |
| 1477 | #define FE_AG_REG_COMM_INT_MSK__W 8 | 1477 | #define FE_AG_REG_COMM_INT_MSK__W 8 |
| 1478 | #define FE_AG_REG_COMM_INT_MSK__M 0xFF | 1478 | #define FE_AG_REG_COMM_INT_MSK__M 0xFF |
| 1479 | #define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 | 1479 | #define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 |
| 1480 | #define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 | 1480 | #define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 |
| 1481 | #define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 | 1481 | #define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 |
| 1482 | #define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 | 1482 | #define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 |
| 1483 | #define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 | 1483 | #define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 |
| 1484 | #define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 | 1484 | #define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 |
| 1485 | #define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 | 1485 | #define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 |
| 1486 | #define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 | 1486 | #define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 |
| 1487 | #define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 | 1487 | #define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 |
| 1488 | #define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 | 1488 | #define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 |
| 1489 | #define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 | 1489 | #define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 |
| 1490 | #define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 | 1490 | #define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 |
| 1491 | #define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 | 1491 | #define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 |
| 1492 | #define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 | 1492 | #define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 |
| 1493 | #define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 | 1493 | #define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 |
| 1494 | #define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 | 1494 | #define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 |
| 1495 | #define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 | 1495 | #define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 |
| 1496 | #define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 | 1496 | #define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 |
| 1497 | #define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__B 6 | 1497 | #define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__B 6 |
| 1498 | #define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__W 1 | 1498 | #define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__W 1 |
| 1499 | #define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__M 0x40 | 1499 | #define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__M 0x40 |
| 1500 | #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 | 1500 | #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 |
| 1501 | #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 | 1501 | #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 |
| 1502 | #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 | 1502 | #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 |
| 1503 | 1503 | ||
| 1504 | #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 | 1504 | #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 |
| 1505 | #define FE_AG_REG_AG_MODE_LOP__W 16 | 1505 | #define FE_AG_REG_AG_MODE_LOP__W 16 |
| 1506 | #define FE_AG_REG_AG_MODE_LOP__M 0xFFFF | 1506 | #define FE_AG_REG_AG_MODE_LOP__M 0xFFFF |
| 1507 | #define FE_AG_REG_AG_MODE_LOP_INIT 0x0 | 1507 | #define FE_AG_REG_AG_MODE_LOP_INIT 0x0 |
| 1508 | 1508 | ||
| 1509 | #define FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 | 1509 | #define FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 |
| 1510 | #define FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 | 1510 | #define FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 |
| 1511 | #define FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 | 1511 | #define FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 |
| 1512 | #define FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 | 1512 | #define FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 |
| 1513 | #define FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 | 1513 | #define FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 |
| 1514 | 1514 | ||
| 1515 | #define FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 | 1515 | #define FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 |
| 1516 | #define FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 | 1516 | #define FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 |
| 1517 | #define FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 | 1517 | #define FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 |
| 1518 | #define FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 | 1518 | #define FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 |
| 1519 | #define FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 | 1519 | #define FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 |
| 1520 | 1520 | ||
| 1521 | #define FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 | 1521 | #define FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 |
| 1522 | #define FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 | 1522 | #define FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 |
| 1523 | #define FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 | 1523 | #define FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 |
| 1524 | #define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 | 1524 | #define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 |
| 1525 | #define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 | 1525 | #define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 |
| 1526 | 1526 | ||
| 1527 | #define FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 | 1527 | #define FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 |
| 1528 | #define FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 | 1528 | #define FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 |
| 1529 | #define FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 | 1529 | #define FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 |
| 1530 | #define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 | 1530 | #define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 |
| 1531 | #define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 | 1531 | #define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 |
| 1532 | 1532 | ||
| 1533 | #define FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 | 1533 | #define FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 |
| 1534 | #define FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 | 1534 | #define FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 |
| 1535 | #define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 | 1535 | #define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 |
| 1536 | #define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 | 1536 | #define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 |
| 1537 | #define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 | 1537 | #define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 |
| 1538 | 1538 | ||
| 1539 | #define FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 | 1539 | #define FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 |
| 1540 | #define FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 | 1540 | #define FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 |
| 1541 | #define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 | 1541 | #define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 |
| 1542 | #define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 | 1542 | #define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 |
| 1543 | #define FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 | 1543 | #define FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 |
| 1544 | 1544 | ||
| 1545 | #define FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 | 1545 | #define FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 |
| 1546 | #define FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 | 1546 | #define FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 |
| 1547 | #define FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 | 1547 | #define FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 |
| 1548 | #define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 | 1548 | #define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 |
| 1549 | #define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 | 1549 | #define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 |
| 1550 | 1550 | ||
| 1551 | #define FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 | 1551 | #define FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 |
| 1552 | #define FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 | 1552 | #define FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 |
| 1553 | #define FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 | 1553 | #define FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 |
| 1554 | #define FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 | 1554 | #define FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 |
| 1555 | #define FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 | 1555 | #define FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 |
| 1556 | 1556 | ||
| 1557 | #define FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 | 1557 | #define FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 |
| 1558 | #define FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 | 1558 | #define FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 |
| 1559 | #define FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 | 1559 | #define FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 |
| 1560 | #define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 | 1560 | #define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 |
| 1561 | #define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 | 1561 | #define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 |
| 1562 | 1562 | ||
| 1563 | #define FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 | 1563 | #define FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 |
| 1564 | #define FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 | 1564 | #define FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 |
| 1565 | #define FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 | 1565 | #define FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 |
| 1566 | #define FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 | 1566 | #define FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 |
| 1567 | #define FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 | 1567 | #define FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 |
| 1568 | 1568 | ||
| 1569 | #define FE_AG_REG_AG_MODE_LOP_MODE_A__B 10 | 1569 | #define FE_AG_REG_AG_MODE_LOP_MODE_A__B 10 |
| 1570 | #define FE_AG_REG_AG_MODE_LOP_MODE_A__W 1 | 1570 | #define FE_AG_REG_AG_MODE_LOP_MODE_A__W 1 |
| 1571 | #define FE_AG_REG_AG_MODE_LOP_MODE_A__M 0x400 | 1571 | #define FE_AG_REG_AG_MODE_LOP_MODE_A__M 0x400 |
| 1572 | #define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_B 0x0 | 1572 | #define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_B 0x0 |
| 1573 | #define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_CB 0x400 | 1573 | #define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_CB 0x400 |
| 1574 | 1574 | ||
| 1575 | #define FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 | 1575 | #define FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 |
| 1576 | #define FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 | 1576 | #define FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 |
| 1577 | #define FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 | 1577 | #define FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 |
| 1578 | #define FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 | 1578 | #define FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 |
| 1579 | #define FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 | 1579 | #define FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 |
| 1580 | 1580 | ||
| 1581 | #define FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 | 1581 | #define FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 |
| 1582 | #define FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 | 1582 | #define FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 |
| 1583 | #define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 | 1583 | #define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 |
| 1584 | #define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 | 1584 | #define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 |
| 1585 | #define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 | 1585 | #define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 |
| 1586 | 1586 | ||
| 1587 | #define FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 | 1587 | #define FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 |
| 1588 | #define FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 | 1588 | #define FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 |
| 1589 | #define FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 | 1589 | #define FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 |
| 1590 | #define FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 | 1590 | #define FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 |
| 1591 | #define FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 | 1591 | #define FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 |
| 1592 | 1592 | ||
| 1593 | #define FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 | 1593 | #define FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 |
| 1594 | #define FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 | 1594 | #define FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 |
| 1595 | #define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 | 1595 | #define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 |
| 1596 | #define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 | 1596 | #define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 |
| 1597 | #define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 | 1597 | #define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 |
| 1598 | 1598 | ||
| 1599 | #define FE_AG_REG_AG_MODE_LOP_MODE_F__B 15 | 1599 | #define FE_AG_REG_AG_MODE_LOP_MODE_F__B 15 |
| 1600 | #define FE_AG_REG_AG_MODE_LOP_MODE_F__W 1 | 1600 | #define FE_AG_REG_AG_MODE_LOP_MODE_F__W 1 |
| 1601 | #define FE_AG_REG_AG_MODE_LOP_MODE_F__M 0x8000 | 1601 | #define FE_AG_REG_AG_MODE_LOP_MODE_F__M 0x8000 |
| 1602 | #define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 | 1602 | #define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 |
| 1603 | #define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 | 1603 | #define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 |
| 1604 | 1604 | ||
| 1605 | #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 | 1605 | #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 |
| 1606 | #define FE_AG_REG_AG_MODE_HIP__W 2 | 1606 | #define FE_AG_REG_AG_MODE_HIP__W 2 |
| 1607 | #define FE_AG_REG_AG_MODE_HIP__M 0x3 | 1607 | #define FE_AG_REG_AG_MODE_HIP__M 0x3 |
| 1608 | #define FE_AG_REG_AG_MODE_HIP_INIT 0x0 | 1608 | #define FE_AG_REG_AG_MODE_HIP_INIT 0x0 |
| 1609 | 1609 | ||
| 1610 | #define FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 | 1610 | #define FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 |
| 1611 | #define FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 | 1611 | #define FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 |
| 1612 | #define FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 | 1612 | #define FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 |
| 1613 | #define FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 | 1613 | #define FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 |
| 1614 | #define FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 | 1614 | #define FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 |
| 1615 | 1615 | ||
| 1616 | #define FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 | 1616 | #define FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 |
| 1617 | #define FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 | 1617 | #define FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 |
| 1618 | #define FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 | 1618 | #define FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 |
| 1619 | #define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 | 1619 | #define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 |
| 1620 | #define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 | 1620 | #define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 |
| 1621 | 1621 | ||
| 1622 | #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 | 1622 | #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 |
| 1623 | #define FE_AG_REG_AG_PGA_MODE__W 3 | 1623 | #define FE_AG_REG_AG_PGA_MODE__W 3 |
| 1624 | #define FE_AG_REG_AG_PGA_MODE__M 0x7 | 1624 | #define FE_AG_REG_AG_PGA_MODE__M 0x7 |
| 1625 | #define FE_AG_REG_AG_PGA_MODE_INIT 0x0 | 1625 | #define FE_AG_REG_AG_PGA_MODE_INIT 0x0 |
| 1626 | #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 | 1626 | #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 |
| 1627 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 | 1627 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 |
| 1628 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 | 1628 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 |
| 1629 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 | 1629 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 |
| 1630 | #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 | 1630 | #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 |
| 1631 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 | 1631 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 |
| 1632 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 | 1632 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 |
| 1633 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 | 1633 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 |
| 1634 | 1634 | ||
| 1635 | #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 | 1635 | #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 |
| 1636 | #define FE_AG_REG_AG_AGC_SIO__W 2 | 1636 | #define FE_AG_REG_AG_AGC_SIO__W 2 |
| 1637 | #define FE_AG_REG_AG_AGC_SIO__M 0x3 | 1637 | #define FE_AG_REG_AG_AGC_SIO__M 0x3 |
| 1638 | #define FE_AG_REG_AG_AGC_SIO_INIT 0x3 | 1638 | #define FE_AG_REG_AG_AGC_SIO_INIT 0x3 |
| 1639 | 1639 | ||
| 1640 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 | 1640 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 |
| 1641 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 | 1641 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 |
| 1642 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 | 1642 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 |
| 1643 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 | 1643 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 |
| 1644 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 | 1644 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 |
| 1645 | 1645 | ||
| 1646 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 | 1646 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 |
| 1647 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 | 1647 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 |
| 1648 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 | 1648 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 |
| 1649 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 | 1649 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 |
| 1650 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 | 1650 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 |
| 1651 | 1651 | ||
| 1652 | #define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 | 1652 | #define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 |
| 1653 | #define FE_AG_REG_AG_AGC_USR_DAT__W 2 | 1653 | #define FE_AG_REG_AG_AGC_USR_DAT__W 2 |
| 1654 | #define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 | 1654 | #define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 |
| 1655 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 | 1655 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 |
| 1656 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 | 1656 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 |
| 1657 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 | 1657 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 |
| 1658 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 | 1658 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 |
| 1659 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 | 1659 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 |
| 1660 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 | 1660 | #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 |
| 1661 | 1661 | ||
| 1662 | #define FE_AG_REG_AG_PWD__A 0xC20015 | 1662 | #define FE_AG_REG_AG_PWD__A 0xC20015 |
| 1663 | #define FE_AG_REG_AG_PWD__W 5 | 1663 | #define FE_AG_REG_AG_PWD__W 5 |
| 1664 | #define FE_AG_REG_AG_PWD__M 0x1F | 1664 | #define FE_AG_REG_AG_PWD__M 0x1F |
| 1665 | #define FE_AG_REG_AG_PWD_INIT 0x1F | 1665 | #define FE_AG_REG_AG_PWD_INIT 0x1F |
| 1666 | 1666 | ||
| 1667 | #define FE_AG_REG_AG_PWD_PWD_PD1__B 0 | 1667 | #define FE_AG_REG_AG_PWD_PWD_PD1__B 0 |
| 1668 | #define FE_AG_REG_AG_PWD_PWD_PD1__W 1 | 1668 | #define FE_AG_REG_AG_PWD_PWD_PD1__W 1 |
| 1669 | #define FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 | 1669 | #define FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 |
| 1670 | #define FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 | 1670 | #define FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 |
| 1671 | #define FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 | 1671 | #define FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 |
| 1672 | 1672 | ||
| 1673 | #define FE_AG_REG_AG_PWD_PWD_PD2__B 1 | 1673 | #define FE_AG_REG_AG_PWD_PWD_PD2__B 1 |
| 1674 | #define FE_AG_REG_AG_PWD_PWD_PD2__W 1 | 1674 | #define FE_AG_REG_AG_PWD_PWD_PD2__W 1 |
| 1675 | #define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 | 1675 | #define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 |
| 1676 | #define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 | 1676 | #define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 |
| 1677 | #define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 | 1677 | #define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 |
| 1678 | 1678 | ||
| 1679 | #define FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 | 1679 | #define FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 |
| 1680 | #define FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 | 1680 | #define FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 |
| 1681 | #define FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 | 1681 | #define FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 |
| 1682 | #define FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 | 1682 | #define FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 |
| 1683 | #define FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 | 1683 | #define FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 |
| 1684 | 1684 | ||
| 1685 | #define FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 | 1685 | #define FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 |
| 1686 | #define FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 | 1686 | #define FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 |
| 1687 | #define FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 | 1687 | #define FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 |
| 1688 | #define FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 | 1688 | #define FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 |
| 1689 | #define FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 | 1689 | #define FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 |
| 1690 | 1690 | ||
| 1691 | #define FE_AG_REG_AG_PWD_PWD_AAF__B 4 | 1691 | #define FE_AG_REG_AG_PWD_PWD_AAF__B 4 |
| 1692 | #define FE_AG_REG_AG_PWD_PWD_AAF__W 1 | 1692 | #define FE_AG_REG_AG_PWD_PWD_AAF__W 1 |
| 1693 | #define FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 | 1693 | #define FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 |
| 1694 | #define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 | 1694 | #define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 |
| 1695 | #define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 | 1695 | #define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 |
| 1696 | 1696 | ||
| 1697 | #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 | 1697 | #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 |
| 1698 | #define FE_AG_REG_DCE_AUR_CNT__W 5 | 1698 | #define FE_AG_REG_DCE_AUR_CNT__W 5 |
| 1699 | #define FE_AG_REG_DCE_AUR_CNT__M 0x1F | 1699 | #define FE_AG_REG_DCE_AUR_CNT__M 0x1F |
| 1700 | #define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 | 1700 | #define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 |
| 1701 | 1701 | ||
| 1702 | #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 | 1702 | #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 |
| 1703 | #define FE_AG_REG_DCE_RUR_CNT__W 5 | 1703 | #define FE_AG_REG_DCE_RUR_CNT__W 5 |
| 1704 | #define FE_AG_REG_DCE_RUR_CNT__M 0x1F | 1704 | #define FE_AG_REG_DCE_RUR_CNT__M 0x1F |
| 1705 | #define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 | 1705 | #define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 |
| 1706 | 1706 | ||
| 1707 | #define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 | 1707 | #define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 |
| 1708 | #define FE_AG_REG_DCE_AVE_DAT__W 10 | 1708 | #define FE_AG_REG_DCE_AVE_DAT__W 10 |
| 1709 | #define FE_AG_REG_DCE_AVE_DAT__M 0x3FF | 1709 | #define FE_AG_REG_DCE_AVE_DAT__M 0x3FF |
| 1710 | 1710 | ||
| 1711 | #define FE_AG_REG_DEC_AVE_WRI__A 0xC20019 | 1711 | #define FE_AG_REG_DEC_AVE_WRI__A 0xC20019 |
| 1712 | #define FE_AG_REG_DEC_AVE_WRI__W 10 | 1712 | #define FE_AG_REG_DEC_AVE_WRI__W 10 |
| 1713 | #define FE_AG_REG_DEC_AVE_WRI__M 0x3FF | 1713 | #define FE_AG_REG_DEC_AVE_WRI__M 0x3FF |
| 1714 | #define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 | 1714 | #define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 |
| 1715 | 1715 | ||
| 1716 | #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A | 1716 | #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A |
| 1717 | #define FE_AG_REG_ACE_AUR_CNT__W 5 | 1717 | #define FE_AG_REG_ACE_AUR_CNT__W 5 |
| 1718 | #define FE_AG_REG_ACE_AUR_CNT__M 0x1F | 1718 | #define FE_AG_REG_ACE_AUR_CNT__M 0x1F |
| 1719 | #define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 | 1719 | #define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 |
| 1720 | 1720 | ||
| 1721 | #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B | 1721 | #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B |
| 1722 | #define FE_AG_REG_ACE_RUR_CNT__W 5 | 1722 | #define FE_AG_REG_ACE_RUR_CNT__W 5 |
| 1723 | #define FE_AG_REG_ACE_RUR_CNT__M 0x1F | 1723 | #define FE_AG_REG_ACE_RUR_CNT__M 0x1F |
| 1724 | #define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 | 1724 | #define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 |
| 1725 | 1725 | ||
| 1726 | #define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C | 1726 | #define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C |
| 1727 | #define FE_AG_REG_ACE_AVE_DAT__W 10 | 1727 | #define FE_AG_REG_ACE_AVE_DAT__W 10 |
| 1728 | #define FE_AG_REG_ACE_AVE_DAT__M 0x3FF | 1728 | #define FE_AG_REG_ACE_AVE_DAT__M 0x3FF |
| 1729 | 1729 | ||
| 1730 | #define FE_AG_REG_AEC_AVE_INC__A 0xC2001D | 1730 | #define FE_AG_REG_AEC_AVE_INC__A 0xC2001D |
| 1731 | #define FE_AG_REG_AEC_AVE_INC__W 10 | 1731 | #define FE_AG_REG_AEC_AVE_INC__W 10 |
| 1732 | #define FE_AG_REG_AEC_AVE_INC__M 0x3FF | 1732 | #define FE_AG_REG_AEC_AVE_INC__M 0x3FF |
| 1733 | #define FE_AG_REG_AEC_AVE_INC_INIT 0x0 | 1733 | #define FE_AG_REG_AEC_AVE_INC_INIT 0x0 |
| 1734 | 1734 | ||
| 1735 | #define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E | 1735 | #define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E |
| 1736 | #define FE_AG_REG_AEC_AVE_DAT__W 10 | 1736 | #define FE_AG_REG_AEC_AVE_DAT__W 10 |
| 1737 | #define FE_AG_REG_AEC_AVE_DAT__M 0x3FF | 1737 | #define FE_AG_REG_AEC_AVE_DAT__M 0x3FF |
| 1738 | 1738 | ||
| 1739 | #define FE_AG_REG_AEC_CLP_LVL__A 0xC2001F | 1739 | #define FE_AG_REG_AEC_CLP_LVL__A 0xC2001F |
| 1740 | #define FE_AG_REG_AEC_CLP_LVL__W 16 | 1740 | #define FE_AG_REG_AEC_CLP_LVL__W 16 |
| 1741 | #define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF | 1741 | #define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF |
| 1742 | #define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 | 1742 | #define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 |
| 1743 | 1743 | ||
| 1744 | #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 | 1744 | #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 |
| 1745 | #define FE_AG_REG_CDR_RUR_CNT__W 5 | 1745 | #define FE_AG_REG_CDR_RUR_CNT__W 5 |
| 1746 | #define FE_AG_REG_CDR_RUR_CNT__M 0x1F | 1746 | #define FE_AG_REG_CDR_RUR_CNT__M 0x1F |
| 1747 | #define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 | 1747 | #define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 |
| 1748 | 1748 | ||
| 1749 | #define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 | 1749 | #define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 |
| 1750 | #define FE_AG_REG_CDR_CLP_DAT__W 16 | 1750 | #define FE_AG_REG_CDR_CLP_DAT__W 16 |
| 1751 | #define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF | 1751 | #define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF |
| 1752 | 1752 | ||
| 1753 | #define FE_AG_REG_CDR_CLP_POS__A 0xC20022 | 1753 | #define FE_AG_REG_CDR_CLP_POS__A 0xC20022 |
| 1754 | #define FE_AG_REG_CDR_CLP_POS__W 10 | 1754 | #define FE_AG_REG_CDR_CLP_POS__W 10 |
| 1755 | #define FE_AG_REG_CDR_CLP_POS__M 0x3FF | 1755 | #define FE_AG_REG_CDR_CLP_POS__M 0x3FF |
| 1756 | #define FE_AG_REG_CDR_CLP_POS_INIT 0x0 | 1756 | #define FE_AG_REG_CDR_CLP_POS_INIT 0x0 |
| 1757 | 1757 | ||
| 1758 | #define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 | 1758 | #define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 |
| 1759 | #define FE_AG_REG_CDR_CLP_NEG__W 10 | 1759 | #define FE_AG_REG_CDR_CLP_NEG__W 10 |
| 1760 | #define FE_AG_REG_CDR_CLP_NEG__M 0x3FF | 1760 | #define FE_AG_REG_CDR_CLP_NEG__M 0x3FF |
| 1761 | #define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 | 1761 | #define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 |
| 1762 | 1762 | ||
| 1763 | #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 | 1763 | #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 |
| 1764 | #define FE_AG_REG_EGC_RUR_CNT__W 5 | 1764 | #define FE_AG_REG_EGC_RUR_CNT__W 5 |
| 1765 | #define FE_AG_REG_EGC_RUR_CNT__M 0x1F | 1765 | #define FE_AG_REG_EGC_RUR_CNT__M 0x1F |
| 1766 | #define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 | 1766 | #define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 |
| 1767 | 1767 | ||
| 1768 | #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 | 1768 | #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 |
| 1769 | #define FE_AG_REG_EGC_SET_LVL__W 9 | 1769 | #define FE_AG_REG_EGC_SET_LVL__W 9 |
| 1770 | #define FE_AG_REG_EGC_SET_LVL__M 0x1FF | 1770 | #define FE_AG_REG_EGC_SET_LVL__M 0x1FF |
| 1771 | #define FE_AG_REG_EGC_SET_LVL_INIT 0x0 | 1771 | #define FE_AG_REG_EGC_SET_LVL_INIT 0x0 |
| 1772 | 1772 | ||
| 1773 | #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 | 1773 | #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 |
| 1774 | #define FE_AG_REG_EGC_FLA_RGN__W 9 | 1774 | #define FE_AG_REG_EGC_FLA_RGN__W 9 |
| 1775 | #define FE_AG_REG_EGC_FLA_RGN__M 0x1FF | 1775 | #define FE_AG_REG_EGC_FLA_RGN__M 0x1FF |
| 1776 | #define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 | 1776 | #define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 |
| 1777 | 1777 | ||
| 1778 | #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 | 1778 | #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 |
| 1779 | #define FE_AG_REG_EGC_SLO_RGN__W 9 | 1779 | #define FE_AG_REG_EGC_SLO_RGN__W 9 |
| 1780 | #define FE_AG_REG_EGC_SLO_RGN__M 0x1FF | 1780 | #define FE_AG_REG_EGC_SLO_RGN__M 0x1FF |
| 1781 | #define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 | 1781 | #define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 |
| 1782 | 1782 | ||
| 1783 | #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 | 1783 | #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 |
| 1784 | #define FE_AG_REG_EGC_JMP_PSN__W 4 | 1784 | #define FE_AG_REG_EGC_JMP_PSN__W 4 |
| 1785 | #define FE_AG_REG_EGC_JMP_PSN__M 0xF | 1785 | #define FE_AG_REG_EGC_JMP_PSN__M 0xF |
| 1786 | #define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 | 1786 | #define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 |
| 1787 | 1787 | ||
| 1788 | #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 | 1788 | #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 |
| 1789 | #define FE_AG_REG_EGC_FLA_INC__W 16 | 1789 | #define FE_AG_REG_EGC_FLA_INC__W 16 |
| 1790 | #define FE_AG_REG_EGC_FLA_INC__M 0xFFFF | 1790 | #define FE_AG_REG_EGC_FLA_INC__M 0xFFFF |
| 1791 | #define FE_AG_REG_EGC_FLA_INC_INIT 0x0 | 1791 | #define FE_AG_REG_EGC_FLA_INC_INIT 0x0 |
| 1792 | 1792 | ||
| 1793 | #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A | 1793 | #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A |
| 1794 | #define FE_AG_REG_EGC_FLA_DEC__W 16 | 1794 | #define FE_AG_REG_EGC_FLA_DEC__W 16 |
| 1795 | #define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF | 1795 | #define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF |
| 1796 | #define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 | 1796 | #define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 |
| 1797 | 1797 | ||
| 1798 | #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B | 1798 | #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B |
| 1799 | #define FE_AG_REG_EGC_SLO_INC__W 16 | 1799 | #define FE_AG_REG_EGC_SLO_INC__W 16 |
| 1800 | #define FE_AG_REG_EGC_SLO_INC__M 0xFFFF | 1800 | #define FE_AG_REG_EGC_SLO_INC__M 0xFFFF |
| 1801 | #define FE_AG_REG_EGC_SLO_INC_INIT 0x0 | 1801 | #define FE_AG_REG_EGC_SLO_INC_INIT 0x0 |
| 1802 | 1802 | ||
| 1803 | #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C | 1803 | #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C |
| 1804 | #define FE_AG_REG_EGC_SLO_DEC__W 16 | 1804 | #define FE_AG_REG_EGC_SLO_DEC__W 16 |
| 1805 | #define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF | 1805 | #define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF |
| 1806 | #define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 | 1806 | #define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 |
| 1807 | 1807 | ||
| 1808 | #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D | 1808 | #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D |
| 1809 | #define FE_AG_REG_EGC_FAS_INC__W 16 | 1809 | #define FE_AG_REG_EGC_FAS_INC__W 16 |
| 1810 | #define FE_AG_REG_EGC_FAS_INC__M 0xFFFF | 1810 | #define FE_AG_REG_EGC_FAS_INC__M 0xFFFF |
| 1811 | #define FE_AG_REG_EGC_FAS_INC_INIT 0x0 | 1811 | #define FE_AG_REG_EGC_FAS_INC_INIT 0x0 |
| 1812 | 1812 | ||
| 1813 | #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E | 1813 | #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E |
| 1814 | #define FE_AG_REG_EGC_FAS_DEC__W 16 | 1814 | #define FE_AG_REG_EGC_FAS_DEC__W 16 |
| 1815 | #define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF | 1815 | #define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF |
| 1816 | #define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 | 1816 | #define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 |
| 1817 | 1817 | ||
| 1818 | #define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F | 1818 | #define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F |
| 1819 | #define FE_AG_REG_EGC_MAP_DAT__W 16 | 1819 | #define FE_AG_REG_EGC_MAP_DAT__W 16 |
| 1820 | #define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF | 1820 | #define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF |
| 1821 | 1821 | ||
| 1822 | #define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 | 1822 | #define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 |
| 1823 | #define FE_AG_REG_PM1_AGC_WRI__W 11 | 1823 | #define FE_AG_REG_PM1_AGC_WRI__W 11 |
| 1824 | #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF | 1824 | #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF |
| 1825 | #define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 | 1825 | #define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 |
| 1826 | 1826 | ||
| 1827 | #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 | 1827 | #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 |
| 1828 | #define FE_AG_REG_GC1_AGC_RIC__W 16 | 1828 | #define FE_AG_REG_GC1_AGC_RIC__W 16 |
| 1829 | #define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF | 1829 | #define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF |
| 1830 | #define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 | 1830 | #define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 |
| 1831 | 1831 | ||
| 1832 | #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 | 1832 | #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 |
| 1833 | #define FE_AG_REG_GC1_AGC_OFF__W 16 | 1833 | #define FE_AG_REG_GC1_AGC_OFF__W 16 |
| 1834 | #define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF | 1834 | #define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF |
| 1835 | #define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 | 1835 | #define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 |
| 1836 | 1836 | ||
| 1837 | #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 | 1837 | #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 |
| 1838 | #define FE_AG_REG_GC1_AGC_MAX__W 10 | 1838 | #define FE_AG_REG_GC1_AGC_MAX__W 10 |
| 1839 | #define FE_AG_REG_GC1_AGC_MAX__M 0x3FF | 1839 | #define FE_AG_REG_GC1_AGC_MAX__M 0x3FF |
| 1840 | #define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 | 1840 | #define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 |
| 1841 | 1841 | ||
| 1842 | #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 | 1842 | #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 |
| 1843 | #define FE_AG_REG_GC1_AGC_MIN__W 10 | 1843 | #define FE_AG_REG_GC1_AGC_MIN__W 10 |
| 1844 | #define FE_AG_REG_GC1_AGC_MIN__M 0x3FF | 1844 | #define FE_AG_REG_GC1_AGC_MIN__M 0x3FF |
| 1845 | #define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 | 1845 | #define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 |
| 1846 | 1846 | ||
| 1847 | #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 | 1847 | #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 |
| 1848 | #define FE_AG_REG_GC1_AGC_DAT__W 10 | 1848 | #define FE_AG_REG_GC1_AGC_DAT__W 10 |
| 1849 | #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF | 1849 | #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF |
| 1850 | 1850 | ||
| 1851 | #define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 | 1851 | #define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 |
| 1852 | #define FE_AG_REG_PM2_AGC_WRI__W 11 | 1852 | #define FE_AG_REG_PM2_AGC_WRI__W 11 |
| 1853 | #define FE_AG_REG_PM2_AGC_WRI__M 0x7FF | 1853 | #define FE_AG_REG_PM2_AGC_WRI__M 0x7FF |
| 1854 | #define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 | 1854 | #define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 |
| 1855 | 1855 | ||
| 1856 | #define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 | 1856 | #define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 |
| 1857 | #define FE_AG_REG_GC2_AGC_RIC__W 16 | 1857 | #define FE_AG_REG_GC2_AGC_RIC__W 16 |
| 1858 | #define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF | 1858 | #define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF |
| 1859 | #define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 | 1859 | #define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 |
| 1860 | 1860 | ||
| 1861 | #define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 | 1861 | #define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 |
| 1862 | #define FE_AG_REG_GC2_AGC_OFF__W 16 | 1862 | #define FE_AG_REG_GC2_AGC_OFF__W 16 |
| 1863 | #define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF | 1863 | #define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF |
| 1864 | #define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 | 1864 | #define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 |
| 1865 | 1865 | ||
| 1866 | #define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 | 1866 | #define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 |
| 1867 | #define FE_AG_REG_GC2_AGC_MAX__W 10 | 1867 | #define FE_AG_REG_GC2_AGC_MAX__W 10 |
| 1868 | #define FE_AG_REG_GC2_AGC_MAX__M 0x3FF | 1868 | #define FE_AG_REG_GC2_AGC_MAX__M 0x3FF |
| 1869 | #define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 | 1869 | #define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 |
| 1870 | 1870 | ||
| 1871 | #define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A | 1871 | #define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A |
| 1872 | #define FE_AG_REG_GC2_AGC_MIN__W 10 | 1872 | #define FE_AG_REG_GC2_AGC_MIN__W 10 |
| 1873 | #define FE_AG_REG_GC2_AGC_MIN__M 0x3FF | 1873 | #define FE_AG_REG_GC2_AGC_MIN__M 0x3FF |
| 1874 | #define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 | 1874 | #define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 |
| 1875 | 1875 | ||
| 1876 | #define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B | 1876 | #define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B |
| 1877 | #define FE_AG_REG_GC2_AGC_DAT__W 10 | 1877 | #define FE_AG_REG_GC2_AGC_DAT__W 10 |
| 1878 | #define FE_AG_REG_GC2_AGC_DAT__M 0x3FF | 1878 | #define FE_AG_REG_GC2_AGC_DAT__M 0x3FF |
| 1879 | 1879 | ||
| 1880 | #define FE_AG_REG_IND_WIN__A 0xC2003C | 1880 | #define FE_AG_REG_IND_WIN__A 0xC2003C |
| 1881 | #define FE_AG_REG_IND_WIN__W 5 | 1881 | #define FE_AG_REG_IND_WIN__W 5 |
| 1882 | #define FE_AG_REG_IND_WIN__M 0x1F | 1882 | #define FE_AG_REG_IND_WIN__M 0x1F |
| 1883 | #define FE_AG_REG_IND_WIN_INIT 0x0 | 1883 | #define FE_AG_REG_IND_WIN_INIT 0x0 |
| 1884 | 1884 | ||
| 1885 | #define FE_AG_REG_IND_THD_LOL__A 0xC2003D | 1885 | #define FE_AG_REG_IND_THD_LOL__A 0xC2003D |
| 1886 | #define FE_AG_REG_IND_THD_LOL__W 6 | 1886 | #define FE_AG_REG_IND_THD_LOL__W 6 |
| 1887 | #define FE_AG_REG_IND_THD_LOL__M 0x3F | 1887 | #define FE_AG_REG_IND_THD_LOL__M 0x3F |
| 1888 | #define FE_AG_REG_IND_THD_LOL_INIT 0x0 | 1888 | #define FE_AG_REG_IND_THD_LOL_INIT 0x0 |
| 1889 | 1889 | ||
| 1890 | #define FE_AG_REG_IND_THD_HIL__A 0xC2003E | 1890 | #define FE_AG_REG_IND_THD_HIL__A 0xC2003E |
| 1891 | #define FE_AG_REG_IND_THD_HIL__W 6 | 1891 | #define FE_AG_REG_IND_THD_HIL__W 6 |
| 1892 | #define FE_AG_REG_IND_THD_HIL__M 0x3F | 1892 | #define FE_AG_REG_IND_THD_HIL__M 0x3F |
| 1893 | #define FE_AG_REG_IND_THD_HIL_INIT 0x0 | 1893 | #define FE_AG_REG_IND_THD_HIL_INIT 0x0 |
| 1894 | 1894 | ||
| 1895 | #define FE_AG_REG_IND_DEL__A 0xC2003F | 1895 | #define FE_AG_REG_IND_DEL__A 0xC2003F |
| 1896 | #define FE_AG_REG_IND_DEL__W 7 | 1896 | #define FE_AG_REG_IND_DEL__W 7 |
| 1897 | #define FE_AG_REG_IND_DEL__M 0x7F | 1897 | #define FE_AG_REG_IND_DEL__M 0x7F |
| 1898 | #define FE_AG_REG_IND_DEL_INIT 0x0 | 1898 | #define FE_AG_REG_IND_DEL_INIT 0x0 |
| 1899 | 1899 | ||
| 1900 | #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 | 1900 | #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 |
| 1901 | #define FE_AG_REG_IND_PD1_WRI__W 6 | 1901 | #define FE_AG_REG_IND_PD1_WRI__W 6 |
| 1902 | #define FE_AG_REG_IND_PD1_WRI__M 0x3F | 1902 | #define FE_AG_REG_IND_PD1_WRI__M 0x3F |
| 1903 | #define FE_AG_REG_IND_PD1_WRI_INIT 0x1F | 1903 | #define FE_AG_REG_IND_PD1_WRI_INIT 0x1F |
| 1904 | 1904 | ||
| 1905 | #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 | 1905 | #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 |
| 1906 | #define FE_AG_REG_PDA_AUR_CNT__W 5 | 1906 | #define FE_AG_REG_PDA_AUR_CNT__W 5 |
| 1907 | #define FE_AG_REG_PDA_AUR_CNT__M 0x1F | 1907 | #define FE_AG_REG_PDA_AUR_CNT__M 0x1F |
| 1908 | #define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 | 1908 | #define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 |
| 1909 | 1909 | ||
| 1910 | #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 | 1910 | #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 |
| 1911 | #define FE_AG_REG_PDA_RUR_CNT__W 5 | 1911 | #define FE_AG_REG_PDA_RUR_CNT__W 5 |
| 1912 | #define FE_AG_REG_PDA_RUR_CNT__M 0x1F | 1912 | #define FE_AG_REG_PDA_RUR_CNT__M 0x1F |
| 1913 | #define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 | 1913 | #define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 |
| 1914 | 1914 | ||
| 1915 | #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 | 1915 | #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 |
| 1916 | #define FE_AG_REG_PDA_AVE_DAT__W 6 | 1916 | #define FE_AG_REG_PDA_AVE_DAT__W 6 |
| 1917 | #define FE_AG_REG_PDA_AVE_DAT__M 0x3F | 1917 | #define FE_AG_REG_PDA_AVE_DAT__M 0x3F |
| 1918 | 1918 | ||
| 1919 | #define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 | 1919 | #define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 |
| 1920 | #define FE_AG_REG_PDC_RUR_CNT__W 5 | 1920 | #define FE_AG_REG_PDC_RUR_CNT__W 5 |
| 1921 | #define FE_AG_REG_PDC_RUR_CNT__M 0x1F | 1921 | #define FE_AG_REG_PDC_RUR_CNT__M 0x1F |
| 1922 | #define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 | 1922 | #define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 |
| 1923 | 1923 | ||
| 1924 | #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 | 1924 | #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 |
| 1925 | #define FE_AG_REG_PDC_SET_LVL__W 6 | 1925 | #define FE_AG_REG_PDC_SET_LVL__W 6 |
| 1926 | #define FE_AG_REG_PDC_SET_LVL__M 0x3F | 1926 | #define FE_AG_REG_PDC_SET_LVL__M 0x3F |
| 1927 | #define FE_AG_REG_PDC_SET_LVL_INIT 0x10 | 1927 | #define FE_AG_REG_PDC_SET_LVL_INIT 0x10 |
| 1928 | 1928 | ||
| 1929 | #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 | 1929 | #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 |
| 1930 | #define FE_AG_REG_PDC_FLA_RGN__W 6 | 1930 | #define FE_AG_REG_PDC_FLA_RGN__W 6 |
| 1931 | #define FE_AG_REG_PDC_FLA_RGN__M 0x3F | 1931 | #define FE_AG_REG_PDC_FLA_RGN__M 0x3F |
| 1932 | #define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 | 1932 | #define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 |
| 1933 | 1933 | ||
| 1934 | #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 | 1934 | #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 |
| 1935 | #define FE_AG_REG_PDC_JMP_PSN__W 3 | 1935 | #define FE_AG_REG_PDC_JMP_PSN__W 3 |
| 1936 | #define FE_AG_REG_PDC_JMP_PSN__M 0x7 | 1936 | #define FE_AG_REG_PDC_JMP_PSN__M 0x7 |
| 1937 | #define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 | 1937 | #define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 |
| 1938 | 1938 | ||
| 1939 | #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 | 1939 | #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 |
| 1940 | #define FE_AG_REG_PDC_FLA_STP__W 16 | 1940 | #define FE_AG_REG_PDC_FLA_STP__W 16 |
| 1941 | #define FE_AG_REG_PDC_FLA_STP__M 0xFFFF | 1941 | #define FE_AG_REG_PDC_FLA_STP__M 0xFFFF |
| 1942 | #define FE_AG_REG_PDC_FLA_STP_INIT 0x0 | 1942 | #define FE_AG_REG_PDC_FLA_STP_INIT 0x0 |
| 1943 | 1943 | ||
| 1944 | #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 | 1944 | #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 |
| 1945 | #define FE_AG_REG_PDC_SLO_STP__W 16 | 1945 | #define FE_AG_REG_PDC_SLO_STP__W 16 |
| 1946 | #define FE_AG_REG_PDC_SLO_STP__M 0xFFFF | 1946 | #define FE_AG_REG_PDC_SLO_STP__M 0xFFFF |
| 1947 | #define FE_AG_REG_PDC_SLO_STP_INIT 0x0 | 1947 | #define FE_AG_REG_PDC_SLO_STP_INIT 0x0 |
| 1948 | 1948 | ||
| 1949 | #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A | 1949 | #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A |
| 1950 | #define FE_AG_REG_PDC_PD2_WRI__W 6 | 1950 | #define FE_AG_REG_PDC_PD2_WRI__W 6 |
| 1951 | #define FE_AG_REG_PDC_PD2_WRI__M 0x3F | 1951 | #define FE_AG_REG_PDC_PD2_WRI__M 0x3F |
| 1952 | #define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 | 1952 | #define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 |
| 1953 | 1953 | ||
| 1954 | #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B | 1954 | #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B |
| 1955 | #define FE_AG_REG_PDC_MAP_DAT__W 6 | 1955 | #define FE_AG_REG_PDC_MAP_DAT__W 6 |
| 1956 | #define FE_AG_REG_PDC_MAP_DAT__M 0x3F | 1956 | #define FE_AG_REG_PDC_MAP_DAT__M 0x3F |
| 1957 | 1957 | ||
| 1958 | #define FE_AG_REG_PDC_MAX__A 0xC2004C | 1958 | #define FE_AG_REG_PDC_MAX__A 0xC2004C |
| 1959 | #define FE_AG_REG_PDC_MAX__W 6 | 1959 | #define FE_AG_REG_PDC_MAX__W 6 |
| 1960 | #define FE_AG_REG_PDC_MAX__M 0x3F | 1960 | #define FE_AG_REG_PDC_MAX__M 0x3F |
| 1961 | #define FE_AG_REG_PDC_MAX_INIT 0x2 | 1961 | #define FE_AG_REG_PDC_MAX_INIT 0x2 |
| 1962 | 1962 | ||
| 1963 | #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D | 1963 | #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D |
| 1964 | #define FE_AG_REG_TGA_AUR_CNT__W 5 | 1964 | #define FE_AG_REG_TGA_AUR_CNT__W 5 |
| 1965 | #define FE_AG_REG_TGA_AUR_CNT__M 0x1F | 1965 | #define FE_AG_REG_TGA_AUR_CNT__M 0x1F |
| 1966 | #define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 | 1966 | #define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 |
| 1967 | 1967 | ||
| 1968 | #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E | 1968 | #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E |
| 1969 | #define FE_AG_REG_TGA_RUR_CNT__W 5 | 1969 | #define FE_AG_REG_TGA_RUR_CNT__W 5 |
| 1970 | #define FE_AG_REG_TGA_RUR_CNT__M 0x1F | 1970 | #define FE_AG_REG_TGA_RUR_CNT__M 0x1F |
| 1971 | #define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 | 1971 | #define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 |
| 1972 | 1972 | ||
| 1973 | #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F | 1973 | #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F |
| 1974 | #define FE_AG_REG_TGA_AVE_DAT__W 6 | 1974 | #define FE_AG_REG_TGA_AVE_DAT__W 6 |
| 1975 | #define FE_AG_REG_TGA_AVE_DAT__M 0x3F | 1975 | #define FE_AG_REG_TGA_AVE_DAT__M 0x3F |
| 1976 | 1976 | ||
| 1977 | #define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 | 1977 | #define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 |
| 1978 | #define FE_AG_REG_TGC_RUR_CNT__W 5 | 1978 | #define FE_AG_REG_TGC_RUR_CNT__W 5 |
| 1979 | #define FE_AG_REG_TGC_RUR_CNT__M 0x1F | 1979 | #define FE_AG_REG_TGC_RUR_CNT__M 0x1F |
| 1980 | #define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 | 1980 | #define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 |
| 1981 | 1981 | ||
| 1982 | #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 | 1982 | #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 |
| 1983 | #define FE_AG_REG_TGC_SET_LVL__W 6 | 1983 | #define FE_AG_REG_TGC_SET_LVL__W 6 |
| 1984 | #define FE_AG_REG_TGC_SET_LVL__M 0x3F | 1984 | #define FE_AG_REG_TGC_SET_LVL__M 0x3F |
| 1985 | #define FE_AG_REG_TGC_SET_LVL_INIT 0x0 | 1985 | #define FE_AG_REG_TGC_SET_LVL_INIT 0x0 |
| 1986 | 1986 | ||
| 1987 | #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 | 1987 | #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 |
| 1988 | #define FE_AG_REG_TGC_FLA_RGN__W 6 | 1988 | #define FE_AG_REG_TGC_FLA_RGN__W 6 |
| 1989 | #define FE_AG_REG_TGC_FLA_RGN__M 0x3F | 1989 | #define FE_AG_REG_TGC_FLA_RGN__M 0x3F |
| 1990 | #define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 | 1990 | #define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 |
| 1991 | 1991 | ||
| 1992 | #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 | 1992 | #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 |
| 1993 | #define FE_AG_REG_TGC_JMP_PSN__W 4 | 1993 | #define FE_AG_REG_TGC_JMP_PSN__W 4 |
| 1994 | #define FE_AG_REG_TGC_JMP_PSN__M 0xF | 1994 | #define FE_AG_REG_TGC_JMP_PSN__M 0xF |
| 1995 | #define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 | 1995 | #define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 |
| 1996 | 1996 | ||
| 1997 | #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 | 1997 | #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 |
| 1998 | #define FE_AG_REG_TGC_FLA_STP__W 16 | 1998 | #define FE_AG_REG_TGC_FLA_STP__W 16 |
| 1999 | #define FE_AG_REG_TGC_FLA_STP__M 0xFFFF | 1999 | #define FE_AG_REG_TGC_FLA_STP__M 0xFFFF |
| 2000 | #define FE_AG_REG_TGC_FLA_STP_INIT 0x0 | 2000 | #define FE_AG_REG_TGC_FLA_STP_INIT 0x0 |
| 2001 | 2001 | ||
| 2002 | #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 | 2002 | #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 |
| 2003 | #define FE_AG_REG_TGC_SLO_STP__W 16 | 2003 | #define FE_AG_REG_TGC_SLO_STP__W 16 |
| 2004 | #define FE_AG_REG_TGC_SLO_STP__M 0xFFFF | 2004 | #define FE_AG_REG_TGC_SLO_STP__M 0xFFFF |
| 2005 | #define FE_AG_REG_TGC_SLO_STP_INIT 0x0 | 2005 | #define FE_AG_REG_TGC_SLO_STP_INIT 0x0 |
| 2006 | 2006 | ||
| 2007 | #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 | 2007 | #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 |
| 2008 | #define FE_AG_REG_TGC_MAP_DAT__W 10 | 2008 | #define FE_AG_REG_TGC_MAP_DAT__W 10 |
| 2009 | #define FE_AG_REG_TGC_MAP_DAT__M 0x3FF | 2009 | #define FE_AG_REG_TGC_MAP_DAT__M 0x3FF |
| 2010 | 2010 | ||
| 2011 | #define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 | 2011 | #define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 |
| 2012 | #define FE_AG_REG_FGA_AUR_CNT__W 5 | 2012 | #define FE_AG_REG_FGA_AUR_CNT__W 5 |
| 2013 | #define FE_AG_REG_FGA_AUR_CNT__M 0x1F | 2013 | #define FE_AG_REG_FGA_AUR_CNT__M 0x1F |
| 2014 | #define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 | 2014 | #define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 |
| 2015 | 2015 | ||
| 2016 | #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 | 2016 | #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 |
| 2017 | #define FE_AG_REG_FGA_RUR_CNT__W 5 | 2017 | #define FE_AG_REG_FGA_RUR_CNT__W 5 |
| 2018 | #define FE_AG_REG_FGA_RUR_CNT__M 0x1F | 2018 | #define FE_AG_REG_FGA_RUR_CNT__M 0x1F |
| 2019 | #define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 | 2019 | #define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 |
| 2020 | 2020 | ||
| 2021 | #define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 | 2021 | #define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 |
| 2022 | #define FE_AG_REG_FGA_AVE_DAT__W 10 | 2022 | #define FE_AG_REG_FGA_AVE_DAT__W 10 |
| 2023 | #define FE_AG_REG_FGA_AVE_DAT__M 0x3FF | 2023 | #define FE_AG_REG_FGA_AVE_DAT__M 0x3FF |
| 2024 | 2024 | ||
| 2025 | #define FE_AG_REG_FGC_RUR_CNT__A 0xC2005A | 2025 | #define FE_AG_REG_FGC_RUR_CNT__A 0xC2005A |
| 2026 | #define FE_AG_REG_FGC_RUR_CNT__W 5 | 2026 | #define FE_AG_REG_FGC_RUR_CNT__W 5 |
| 2027 | #define FE_AG_REG_FGC_RUR_CNT__M 0x1F | 2027 | #define FE_AG_REG_FGC_RUR_CNT__M 0x1F |
| 2028 | #define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 | 2028 | #define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 |
| 2029 | 2029 | ||
| 2030 | #define FE_AG_REG_FGC_SET_LVL__A 0xC2005B | 2030 | #define FE_AG_REG_FGC_SET_LVL__A 0xC2005B |
| 2031 | #define FE_AG_REG_FGC_SET_LVL__W 9 | 2031 | #define FE_AG_REG_FGC_SET_LVL__W 9 |
| 2032 | #define FE_AG_REG_FGC_SET_LVL__M 0x1FF | 2032 | #define FE_AG_REG_FGC_SET_LVL__M 0x1FF |
| 2033 | #define FE_AG_REG_FGC_SET_LVL_INIT 0x0 | 2033 | #define FE_AG_REG_FGC_SET_LVL_INIT 0x0 |
| 2034 | 2034 | ||
| 2035 | #define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C | 2035 | #define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C |
| 2036 | #define FE_AG_REG_FGC_FLA_RGN__W 9 | 2036 | #define FE_AG_REG_FGC_FLA_RGN__W 9 |
| 2037 | #define FE_AG_REG_FGC_FLA_RGN__M 0x1FF | 2037 | #define FE_AG_REG_FGC_FLA_RGN__M 0x1FF |
| 2038 | #define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 | 2038 | #define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 |
| 2039 | 2039 | ||
| 2040 | #define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D | 2040 | #define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D |
| 2041 | #define FE_AG_REG_FGC_JMP_PSN__W 4 | 2041 | #define FE_AG_REG_FGC_JMP_PSN__W 4 |
| 2042 | #define FE_AG_REG_FGC_JMP_PSN__M 0xF | 2042 | #define FE_AG_REG_FGC_JMP_PSN__M 0xF |
| 2043 | #define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 | 2043 | #define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 |
| 2044 | 2044 | ||
| 2045 | #define FE_AG_REG_FGC_FLA_STP__A 0xC2005E | 2045 | #define FE_AG_REG_FGC_FLA_STP__A 0xC2005E |
| 2046 | #define FE_AG_REG_FGC_FLA_STP__W 16 | 2046 | #define FE_AG_REG_FGC_FLA_STP__W 16 |
| 2047 | #define FE_AG_REG_FGC_FLA_STP__M 0xFFFF | 2047 | #define FE_AG_REG_FGC_FLA_STP__M 0xFFFF |
| 2048 | #define FE_AG_REG_FGC_FLA_STP_INIT 0x0 | 2048 | #define FE_AG_REG_FGC_FLA_STP_INIT 0x0 |
| 2049 | 2049 | ||
| 2050 | #define FE_AG_REG_FGC_SLO_STP__A 0xC2005F | 2050 | #define FE_AG_REG_FGC_SLO_STP__A 0xC2005F |
| 2051 | #define FE_AG_REG_FGC_SLO_STP__W 16 | 2051 | #define FE_AG_REG_FGC_SLO_STP__W 16 |
| 2052 | #define FE_AG_REG_FGC_SLO_STP__M 0xFFFF | 2052 | #define FE_AG_REG_FGC_SLO_STP__M 0xFFFF |
| 2053 | #define FE_AG_REG_FGC_SLO_STP_INIT 0x0 | 2053 | #define FE_AG_REG_FGC_SLO_STP_INIT 0x0 |
| 2054 | 2054 | ||
| 2055 | #define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 | 2055 | #define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 |
| 2056 | #define FE_AG_REG_FGC_MAP_DAT__W 10 | 2056 | #define FE_AG_REG_FGC_MAP_DAT__W 10 |
| 2057 | #define FE_AG_REG_FGC_MAP_DAT__M 0x3FF | 2057 | #define FE_AG_REG_FGC_MAP_DAT__M 0x3FF |
| 2058 | 2058 | ||
| 2059 | #define FE_AG_REG_FGM_WRI__A 0xC20061 | 2059 | #define FE_AG_REG_FGM_WRI__A 0xC20061 |
| 2060 | #define FE_AG_REG_FGM_WRI__W 10 | 2060 | #define FE_AG_REG_FGM_WRI__W 10 |
| 2061 | #define FE_AG_REG_FGM_WRI__M 0x3FF | 2061 | #define FE_AG_REG_FGM_WRI__M 0x3FF |
| 2062 | #define FE_AG_REG_FGM_WRI_INIT 0x20 | 2062 | #define FE_AG_REG_FGM_WRI_INIT 0x20 |
| 2063 | 2063 | ||
| 2064 | #define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 | 2064 | #define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 |
| 2065 | #define FE_AG_REG_BGC_RUR_CNT__W 5 | 2065 | #define FE_AG_REG_BGC_RUR_CNT__W 5 |
| 2066 | #define FE_AG_REG_BGC_RUR_CNT__M 0x1F | 2066 | #define FE_AG_REG_BGC_RUR_CNT__M 0x1F |
| 2067 | #define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 | 2067 | #define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 |
| 2068 | 2068 | ||
| 2069 | #define FE_AG_REG_BGC_SET_LVL__A 0xC20063 | 2069 | #define FE_AG_REG_BGC_SET_LVL__A 0xC20063 |
| 2070 | #define FE_AG_REG_BGC_SET_LVL__W 9 | 2070 | #define FE_AG_REG_BGC_SET_LVL__W 9 |
| 2071 | #define FE_AG_REG_BGC_SET_LVL__M 0x1FF | 2071 | #define FE_AG_REG_BGC_SET_LVL__M 0x1FF |
| 2072 | #define FE_AG_REG_BGC_SET_LVL_INIT 0x0 | 2072 | #define FE_AG_REG_BGC_SET_LVL_INIT 0x0 |
| 2073 | 2073 | ||
| 2074 | #define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 | 2074 | #define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 |
| 2075 | #define FE_AG_REG_BGC_FLA_RGN__W 9 | 2075 | #define FE_AG_REG_BGC_FLA_RGN__W 9 |
| 2076 | #define FE_AG_REG_BGC_FLA_RGN__M 0x1FF | 2076 | #define FE_AG_REG_BGC_FLA_RGN__M 0x1FF |
| 2077 | #define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 | 2077 | #define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 |
| 2078 | 2078 | ||
| 2079 | #define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 | 2079 | #define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 |
| 2080 | #define FE_AG_REG_BGC_JMP_PSN__W 4 | 2080 | #define FE_AG_REG_BGC_JMP_PSN__W 4 |
| 2081 | #define FE_AG_REG_BGC_JMP_PSN__M 0xF | 2081 | #define FE_AG_REG_BGC_JMP_PSN__M 0xF |
| 2082 | #define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 | 2082 | #define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 |
| 2083 | 2083 | ||
| 2084 | #define FE_AG_REG_BGC_FLA_STP__A 0xC20066 | 2084 | #define FE_AG_REG_BGC_FLA_STP__A 0xC20066 |
| 2085 | #define FE_AG_REG_BGC_FLA_STP__W 16 | 2085 | #define FE_AG_REG_BGC_FLA_STP__W 16 |
| 2086 | #define FE_AG_REG_BGC_FLA_STP__M 0xFFFF | 2086 | #define FE_AG_REG_BGC_FLA_STP__M 0xFFFF |
| 2087 | #define FE_AG_REG_BGC_FLA_STP_INIT 0x0 | 2087 | #define FE_AG_REG_BGC_FLA_STP_INIT 0x0 |
| 2088 | 2088 | ||
| 2089 | #define FE_AG_REG_BGC_SLO_STP__A 0xC20067 | 2089 | #define FE_AG_REG_BGC_SLO_STP__A 0xC20067 |
| 2090 | #define FE_AG_REG_BGC_SLO_STP__W 16 | 2090 | #define FE_AG_REG_BGC_SLO_STP__W 16 |
| 2091 | #define FE_AG_REG_BGC_SLO_STP__M 0xFFFF | 2091 | #define FE_AG_REG_BGC_SLO_STP__M 0xFFFF |
| 2092 | #define FE_AG_REG_BGC_SLO_STP_INIT 0x0 | 2092 | #define FE_AG_REG_BGC_SLO_STP_INIT 0x0 |
| 2093 | 2093 | ||
| 2094 | #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 | 2094 | #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 |
| 2095 | #define FE_AG_REG_BGC_FGC_WRI__W 4 | 2095 | #define FE_AG_REG_BGC_FGC_WRI__W 4 |
| 2096 | #define FE_AG_REG_BGC_FGC_WRI__M 0xF | 2096 | #define FE_AG_REG_BGC_FGC_WRI__M 0xF |
| 2097 | #define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 | 2097 | #define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 |
| 2098 | 2098 | ||
| 2099 | #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 | 2099 | #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 |
| 2100 | #define FE_AG_REG_BGC_CGC_WRI__W 2 | 2100 | #define FE_AG_REG_BGC_CGC_WRI__W 2 |
| 2101 | #define FE_AG_REG_BGC_CGC_WRI__M 0x3 | 2101 | #define FE_AG_REG_BGC_CGC_WRI__M 0x3 |
| 2102 | #define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 | 2102 | #define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 |
| 2103 | 2103 | ||
| 2104 | #define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A | 2104 | #define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A |
| 2105 | #define FE_AG_REG_BGC_FGC_DAT__W 4 | 2105 | #define FE_AG_REG_BGC_FGC_DAT__W 4 |
| 2106 | #define FE_AG_REG_BGC_FGC_DAT__M 0xF | 2106 | #define FE_AG_REG_BGC_FGC_DAT__M 0xF |
| 2107 | 2107 | ||
| 2108 | #define FE_FS_SID 0x3 | 2108 | #define FE_FS_SID 0x3 |
| 2109 | 2109 | ||
| 2110 | #define FE_FS_REG_COMM_EXEC__A 0xC30000 | 2110 | #define FE_FS_REG_COMM_EXEC__A 0xC30000 |
| 2111 | #define FE_FS_REG_COMM_EXEC__W 3 | 2111 | #define FE_FS_REG_COMM_EXEC__W 3 |
| 2112 | #define FE_FS_REG_COMM_EXEC__M 0x7 | 2112 | #define FE_FS_REG_COMM_EXEC__M 0x7 |
| 2113 | #define FE_FS_REG_COMM_EXEC_CTL__B 0 | 2113 | #define FE_FS_REG_COMM_EXEC_CTL__B 0 |
| 2114 | #define FE_FS_REG_COMM_EXEC_CTL__W 3 | 2114 | #define FE_FS_REG_COMM_EXEC_CTL__W 3 |
| 2115 | #define FE_FS_REG_COMM_EXEC_CTL__M 0x7 | 2115 | #define FE_FS_REG_COMM_EXEC_CTL__M 0x7 |
| 2116 | #define FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 | 2116 | #define FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 |
| 2117 | #define FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 2117 | #define FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2118 | #define FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 | 2118 | #define FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 2119 | #define FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 | 2119 | #define FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 |
| 2120 | 2120 | ||
| 2121 | #define FE_FS_REG_COMM_STATE__A 0xC30001 | 2121 | #define FE_FS_REG_COMM_STATE__A 0xC30001 |
| 2122 | #define FE_FS_REG_COMM_STATE__W 4 | 2122 | #define FE_FS_REG_COMM_STATE__W 4 |
| 2123 | #define FE_FS_REG_COMM_STATE__M 0xF | 2123 | #define FE_FS_REG_COMM_STATE__M 0xF |
| 2124 | 2124 | ||
| 2125 | #define FE_FS_REG_COMM_MB__A 0xC30002 | 2125 | #define FE_FS_REG_COMM_MB__A 0xC30002 |
| 2126 | #define FE_FS_REG_COMM_MB__W 3 | 2126 | #define FE_FS_REG_COMM_MB__W 3 |
| 2127 | #define FE_FS_REG_COMM_MB__M 0x7 | 2127 | #define FE_FS_REG_COMM_MB__M 0x7 |
| 2128 | #define FE_FS_REG_COMM_MB_CTR__B 0 | 2128 | #define FE_FS_REG_COMM_MB_CTR__B 0 |
| 2129 | #define FE_FS_REG_COMM_MB_CTR__W 1 | 2129 | #define FE_FS_REG_COMM_MB_CTR__W 1 |
| 2130 | #define FE_FS_REG_COMM_MB_CTR__M 0x1 | 2130 | #define FE_FS_REG_COMM_MB_CTR__M 0x1 |
| 2131 | #define FE_FS_REG_COMM_MB_CTR_OFF 0x0 | 2131 | #define FE_FS_REG_COMM_MB_CTR_OFF 0x0 |
| 2132 | #define FE_FS_REG_COMM_MB_CTR_ON 0x1 | 2132 | #define FE_FS_REG_COMM_MB_CTR_ON 0x1 |
| 2133 | #define FE_FS_REG_COMM_MB_OBS__B 1 | 2133 | #define FE_FS_REG_COMM_MB_OBS__B 1 |
| 2134 | #define FE_FS_REG_COMM_MB_OBS__W 1 | 2134 | #define FE_FS_REG_COMM_MB_OBS__W 1 |
| 2135 | #define FE_FS_REG_COMM_MB_OBS__M 0x2 | 2135 | #define FE_FS_REG_COMM_MB_OBS__M 0x2 |
| 2136 | #define FE_FS_REG_COMM_MB_OBS_OFF 0x0 | 2136 | #define FE_FS_REG_COMM_MB_OBS_OFF 0x0 |
| 2137 | #define FE_FS_REG_COMM_MB_OBS_ON 0x2 | 2137 | #define FE_FS_REG_COMM_MB_OBS_ON 0x2 |
| 2138 | #define FE_FS_REG_COMM_MB_MUX__B 2 | 2138 | #define FE_FS_REG_COMM_MB_MUX__B 2 |
| 2139 | #define FE_FS_REG_COMM_MB_MUX__W 1 | 2139 | #define FE_FS_REG_COMM_MB_MUX__W 1 |
| 2140 | #define FE_FS_REG_COMM_MB_MUX__M 0x4 | 2140 | #define FE_FS_REG_COMM_MB_MUX__M 0x4 |
| 2141 | #define FE_FS_REG_COMM_MB_MUX_REAL 0x0 | 2141 | #define FE_FS_REG_COMM_MB_MUX_REAL 0x0 |
| 2142 | #define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 | 2142 | #define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 |
| 2143 | 2143 | ||
| 2144 | #define FE_FS_REG_COMM_SERVICE0__A 0xC30003 | 2144 | #define FE_FS_REG_COMM_SERVICE0__A 0xC30003 |
| 2145 | #define FE_FS_REG_COMM_SERVICE0__W 10 | 2145 | #define FE_FS_REG_COMM_SERVICE0__W 10 |
| 2146 | #define FE_FS_REG_COMM_SERVICE0__M 0x3FF | 2146 | #define FE_FS_REG_COMM_SERVICE0__M 0x3FF |
| 2147 | 2147 | ||
| 2148 | #define FE_FS_REG_COMM_SERVICE1__A 0xC30004 | 2148 | #define FE_FS_REG_COMM_SERVICE1__A 0xC30004 |
| 2149 | #define FE_FS_REG_COMM_SERVICE1__W 11 | 2149 | #define FE_FS_REG_COMM_SERVICE1__W 11 |
| 2150 | #define FE_FS_REG_COMM_SERVICE1__M 0x7FF | 2150 | #define FE_FS_REG_COMM_SERVICE1__M 0x7FF |
| 2151 | 2151 | ||
| 2152 | #define FE_FS_REG_COMM_ACT__A 0xC30005 | 2152 | #define FE_FS_REG_COMM_ACT__A 0xC30005 |
| 2153 | #define FE_FS_REG_COMM_ACT__W 2 | 2153 | #define FE_FS_REG_COMM_ACT__W 2 |
| 2154 | #define FE_FS_REG_COMM_ACT__M 0x3 | 2154 | #define FE_FS_REG_COMM_ACT__M 0x3 |
| 2155 | 2155 | ||
| 2156 | #define FE_FS_REG_COMM_CNT__A 0xC30006 | 2156 | #define FE_FS_REG_COMM_CNT__A 0xC30006 |
| 2157 | #define FE_FS_REG_COMM_CNT__W 16 | 2157 | #define FE_FS_REG_COMM_CNT__W 16 |
| 2158 | #define FE_FS_REG_COMM_CNT__M 0xFFFF | 2158 | #define FE_FS_REG_COMM_CNT__M 0xFFFF |
| 2159 | 2159 | ||
| 2160 | #define FE_FS_REG_ADD_INC_LOP__A 0xC30010 | 2160 | #define FE_FS_REG_ADD_INC_LOP__A 0xC30010 |
| 2161 | #define FE_FS_REG_ADD_INC_LOP__W 16 | 2161 | #define FE_FS_REG_ADD_INC_LOP__W 16 |
| 2162 | #define FE_FS_REG_ADD_INC_LOP__M 0xFFFF | 2162 | #define FE_FS_REG_ADD_INC_LOP__M 0xFFFF |
| 2163 | #define FE_FS_REG_ADD_INC_LOP_INIT 0x0 | 2163 | #define FE_FS_REG_ADD_INC_LOP_INIT 0x0 |
| 2164 | 2164 | ||
| 2165 | #define FE_FS_REG_ADD_INC_HIP__A 0xC30011 | 2165 | #define FE_FS_REG_ADD_INC_HIP__A 0xC30011 |
| 2166 | #define FE_FS_REG_ADD_INC_HIP__W 12 | 2166 | #define FE_FS_REG_ADD_INC_HIP__W 12 |
| 2167 | #define FE_FS_REG_ADD_INC_HIP__M 0xFFF | 2167 | #define FE_FS_REG_ADD_INC_HIP__M 0xFFF |
| 2168 | #define FE_FS_REG_ADD_INC_HIP_INIT 0x0 | 2168 | #define FE_FS_REG_ADD_INC_HIP_INIT 0x0 |
| 2169 | 2169 | ||
| 2170 | #define FE_FS_REG_ADD_OFF__A 0xC30012 | 2170 | #define FE_FS_REG_ADD_OFF__A 0xC30012 |
| 2171 | #define FE_FS_REG_ADD_OFF__W 12 | 2171 | #define FE_FS_REG_ADD_OFF__W 12 |
| 2172 | #define FE_FS_REG_ADD_OFF__M 0xFFF | 2172 | #define FE_FS_REG_ADD_OFF__M 0xFFF |
| 2173 | #define FE_FS_REG_ADD_OFF_INIT 0x0 | 2173 | #define FE_FS_REG_ADD_OFF_INIT 0x0 |
| 2174 | 2174 | ||
| 2175 | #define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 | 2175 | #define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 |
| 2176 | #define FE_FS_REG_ADD_OFF_VAL__W 1 | 2176 | #define FE_FS_REG_ADD_OFF_VAL__W 1 |
| 2177 | #define FE_FS_REG_ADD_OFF_VAL__M 0x1 | 2177 | #define FE_FS_REG_ADD_OFF_VAL__M 0x1 |
| 2178 | #define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 | 2178 | #define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 |
| 2179 | 2179 | ||
| 2180 | #define FE_FD_SID 0x4 | 2180 | #define FE_FD_SID 0x4 |
| 2181 | 2181 | ||
| 2182 | #define FE_FD_REG_COMM_EXEC__A 0xC40000 | 2182 | #define FE_FD_REG_COMM_EXEC__A 0xC40000 |
| 2183 | #define FE_FD_REG_COMM_EXEC__W 3 | 2183 | #define FE_FD_REG_COMM_EXEC__W 3 |
| 2184 | #define FE_FD_REG_COMM_EXEC__M 0x7 | 2184 | #define FE_FD_REG_COMM_EXEC__M 0x7 |
| 2185 | #define FE_FD_REG_COMM_EXEC_CTL__B 0 | 2185 | #define FE_FD_REG_COMM_EXEC_CTL__B 0 |
| 2186 | #define FE_FD_REG_COMM_EXEC_CTL__W 3 | 2186 | #define FE_FD_REG_COMM_EXEC_CTL__W 3 |
| 2187 | #define FE_FD_REG_COMM_EXEC_CTL__M 0x7 | 2187 | #define FE_FD_REG_COMM_EXEC_CTL__M 0x7 |
| 2188 | #define FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 | 2188 | #define FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 2189 | #define FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 2189 | #define FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2190 | #define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 | 2190 | #define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 2191 | #define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 | 2191 | #define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 |
| 2192 | 2192 | ||
| 2193 | #define FE_FD_REG_COMM_MB__A 0xC40002 | 2193 | #define FE_FD_REG_COMM_MB__A 0xC40002 |
| 2194 | #define FE_FD_REG_COMM_MB__W 3 | 2194 | #define FE_FD_REG_COMM_MB__W 3 |
| 2195 | #define FE_FD_REG_COMM_MB__M 0x7 | 2195 | #define FE_FD_REG_COMM_MB__M 0x7 |
| 2196 | #define FE_FD_REG_COMM_MB_CTR__B 0 | 2196 | #define FE_FD_REG_COMM_MB_CTR__B 0 |
| 2197 | #define FE_FD_REG_COMM_MB_CTR__W 1 | 2197 | #define FE_FD_REG_COMM_MB_CTR__W 1 |
| 2198 | #define FE_FD_REG_COMM_MB_CTR__M 0x1 | 2198 | #define FE_FD_REG_COMM_MB_CTR__M 0x1 |
| 2199 | #define FE_FD_REG_COMM_MB_CTR_OFF 0x0 | 2199 | #define FE_FD_REG_COMM_MB_CTR_OFF 0x0 |
| 2200 | #define FE_FD_REG_COMM_MB_CTR_ON 0x1 | 2200 | #define FE_FD_REG_COMM_MB_CTR_ON 0x1 |
| 2201 | #define FE_FD_REG_COMM_MB_OBS__B 1 | 2201 | #define FE_FD_REG_COMM_MB_OBS__B 1 |
| 2202 | #define FE_FD_REG_COMM_MB_OBS__W 1 | 2202 | #define FE_FD_REG_COMM_MB_OBS__W 1 |
| 2203 | #define FE_FD_REG_COMM_MB_OBS__M 0x2 | 2203 | #define FE_FD_REG_COMM_MB_OBS__M 0x2 |
| 2204 | #define FE_FD_REG_COMM_MB_OBS_OFF 0x0 | 2204 | #define FE_FD_REG_COMM_MB_OBS_OFF 0x0 |
| 2205 | #define FE_FD_REG_COMM_MB_OBS_ON 0x2 | 2205 | #define FE_FD_REG_COMM_MB_OBS_ON 0x2 |
| 2206 | 2206 | ||
| 2207 | #define FE_FD_REG_COMM_SERVICE0__A 0xC40003 | 2207 | #define FE_FD_REG_COMM_SERVICE0__A 0xC40003 |
| 2208 | #define FE_FD_REG_COMM_SERVICE0__W 10 | 2208 | #define FE_FD_REG_COMM_SERVICE0__W 10 |
| 2209 | #define FE_FD_REG_COMM_SERVICE0__M 0x3FF | 2209 | #define FE_FD_REG_COMM_SERVICE0__M 0x3FF |
| 2210 | #define FE_FD_REG_COMM_SERVICE1__A 0xC40004 | 2210 | #define FE_FD_REG_COMM_SERVICE1__A 0xC40004 |
| 2211 | #define FE_FD_REG_COMM_SERVICE1__W 11 | 2211 | #define FE_FD_REG_COMM_SERVICE1__W 11 |
| 2212 | #define FE_FD_REG_COMM_SERVICE1__M 0x7FF | 2212 | #define FE_FD_REG_COMM_SERVICE1__M 0x7FF |
| 2213 | 2213 | ||
| 2214 | #define FE_FD_REG_COMM_INT_STA__A 0xC40007 | 2214 | #define FE_FD_REG_COMM_INT_STA__A 0xC40007 |
| 2215 | #define FE_FD_REG_COMM_INT_STA__W 1 | 2215 | #define FE_FD_REG_COMM_INT_STA__W 1 |
| 2216 | #define FE_FD_REG_COMM_INT_STA__M 0x1 | 2216 | #define FE_FD_REG_COMM_INT_STA__M 0x1 |
| 2217 | #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 | 2217 | #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 |
| 2218 | #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 | 2218 | #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 |
| 2219 | #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 | 2219 | #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 |
| 2220 | 2220 | ||
| 2221 | #define FE_FD_REG_COMM_INT_MSK__A 0xC40008 | 2221 | #define FE_FD_REG_COMM_INT_MSK__A 0xC40008 |
| 2222 | #define FE_FD_REG_COMM_INT_MSK__W 1 | 2222 | #define FE_FD_REG_COMM_INT_MSK__W 1 |
| 2223 | #define FE_FD_REG_COMM_INT_MSK__M 0x1 | 2223 | #define FE_FD_REG_COMM_INT_MSK__M 0x1 |
| 2224 | #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 | 2224 | #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 |
| 2225 | #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 | 2225 | #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 |
| 2226 | #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 | 2226 | #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 |
| 2227 | 2227 | ||
| 2228 | #define FE_FD_REG_SCL__A 0xC40010 | 2228 | #define FE_FD_REG_SCL__A 0xC40010 |
| 2229 | #define FE_FD_REG_SCL__W 6 | 2229 | #define FE_FD_REG_SCL__W 6 |
| 2230 | #define FE_FD_REG_SCL__M 0x3F | 2230 | #define FE_FD_REG_SCL__M 0x3F |
| 2231 | 2231 | ||
| 2232 | #define FE_FD_REG_MAX_LEV__A 0xC40011 | 2232 | #define FE_FD_REG_MAX_LEV__A 0xC40011 |
| 2233 | #define FE_FD_REG_MAX_LEV__W 3 | 2233 | #define FE_FD_REG_MAX_LEV__W 3 |
| 2234 | #define FE_FD_REG_MAX_LEV__M 0x7 | 2234 | #define FE_FD_REG_MAX_LEV__M 0x7 |
| 2235 | 2235 | ||
| 2236 | #define FE_FD_REG_NR__A 0xC40012 | 2236 | #define FE_FD_REG_NR__A 0xC40012 |
| 2237 | #define FE_FD_REG_NR__W 5 | 2237 | #define FE_FD_REG_NR__W 5 |
| 2238 | #define FE_FD_REG_NR__M 0x1F | 2238 | #define FE_FD_REG_NR__M 0x1F |
| 2239 | 2239 | ||
| 2240 | #define FE_FD_REG_MEAS_SEL__A 0xC40013 | 2240 | #define FE_FD_REG_MEAS_SEL__A 0xC40013 |
| 2241 | #define FE_FD_REG_MEAS_SEL__W 1 | 2241 | #define FE_FD_REG_MEAS_SEL__W 1 |
| 2242 | #define FE_FD_REG_MEAS_SEL__M 0x1 | 2242 | #define FE_FD_REG_MEAS_SEL__M 0x1 |
| 2243 | 2243 | ||
| 2244 | #define FE_FD_REG_MEAS_VAL__A 0xC40014 | 2244 | #define FE_FD_REG_MEAS_VAL__A 0xC40014 |
| 2245 | #define FE_FD_REG_MEAS_VAL__W 1 | 2245 | #define FE_FD_REG_MEAS_VAL__W 1 |
| 2246 | #define FE_FD_REG_MEAS_VAL__M 0x1 | 2246 | #define FE_FD_REG_MEAS_VAL__M 0x1 |
| 2247 | 2247 | ||
| 2248 | #define FE_FD_REG_MAX__A 0xC40015 | 2248 | #define FE_FD_REG_MAX__A 0xC40015 |
| 2249 | #define FE_FD_REG_MAX__W 16 | 2249 | #define FE_FD_REG_MAX__W 16 |
| 2250 | #define FE_FD_REG_MAX__M 0xFFFF | 2250 | #define FE_FD_REG_MAX__M 0xFFFF |
| 2251 | 2251 | ||
| 2252 | #define FE_FD_REG_POWER__A 0xC40016 | 2252 | #define FE_FD_REG_POWER__A 0xC40016 |
| 2253 | #define FE_FD_REG_POWER__W 10 | 2253 | #define FE_FD_REG_POWER__W 10 |
| 2254 | #define FE_FD_REG_POWER__M 0x3FF | 2254 | #define FE_FD_REG_POWER__M 0x3FF |
| 2255 | 2255 | ||
| 2256 | #define FE_IF_SID 0x5 | 2256 | #define FE_IF_SID 0x5 |
| 2257 | 2257 | ||
| 2258 | #define FE_IF_REG_COMM_EXEC__A 0xC50000 | 2258 | #define FE_IF_REG_COMM_EXEC__A 0xC50000 |
| 2259 | #define FE_IF_REG_COMM_EXEC__W 3 | 2259 | #define FE_IF_REG_COMM_EXEC__W 3 |
| 2260 | #define FE_IF_REG_COMM_EXEC__M 0x7 | 2260 | #define FE_IF_REG_COMM_EXEC__M 0x7 |
| 2261 | #define FE_IF_REG_COMM_EXEC_CTL__B 0 | 2261 | #define FE_IF_REG_COMM_EXEC_CTL__B 0 |
| 2262 | #define FE_IF_REG_COMM_EXEC_CTL__W 3 | 2262 | #define FE_IF_REG_COMM_EXEC_CTL__W 3 |
| 2263 | #define FE_IF_REG_COMM_EXEC_CTL__M 0x7 | 2263 | #define FE_IF_REG_COMM_EXEC_CTL__M 0x7 |
| 2264 | #define FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 | 2264 | #define FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 |
| 2265 | #define FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 2265 | #define FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2266 | #define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 | 2266 | #define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 2267 | #define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 | 2267 | #define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 |
| 2268 | 2268 | ||
| 2269 | #define FE_IF_REG_COMM_MB__A 0xC50002 | 2269 | #define FE_IF_REG_COMM_MB__A 0xC50002 |
| 2270 | #define FE_IF_REG_COMM_MB__W 3 | 2270 | #define FE_IF_REG_COMM_MB__W 3 |
| 2271 | #define FE_IF_REG_COMM_MB__M 0x7 | 2271 | #define FE_IF_REG_COMM_MB__M 0x7 |
| 2272 | #define FE_IF_REG_COMM_MB_CTR__B 0 | 2272 | #define FE_IF_REG_COMM_MB_CTR__B 0 |
| 2273 | #define FE_IF_REG_COMM_MB_CTR__W 1 | 2273 | #define FE_IF_REG_COMM_MB_CTR__W 1 |
| 2274 | #define FE_IF_REG_COMM_MB_CTR__M 0x1 | 2274 | #define FE_IF_REG_COMM_MB_CTR__M 0x1 |
| 2275 | #define FE_IF_REG_COMM_MB_CTR_OFF 0x0 | 2275 | #define FE_IF_REG_COMM_MB_CTR_OFF 0x0 |
| 2276 | #define FE_IF_REG_COMM_MB_CTR_ON 0x1 | 2276 | #define FE_IF_REG_COMM_MB_CTR_ON 0x1 |
| 2277 | #define FE_IF_REG_COMM_MB_OBS__B 1 | 2277 | #define FE_IF_REG_COMM_MB_OBS__B 1 |
| 2278 | #define FE_IF_REG_COMM_MB_OBS__W 1 | 2278 | #define FE_IF_REG_COMM_MB_OBS__W 1 |
| 2279 | #define FE_IF_REG_COMM_MB_OBS__M 0x2 | 2279 | #define FE_IF_REG_COMM_MB_OBS__M 0x2 |
| 2280 | #define FE_IF_REG_COMM_MB_OBS_OFF 0x0 | 2280 | #define FE_IF_REG_COMM_MB_OBS_OFF 0x0 |
| 2281 | #define FE_IF_REG_COMM_MB_OBS_ON 0x2 | 2281 | #define FE_IF_REG_COMM_MB_OBS_ON 0x2 |
| 2282 | 2282 | ||
| 2283 | #define FE_IF_REG_INCR0__A 0xC50010 | 2283 | #define FE_IF_REG_INCR0__A 0xC50010 |
| 2284 | #define FE_IF_REG_INCR0__W 16 | 2284 | #define FE_IF_REG_INCR0__W 16 |
| 2285 | #define FE_IF_REG_INCR0__M 0xFFFF | 2285 | #define FE_IF_REG_INCR0__M 0xFFFF |
| 2286 | #define FE_IF_REG_INCR0_INIT 0x0 | 2286 | #define FE_IF_REG_INCR0_INIT 0x0 |
| 2287 | 2287 | ||
| 2288 | #define FE_IF_REG_INCR1__A 0xC50011 | 2288 | #define FE_IF_REG_INCR1__A 0xC50011 |
| 2289 | #define FE_IF_REG_INCR1__W 8 | 2289 | #define FE_IF_REG_INCR1__W 8 |
| 2290 | #define FE_IF_REG_INCR1__M 0xFF | 2290 | #define FE_IF_REG_INCR1__M 0xFF |
| 2291 | #define FE_IF_REG_INCR1_INIT 0x28 | 2291 | #define FE_IF_REG_INCR1_INIT 0x28 |
| 2292 | 2292 | ||
| 2293 | #define FE_CF_SID 0x6 | 2293 | #define FE_CF_SID 0x6 |
| 2294 | 2294 | ||
| 2295 | #define FE_CF_REG_COMM_EXEC__A 0xC60000 | 2295 | #define FE_CF_REG_COMM_EXEC__A 0xC60000 |
| 2296 | #define FE_CF_REG_COMM_EXEC__W 3 | 2296 | #define FE_CF_REG_COMM_EXEC__W 3 |
| 2297 | #define FE_CF_REG_COMM_EXEC__M 0x7 | 2297 | #define FE_CF_REG_COMM_EXEC__M 0x7 |
| 2298 | #define FE_CF_REG_COMM_EXEC_CTL__B 0 | 2298 | #define FE_CF_REG_COMM_EXEC_CTL__B 0 |
| 2299 | #define FE_CF_REG_COMM_EXEC_CTL__W 3 | 2299 | #define FE_CF_REG_COMM_EXEC_CTL__W 3 |
| 2300 | #define FE_CF_REG_COMM_EXEC_CTL__M 0x7 | 2300 | #define FE_CF_REG_COMM_EXEC_CTL__M 0x7 |
| 2301 | #define FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 | 2301 | #define FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 |
| 2302 | #define FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 2302 | #define FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2303 | #define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 | 2303 | #define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 2304 | #define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 | 2304 | #define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 |
| 2305 | 2305 | ||
| 2306 | #define FE_CF_REG_COMM_MB__A 0xC60002 | 2306 | #define FE_CF_REG_COMM_MB__A 0xC60002 |
| 2307 | #define FE_CF_REG_COMM_MB__W 3 | 2307 | #define FE_CF_REG_COMM_MB__W 3 |
| 2308 | #define FE_CF_REG_COMM_MB__M 0x7 | 2308 | #define FE_CF_REG_COMM_MB__M 0x7 |
| 2309 | #define FE_CF_REG_COMM_MB_CTR__B 0 | 2309 | #define FE_CF_REG_COMM_MB_CTR__B 0 |
| 2310 | #define FE_CF_REG_COMM_MB_CTR__W 1 | 2310 | #define FE_CF_REG_COMM_MB_CTR__W 1 |
| 2311 | #define FE_CF_REG_COMM_MB_CTR__M 0x1 | 2311 | #define FE_CF_REG_COMM_MB_CTR__M 0x1 |
| 2312 | #define FE_CF_REG_COMM_MB_CTR_OFF 0x0 | 2312 | #define FE_CF_REG_COMM_MB_CTR_OFF 0x0 |
| 2313 | #define FE_CF_REG_COMM_MB_CTR_ON 0x1 | 2313 | #define FE_CF_REG_COMM_MB_CTR_ON 0x1 |
| 2314 | #define FE_CF_REG_COMM_MB_OBS__B 1 | 2314 | #define FE_CF_REG_COMM_MB_OBS__B 1 |
| 2315 | #define FE_CF_REG_COMM_MB_OBS__W 1 | 2315 | #define FE_CF_REG_COMM_MB_OBS__W 1 |
| 2316 | #define FE_CF_REG_COMM_MB_OBS__M 0x2 | 2316 | #define FE_CF_REG_COMM_MB_OBS__M 0x2 |
| 2317 | #define FE_CF_REG_COMM_MB_OBS_OFF 0x0 | 2317 | #define FE_CF_REG_COMM_MB_OBS_OFF 0x0 |
| 2318 | #define FE_CF_REG_COMM_MB_OBS_ON 0x2 | 2318 | #define FE_CF_REG_COMM_MB_OBS_ON 0x2 |
| 2319 | 2319 | ||
| 2320 | #define FE_CF_REG_COMM_SERVICE0__A 0xC60003 | 2320 | #define FE_CF_REG_COMM_SERVICE0__A 0xC60003 |
| 2321 | #define FE_CF_REG_COMM_SERVICE0__W 10 | 2321 | #define FE_CF_REG_COMM_SERVICE0__W 10 |
| 2322 | #define FE_CF_REG_COMM_SERVICE0__M 0x3FF | 2322 | #define FE_CF_REG_COMM_SERVICE0__M 0x3FF |
| 2323 | #define FE_CF_REG_COMM_SERVICE1__A 0xC60004 | 2323 | #define FE_CF_REG_COMM_SERVICE1__A 0xC60004 |
| 2324 | #define FE_CF_REG_COMM_SERVICE1__W 11 | 2324 | #define FE_CF_REG_COMM_SERVICE1__W 11 |
| 2325 | #define FE_CF_REG_COMM_SERVICE1__M 0x7FF | 2325 | #define FE_CF_REG_COMM_SERVICE1__M 0x7FF |
| 2326 | 2326 | ||
| 2327 | #define FE_CF_REG_COMM_INT_STA__A 0xC60007 | 2327 | #define FE_CF_REG_COMM_INT_STA__A 0xC60007 |
| 2328 | #define FE_CF_REG_COMM_INT_STA__W 2 | 2328 | #define FE_CF_REG_COMM_INT_STA__W 2 |
| 2329 | #define FE_CF_REG_COMM_INT_STA__M 0x3 | 2329 | #define FE_CF_REG_COMM_INT_STA__M 0x3 |
| 2330 | #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 | 2330 | #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 |
| 2331 | #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 | 2331 | #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 |
| 2332 | #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 | 2332 | #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 |
| 2333 | 2333 | ||
| 2334 | #define FE_CF_REG_COMM_INT_MSK__A 0xC60008 | 2334 | #define FE_CF_REG_COMM_INT_MSK__A 0xC60008 |
| 2335 | #define FE_CF_REG_COMM_INT_MSK__W 2 | 2335 | #define FE_CF_REG_COMM_INT_MSK__W 2 |
| 2336 | #define FE_CF_REG_COMM_INT_MSK__M 0x3 | 2336 | #define FE_CF_REG_COMM_INT_MSK__M 0x3 |
| 2337 | #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 | 2337 | #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 |
| 2338 | #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 | 2338 | #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 |
| 2339 | #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 | 2339 | #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 |
| 2340 | 2340 | ||
| 2341 | #define FE_CF_REG_SCL__A 0xC60010 | 2341 | #define FE_CF_REG_SCL__A 0xC60010 |
| 2342 | #define FE_CF_REG_SCL__W 9 | 2342 | #define FE_CF_REG_SCL__W 9 |
| 2343 | #define FE_CF_REG_SCL__M 0x1FF | 2343 | #define FE_CF_REG_SCL__M 0x1FF |
| 2344 | 2344 | ||
| 2345 | #define FE_CF_REG_MAX_LEV__A 0xC60011 | 2345 | #define FE_CF_REG_MAX_LEV__A 0xC60011 |
| 2346 | #define FE_CF_REG_MAX_LEV__W 3 | 2346 | #define FE_CF_REG_MAX_LEV__W 3 |
| 2347 | #define FE_CF_REG_MAX_LEV__M 0x7 | 2347 | #define FE_CF_REG_MAX_LEV__M 0x7 |
| 2348 | 2348 | ||
| 2349 | #define FE_CF_REG_NR__A 0xC60012 | 2349 | #define FE_CF_REG_NR__A 0xC60012 |
| 2350 | #define FE_CF_REG_NR__W 5 | 2350 | #define FE_CF_REG_NR__W 5 |
| 2351 | #define FE_CF_REG_NR__M 0x1F | 2351 | #define FE_CF_REG_NR__M 0x1F |
| 2352 | 2352 | ||
| 2353 | #define FE_CF_REG_IMP_VAL__A 0xC60013 | 2353 | #define FE_CF_REG_IMP_VAL__A 0xC60013 |
| 2354 | #define FE_CF_REG_IMP_VAL__W 1 | 2354 | #define FE_CF_REG_IMP_VAL__W 1 |
| 2355 | #define FE_CF_REG_IMP_VAL__M 0x1 | 2355 | #define FE_CF_REG_IMP_VAL__M 0x1 |
| 2356 | 2356 | ||
| 2357 | #define FE_CF_REG_MEAS_VAL__A 0xC60014 | 2357 | #define FE_CF_REG_MEAS_VAL__A 0xC60014 |
| 2358 | #define FE_CF_REG_MEAS_VAL__W 1 | 2358 | #define FE_CF_REG_MEAS_VAL__W 1 |
| 2359 | #define FE_CF_REG_MEAS_VAL__M 0x1 | 2359 | #define FE_CF_REG_MEAS_VAL__M 0x1 |
| 2360 | 2360 | ||
| 2361 | #define FE_CF_REG_MAX__A 0xC60015 | 2361 | #define FE_CF_REG_MAX__A 0xC60015 |
| 2362 | #define FE_CF_REG_MAX__W 16 | 2362 | #define FE_CF_REG_MAX__W 16 |
| 2363 | #define FE_CF_REG_MAX__M 0xFFFF | 2363 | #define FE_CF_REG_MAX__M 0xFFFF |
| 2364 | 2364 | ||
| 2365 | #define FE_CF_REG_POWER__A 0xC60016 | 2365 | #define FE_CF_REG_POWER__A 0xC60016 |
| 2366 | #define FE_CF_REG_POWER__W 10 | 2366 | #define FE_CF_REG_POWER__W 10 |
| 2367 | #define FE_CF_REG_POWER__M 0x3FF | 2367 | #define FE_CF_REG_POWER__M 0x3FF |
| 2368 | 2368 | ||
| 2369 | #define FE_CU_SID 0x7 | 2369 | #define FE_CU_SID 0x7 |
| 2370 | 2370 | ||
| 2371 | #define FE_CU_REG_COMM_EXEC__A 0xC70000 | 2371 | #define FE_CU_REG_COMM_EXEC__A 0xC70000 |
| 2372 | #define FE_CU_REG_COMM_EXEC__W 3 | 2372 | #define FE_CU_REG_COMM_EXEC__W 3 |
| 2373 | #define FE_CU_REG_COMM_EXEC__M 0x7 | 2373 | #define FE_CU_REG_COMM_EXEC__M 0x7 |
| 2374 | #define FE_CU_REG_COMM_EXEC_CTL__B 0 | 2374 | #define FE_CU_REG_COMM_EXEC_CTL__B 0 |
| 2375 | #define FE_CU_REG_COMM_EXEC_CTL__W 3 | 2375 | #define FE_CU_REG_COMM_EXEC_CTL__W 3 |
| 2376 | #define FE_CU_REG_COMM_EXEC_CTL__M 0x7 | 2376 | #define FE_CU_REG_COMM_EXEC_CTL__M 0x7 |
| 2377 | #define FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 | 2377 | #define FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 |
| 2378 | #define FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 2378 | #define FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2379 | #define FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 | 2379 | #define FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 2380 | #define FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 | 2380 | #define FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 |
| 2381 | 2381 | ||
| 2382 | #define FE_CU_REG_COMM_STATE__A 0xC70001 | 2382 | #define FE_CU_REG_COMM_STATE__A 0xC70001 |
| 2383 | #define FE_CU_REG_COMM_STATE__W 4 | 2383 | #define FE_CU_REG_COMM_STATE__W 4 |
| 2384 | #define FE_CU_REG_COMM_STATE__M 0xF | 2384 | #define FE_CU_REG_COMM_STATE__M 0xF |
| 2385 | 2385 | ||
| 2386 | #define FE_CU_REG_COMM_MB__A 0xC70002 | 2386 | #define FE_CU_REG_COMM_MB__A 0xC70002 |
| 2387 | #define FE_CU_REG_COMM_MB__W 3 | 2387 | #define FE_CU_REG_COMM_MB__W 3 |
| 2388 | #define FE_CU_REG_COMM_MB__M 0x7 | 2388 | #define FE_CU_REG_COMM_MB__M 0x7 |
| 2389 | #define FE_CU_REG_COMM_MB_CTR__B 0 | 2389 | #define FE_CU_REG_COMM_MB_CTR__B 0 |
| 2390 | #define FE_CU_REG_COMM_MB_CTR__W 1 | 2390 | #define FE_CU_REG_COMM_MB_CTR__W 1 |
| 2391 | #define FE_CU_REG_COMM_MB_CTR__M 0x1 | 2391 | #define FE_CU_REG_COMM_MB_CTR__M 0x1 |
| 2392 | #define FE_CU_REG_COMM_MB_CTR_OFF 0x0 | 2392 | #define FE_CU_REG_COMM_MB_CTR_OFF 0x0 |
| 2393 | #define FE_CU_REG_COMM_MB_CTR_ON 0x1 | 2393 | #define FE_CU_REG_COMM_MB_CTR_ON 0x1 |
| 2394 | #define FE_CU_REG_COMM_MB_OBS__B 1 | 2394 | #define FE_CU_REG_COMM_MB_OBS__B 1 |
| 2395 | #define FE_CU_REG_COMM_MB_OBS__W 1 | 2395 | #define FE_CU_REG_COMM_MB_OBS__W 1 |
| 2396 | #define FE_CU_REG_COMM_MB_OBS__M 0x2 | 2396 | #define FE_CU_REG_COMM_MB_OBS__M 0x2 |
| 2397 | #define FE_CU_REG_COMM_MB_OBS_OFF 0x0 | 2397 | #define FE_CU_REG_COMM_MB_OBS_OFF 0x0 |
| 2398 | #define FE_CU_REG_COMM_MB_OBS_ON 0x2 | 2398 | #define FE_CU_REG_COMM_MB_OBS_ON 0x2 |
| 2399 | #define FE_CU_REG_COMM_MB_MUX__B 2 | 2399 | #define FE_CU_REG_COMM_MB_MUX__B 2 |
| 2400 | #define FE_CU_REG_COMM_MB_MUX__W 1 | 2400 | #define FE_CU_REG_COMM_MB_MUX__W 1 |
| 2401 | #define FE_CU_REG_COMM_MB_MUX__M 0x4 | 2401 | #define FE_CU_REG_COMM_MB_MUX__M 0x4 |
| 2402 | #define FE_CU_REG_COMM_MB_MUX_REAL 0x0 | 2402 | #define FE_CU_REG_COMM_MB_MUX_REAL 0x0 |
| 2403 | #define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 | 2403 | #define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 |
| 2404 | 2404 | ||
| 2405 | #define FE_CU_REG_COMM_SERVICE0__A 0xC70003 | 2405 | #define FE_CU_REG_COMM_SERVICE0__A 0xC70003 |
| 2406 | #define FE_CU_REG_COMM_SERVICE0__W 10 | 2406 | #define FE_CU_REG_COMM_SERVICE0__W 10 |
| 2407 | #define FE_CU_REG_COMM_SERVICE0__M 0x3FF | 2407 | #define FE_CU_REG_COMM_SERVICE0__M 0x3FF |
| 2408 | 2408 | ||
| 2409 | #define FE_CU_REG_COMM_SERVICE1__A 0xC70004 | 2409 | #define FE_CU_REG_COMM_SERVICE1__A 0xC70004 |
| 2410 | #define FE_CU_REG_COMM_SERVICE1__W 11 | 2410 | #define FE_CU_REG_COMM_SERVICE1__W 11 |
| 2411 | #define FE_CU_REG_COMM_SERVICE1__M 0x7FF | 2411 | #define FE_CU_REG_COMM_SERVICE1__M 0x7FF |
| 2412 | 2412 | ||
| 2413 | #define FE_CU_REG_COMM_ACT__A 0xC70005 | 2413 | #define FE_CU_REG_COMM_ACT__A 0xC70005 |
| 2414 | #define FE_CU_REG_COMM_ACT__W 2 | 2414 | #define FE_CU_REG_COMM_ACT__W 2 |
| 2415 | #define FE_CU_REG_COMM_ACT__M 0x3 | 2415 | #define FE_CU_REG_COMM_ACT__M 0x3 |
| 2416 | 2416 | ||
| 2417 | #define FE_CU_REG_COMM_CNT__A 0xC70006 | 2417 | #define FE_CU_REG_COMM_CNT__A 0xC70006 |
| 2418 | #define FE_CU_REG_COMM_CNT__W 16 | 2418 | #define FE_CU_REG_COMM_CNT__W 16 |
| 2419 | #define FE_CU_REG_COMM_CNT__M 0xFFFF | 2419 | #define FE_CU_REG_COMM_CNT__M 0xFFFF |
| 2420 | 2420 | ||
| 2421 | #define FE_CU_REG_COMM_INT_STA__A 0xC70007 | 2421 | #define FE_CU_REG_COMM_INT_STA__A 0xC70007 |
| 2422 | #define FE_CU_REG_COMM_INT_STA__W 2 | 2422 | #define FE_CU_REG_COMM_INT_STA__W 2 |
| 2423 | #define FE_CU_REG_COMM_INT_STA__M 0x3 | 2423 | #define FE_CU_REG_COMM_INT_STA__M 0x3 |
| 2424 | #define FE_CU_REG_COMM_INT_STA_FE_START__B 0 | 2424 | #define FE_CU_REG_COMM_INT_STA_FE_START__B 0 |
| 2425 | #define FE_CU_REG_COMM_INT_STA_FE_START__W 1 | 2425 | #define FE_CU_REG_COMM_INT_STA_FE_START__W 1 |
| 2426 | #define FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 | 2426 | #define FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 |
| 2427 | #define FE_CU_REG_COMM_INT_STA_FT_START__B 1 | 2427 | #define FE_CU_REG_COMM_INT_STA_FT_START__B 1 |
| 2428 | #define FE_CU_REG_COMM_INT_STA_FT_START__W 1 | 2428 | #define FE_CU_REG_COMM_INT_STA_FT_START__W 1 |
| 2429 | #define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 | 2429 | #define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 |
| 2430 | 2430 | ||
| 2431 | #define FE_CU_REG_COMM_INT_MSK__A 0xC70008 | 2431 | #define FE_CU_REG_COMM_INT_MSK__A 0xC70008 |
| 2432 | #define FE_CU_REG_COMM_INT_MSK__W 2 | 2432 | #define FE_CU_REG_COMM_INT_MSK__W 2 |
| 2433 | #define FE_CU_REG_COMM_INT_MSK__M 0x3 | 2433 | #define FE_CU_REG_COMM_INT_MSK__M 0x3 |
| 2434 | #define FE_CU_REG_COMM_INT_MSK_FE_START__B 0 | 2434 | #define FE_CU_REG_COMM_INT_MSK_FE_START__B 0 |
| 2435 | #define FE_CU_REG_COMM_INT_MSK_FE_START__W 1 | 2435 | #define FE_CU_REG_COMM_INT_MSK_FE_START__W 1 |
| 2436 | #define FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 | 2436 | #define FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 |
| 2437 | #define FE_CU_REG_COMM_INT_MSK_FT_START__B 1 | 2437 | #define FE_CU_REG_COMM_INT_MSK_FT_START__B 1 |
| 2438 | #define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 | 2438 | #define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 |
| 2439 | #define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 | 2439 | #define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 |
| 2440 | 2440 | ||
| 2441 | #define FE_CU_REG_MODE__A 0xC70010 | 2441 | #define FE_CU_REG_MODE__A 0xC70010 |
| 2442 | #define FE_CU_REG_MODE__W 3 | 2442 | #define FE_CU_REG_MODE__W 3 |
| 2443 | #define FE_CU_REG_MODE__M 0x7 | 2443 | #define FE_CU_REG_MODE__M 0x7 |
| 2444 | #define FE_CU_REG_MODE_INIT 0x0 | 2444 | #define FE_CU_REG_MODE_INIT 0x0 |
| 2445 | 2445 | ||
| 2446 | #define FE_CU_REG_MODE_FFT__B 0 | 2446 | #define FE_CU_REG_MODE_FFT__B 0 |
| 2447 | #define FE_CU_REG_MODE_FFT__W 1 | 2447 | #define FE_CU_REG_MODE_FFT__W 1 |
| 2448 | #define FE_CU_REG_MODE_FFT__M 0x1 | 2448 | #define FE_CU_REG_MODE_FFT__M 0x1 |
| 2449 | #define FE_CU_REG_MODE_FFT_M8K 0x0 | 2449 | #define FE_CU_REG_MODE_FFT_M8K 0x0 |
| 2450 | #define FE_CU_REG_MODE_FFT_M2K 0x1 | 2450 | #define FE_CU_REG_MODE_FFT_M2K 0x1 |
| 2451 | 2451 | ||
| 2452 | #define FE_CU_REG_MODE_COR__B 1 | 2452 | #define FE_CU_REG_MODE_COR__B 1 |
| 2453 | #define FE_CU_REG_MODE_COR__W 1 | 2453 | #define FE_CU_REG_MODE_COR__W 1 |
| 2454 | #define FE_CU_REG_MODE_COR__M 0x2 | 2454 | #define FE_CU_REG_MODE_COR__M 0x2 |
| 2455 | #define FE_CU_REG_MODE_COR_OFF 0x0 | 2455 | #define FE_CU_REG_MODE_COR_OFF 0x0 |
| 2456 | #define FE_CU_REG_MODE_COR_ON 0x2 | 2456 | #define FE_CU_REG_MODE_COR_ON 0x2 |
| 2457 | 2457 | ||
| 2458 | #define FE_CU_REG_MODE_IFD__B 2 | 2458 | #define FE_CU_REG_MODE_IFD__B 2 |
| 2459 | #define FE_CU_REG_MODE_IFD__W 1 | 2459 | #define FE_CU_REG_MODE_IFD__W 1 |
| 2460 | #define FE_CU_REG_MODE_IFD__M 0x4 | 2460 | #define FE_CU_REG_MODE_IFD__M 0x4 |
| 2461 | #define FE_CU_REG_MODE_IFD_ENABLE 0x0 | 2461 | #define FE_CU_REG_MODE_IFD_ENABLE 0x0 |
| 2462 | #define FE_CU_REG_MODE_IFD_DISABLE 0x4 | 2462 | #define FE_CU_REG_MODE_IFD_DISABLE 0x4 |
| 2463 | 2463 | ||
| 2464 | #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 | 2464 | #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 |
| 2465 | #define FE_CU_REG_FRM_CNT_RST__W 15 | 2465 | #define FE_CU_REG_FRM_CNT_RST__W 15 |
| 2466 | #define FE_CU_REG_FRM_CNT_RST__M 0x7FFF | 2466 | #define FE_CU_REG_FRM_CNT_RST__M 0x7FFF |
| 2467 | #define FE_CU_REG_FRM_CNT_RST_INIT 0x0 | 2467 | #define FE_CU_REG_FRM_CNT_RST_INIT 0x0 |
| 2468 | 2468 | ||
| 2469 | #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 | 2469 | #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 |
| 2470 | #define FE_CU_REG_FRM_CNT_STR__W 15 | 2470 | #define FE_CU_REG_FRM_CNT_STR__W 15 |
| 2471 | #define FE_CU_REG_FRM_CNT_STR__M 0x7FFF | 2471 | #define FE_CU_REG_FRM_CNT_STR__M 0x7FFF |
| 2472 | #define FE_CU_REG_FRM_CNT_STR_INIT 0x0 | 2472 | #define FE_CU_REG_FRM_CNT_STR_INIT 0x0 |
| 2473 | 2473 | ||
| 2474 | #define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 | 2474 | #define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 |
| 2475 | #define FE_CU_REG_FRM_SMP_CNT__W 15 | 2475 | #define FE_CU_REG_FRM_SMP_CNT__W 15 |
| 2476 | #define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF | 2476 | #define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF |
| 2477 | 2477 | ||
| 2478 | #define FE_CU_REG_FRM_SMB_CNT__A 0xC70014 | 2478 | #define FE_CU_REG_FRM_SMB_CNT__A 0xC70014 |
| 2479 | #define FE_CU_REG_FRM_SMB_CNT__W 16 | 2479 | #define FE_CU_REG_FRM_SMB_CNT__W 16 |
| 2480 | #define FE_CU_REG_FRM_SMB_CNT__M 0xFFFF | 2480 | #define FE_CU_REG_FRM_SMB_CNT__M 0xFFFF |
| 2481 | 2481 | ||
| 2482 | #define FE_CU_REG_CMP_MAX_DAT__A 0xC70015 | 2482 | #define FE_CU_REG_CMP_MAX_DAT__A 0xC70015 |
| 2483 | #define FE_CU_REG_CMP_MAX_DAT__W 12 | 2483 | #define FE_CU_REG_CMP_MAX_DAT__W 12 |
| 2484 | #define FE_CU_REG_CMP_MAX_DAT__M 0xFFF | 2484 | #define FE_CU_REG_CMP_MAX_DAT__M 0xFFF |
| 2485 | 2485 | ||
| 2486 | #define FE_CU_REG_CMP_MAX_ADR__A 0xC70016 | 2486 | #define FE_CU_REG_CMP_MAX_ADR__A 0xC70016 |
| 2487 | #define FE_CU_REG_CMP_MAX_ADR__W 10 | 2487 | #define FE_CU_REG_CMP_MAX_ADR__W 10 |
| 2488 | #define FE_CU_REG_CMP_MAX_ADR__M 0x3FF | 2488 | #define FE_CU_REG_CMP_MAX_ADR__M 0x3FF |
| 2489 | 2489 | ||
| 2490 | #define FE_CU_REG_CTR_NF1_WLO__A 0xC70017 | 2490 | #define FE_CU_REG_CTR_NF1_WLO__A 0xC70017 |
| 2491 | #define FE_CU_REG_CTR_NF1_WLO__W 15 | 2491 | #define FE_CU_REG_CTR_NF1_WLO__W 15 |
| 2492 | #define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF | 2492 | #define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF |
| 2493 | #define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 | 2493 | #define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 |
| 2494 | 2494 | ||
| 2495 | #define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 | 2495 | #define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 |
| 2496 | #define FE_CU_REG_CTR_NF1_WHI__W 15 | 2496 | #define FE_CU_REG_CTR_NF1_WHI__W 15 |
| 2497 | #define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF | 2497 | #define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF |
| 2498 | #define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 | 2498 | #define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 |
| 2499 | 2499 | ||
| 2500 | #define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 | 2500 | #define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 |
| 2501 | #define FE_CU_REG_CTR_NF2_WLO__W 15 | 2501 | #define FE_CU_REG_CTR_NF2_WLO__W 15 |
| 2502 | #define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF | 2502 | #define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF |
| 2503 | #define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 | 2503 | #define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 |
| 2504 | 2504 | ||
| 2505 | #define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A | 2505 | #define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A |
| 2506 | #define FE_CU_REG_CTR_NF2_WHI__W 15 | 2506 | #define FE_CU_REG_CTR_NF2_WHI__W 15 |
| 2507 | #define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF | 2507 | #define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF |
| 2508 | #define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 | 2508 | #define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 |
| 2509 | 2509 | ||
| 2510 | #define FE_CU_REG_DIV_NF1_REA__A 0xC7001B | 2510 | #define FE_CU_REG_DIV_NF1_REA__A 0xC7001B |
| 2511 | #define FE_CU_REG_DIV_NF1_REA__W 12 | 2511 | #define FE_CU_REG_DIV_NF1_REA__W 12 |
| 2512 | #define FE_CU_REG_DIV_NF1_REA__M 0xFFF | 2512 | #define FE_CU_REG_DIV_NF1_REA__M 0xFFF |
| 2513 | 2513 | ||
| 2514 | #define FE_CU_REG_DIV_NF1_IMA__A 0xC7001C | 2514 | #define FE_CU_REG_DIV_NF1_IMA__A 0xC7001C |
| 2515 | #define FE_CU_REG_DIV_NF1_IMA__W 12 | 2515 | #define FE_CU_REG_DIV_NF1_IMA__W 12 |
| 2516 | #define FE_CU_REG_DIV_NF1_IMA__M 0xFFF | 2516 | #define FE_CU_REG_DIV_NF1_IMA__M 0xFFF |
| 2517 | 2517 | ||
| 2518 | #define FE_CU_REG_DIV_NF2_REA__A 0xC7001D | 2518 | #define FE_CU_REG_DIV_NF2_REA__A 0xC7001D |
| 2519 | #define FE_CU_REG_DIV_NF2_REA__W 12 | 2519 | #define FE_CU_REG_DIV_NF2_REA__W 12 |
| 2520 | #define FE_CU_REG_DIV_NF2_REA__M 0xFFF | 2520 | #define FE_CU_REG_DIV_NF2_REA__M 0xFFF |
| 2521 | 2521 | ||
| 2522 | #define FE_CU_REG_DIV_NF2_IMA__A 0xC7001E | 2522 | #define FE_CU_REG_DIV_NF2_IMA__A 0xC7001E |
| 2523 | #define FE_CU_REG_DIV_NF2_IMA__W 12 | 2523 | #define FE_CU_REG_DIV_NF2_IMA__W 12 |
| 2524 | #define FE_CU_REG_DIV_NF2_IMA__M 0xFFF | 2524 | #define FE_CU_REG_DIV_NF2_IMA__M 0xFFF |
| 2525 | 2525 | ||
| 2526 | #define FE_CU_BUF_RAM__A 0xC80000 | 2526 | #define FE_CU_BUF_RAM__A 0xC80000 |
| 2527 | 2527 | ||
| 2528 | #define FE_CU_CMP_RAM__A 0xC90000 | 2528 | #define FE_CU_CMP_RAM__A 0xC90000 |
| 2529 | 2529 | ||
| 2530 | #define FT_SID 0x8 | 2530 | #define FT_SID 0x8 |
| 2531 | 2531 | ||
| 2532 | #define FT_COMM_EXEC__A 0x1000000 | 2532 | #define FT_COMM_EXEC__A 0x1000000 |
| 2533 | #define FT_COMM_EXEC__W 3 | 2533 | #define FT_COMM_EXEC__W 3 |
| 2534 | #define FT_COMM_EXEC__M 0x7 | 2534 | #define FT_COMM_EXEC__M 0x7 |
| 2535 | #define FT_COMM_EXEC_CTL__B 0 | 2535 | #define FT_COMM_EXEC_CTL__B 0 |
| 2536 | #define FT_COMM_EXEC_CTL__W 3 | 2536 | #define FT_COMM_EXEC_CTL__W 3 |
| 2537 | #define FT_COMM_EXEC_CTL__M 0x7 | 2537 | #define FT_COMM_EXEC_CTL__M 0x7 |
| 2538 | #define FT_COMM_EXEC_CTL_STOP 0x0 | 2538 | #define FT_COMM_EXEC_CTL_STOP 0x0 |
| 2539 | #define FT_COMM_EXEC_CTL_ACTIVE 0x1 | 2539 | #define FT_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2540 | #define FT_COMM_EXEC_CTL_HOLD 0x2 | 2540 | #define FT_COMM_EXEC_CTL_HOLD 0x2 |
| 2541 | #define FT_COMM_EXEC_CTL_STEP 0x3 | 2541 | #define FT_COMM_EXEC_CTL_STEP 0x3 |
| 2542 | #define FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 2542 | #define FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 2543 | #define FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 2543 | #define FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 2544 | 2544 | ||
| 2545 | #define FT_COMM_STATE__A 0x1000001 | 2545 | #define FT_COMM_STATE__A 0x1000001 |
| 2546 | #define FT_COMM_STATE__W 16 | 2546 | #define FT_COMM_STATE__W 16 |
| 2547 | #define FT_COMM_STATE__M 0xFFFF | 2547 | #define FT_COMM_STATE__M 0xFFFF |
| 2548 | #define FT_COMM_MB__A 0x1000002 | 2548 | #define FT_COMM_MB__A 0x1000002 |
| 2549 | #define FT_COMM_MB__W 16 | 2549 | #define FT_COMM_MB__W 16 |
| 2550 | #define FT_COMM_MB__M 0xFFFF | 2550 | #define FT_COMM_MB__M 0xFFFF |
| 2551 | #define FT_COMM_SERVICE0__A 0x1000003 | 2551 | #define FT_COMM_SERVICE0__A 0x1000003 |
| 2552 | #define FT_COMM_SERVICE0__W 16 | 2552 | #define FT_COMM_SERVICE0__W 16 |
| 2553 | #define FT_COMM_SERVICE0__M 0xFFFF | 2553 | #define FT_COMM_SERVICE0__M 0xFFFF |
| 2554 | #define FT_COMM_SERVICE1__A 0x1000004 | 2554 | #define FT_COMM_SERVICE1__A 0x1000004 |
| 2555 | #define FT_COMM_SERVICE1__W 16 | 2555 | #define FT_COMM_SERVICE1__W 16 |
| 2556 | #define FT_COMM_SERVICE1__M 0xFFFF | 2556 | #define FT_COMM_SERVICE1__M 0xFFFF |
| 2557 | #define FT_COMM_INT_STA__A 0x1000007 | 2557 | #define FT_COMM_INT_STA__A 0x1000007 |
| 2558 | #define FT_COMM_INT_STA__W 16 | 2558 | #define FT_COMM_INT_STA__W 16 |
| 2559 | #define FT_COMM_INT_STA__M 0xFFFF | 2559 | #define FT_COMM_INT_STA__M 0xFFFF |
| 2560 | #define FT_COMM_INT_MSK__A 0x1000008 | 2560 | #define FT_COMM_INT_MSK__A 0x1000008 |
| 2561 | #define FT_COMM_INT_MSK__W 16 | 2561 | #define FT_COMM_INT_MSK__W 16 |
| 2562 | #define FT_COMM_INT_MSK__M 0xFFFF | 2562 | #define FT_COMM_INT_MSK__M 0xFFFF |
| 2563 | 2563 | ||
| 2564 | #define FT_REG_COMM_EXEC__A 0x1010000 | 2564 | #define FT_REG_COMM_EXEC__A 0x1010000 |
| 2565 | #define FT_REG_COMM_EXEC__W 3 | 2565 | #define FT_REG_COMM_EXEC__W 3 |
| 2566 | #define FT_REG_COMM_EXEC__M 0x7 | 2566 | #define FT_REG_COMM_EXEC__M 0x7 |
| 2567 | #define FT_REG_COMM_EXEC_CTL__B 0 | 2567 | #define FT_REG_COMM_EXEC_CTL__B 0 |
| 2568 | #define FT_REG_COMM_EXEC_CTL__W 3 | 2568 | #define FT_REG_COMM_EXEC_CTL__W 3 |
| 2569 | #define FT_REG_COMM_EXEC_CTL__M 0x7 | 2569 | #define FT_REG_COMM_EXEC_CTL__M 0x7 |
| 2570 | #define FT_REG_COMM_EXEC_CTL_STOP 0x0 | 2570 | #define FT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 2571 | #define FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 2571 | #define FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2572 | #define FT_REG_COMM_EXEC_CTL_HOLD 0x2 | 2572 | #define FT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 2573 | #define FT_REG_COMM_EXEC_CTL_STEP 0x3 | 2573 | #define FT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 2574 | 2574 | ||
| 2575 | #define FT_REG_COMM_MB__A 0x1010002 | 2575 | #define FT_REG_COMM_MB__A 0x1010002 |
| 2576 | #define FT_REG_COMM_MB__W 3 | 2576 | #define FT_REG_COMM_MB__W 3 |
| 2577 | #define FT_REG_COMM_MB__M 0x7 | 2577 | #define FT_REG_COMM_MB__M 0x7 |
| 2578 | #define FT_REG_COMM_MB_CTR__B 0 | 2578 | #define FT_REG_COMM_MB_CTR__B 0 |
| 2579 | #define FT_REG_COMM_MB_CTR__W 1 | 2579 | #define FT_REG_COMM_MB_CTR__W 1 |
| 2580 | #define FT_REG_COMM_MB_CTR__M 0x1 | 2580 | #define FT_REG_COMM_MB_CTR__M 0x1 |
| 2581 | #define FT_REG_COMM_MB_CTR_OFF 0x0 | 2581 | #define FT_REG_COMM_MB_CTR_OFF 0x0 |
| 2582 | #define FT_REG_COMM_MB_CTR_ON 0x1 | 2582 | #define FT_REG_COMM_MB_CTR_ON 0x1 |
| 2583 | #define FT_REG_COMM_MB_OBS__B 1 | 2583 | #define FT_REG_COMM_MB_OBS__B 1 |
| 2584 | #define FT_REG_COMM_MB_OBS__W 1 | 2584 | #define FT_REG_COMM_MB_OBS__W 1 |
| 2585 | #define FT_REG_COMM_MB_OBS__M 0x2 | 2585 | #define FT_REG_COMM_MB_OBS__M 0x2 |
| 2586 | #define FT_REG_COMM_MB_OBS_OFF 0x0 | 2586 | #define FT_REG_COMM_MB_OBS_OFF 0x0 |
| 2587 | #define FT_REG_COMM_MB_OBS_ON 0x2 | 2587 | #define FT_REG_COMM_MB_OBS_ON 0x2 |
| 2588 | 2588 | ||
| 2589 | #define FT_REG_COMM_SERVICE0__A 0x1010003 | 2589 | #define FT_REG_COMM_SERVICE0__A 0x1010003 |
| 2590 | #define FT_REG_COMM_SERVICE0__W 10 | 2590 | #define FT_REG_COMM_SERVICE0__W 10 |
| 2591 | #define FT_REG_COMM_SERVICE0__M 0x3FF | 2591 | #define FT_REG_COMM_SERVICE0__M 0x3FF |
| 2592 | #define FT_REG_COMM_SERVICE0_FT__B 8 | 2592 | #define FT_REG_COMM_SERVICE0_FT__B 8 |
| 2593 | #define FT_REG_COMM_SERVICE0_FT__W 1 | 2593 | #define FT_REG_COMM_SERVICE0_FT__W 1 |
| 2594 | #define FT_REG_COMM_SERVICE0_FT__M 0x100 | 2594 | #define FT_REG_COMM_SERVICE0_FT__M 0x100 |
| 2595 | 2595 | ||
| 2596 | #define FT_REG_COMM_SERVICE1__A 0x1010004 | 2596 | #define FT_REG_COMM_SERVICE1__A 0x1010004 |
| 2597 | #define FT_REG_COMM_SERVICE1__W 11 | 2597 | #define FT_REG_COMM_SERVICE1__W 11 |
| 2598 | #define FT_REG_COMM_SERVICE1__M 0x7FF | 2598 | #define FT_REG_COMM_SERVICE1__M 0x7FF |
| 2599 | 2599 | ||
| 2600 | #define FT_REG_COMM_INT_STA__A 0x1010007 | 2600 | #define FT_REG_COMM_INT_STA__A 0x1010007 |
| 2601 | #define FT_REG_COMM_INT_STA__W 2 | 2601 | #define FT_REG_COMM_INT_STA__W 2 |
| 2602 | #define FT_REG_COMM_INT_STA__M 0x3 | 2602 | #define FT_REG_COMM_INT_STA__M 0x3 |
| 2603 | #define FT_REG_COMM_INT_STA_NEW_MEAS__B 0 | 2603 | #define FT_REG_COMM_INT_STA_NEW_MEAS__B 0 |
| 2604 | #define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 | 2604 | #define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 |
| 2605 | #define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 | 2605 | #define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 |
| 2606 | 2606 | ||
| 2607 | #define FT_REG_COMM_INT_MSK__A 0x1010008 | 2607 | #define FT_REG_COMM_INT_MSK__A 0x1010008 |
| 2608 | #define FT_REG_COMM_INT_MSK__W 2 | 2608 | #define FT_REG_COMM_INT_MSK__W 2 |
| 2609 | #define FT_REG_COMM_INT_MSK__M 0x3 | 2609 | #define FT_REG_COMM_INT_MSK__M 0x3 |
| 2610 | #define FT_REG_COMM_INT_MSK_NEW_MEAS__B 0 | 2610 | #define FT_REG_COMM_INT_MSK_NEW_MEAS__B 0 |
| 2611 | #define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 | 2611 | #define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 |
| 2612 | #define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 | 2612 | #define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 |
| 2613 | 2613 | ||
| 2614 | #define FT_REG_MODE_2K__A 0x1010010 | 2614 | #define FT_REG_MODE_2K__A 0x1010010 |
| 2615 | #define FT_REG_MODE_2K__W 1 | 2615 | #define FT_REG_MODE_2K__W 1 |
| 2616 | #define FT_REG_MODE_2K__M 0x1 | 2616 | #define FT_REG_MODE_2K__M 0x1 |
| 2617 | #define FT_REG_MODE_2K_MODE_8K 0x0 | 2617 | #define FT_REG_MODE_2K_MODE_8K 0x0 |
| 2618 | #define FT_REG_MODE_2K_MODE_2K 0x1 | 2618 | #define FT_REG_MODE_2K_MODE_2K 0x1 |
| 2619 | #define FT_REG_MODE_2K_INIT 0x0 | 2619 | #define FT_REG_MODE_2K_INIT 0x0 |
| 2620 | 2620 | ||
| 2621 | #define FT_REG_BUS_MOD__A 0x1010011 | 2621 | #define FT_REG_BUS_MOD__A 0x1010011 |
| 2622 | #define FT_REG_BUS_MOD__W 1 | 2622 | #define FT_REG_BUS_MOD__W 1 |
| 2623 | #define FT_REG_BUS_MOD__M 0x1 | 2623 | #define FT_REG_BUS_MOD__M 0x1 |
| 2624 | #define FT_REG_BUS_MOD_INPUT 0x0 | 2624 | #define FT_REG_BUS_MOD_INPUT 0x0 |
| 2625 | #define FT_REG_BUS_MOD_PILOT 0x1 | 2625 | #define FT_REG_BUS_MOD_PILOT 0x1 |
| 2626 | #define FT_REG_BUS_MOD_INIT 0x0 | 2626 | #define FT_REG_BUS_MOD_INIT 0x0 |
| 2627 | 2627 | ||
| 2628 | #define FT_REG_BUS_REAL__A 0x1010012 | 2628 | #define FT_REG_BUS_REAL__A 0x1010012 |
| 2629 | #define FT_REG_BUS_REAL__W 10 | 2629 | #define FT_REG_BUS_REAL__W 10 |
| 2630 | #define FT_REG_BUS_REAL__M 0x3FF | 2630 | #define FT_REG_BUS_REAL__M 0x3FF |
| 2631 | #define FT_REG_BUS_REAL_INIT 0x0 | 2631 | #define FT_REG_BUS_REAL_INIT 0x0 |
| 2632 | 2632 | ||
| 2633 | #define FT_REG_BUS_IMAG__A 0x1010013 | 2633 | #define FT_REG_BUS_IMAG__A 0x1010013 |
| 2634 | #define FT_REG_BUS_IMAG__W 10 | 2634 | #define FT_REG_BUS_IMAG__W 10 |
| 2635 | #define FT_REG_BUS_IMAG__M 0x3FF | 2635 | #define FT_REG_BUS_IMAG__M 0x3FF |
| 2636 | #define FT_REG_BUS_IMAG_INIT 0x0 | 2636 | #define FT_REG_BUS_IMAG_INIT 0x0 |
| 2637 | 2637 | ||
| 2638 | #define FT_REG_BUS_VAL__A 0x1010014 | 2638 | #define FT_REG_BUS_VAL__A 0x1010014 |
| 2639 | #define FT_REG_BUS_VAL__W 1 | 2639 | #define FT_REG_BUS_VAL__W 1 |
| 2640 | #define FT_REG_BUS_VAL__M 0x1 | 2640 | #define FT_REG_BUS_VAL__M 0x1 |
| 2641 | #define FT_REG_BUS_VAL_INIT 0x0 | 2641 | #define FT_REG_BUS_VAL_INIT 0x0 |
| 2642 | 2642 | ||
| 2643 | #define FT_REG_PEAK__A 0x1010015 | 2643 | #define FT_REG_PEAK__A 0x1010015 |
| 2644 | #define FT_REG_PEAK__W 11 | 2644 | #define FT_REG_PEAK__W 11 |
| 2645 | #define FT_REG_PEAK__M 0x7FF | 2645 | #define FT_REG_PEAK__M 0x7FF |
| 2646 | #define FT_REG_PEAK_INIT 0x0 | 2646 | #define FT_REG_PEAK_INIT 0x0 |
| 2647 | 2647 | ||
| 2648 | #define FT_REG_NORM_OFF__A 0x1010016 | 2648 | #define FT_REG_NORM_OFF__A 0x1010016 |
| 2649 | #define FT_REG_NORM_OFF__W 4 | 2649 | #define FT_REG_NORM_OFF__W 4 |
| 2650 | #define FT_REG_NORM_OFF__M 0xF | 2650 | #define FT_REG_NORM_OFF__M 0xF |
| 2651 | #define FT_REG_NORM_OFF_INIT 0x2 | 2651 | #define FT_REG_NORM_OFF_INIT 0x2 |
| 2652 | 2652 | ||
| 2653 | #define FT_ST1_RAM__A 0x1020000 | 2653 | #define FT_ST1_RAM__A 0x1020000 |
| 2654 | 2654 | ||
| 2655 | #define FT_ST2_RAM__A 0x1030000 | 2655 | #define FT_ST2_RAM__A 0x1030000 |
| 2656 | 2656 | ||
| 2657 | #define FT_ST3_RAM__A 0x1040000 | 2657 | #define FT_ST3_RAM__A 0x1040000 |
| 2658 | 2658 | ||
| 2659 | #define FT_ST5_RAM__A 0x1050000 | 2659 | #define FT_ST5_RAM__A 0x1050000 |
| 2660 | 2660 | ||
| 2661 | #define FT_ST6_RAM__A 0x1060000 | 2661 | #define FT_ST6_RAM__A 0x1060000 |
| 2662 | 2662 | ||
| 2663 | #define FT_ST8_RAM__A 0x1070000 | 2663 | #define FT_ST8_RAM__A 0x1070000 |
| 2664 | 2664 | ||
| 2665 | #define FT_ST9_RAM__A 0x1080000 | 2665 | #define FT_ST9_RAM__A 0x1080000 |
| 2666 | 2666 | ||
| 2667 | #define CP_SID 0x9 | 2667 | #define CP_SID 0x9 |
| 2668 | 2668 | ||
| 2669 | #define CP_COMM_EXEC__A 0x1400000 | 2669 | #define CP_COMM_EXEC__A 0x1400000 |
| 2670 | #define CP_COMM_EXEC__W 3 | 2670 | #define CP_COMM_EXEC__W 3 |
| 2671 | #define CP_COMM_EXEC__M 0x7 | 2671 | #define CP_COMM_EXEC__M 0x7 |
| 2672 | #define CP_COMM_EXEC_CTL__B 0 | 2672 | #define CP_COMM_EXEC_CTL__B 0 |
| 2673 | #define CP_COMM_EXEC_CTL__W 3 | 2673 | #define CP_COMM_EXEC_CTL__W 3 |
| 2674 | #define CP_COMM_EXEC_CTL__M 0x7 | 2674 | #define CP_COMM_EXEC_CTL__M 0x7 |
| 2675 | #define CP_COMM_EXEC_CTL_STOP 0x0 | 2675 | #define CP_COMM_EXEC_CTL_STOP 0x0 |
| 2676 | #define CP_COMM_EXEC_CTL_ACTIVE 0x1 | 2676 | #define CP_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2677 | #define CP_COMM_EXEC_CTL_HOLD 0x2 | 2677 | #define CP_COMM_EXEC_CTL_HOLD 0x2 |
| 2678 | #define CP_COMM_EXEC_CTL_STEP 0x3 | 2678 | #define CP_COMM_EXEC_CTL_STEP 0x3 |
| 2679 | #define CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 2679 | #define CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 2680 | #define CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 2680 | #define CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 2681 | 2681 | ||
| 2682 | #define CP_COMM_STATE__A 0x1400001 | 2682 | #define CP_COMM_STATE__A 0x1400001 |
| 2683 | #define CP_COMM_STATE__W 16 | 2683 | #define CP_COMM_STATE__W 16 |
| 2684 | #define CP_COMM_STATE__M 0xFFFF | 2684 | #define CP_COMM_STATE__M 0xFFFF |
| 2685 | #define CP_COMM_MB__A 0x1400002 | 2685 | #define CP_COMM_MB__A 0x1400002 |
| 2686 | #define CP_COMM_MB__W 16 | 2686 | #define CP_COMM_MB__W 16 |
| 2687 | #define CP_COMM_MB__M 0xFFFF | 2687 | #define CP_COMM_MB__M 0xFFFF |
| 2688 | #define CP_COMM_SERVICE0__A 0x1400003 | 2688 | #define CP_COMM_SERVICE0__A 0x1400003 |
| 2689 | #define CP_COMM_SERVICE0__W 16 | 2689 | #define CP_COMM_SERVICE0__W 16 |
| 2690 | #define CP_COMM_SERVICE0__M 0xFFFF | 2690 | #define CP_COMM_SERVICE0__M 0xFFFF |
| 2691 | #define CP_COMM_SERVICE1__A 0x1400004 | 2691 | #define CP_COMM_SERVICE1__A 0x1400004 |
| 2692 | #define CP_COMM_SERVICE1__W 16 | 2692 | #define CP_COMM_SERVICE1__W 16 |
| 2693 | #define CP_COMM_SERVICE1__M 0xFFFF | 2693 | #define CP_COMM_SERVICE1__M 0xFFFF |
| 2694 | #define CP_COMM_INT_STA__A 0x1400007 | 2694 | #define CP_COMM_INT_STA__A 0x1400007 |
| 2695 | #define CP_COMM_INT_STA__W 16 | 2695 | #define CP_COMM_INT_STA__W 16 |
| 2696 | #define CP_COMM_INT_STA__M 0xFFFF | 2696 | #define CP_COMM_INT_STA__M 0xFFFF |
| 2697 | #define CP_COMM_INT_MSK__A 0x1400008 | 2697 | #define CP_COMM_INT_MSK__A 0x1400008 |
| 2698 | #define CP_COMM_INT_MSK__W 16 | 2698 | #define CP_COMM_INT_MSK__W 16 |
| 2699 | #define CP_COMM_INT_MSK__M 0xFFFF | 2699 | #define CP_COMM_INT_MSK__M 0xFFFF |
| 2700 | 2700 | ||
| 2701 | #define CP_REG_COMM_EXEC__A 0x1410000 | 2701 | #define CP_REG_COMM_EXEC__A 0x1410000 |
| 2702 | #define CP_REG_COMM_EXEC__W 3 | 2702 | #define CP_REG_COMM_EXEC__W 3 |
| 2703 | #define CP_REG_COMM_EXEC__M 0x7 | 2703 | #define CP_REG_COMM_EXEC__M 0x7 |
| 2704 | #define CP_REG_COMM_EXEC_CTL__B 0 | 2704 | #define CP_REG_COMM_EXEC_CTL__B 0 |
| 2705 | #define CP_REG_COMM_EXEC_CTL__W 3 | 2705 | #define CP_REG_COMM_EXEC_CTL__W 3 |
| 2706 | #define CP_REG_COMM_EXEC_CTL__M 0x7 | 2706 | #define CP_REG_COMM_EXEC_CTL__M 0x7 |
| 2707 | #define CP_REG_COMM_EXEC_CTL_STOP 0x0 | 2707 | #define CP_REG_COMM_EXEC_CTL_STOP 0x0 |
| 2708 | #define CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 2708 | #define CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 2709 | #define CP_REG_COMM_EXEC_CTL_HOLD 0x2 | 2709 | #define CP_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 2710 | #define CP_REG_COMM_EXEC_CTL_STEP 0x3 | 2710 | #define CP_REG_COMM_EXEC_CTL_STEP 0x3 |
| 2711 | 2711 | ||
| 2712 | #define CP_REG_COMM_MB__A 0x1410002 | 2712 | #define CP_REG_COMM_MB__A 0x1410002 |
| 2713 | #define CP_REG_COMM_MB__W 3 | 2713 | #define CP_REG_COMM_MB__W 3 |
| 2714 | #define CP_REG_COMM_MB__M 0x7 | 2714 | #define CP_REG_COMM_MB__M 0x7 |
| 2715 | #define CP_REG_COMM_MB_CTR__B 0 | 2715 | #define CP_REG_COMM_MB_CTR__B 0 |
| 2716 | #define CP_REG_COMM_MB_CTR__W 1 | 2716 | #define CP_REG_COMM_MB_CTR__W 1 |
| 2717 | #define CP_REG_COMM_MB_CTR__M 0x1 | 2717 | #define CP_REG_COMM_MB_CTR__M 0x1 |
| 2718 | #define CP_REG_COMM_MB_CTR_OFF 0x0 | 2718 | #define CP_REG_COMM_MB_CTR_OFF 0x0 |
| 2719 | #define CP_REG_COMM_MB_CTR_ON 0x1 | 2719 | #define CP_REG_COMM_MB_CTR_ON 0x1 |
| 2720 | #define CP_REG_COMM_MB_OBS__B 1 | 2720 | #define CP_REG_COMM_MB_OBS__B 1 |
| 2721 | #define CP_REG_COMM_MB_OBS__W 1 | 2721 | #define CP_REG_COMM_MB_OBS__W 1 |
| 2722 | #define CP_REG_COMM_MB_OBS__M 0x2 | 2722 | #define CP_REG_COMM_MB_OBS__M 0x2 |
| 2723 | #define CP_REG_COMM_MB_OBS_OFF 0x0 | 2723 | #define CP_REG_COMM_MB_OBS_OFF 0x0 |
| 2724 | #define CP_REG_COMM_MB_OBS_ON 0x2 | 2724 | #define CP_REG_COMM_MB_OBS_ON 0x2 |
| 2725 | 2725 | ||
| 2726 | #define CP_REG_COMM_SERVICE0__A 0x1410003 | 2726 | #define CP_REG_COMM_SERVICE0__A 0x1410003 |
| 2727 | #define CP_REG_COMM_SERVICE0__W 10 | 2727 | #define CP_REG_COMM_SERVICE0__W 10 |
| 2728 | #define CP_REG_COMM_SERVICE0__M 0x3FF | 2728 | #define CP_REG_COMM_SERVICE0__M 0x3FF |
| 2729 | #define CP_REG_COMM_SERVICE0_CP__B 9 | 2729 | #define CP_REG_COMM_SERVICE0_CP__B 9 |
| 2730 | #define CP_REG_COMM_SERVICE0_CP__W 1 | 2730 | #define CP_REG_COMM_SERVICE0_CP__W 1 |
| 2731 | #define CP_REG_COMM_SERVICE0_CP__M 0x200 | 2731 | #define CP_REG_COMM_SERVICE0_CP__M 0x200 |
| 2732 | 2732 | ||
| 2733 | #define CP_REG_COMM_SERVICE1__A 0x1410004 | 2733 | #define CP_REG_COMM_SERVICE1__A 0x1410004 |
| 2734 | #define CP_REG_COMM_SERVICE1__W 11 | 2734 | #define CP_REG_COMM_SERVICE1__W 11 |
| 2735 | #define CP_REG_COMM_SERVICE1__M 0x7FF | 2735 | #define CP_REG_COMM_SERVICE1__M 0x7FF |
| 2736 | 2736 | ||
| 2737 | #define CP_REG_COMM_INT_STA__A 0x1410007 | 2737 | #define CP_REG_COMM_INT_STA__A 0x1410007 |
| 2738 | #define CP_REG_COMM_INT_STA__W 2 | 2738 | #define CP_REG_COMM_INT_STA__W 2 |
| 2739 | #define CP_REG_COMM_INT_STA__M 0x3 | 2739 | #define CP_REG_COMM_INT_STA__M 0x3 |
| 2740 | #define CP_REG_COMM_INT_STA_NEW_MEAS__B 0 | 2740 | #define CP_REG_COMM_INT_STA_NEW_MEAS__B 0 |
| 2741 | #define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 | 2741 | #define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 |
| 2742 | #define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 | 2742 | #define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 |
| 2743 | 2743 | ||
| 2744 | #define CP_REG_COMM_INT_MSK__A 0x1410008 | 2744 | #define CP_REG_COMM_INT_MSK__A 0x1410008 |
| 2745 | #define CP_REG_COMM_INT_MSK__W 2 | 2745 | #define CP_REG_COMM_INT_MSK__W 2 |
| 2746 | #define CP_REG_COMM_INT_MSK__M 0x3 | 2746 | #define CP_REG_COMM_INT_MSK__M 0x3 |
| 2747 | #define CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 | 2747 | #define CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 |
| 2748 | #define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 | 2748 | #define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 |
| 2749 | #define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 | 2749 | #define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 |
| 2750 | 2750 | ||
| 2751 | #define CP_REG_MODE_2K__A 0x1410010 | 2751 | #define CP_REG_MODE_2K__A 0x1410010 |
| 2752 | #define CP_REG_MODE_2K__W 1 | 2752 | #define CP_REG_MODE_2K__W 1 |
| 2753 | #define CP_REG_MODE_2K__M 0x1 | 2753 | #define CP_REG_MODE_2K__M 0x1 |
| 2754 | #define CP_REG_MODE_2K_INIT 0x0 | 2754 | #define CP_REG_MODE_2K_INIT 0x0 |
| 2755 | 2755 | ||
| 2756 | #define CP_REG_INTERVAL__A 0x1410011 | 2756 | #define CP_REG_INTERVAL__A 0x1410011 |
| 2757 | #define CP_REG_INTERVAL__W 4 | 2757 | #define CP_REG_INTERVAL__W 4 |
| 2758 | #define CP_REG_INTERVAL__M 0xF | 2758 | #define CP_REG_INTERVAL__M 0xF |
| 2759 | #define CP_REG_INTERVAL_INIT 0x5 | 2759 | #define CP_REG_INTERVAL_INIT 0x5 |
| 2760 | 2760 | ||
| 2761 | #define CP_REG_SKIP_START0__A 0x1410012 | 2761 | #define CP_REG_SKIP_START0__A 0x1410012 |
| 2762 | #define CP_REG_SKIP_START0__W 13 | 2762 | #define CP_REG_SKIP_START0__W 13 |
| 2763 | #define CP_REG_SKIP_START0__M 0x1FFF | 2763 | #define CP_REG_SKIP_START0__M 0x1FFF |
| 2764 | #define CP_REG_SKIP_START0_INIT 0x0 | 2764 | #define CP_REG_SKIP_START0_INIT 0x0 |
| 2765 | 2765 | ||
| 2766 | #define CP_REG_SKIP_STOP0__A 0x1410013 | 2766 | #define CP_REG_SKIP_STOP0__A 0x1410013 |
| 2767 | #define CP_REG_SKIP_STOP0__W 13 | 2767 | #define CP_REG_SKIP_STOP0__W 13 |
| 2768 | #define CP_REG_SKIP_STOP0__M 0x1FFF | 2768 | #define CP_REG_SKIP_STOP0__M 0x1FFF |
| 2769 | #define CP_REG_SKIP_STOP0_INIT 0x0 | 2769 | #define CP_REG_SKIP_STOP0_INIT 0x0 |
| 2770 | 2770 | ||
| 2771 | #define CP_REG_SKIP_START1__A 0x1410014 | 2771 | #define CP_REG_SKIP_START1__A 0x1410014 |
| 2772 | #define CP_REG_SKIP_START1__W 13 | 2772 | #define CP_REG_SKIP_START1__W 13 |
| 2773 | #define CP_REG_SKIP_START1__M 0x1FFF | 2773 | #define CP_REG_SKIP_START1__M 0x1FFF |
| 2774 | #define CP_REG_SKIP_START1_INIT 0x0 | 2774 | #define CP_REG_SKIP_START1_INIT 0x0 |
| 2775 | 2775 | ||
| 2776 | #define CP_REG_SKIP_STOP1__A 0x1410015 | 2776 | #define CP_REG_SKIP_STOP1__A 0x1410015 |
| 2777 | #define CP_REG_SKIP_STOP1__W 13 | 2777 | #define CP_REG_SKIP_STOP1__W 13 |
| 2778 | #define CP_REG_SKIP_STOP1__M 0x1FFF | 2778 | #define CP_REG_SKIP_STOP1__M 0x1FFF |
| 2779 | #define CP_REG_SKIP_STOP1_INIT 0x0 | 2779 | #define CP_REG_SKIP_STOP1_INIT 0x0 |
| 2780 | 2780 | ||
| 2781 | #define CP_REG_SKIP_START2__A 0x1410016 | 2781 | #define CP_REG_SKIP_START2__A 0x1410016 |
| 2782 | #define CP_REG_SKIP_START2__W 13 | 2782 | #define CP_REG_SKIP_START2__W 13 |
| 2783 | #define CP_REG_SKIP_START2__M 0x1FFF | 2783 | #define CP_REG_SKIP_START2__M 0x1FFF |
| 2784 | #define CP_REG_SKIP_START2_INIT 0x0 | 2784 | #define CP_REG_SKIP_START2_INIT 0x0 |
| 2785 | 2785 | ||
| 2786 | #define CP_REG_SKIP_STOP2__A 0x1410017 | 2786 | #define CP_REG_SKIP_STOP2__A 0x1410017 |
| 2787 | #define CP_REG_SKIP_STOP2__W 13 | 2787 | #define CP_REG_SKIP_STOP2__W 13 |
| 2788 | #define CP_REG_SKIP_STOP2__M 0x1FFF | 2788 | #define CP_REG_SKIP_STOP2__M 0x1FFF |
| 2789 | #define CP_REG_SKIP_STOP2_INIT 0x0 | 2789 | #define CP_REG_SKIP_STOP2_INIT 0x0 |
| 2790 | 2790 | ||
| 2791 | #define CP_REG_SKIP_ENA__A 0x1410018 | 2791 | #define CP_REG_SKIP_ENA__A 0x1410018 |
| 2792 | #define CP_REG_SKIP_ENA__W 3 | 2792 | #define CP_REG_SKIP_ENA__W 3 |
| 2793 | #define CP_REG_SKIP_ENA__M 0x7 | 2793 | #define CP_REG_SKIP_ENA__M 0x7 |
| 2794 | 2794 | ||
| 2795 | #define CP_REG_SKIP_ENA_CPL__B 0 | 2795 | #define CP_REG_SKIP_ENA_CPL__B 0 |
| 2796 | #define CP_REG_SKIP_ENA_CPL__W 1 | 2796 | #define CP_REG_SKIP_ENA_CPL__W 1 |
| 2797 | #define CP_REG_SKIP_ENA_CPL__M 0x1 | 2797 | #define CP_REG_SKIP_ENA_CPL__M 0x1 |
| 2798 | 2798 | ||
| 2799 | #define CP_REG_SKIP_ENA_SPD__B 1 | 2799 | #define CP_REG_SKIP_ENA_SPD__B 1 |
| 2800 | #define CP_REG_SKIP_ENA_SPD__W 1 | 2800 | #define CP_REG_SKIP_ENA_SPD__W 1 |
| 2801 | #define CP_REG_SKIP_ENA_SPD__M 0x2 | 2801 | #define CP_REG_SKIP_ENA_SPD__M 0x2 |
| 2802 | 2802 | ||
| 2803 | #define CP_REG_SKIP_ENA_CPD__B 2 | 2803 | #define CP_REG_SKIP_ENA_CPD__B 2 |
| 2804 | #define CP_REG_SKIP_ENA_CPD__W 1 | 2804 | #define CP_REG_SKIP_ENA_CPD__W 1 |
| 2805 | #define CP_REG_SKIP_ENA_CPD__M 0x4 | 2805 | #define CP_REG_SKIP_ENA_CPD__M 0x4 |
| 2806 | #define CP_REG_SKIP_ENA_INIT 0x0 | 2806 | #define CP_REG_SKIP_ENA_INIT 0x0 |
| 2807 | 2807 | ||
| 2808 | #define CP_REG_BR_MODE_MIX__A 0x1410020 | 2808 | #define CP_REG_BR_MODE_MIX__A 0x1410020 |
| 2809 | #define CP_REG_BR_MODE_MIX__W 1 | 2809 | #define CP_REG_BR_MODE_MIX__W 1 |
| 2810 | #define CP_REG_BR_MODE_MIX__M 0x1 | 2810 | #define CP_REG_BR_MODE_MIX__M 0x1 |
| 2811 | #define CP_REG_BR_MODE_MIX_INIT 0x0 | 2811 | #define CP_REG_BR_MODE_MIX_INIT 0x0 |
| 2812 | 2812 | ||
| 2813 | #define CP_REG_BR_SMB_NR__A 0x1410021 | 2813 | #define CP_REG_BR_SMB_NR__A 0x1410021 |
| 2814 | #define CP_REG_BR_SMB_NR__W 3 | 2814 | #define CP_REG_BR_SMB_NR__W 3 |
| 2815 | #define CP_REG_BR_SMB_NR__M 0x7 | 2815 | #define CP_REG_BR_SMB_NR__M 0x7 |
| 2816 | 2816 | ||
| 2817 | #define CP_REG_BR_SMB_NR_SMB__B 0 | 2817 | #define CP_REG_BR_SMB_NR_SMB__B 0 |
| 2818 | #define CP_REG_BR_SMB_NR_SMB__W 2 | 2818 | #define CP_REG_BR_SMB_NR_SMB__W 2 |
| 2819 | #define CP_REG_BR_SMB_NR_SMB__M 0x3 | 2819 | #define CP_REG_BR_SMB_NR_SMB__M 0x3 |
| 2820 | 2820 | ||
| 2821 | #define CP_REG_BR_SMB_NR_VAL__B 2 | 2821 | #define CP_REG_BR_SMB_NR_VAL__B 2 |
| 2822 | #define CP_REG_BR_SMB_NR_VAL__W 1 | 2822 | #define CP_REG_BR_SMB_NR_VAL__W 1 |
| 2823 | #define CP_REG_BR_SMB_NR_VAL__M 0x4 | 2823 | #define CP_REG_BR_SMB_NR_VAL__M 0x4 |
| 2824 | #define CP_REG_BR_SMB_NR_INIT 0x0 | 2824 | #define CP_REG_BR_SMB_NR_INIT 0x0 |
| 2825 | 2825 | ||
| 2826 | #define CP_REG_BR_CP_SMB_NR__A 0x1410022 | 2826 | #define CP_REG_BR_CP_SMB_NR__A 0x1410022 |
| 2827 | #define CP_REG_BR_CP_SMB_NR__W 2 | 2827 | #define CP_REG_BR_CP_SMB_NR__W 2 |
| 2828 | #define CP_REG_BR_CP_SMB_NR__M 0x3 | 2828 | #define CP_REG_BR_CP_SMB_NR__M 0x3 |
| 2829 | #define CP_REG_BR_CP_SMB_NR_INIT 0x0 | 2829 | #define CP_REG_BR_CP_SMB_NR_INIT 0x0 |
| 2830 | 2830 | ||
| 2831 | #define CP_REG_BR_SPL_OFFSET__A 0x1410023 | 2831 | #define CP_REG_BR_SPL_OFFSET__A 0x1410023 |
| 2832 | #define CP_REG_BR_SPL_OFFSET__W 3 | 2832 | #define CP_REG_BR_SPL_OFFSET__W 3 |
| 2833 | #define CP_REG_BR_SPL_OFFSET__M 0x7 | 2833 | #define CP_REG_BR_SPL_OFFSET__M 0x7 |
| 2834 | #define CP_REG_BR_SPL_OFFSET_INIT 0x0 | 2834 | #define CP_REG_BR_SPL_OFFSET_INIT 0x0 |
| 2835 | 2835 | ||
| 2836 | #define CP_REG_BR_STR_DEL__A 0x1410024 | 2836 | #define CP_REG_BR_STR_DEL__A 0x1410024 |
| 2837 | #define CP_REG_BR_STR_DEL__W 10 | 2837 | #define CP_REG_BR_STR_DEL__W 10 |
| 2838 | #define CP_REG_BR_STR_DEL__M 0x3FF | 2838 | #define CP_REG_BR_STR_DEL__M 0x3FF |
| 2839 | #define CP_REG_BR_STR_DEL_INIT 0xA | 2839 | #define CP_REG_BR_STR_DEL_INIT 0xA |
| 2840 | 2840 | ||
| 2841 | #define CP_REG_RT_ANG_INC0__A 0x1410030 | 2841 | #define CP_REG_RT_ANG_INC0__A 0x1410030 |
| 2842 | #define CP_REG_RT_ANG_INC0__W 16 | 2842 | #define CP_REG_RT_ANG_INC0__W 16 |
| 2843 | #define CP_REG_RT_ANG_INC0__M 0xFFFF | 2843 | #define CP_REG_RT_ANG_INC0__M 0xFFFF |
| 2844 | #define CP_REG_RT_ANG_INC0_INIT 0x0 | 2844 | #define CP_REG_RT_ANG_INC0_INIT 0x0 |
| 2845 | 2845 | ||
| 2846 | #define CP_REG_RT_ANG_INC1__A 0x1410031 | 2846 | #define CP_REG_RT_ANG_INC1__A 0x1410031 |
| 2847 | #define CP_REG_RT_ANG_INC1__W 8 | 2847 | #define CP_REG_RT_ANG_INC1__W 8 |
| 2848 | #define CP_REG_RT_ANG_INC1__M 0xFF | 2848 | #define CP_REG_RT_ANG_INC1__M 0xFF |
| 2849 | #define CP_REG_RT_ANG_INC1_INIT 0x0 | 2849 | #define CP_REG_RT_ANG_INC1_INIT 0x0 |
| 2850 | 2850 | ||
| 2851 | #define CP_REG_RT_DETECT_ENA__A 0x1410032 | 2851 | #define CP_REG_RT_DETECT_ENA__A 0x1410032 |
| 2852 | #define CP_REG_RT_DETECT_ENA__W 2 | 2852 | #define CP_REG_RT_DETECT_ENA__W 2 |
| 2853 | #define CP_REG_RT_DETECT_ENA__M 0x3 | 2853 | #define CP_REG_RT_DETECT_ENA__M 0x3 |
| 2854 | 2854 | ||
| 2855 | #define CP_REG_RT_DETECT_ENA_SCATTERED__B 0 | 2855 | #define CP_REG_RT_DETECT_ENA_SCATTERED__B 0 |
| 2856 | #define CP_REG_RT_DETECT_ENA_SCATTERED__W 1 | 2856 | #define CP_REG_RT_DETECT_ENA_SCATTERED__W 1 |
| 2857 | #define CP_REG_RT_DETECT_ENA_SCATTERED__M 0x1 | 2857 | #define CP_REG_RT_DETECT_ENA_SCATTERED__M 0x1 |
| 2858 | 2858 | ||
| 2859 | #define CP_REG_RT_DETECT_ENA_CONTINUOUS__B 1 | 2859 | #define CP_REG_RT_DETECT_ENA_CONTINUOUS__B 1 |
| 2860 | #define CP_REG_RT_DETECT_ENA_CONTINUOUS__W 1 | 2860 | #define CP_REG_RT_DETECT_ENA_CONTINUOUS__W 1 |
| 2861 | #define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 | 2861 | #define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 |
| 2862 | #define CP_REG_RT_DETECT_ENA_INIT 0x0 | 2862 | #define CP_REG_RT_DETECT_ENA_INIT 0x0 |
| 2863 | 2863 | ||
| 2864 | #define CP_REG_RT_DETECT_TRH__A 0x1410033 | 2864 | #define CP_REG_RT_DETECT_TRH__A 0x1410033 |
| 2865 | #define CP_REG_RT_DETECT_TRH__W 2 | 2865 | #define CP_REG_RT_DETECT_TRH__W 2 |
| 2866 | #define CP_REG_RT_DETECT_TRH__M 0x3 | 2866 | #define CP_REG_RT_DETECT_TRH__M 0x3 |
| 2867 | #define CP_REG_RT_DETECT_TRH_INIT 0x3 | 2867 | #define CP_REG_RT_DETECT_TRH_INIT 0x3 |
| 2868 | 2868 | ||
| 2869 | #define CP_REG_RT_SPD_RELIABLE__A 0x1410034 | 2869 | #define CP_REG_RT_SPD_RELIABLE__A 0x1410034 |
| 2870 | #define CP_REG_RT_SPD_RELIABLE__W 3 | 2870 | #define CP_REG_RT_SPD_RELIABLE__W 3 |
| 2871 | #define CP_REG_RT_SPD_RELIABLE__M 0x7 | 2871 | #define CP_REG_RT_SPD_RELIABLE__M 0x7 |
| 2872 | #define CP_REG_RT_SPD_RELIABLE_INIT 0x0 | 2872 | #define CP_REG_RT_SPD_RELIABLE_INIT 0x0 |
| 2873 | 2873 | ||
| 2874 | #define CP_REG_RT_SPD_DIRECTION__A 0x1410035 | 2874 | #define CP_REG_RT_SPD_DIRECTION__A 0x1410035 |
| 2875 | #define CP_REG_RT_SPD_DIRECTION__W 1 | 2875 | #define CP_REG_RT_SPD_DIRECTION__W 1 |
| 2876 | #define CP_REG_RT_SPD_DIRECTION__M 0x1 | 2876 | #define CP_REG_RT_SPD_DIRECTION__M 0x1 |
| 2877 | #define CP_REG_RT_SPD_DIRECTION_INIT 0x0 | 2877 | #define CP_REG_RT_SPD_DIRECTION_INIT 0x0 |
| 2878 | 2878 | ||
| 2879 | #define CP_REG_RT_SPD_MOD__A 0x1410036 | 2879 | #define CP_REG_RT_SPD_MOD__A 0x1410036 |
| 2880 | #define CP_REG_RT_SPD_MOD__W 2 | 2880 | #define CP_REG_RT_SPD_MOD__W 2 |
| 2881 | #define CP_REG_RT_SPD_MOD__M 0x3 | 2881 | #define CP_REG_RT_SPD_MOD__M 0x3 |
| 2882 | #define CP_REG_RT_SPD_MOD_INIT 0x0 | 2882 | #define CP_REG_RT_SPD_MOD_INIT 0x0 |
| 2883 | 2883 | ||
| 2884 | #define CP_REG_RT_SPD_SMB__A 0x1410037 | 2884 | #define CP_REG_RT_SPD_SMB__A 0x1410037 |
| 2885 | #define CP_REG_RT_SPD_SMB__W 2 | 2885 | #define CP_REG_RT_SPD_SMB__W 2 |
| 2886 | #define CP_REG_RT_SPD_SMB__M 0x3 | 2886 | #define CP_REG_RT_SPD_SMB__M 0x3 |
| 2887 | #define CP_REG_RT_SPD_SMB_INIT 0x0 | 2887 | #define CP_REG_RT_SPD_SMB_INIT 0x0 |
| 2888 | 2888 | ||
| 2889 | #define CP_REG_RT_CPD_MODE__A 0x1410038 | 2889 | #define CP_REG_RT_CPD_MODE__A 0x1410038 |
| 2890 | #define CP_REG_RT_CPD_MODE__W 3 | 2890 | #define CP_REG_RT_CPD_MODE__W 3 |
| 2891 | #define CP_REG_RT_CPD_MODE__M 0x7 | 2891 | #define CP_REG_RT_CPD_MODE__M 0x7 |
| 2892 | 2892 | ||
| 2893 | #define CP_REG_RT_CPD_MODE_MOD3__B 0 | 2893 | #define CP_REG_RT_CPD_MODE_MOD3__B 0 |
| 2894 | #define CP_REG_RT_CPD_MODE_MOD3__W 2 | 2894 | #define CP_REG_RT_CPD_MODE_MOD3__W 2 |
| 2895 | #define CP_REG_RT_CPD_MODE_MOD3__M 0x3 | 2895 | #define CP_REG_RT_CPD_MODE_MOD3__M 0x3 |
| 2896 | 2896 | ||
| 2897 | #define CP_REG_RT_CPD_MODE_ADD__B 2 | 2897 | #define CP_REG_RT_CPD_MODE_ADD__B 2 |
| 2898 | #define CP_REG_RT_CPD_MODE_ADD__W 1 | 2898 | #define CP_REG_RT_CPD_MODE_ADD__W 1 |
| 2899 | #define CP_REG_RT_CPD_MODE_ADD__M 0x4 | 2899 | #define CP_REG_RT_CPD_MODE_ADD__M 0x4 |
| 2900 | #define CP_REG_RT_CPD_MODE_INIT 0x0 | 2900 | #define CP_REG_RT_CPD_MODE_INIT 0x0 |
| 2901 | 2901 | ||
| 2902 | #define CP_REG_RT_CPD_RELIABLE__A 0x1410039 | 2902 | #define CP_REG_RT_CPD_RELIABLE__A 0x1410039 |
| 2903 | #define CP_REG_RT_CPD_RELIABLE__W 3 | 2903 | #define CP_REG_RT_CPD_RELIABLE__W 3 |
| 2904 | #define CP_REG_RT_CPD_RELIABLE__M 0x7 | 2904 | #define CP_REG_RT_CPD_RELIABLE__M 0x7 |
| 2905 | #define CP_REG_RT_CPD_RELIABLE_INIT 0x0 | 2905 | #define CP_REG_RT_CPD_RELIABLE_INIT 0x0 |
| 2906 | 2906 | ||
| 2907 | #define CP_REG_RT_CPD_BIN__A 0x141003A | 2907 | #define CP_REG_RT_CPD_BIN__A 0x141003A |
| 2908 | #define CP_REG_RT_CPD_BIN__W 5 | 2908 | #define CP_REG_RT_CPD_BIN__W 5 |
| 2909 | #define CP_REG_RT_CPD_BIN__M 0x1F | 2909 | #define CP_REG_RT_CPD_BIN__M 0x1F |
| 2910 | #define CP_REG_RT_CPD_BIN_INIT 0x0 | 2910 | #define CP_REG_RT_CPD_BIN_INIT 0x0 |
| 2911 | 2911 | ||
| 2912 | #define CP_REG_RT_CPD_MAX__A 0x141003B | 2912 | #define CP_REG_RT_CPD_MAX__A 0x141003B |
| 2913 | #define CP_REG_RT_CPD_MAX__W 4 | 2913 | #define CP_REG_RT_CPD_MAX__W 4 |
| 2914 | #define CP_REG_RT_CPD_MAX__M 0xF | 2914 | #define CP_REG_RT_CPD_MAX__M 0xF |
| 2915 | #define CP_REG_RT_CPD_MAX_INIT 0x0 | 2915 | #define CP_REG_RT_CPD_MAX_INIT 0x0 |
| 2916 | 2916 | ||
| 2917 | #define CP_REG_RT_SUPR_VAL__A 0x141003C | 2917 | #define CP_REG_RT_SUPR_VAL__A 0x141003C |
| 2918 | #define CP_REG_RT_SUPR_VAL__W 2 | 2918 | #define CP_REG_RT_SUPR_VAL__W 2 |
| 2919 | #define CP_REG_RT_SUPR_VAL__M 0x3 | 2919 | #define CP_REG_RT_SUPR_VAL__M 0x3 |
| 2920 | 2920 | ||
| 2921 | #define CP_REG_RT_SUPR_VAL_CE__B 0 | 2921 | #define CP_REG_RT_SUPR_VAL_CE__B 0 |
| 2922 | #define CP_REG_RT_SUPR_VAL_CE__W 1 | 2922 | #define CP_REG_RT_SUPR_VAL_CE__W 1 |
| 2923 | #define CP_REG_RT_SUPR_VAL_CE__M 0x1 | 2923 | #define CP_REG_RT_SUPR_VAL_CE__M 0x1 |
| 2924 | 2924 | ||
| 2925 | #define CP_REG_RT_SUPR_VAL_DL__B 1 | 2925 | #define CP_REG_RT_SUPR_VAL_DL__B 1 |
| 2926 | #define CP_REG_RT_SUPR_VAL_DL__W 1 | 2926 | #define CP_REG_RT_SUPR_VAL_DL__W 1 |
| 2927 | #define CP_REG_RT_SUPR_VAL_DL__M 0x2 | 2927 | #define CP_REG_RT_SUPR_VAL_DL__M 0x2 |
| 2928 | #define CP_REG_RT_SUPR_VAL_INIT 0x0 | 2928 | #define CP_REG_RT_SUPR_VAL_INIT 0x0 |
| 2929 | 2929 | ||
| 2930 | #define CP_REG_RT_EXP_AVE__A 0x141003D | 2930 | #define CP_REG_RT_EXP_AVE__A 0x141003D |
| 2931 | #define CP_REG_RT_EXP_AVE__W 5 | 2931 | #define CP_REG_RT_EXP_AVE__W 5 |
| 2932 | #define CP_REG_RT_EXP_AVE__M 0x1F | 2932 | #define CP_REG_RT_EXP_AVE__M 0x1F |
| 2933 | #define CP_REG_RT_EXP_AVE_INIT 0x0 | 2933 | #define CP_REG_RT_EXP_AVE_INIT 0x0 |
| 2934 | 2934 | ||
| 2935 | #define CP_REG_RT_EXP_MARG__A 0x141003E | 2935 | #define CP_REG_RT_EXP_MARG__A 0x141003E |
| 2936 | #define CP_REG_RT_EXP_MARG__W 5 | 2936 | #define CP_REG_RT_EXP_MARG__W 5 |
| 2937 | #define CP_REG_RT_EXP_MARG__M 0x1F | 2937 | #define CP_REG_RT_EXP_MARG__M 0x1F |
| 2938 | #define CP_REG_RT_EXP_MARG_INIT 0x0 | 2938 | #define CP_REG_RT_EXP_MARG_INIT 0x0 |
| 2939 | 2939 | ||
| 2940 | #define CP_REG_AC_NEXP_OFFS__A 0x1410040 | 2940 | #define CP_REG_AC_NEXP_OFFS__A 0x1410040 |
| 2941 | #define CP_REG_AC_NEXP_OFFS__W 8 | 2941 | #define CP_REG_AC_NEXP_OFFS__W 8 |
| 2942 | #define CP_REG_AC_NEXP_OFFS__M 0xFF | 2942 | #define CP_REG_AC_NEXP_OFFS__M 0xFF |
| 2943 | #define CP_REG_AC_NEXP_OFFS_INIT 0x0 | 2943 | #define CP_REG_AC_NEXP_OFFS_INIT 0x0 |
| 2944 | 2944 | ||
| 2945 | #define CP_REG_AC_AVER_POW__A 0x1410041 | 2945 | #define CP_REG_AC_AVER_POW__A 0x1410041 |
| 2946 | #define CP_REG_AC_AVER_POW__W 8 | 2946 | #define CP_REG_AC_AVER_POW__W 8 |
| 2947 | #define CP_REG_AC_AVER_POW__M 0xFF | 2947 | #define CP_REG_AC_AVER_POW__M 0xFF |
| 2948 | #define CP_REG_AC_AVER_POW_INIT 0x5F | 2948 | #define CP_REG_AC_AVER_POW_INIT 0x5F |
| 2949 | 2949 | ||
| 2950 | #define CP_REG_AC_MAX_POW__A 0x1410042 | 2950 | #define CP_REG_AC_MAX_POW__A 0x1410042 |
| 2951 | #define CP_REG_AC_MAX_POW__W 8 | 2951 | #define CP_REG_AC_MAX_POW__W 8 |
| 2952 | #define CP_REG_AC_MAX_POW__M 0xFF | 2952 | #define CP_REG_AC_MAX_POW__M 0xFF |
| 2953 | #define CP_REG_AC_MAX_POW_INIT 0x7A | 2953 | #define CP_REG_AC_MAX_POW_INIT 0x7A |
| 2954 | 2954 | ||
| 2955 | #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 | 2955 | #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 |
| 2956 | #define CP_REG_AC_WEIGHT_MAN__W 6 | 2956 | #define CP_REG_AC_WEIGHT_MAN__W 6 |
| 2957 | #define CP_REG_AC_WEIGHT_MAN__M 0x3F | 2957 | #define CP_REG_AC_WEIGHT_MAN__M 0x3F |
| 2958 | #define CP_REG_AC_WEIGHT_MAN_INIT 0x31 | 2958 | #define CP_REG_AC_WEIGHT_MAN_INIT 0x31 |
| 2959 | 2959 | ||
| 2960 | #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 | 2960 | #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 |
| 2961 | #define CP_REG_AC_WEIGHT_EXP__W 5 | 2961 | #define CP_REG_AC_WEIGHT_EXP__W 5 |
| 2962 | #define CP_REG_AC_WEIGHT_EXP__M 0x1F | 2962 | #define CP_REG_AC_WEIGHT_EXP__M 0x1F |
| 2963 | #define CP_REG_AC_WEIGHT_EXP_INIT 0x10 | 2963 | #define CP_REG_AC_WEIGHT_EXP_INIT 0x10 |
| 2964 | 2964 | ||
| 2965 | #define CP_REG_AC_GAIN_MAN__A 0x1410045 | 2965 | #define CP_REG_AC_GAIN_MAN__A 0x1410045 |
| 2966 | #define CP_REG_AC_GAIN_MAN__W 16 | 2966 | #define CP_REG_AC_GAIN_MAN__W 16 |
| 2967 | #define CP_REG_AC_GAIN_MAN__M 0xFFFF | 2967 | #define CP_REG_AC_GAIN_MAN__M 0xFFFF |
| 2968 | #define CP_REG_AC_GAIN_MAN_INIT 0x0 | 2968 | #define CP_REG_AC_GAIN_MAN_INIT 0x0 |
| 2969 | 2969 | ||
| 2970 | #define CP_REG_AC_GAIN_EXP__A 0x1410046 | 2970 | #define CP_REG_AC_GAIN_EXP__A 0x1410046 |
| 2971 | #define CP_REG_AC_GAIN_EXP__W 5 | 2971 | #define CP_REG_AC_GAIN_EXP__W 5 |
| 2972 | #define CP_REG_AC_GAIN_EXP__M 0x1F | 2972 | #define CP_REG_AC_GAIN_EXP__M 0x1F |
| 2973 | #define CP_REG_AC_GAIN_EXP_INIT 0x0 | 2973 | #define CP_REG_AC_GAIN_EXP_INIT 0x0 |
| 2974 | 2974 | ||
| 2975 | #define CP_REG_AC_AMP_MODE__A 0x1410047 | 2975 | #define CP_REG_AC_AMP_MODE__A 0x1410047 |
| 2976 | #define CP_REG_AC_AMP_MODE__W 2 | 2976 | #define CP_REG_AC_AMP_MODE__W 2 |
| 2977 | #define CP_REG_AC_AMP_MODE__M 0x3 | 2977 | #define CP_REG_AC_AMP_MODE__M 0x3 |
| 2978 | #define CP_REG_AC_AMP_MODE_NEW 0x0 | 2978 | #define CP_REG_AC_AMP_MODE_NEW 0x0 |
| 2979 | #define CP_REG_AC_AMP_MODE_OLD 0x1 | 2979 | #define CP_REG_AC_AMP_MODE_OLD 0x1 |
| 2980 | #define CP_REG_AC_AMP_MODE_FIXED 0x2 | 2980 | #define CP_REG_AC_AMP_MODE_FIXED 0x2 |
| 2981 | #define CP_REG_AC_AMP_MODE_INIT 0x2 | 2981 | #define CP_REG_AC_AMP_MODE_INIT 0x2 |
| 2982 | 2982 | ||
| 2983 | #define CP_REG_AC_AMP_FIX__A 0x1410048 | 2983 | #define CP_REG_AC_AMP_FIX__A 0x1410048 |
| 2984 | #define CP_REG_AC_AMP_FIX__W 14 | 2984 | #define CP_REG_AC_AMP_FIX__W 14 |
| 2985 | #define CP_REG_AC_AMP_FIX__M 0x3FFF | 2985 | #define CP_REG_AC_AMP_FIX__M 0x3FFF |
| 2986 | #define CP_REG_AC_AMP_FIX_INIT 0x1FF | 2986 | #define CP_REG_AC_AMP_FIX_INIT 0x1FF |
| 2987 | 2987 | ||
| 2988 | #define CP_REG_AC_AMP_READ__A 0x1410049 | 2988 | #define CP_REG_AC_AMP_READ__A 0x1410049 |
| 2989 | #define CP_REG_AC_AMP_READ__W 14 | 2989 | #define CP_REG_AC_AMP_READ__W 14 |
| 2990 | #define CP_REG_AC_AMP_READ__M 0x3FFF | 2990 | #define CP_REG_AC_AMP_READ__M 0x3FFF |
| 2991 | #define CP_REG_AC_AMP_READ_INIT 0x0 | 2991 | #define CP_REG_AC_AMP_READ_INIT 0x0 |
| 2992 | 2992 | ||
| 2993 | #define CP_REG_AC_ANG_MODE__A 0x141004A | 2993 | #define CP_REG_AC_ANG_MODE__A 0x141004A |
| 2994 | #define CP_REG_AC_ANG_MODE__W 2 | 2994 | #define CP_REG_AC_ANG_MODE__W 2 |
| 2995 | #define CP_REG_AC_ANG_MODE__M 0x3 | 2995 | #define CP_REG_AC_ANG_MODE__M 0x3 |
| 2996 | #define CP_REG_AC_ANG_MODE_NEW 0x0 | 2996 | #define CP_REG_AC_ANG_MODE_NEW 0x0 |
| 2997 | #define CP_REG_AC_ANG_MODE_OLD 0x1 | 2997 | #define CP_REG_AC_ANG_MODE_OLD 0x1 |
| 2998 | #define CP_REG_AC_ANG_MODE_NO_INT 0x2 | 2998 | #define CP_REG_AC_ANG_MODE_NO_INT 0x2 |
| 2999 | #define CP_REG_AC_ANG_MODE_OFFSET 0x3 | 2999 | #define CP_REG_AC_ANG_MODE_OFFSET 0x3 |
| 3000 | #define CP_REG_AC_ANG_MODE_INIT 0x3 | 3000 | #define CP_REG_AC_ANG_MODE_INIT 0x3 |
| 3001 | 3001 | ||
| 3002 | #define CP_REG_AC_ANG_OFFS__A 0x141004B | 3002 | #define CP_REG_AC_ANG_OFFS__A 0x141004B |
| 3003 | #define CP_REG_AC_ANG_OFFS__W 14 | 3003 | #define CP_REG_AC_ANG_OFFS__W 14 |
| 3004 | #define CP_REG_AC_ANG_OFFS__M 0x3FFF | 3004 | #define CP_REG_AC_ANG_OFFS__M 0x3FFF |
| 3005 | #define CP_REG_AC_ANG_OFFS_INIT 0x0 | 3005 | #define CP_REG_AC_ANG_OFFS_INIT 0x0 |
| 3006 | 3006 | ||
| 3007 | #define CP_REG_AC_ANG_READ__A 0x141004C | 3007 | #define CP_REG_AC_ANG_READ__A 0x141004C |
| 3008 | #define CP_REG_AC_ANG_READ__W 16 | 3008 | #define CP_REG_AC_ANG_READ__W 16 |
| 3009 | #define CP_REG_AC_ANG_READ__M 0xFFFF | 3009 | #define CP_REG_AC_ANG_READ__M 0xFFFF |
| 3010 | #define CP_REG_AC_ANG_READ_INIT 0x0 | 3010 | #define CP_REG_AC_ANG_READ_INIT 0x0 |
| 3011 | 3011 | ||
| 3012 | #define CP_REG_DL_MB_WR_ADDR__A 0x1410050 | 3012 | #define CP_REG_DL_MB_WR_ADDR__A 0x1410050 |
| 3013 | #define CP_REG_DL_MB_WR_ADDR__W 15 | 3013 | #define CP_REG_DL_MB_WR_ADDR__W 15 |
| 3014 | #define CP_REG_DL_MB_WR_ADDR__M 0x7FFF | 3014 | #define CP_REG_DL_MB_WR_ADDR__M 0x7FFF |
| 3015 | #define CP_REG_DL_MB_WR_ADDR_INIT 0x0 | 3015 | #define CP_REG_DL_MB_WR_ADDR_INIT 0x0 |
| 3016 | 3016 | ||
| 3017 | #define CP_REG_DL_MB_WR_CTR__A 0x1410051 | 3017 | #define CP_REG_DL_MB_WR_CTR__A 0x1410051 |
| 3018 | #define CP_REG_DL_MB_WR_CTR__W 5 | 3018 | #define CP_REG_DL_MB_WR_CTR__W 5 |
| 3019 | #define CP_REG_DL_MB_WR_CTR__M 0x1F | 3019 | #define CP_REG_DL_MB_WR_CTR__M 0x1F |
| 3020 | 3020 | ||
| 3021 | #define CP_REG_DL_MB_WR_CTR_WORD__B 2 | 3021 | #define CP_REG_DL_MB_WR_CTR_WORD__B 2 |
| 3022 | #define CP_REG_DL_MB_WR_CTR_WORD__W 3 | 3022 | #define CP_REG_DL_MB_WR_CTR_WORD__W 3 |
| 3023 | #define CP_REG_DL_MB_WR_CTR_WORD__M 0x1C | 3023 | #define CP_REG_DL_MB_WR_CTR_WORD__M 0x1C |
| 3024 | 3024 | ||
| 3025 | #define CP_REG_DL_MB_WR_CTR_OBS__B 1 | 3025 | #define CP_REG_DL_MB_WR_CTR_OBS__B 1 |
| 3026 | #define CP_REG_DL_MB_WR_CTR_OBS__W 1 | 3026 | #define CP_REG_DL_MB_WR_CTR_OBS__W 1 |
| 3027 | #define CP_REG_DL_MB_WR_CTR_OBS__M 0x2 | 3027 | #define CP_REG_DL_MB_WR_CTR_OBS__M 0x2 |
| 3028 | 3028 | ||
| 3029 | #define CP_REG_DL_MB_WR_CTR_CTR__B 0 | 3029 | #define CP_REG_DL_MB_WR_CTR_CTR__B 0 |
| 3030 | #define CP_REG_DL_MB_WR_CTR_CTR__W 1 | 3030 | #define CP_REG_DL_MB_WR_CTR_CTR__W 1 |
| 3031 | #define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 | 3031 | #define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 |
| 3032 | #define CP_REG_DL_MB_WR_CTR_INIT 0x0 | 3032 | #define CP_REG_DL_MB_WR_CTR_INIT 0x0 |
| 3033 | 3033 | ||
| 3034 | #define CP_REG_DL_MB_RD_ADDR__A 0x1410052 | 3034 | #define CP_REG_DL_MB_RD_ADDR__A 0x1410052 |
| 3035 | #define CP_REG_DL_MB_RD_ADDR__W 15 | 3035 | #define CP_REG_DL_MB_RD_ADDR__W 15 |
| 3036 | #define CP_REG_DL_MB_RD_ADDR__M 0x7FFF | 3036 | #define CP_REG_DL_MB_RD_ADDR__M 0x7FFF |
| 3037 | #define CP_REG_DL_MB_RD_ADDR_INIT 0x0 | 3037 | #define CP_REG_DL_MB_RD_ADDR_INIT 0x0 |
| 3038 | 3038 | ||
| 3039 | #define CP_REG_DL_MB_RD_CTR__A 0x1410053 | 3039 | #define CP_REG_DL_MB_RD_CTR__A 0x1410053 |
| 3040 | #define CP_REG_DL_MB_RD_CTR__W 11 | 3040 | #define CP_REG_DL_MB_RD_CTR__W 11 |
| 3041 | #define CP_REG_DL_MB_RD_CTR__M 0x7FF | 3041 | #define CP_REG_DL_MB_RD_CTR__M 0x7FF |
| 3042 | 3042 | ||
| 3043 | #define CP_REG_DL_MB_RD_CTR_TEST__B 10 | 3043 | #define CP_REG_DL_MB_RD_CTR_TEST__B 10 |
| 3044 | #define CP_REG_DL_MB_RD_CTR_TEST__W 1 | 3044 | #define CP_REG_DL_MB_RD_CTR_TEST__W 1 |
| 3045 | #define CP_REG_DL_MB_RD_CTR_TEST__M 0x400 | 3045 | #define CP_REG_DL_MB_RD_CTR_TEST__M 0x400 |
| 3046 | 3046 | ||
| 3047 | #define CP_REG_DL_MB_RD_CTR_OFFSET__B 8 | 3047 | #define CP_REG_DL_MB_RD_CTR_OFFSET__B 8 |
| 3048 | #define CP_REG_DL_MB_RD_CTR_OFFSET__W 2 | 3048 | #define CP_REG_DL_MB_RD_CTR_OFFSET__W 2 |
| 3049 | #define CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 | 3049 | #define CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 |
| 3050 | 3050 | ||
| 3051 | #define CP_REG_DL_MB_RD_CTR_VALID__B 5 | 3051 | #define CP_REG_DL_MB_RD_CTR_VALID__B 5 |
| 3052 | #define CP_REG_DL_MB_RD_CTR_VALID__W 3 | 3052 | #define CP_REG_DL_MB_RD_CTR_VALID__W 3 |
| 3053 | #define CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 | 3053 | #define CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 |
| 3054 | 3054 | ||
| 3055 | #define CP_REG_DL_MB_RD_CTR_WORD__B 2 | 3055 | #define CP_REG_DL_MB_RD_CTR_WORD__B 2 |
| 3056 | #define CP_REG_DL_MB_RD_CTR_WORD__W 3 | 3056 | #define CP_REG_DL_MB_RD_CTR_WORD__W 3 |
| 3057 | #define CP_REG_DL_MB_RD_CTR_WORD__M 0x1C | 3057 | #define CP_REG_DL_MB_RD_CTR_WORD__M 0x1C |
| 3058 | 3058 | ||
| 3059 | #define CP_REG_DL_MB_RD_CTR_OBS__B 1 | 3059 | #define CP_REG_DL_MB_RD_CTR_OBS__B 1 |
| 3060 | #define CP_REG_DL_MB_RD_CTR_OBS__W 1 | 3060 | #define CP_REG_DL_MB_RD_CTR_OBS__W 1 |
| 3061 | #define CP_REG_DL_MB_RD_CTR_OBS__M 0x2 | 3061 | #define CP_REG_DL_MB_RD_CTR_OBS__M 0x2 |
| 3062 | 3062 | ||
| 3063 | #define CP_REG_DL_MB_RD_CTR_CTR__B 0 | 3063 | #define CP_REG_DL_MB_RD_CTR_CTR__B 0 |
| 3064 | #define CP_REG_DL_MB_RD_CTR_CTR__W 1 | 3064 | #define CP_REG_DL_MB_RD_CTR_CTR__W 1 |
| 3065 | #define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 | 3065 | #define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 |
| 3066 | #define CP_REG_DL_MB_RD_CTR_INIT 0x0 | 3066 | #define CP_REG_DL_MB_RD_CTR_INIT 0x0 |
| 3067 | 3067 | ||
| 3068 | #define CP_BR_BUF_RAM__A 0x1420000 | 3068 | #define CP_BR_BUF_RAM__A 0x1420000 |
| 3069 | 3069 | ||
| 3070 | #define CP_BR_CPL_RAM__A 0x1430000 | 3070 | #define CP_BR_CPL_RAM__A 0x1430000 |
| 3071 | 3071 | ||
| 3072 | #define CP_PB_DL0_RAM__A 0x1440000 | 3072 | #define CP_PB_DL0_RAM__A 0x1440000 |
| 3073 | 3073 | ||
| 3074 | #define CP_PB_DL1_RAM__A 0x1450000 | 3074 | #define CP_PB_DL1_RAM__A 0x1450000 |
| 3075 | 3075 | ||
| 3076 | #define CP_PB_DL2_RAM__A 0x1460000 | 3076 | #define CP_PB_DL2_RAM__A 0x1460000 |
| 3077 | 3077 | ||
| 3078 | #define CE_SID 0xA | 3078 | #define CE_SID 0xA |
| 3079 | 3079 | ||
| 3080 | #define CE_COMM_EXEC__A 0x1800000 | 3080 | #define CE_COMM_EXEC__A 0x1800000 |
| 3081 | #define CE_COMM_EXEC__W 3 | 3081 | #define CE_COMM_EXEC__W 3 |
| 3082 | #define CE_COMM_EXEC__M 0x7 | 3082 | #define CE_COMM_EXEC__M 0x7 |
| 3083 | #define CE_COMM_EXEC_CTL__B 0 | 3083 | #define CE_COMM_EXEC_CTL__B 0 |
| 3084 | #define CE_COMM_EXEC_CTL__W 3 | 3084 | #define CE_COMM_EXEC_CTL__W 3 |
| 3085 | #define CE_COMM_EXEC_CTL__M 0x7 | 3085 | #define CE_COMM_EXEC_CTL__M 0x7 |
| 3086 | #define CE_COMM_EXEC_CTL_STOP 0x0 | 3086 | #define CE_COMM_EXEC_CTL_STOP 0x0 |
| 3087 | #define CE_COMM_EXEC_CTL_ACTIVE 0x1 | 3087 | #define CE_COMM_EXEC_CTL_ACTIVE 0x1 |
| 3088 | #define CE_COMM_EXEC_CTL_HOLD 0x2 | 3088 | #define CE_COMM_EXEC_CTL_HOLD 0x2 |
| 3089 | #define CE_COMM_EXEC_CTL_STEP 0x3 | 3089 | #define CE_COMM_EXEC_CTL_STEP 0x3 |
| 3090 | #define CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 3090 | #define CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 3091 | #define CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 3091 | #define CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 3092 | 3092 | ||
| 3093 | #define CE_COMM_STATE__A 0x1800001 | 3093 | #define CE_COMM_STATE__A 0x1800001 |
| 3094 | #define CE_COMM_STATE__W 16 | 3094 | #define CE_COMM_STATE__W 16 |
| 3095 | #define CE_COMM_STATE__M 0xFFFF | 3095 | #define CE_COMM_STATE__M 0xFFFF |
| 3096 | #define CE_COMM_MB__A 0x1800002 | 3096 | #define CE_COMM_MB__A 0x1800002 |
| 3097 | #define CE_COMM_MB__W 16 | 3097 | #define CE_COMM_MB__W 16 |
| 3098 | #define CE_COMM_MB__M 0xFFFF | 3098 | #define CE_COMM_MB__M 0xFFFF |
| 3099 | #define CE_COMM_SERVICE0__A 0x1800003 | 3099 | #define CE_COMM_SERVICE0__A 0x1800003 |
| 3100 | #define CE_COMM_SERVICE0__W 16 | 3100 | #define CE_COMM_SERVICE0__W 16 |
| 3101 | #define CE_COMM_SERVICE0__M 0xFFFF | 3101 | #define CE_COMM_SERVICE0__M 0xFFFF |
| 3102 | #define CE_COMM_SERVICE1__A 0x1800004 | 3102 | #define CE_COMM_SERVICE1__A 0x1800004 |
| 3103 | #define CE_COMM_SERVICE1__W 16 | 3103 | #define CE_COMM_SERVICE1__W 16 |
| 3104 | #define CE_COMM_SERVICE1__M 0xFFFF | 3104 | #define CE_COMM_SERVICE1__M 0xFFFF |
| 3105 | #define CE_COMM_INT_STA__A 0x1800007 | 3105 | #define CE_COMM_INT_STA__A 0x1800007 |
| 3106 | #define CE_COMM_INT_STA__W 16 | 3106 | #define CE_COMM_INT_STA__W 16 |
| 3107 | #define CE_COMM_INT_STA__M 0xFFFF | 3107 | #define CE_COMM_INT_STA__M 0xFFFF |
| 3108 | #define CE_COMM_INT_MSK__A 0x1800008 | 3108 | #define CE_COMM_INT_MSK__A 0x1800008 |
| 3109 | #define CE_COMM_INT_MSK__W 16 | 3109 | #define CE_COMM_INT_MSK__W 16 |
| 3110 | #define CE_COMM_INT_MSK__M 0xFFFF | 3110 | #define CE_COMM_INT_MSK__M 0xFFFF |
| 3111 | 3111 | ||
| 3112 | #define CE_REG_COMM_EXEC__A 0x1810000 | 3112 | #define CE_REG_COMM_EXEC__A 0x1810000 |
| 3113 | #define CE_REG_COMM_EXEC__W 3 | 3113 | #define CE_REG_COMM_EXEC__W 3 |
| 3114 | #define CE_REG_COMM_EXEC__M 0x7 | 3114 | #define CE_REG_COMM_EXEC__M 0x7 |
| 3115 | #define CE_REG_COMM_EXEC_CTL__B 0 | 3115 | #define CE_REG_COMM_EXEC_CTL__B 0 |
| 3116 | #define CE_REG_COMM_EXEC_CTL__W 3 | 3116 | #define CE_REG_COMM_EXEC_CTL__W 3 |
| 3117 | #define CE_REG_COMM_EXEC_CTL__M 0x7 | 3117 | #define CE_REG_COMM_EXEC_CTL__M 0x7 |
| 3118 | #define CE_REG_COMM_EXEC_CTL_STOP 0x0 | 3118 | #define CE_REG_COMM_EXEC_CTL_STOP 0x0 |
| 3119 | #define CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 3119 | #define CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 3120 | #define CE_REG_COMM_EXEC_CTL_HOLD 0x2 | 3120 | #define CE_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 3121 | #define CE_REG_COMM_EXEC_CTL_STEP 0x3 | 3121 | #define CE_REG_COMM_EXEC_CTL_STEP 0x3 |
| 3122 | 3122 | ||
| 3123 | #define CE_REG_COMM_MB__A 0x1810002 | 3123 | #define CE_REG_COMM_MB__A 0x1810002 |
| 3124 | #define CE_REG_COMM_MB__W 4 | 3124 | #define CE_REG_COMM_MB__W 4 |
| 3125 | #define CE_REG_COMM_MB__M 0xF | 3125 | #define CE_REG_COMM_MB__M 0xF |
| 3126 | #define CE_REG_COMM_MB_CTR__B 0 | 3126 | #define CE_REG_COMM_MB_CTR__B 0 |
| 3127 | #define CE_REG_COMM_MB_CTR__W 1 | 3127 | #define CE_REG_COMM_MB_CTR__W 1 |
| 3128 | #define CE_REG_COMM_MB_CTR__M 0x1 | 3128 | #define CE_REG_COMM_MB_CTR__M 0x1 |
| 3129 | #define CE_REG_COMM_MB_CTR_OFF 0x0 | 3129 | #define CE_REG_COMM_MB_CTR_OFF 0x0 |
| 3130 | #define CE_REG_COMM_MB_CTR_ON 0x1 | 3130 | #define CE_REG_COMM_MB_CTR_ON 0x1 |
| 3131 | #define CE_REG_COMM_MB_OBS__B 1 | 3131 | #define CE_REG_COMM_MB_OBS__B 1 |
| 3132 | #define CE_REG_COMM_MB_OBS__W 1 | 3132 | #define CE_REG_COMM_MB_OBS__W 1 |
| 3133 | #define CE_REG_COMM_MB_OBS__M 0x2 | 3133 | #define CE_REG_COMM_MB_OBS__M 0x2 |
| 3134 | #define CE_REG_COMM_MB_OBS_OFF 0x0 | 3134 | #define CE_REG_COMM_MB_OBS_OFF 0x0 |
| 3135 | #define CE_REG_COMM_MB_OBS_ON 0x2 | 3135 | #define CE_REG_COMM_MB_OBS_ON 0x2 |
| 3136 | #define CE_REG_COMM_MB_OBS_SEL__B 2 | 3136 | #define CE_REG_COMM_MB_OBS_SEL__B 2 |
| 3137 | #define CE_REG_COMM_MB_OBS_SEL__W 2 | 3137 | #define CE_REG_COMM_MB_OBS_SEL__W 2 |
| 3138 | #define CE_REG_COMM_MB_OBS_SEL__M 0xC | 3138 | #define CE_REG_COMM_MB_OBS_SEL__M 0xC |
| 3139 | #define CE_REG_COMM_MB_OBS_SEL_FI 0x0 | 3139 | #define CE_REG_COMM_MB_OBS_SEL_FI 0x0 |
| 3140 | #define CE_REG_COMM_MB_OBS_SEL_TP 0x4 | 3140 | #define CE_REG_COMM_MB_OBS_SEL_TP 0x4 |
| 3141 | #define CE_REG_COMM_MB_OBS_SEL_TI 0x8 | 3141 | #define CE_REG_COMM_MB_OBS_SEL_TI 0x8 |
| 3142 | #define CE_REG_COMM_MB_OBS_SEL_FR 0x8 | 3142 | #define CE_REG_COMM_MB_OBS_SEL_FR 0x8 |
| 3143 | 3143 | ||
| 3144 | #define CE_REG_COMM_SERVICE0__A 0x1810003 | 3144 | #define CE_REG_COMM_SERVICE0__A 0x1810003 |
| 3145 | #define CE_REG_COMM_SERVICE0__W 10 | 3145 | #define CE_REG_COMM_SERVICE0__W 10 |
| 3146 | #define CE_REG_COMM_SERVICE0__M 0x3FF | 3146 | #define CE_REG_COMM_SERVICE0__M 0x3FF |
| 3147 | #define CE_REG_COMM_SERVICE0_FT__B 8 | 3147 | #define CE_REG_COMM_SERVICE0_FT__B 8 |
| 3148 | #define CE_REG_COMM_SERVICE0_FT__W 1 | 3148 | #define CE_REG_COMM_SERVICE0_FT__W 1 |
| 3149 | #define CE_REG_COMM_SERVICE0_FT__M 0x100 | 3149 | #define CE_REG_COMM_SERVICE0_FT__M 0x100 |
| 3150 | 3150 | ||
| 3151 | #define CE_REG_COMM_SERVICE1__A 0x1810004 | 3151 | #define CE_REG_COMM_SERVICE1__A 0x1810004 |
| 3152 | #define CE_REG_COMM_SERVICE1__W 11 | 3152 | #define CE_REG_COMM_SERVICE1__W 11 |
| 3153 | #define CE_REG_COMM_SERVICE1__M 0x7FF | 3153 | #define CE_REG_COMM_SERVICE1__M 0x7FF |
| 3154 | 3154 | ||
| 3155 | #define CE_REG_COMM_INT_STA__A 0x1810007 | 3155 | #define CE_REG_COMM_INT_STA__A 0x1810007 |
| 3156 | #define CE_REG_COMM_INT_STA__W 3 | 3156 | #define CE_REG_COMM_INT_STA__W 3 |
| 3157 | #define CE_REG_COMM_INT_STA__M 0x7 | 3157 | #define CE_REG_COMM_INT_STA__M 0x7 |
| 3158 | #define CE_REG_COMM_INT_STA_CE_PE__B 0 | 3158 | #define CE_REG_COMM_INT_STA_CE_PE__B 0 |
| 3159 | #define CE_REG_COMM_INT_STA_CE_PE__W 1 | 3159 | #define CE_REG_COMM_INT_STA_CE_PE__W 1 |
| 3160 | #define CE_REG_COMM_INT_STA_CE_PE__M 0x1 | 3160 | #define CE_REG_COMM_INT_STA_CE_PE__M 0x1 |
| 3161 | #define CE_REG_COMM_INT_STA_CE_IR__B 1 | 3161 | #define CE_REG_COMM_INT_STA_CE_IR__B 1 |
| 3162 | #define CE_REG_COMM_INT_STA_CE_IR__W 1 | 3162 | #define CE_REG_COMM_INT_STA_CE_IR__W 1 |
| 3163 | #define CE_REG_COMM_INT_STA_CE_IR__M 0x2 | 3163 | #define CE_REG_COMM_INT_STA_CE_IR__M 0x2 |
| 3164 | #define CE_REG_COMM_INT_STA_CE_FI__B 2 | 3164 | #define CE_REG_COMM_INT_STA_CE_FI__B 2 |
| 3165 | #define CE_REG_COMM_INT_STA_CE_FI__W 1 | 3165 | #define CE_REG_COMM_INT_STA_CE_FI__W 1 |
| 3166 | #define CE_REG_COMM_INT_STA_CE_FI__M 0x4 | 3166 | #define CE_REG_COMM_INT_STA_CE_FI__M 0x4 |
| 3167 | 3167 | ||
| 3168 | #define CE_REG_COMM_INT_MSK__A 0x1810008 | 3168 | #define CE_REG_COMM_INT_MSK__A 0x1810008 |
| 3169 | #define CE_REG_COMM_INT_MSK__W 3 | 3169 | #define CE_REG_COMM_INT_MSK__W 3 |
| 3170 | #define CE_REG_COMM_INT_MSK__M 0x7 | 3170 | #define CE_REG_COMM_INT_MSK__M 0x7 |
| 3171 | #define CE_REG_COMM_INT_MSK_CE_PE__B 0 | 3171 | #define CE_REG_COMM_INT_MSK_CE_PE__B 0 |
| 3172 | #define CE_REG_COMM_INT_MSK_CE_PE__W 1 | 3172 | #define CE_REG_COMM_INT_MSK_CE_PE__W 1 |
| 3173 | #define CE_REG_COMM_INT_MSK_CE_PE__M 0x1 | 3173 | #define CE_REG_COMM_INT_MSK_CE_PE__M 0x1 |
| 3174 | #define CE_REG_COMM_INT_MSK_CE_IR__B 1 | 3174 | #define CE_REG_COMM_INT_MSK_CE_IR__B 1 |
| 3175 | #define CE_REG_COMM_INT_MSK_CE_IR__W 1 | 3175 | #define CE_REG_COMM_INT_MSK_CE_IR__W 1 |
| 3176 | #define CE_REG_COMM_INT_MSK_CE_IR__M 0x2 | 3176 | #define CE_REG_COMM_INT_MSK_CE_IR__M 0x2 |
| 3177 | #define CE_REG_COMM_INT_MSK_CE_FI__B 2 | 3177 | #define CE_REG_COMM_INT_MSK_CE_FI__B 2 |
| 3178 | #define CE_REG_COMM_INT_MSK_CE_FI__W 1 | 3178 | #define CE_REG_COMM_INT_MSK_CE_FI__W 1 |
| 3179 | #define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 | 3179 | #define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 |
| 3180 | 3180 | ||
| 3181 | #define CE_REG_2K__A 0x1810010 | 3181 | #define CE_REG_2K__A 0x1810010 |
| 3182 | #define CE_REG_2K__W 1 | 3182 | #define CE_REG_2K__W 1 |
| 3183 | #define CE_REG_2K__M 0x1 | 3183 | #define CE_REG_2K__M 0x1 |
| 3184 | #define CE_REG_2K_INIT 0x0 | 3184 | #define CE_REG_2K_INIT 0x0 |
| 3185 | 3185 | ||
| 3186 | #define CE_REG_TAPSET__A 0x1810011 | 3186 | #define CE_REG_TAPSET__A 0x1810011 |
| 3187 | #define CE_REG_TAPSET__W 2 | 3187 | #define CE_REG_TAPSET__W 2 |
| 3188 | #define CE_REG_TAPSET__M 0x3 | 3188 | #define CE_REG_TAPSET__M 0x3 |
| 3189 | 3189 | ||
| 3190 | #define CE_REG_TAPSET_MOTION_INIT 0x0 | 3190 | #define CE_REG_TAPSET_MOTION_INIT 0x0 |
| 3191 | 3191 | ||
| 3192 | #define CE_REG_TAPSET_MOTION_NO 0x0 | 3192 | #define CE_REG_TAPSET_MOTION_NO 0x0 |
| 3193 | 3193 | ||
| 3194 | #define CE_REG_TAPSET_MOTION_LOW 0x1 | 3194 | #define CE_REG_TAPSET_MOTION_LOW 0x1 |
| 3195 | 3195 | ||
| 3196 | #define CE_REG_TAPSET_MOTION_HIGH 0x2 | 3196 | #define CE_REG_TAPSET_MOTION_HIGH 0x2 |
| 3197 | 3197 | ||
| 3198 | #define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 | 3198 | #define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 |
| 3199 | 3199 | ||
| 3200 | #define CE_REG_AVG_POW__A 0x1810012 | 3200 | #define CE_REG_AVG_POW__A 0x1810012 |
| 3201 | #define CE_REG_AVG_POW__W 8 | 3201 | #define CE_REG_AVG_POW__W 8 |
| 3202 | #define CE_REG_AVG_POW__M 0xFF | 3202 | #define CE_REG_AVG_POW__M 0xFF |
| 3203 | #define CE_REG_AVG_POW_INIT 0x0 | 3203 | #define CE_REG_AVG_POW_INIT 0x0 |
| 3204 | 3204 | ||
| 3205 | #define CE_REG_MAX_POW__A 0x1810013 | 3205 | #define CE_REG_MAX_POW__A 0x1810013 |
| 3206 | #define CE_REG_MAX_POW__W 8 | 3206 | #define CE_REG_MAX_POW__W 8 |
| 3207 | #define CE_REG_MAX_POW__M 0xFF | 3207 | #define CE_REG_MAX_POW__M 0xFF |
| 3208 | #define CE_REG_MAX_POW_INIT 0x0 | 3208 | #define CE_REG_MAX_POW_INIT 0x0 |
| 3209 | 3209 | ||
| 3210 | #define CE_REG_ATT__A 0x1810014 | 3210 | #define CE_REG_ATT__A 0x1810014 |
| 3211 | #define CE_REG_ATT__W 8 | 3211 | #define CE_REG_ATT__W 8 |
| 3212 | #define CE_REG_ATT__M 0xFF | 3212 | #define CE_REG_ATT__M 0xFF |
| 3213 | #define CE_REG_ATT_INIT 0x0 | 3213 | #define CE_REG_ATT_INIT 0x0 |
| 3214 | 3214 | ||
| 3215 | #define CE_REG_NRED__A 0x1810015 | 3215 | #define CE_REG_NRED__A 0x1810015 |
| 3216 | #define CE_REG_NRED__W 6 | 3216 | #define CE_REG_NRED__W 6 |
| 3217 | #define CE_REG_NRED__M 0x3F | 3217 | #define CE_REG_NRED__M 0x3F |
| 3218 | #define CE_REG_NRED_INIT 0x0 | 3218 | #define CE_REG_NRED_INIT 0x0 |
| 3219 | 3219 | ||
| 3220 | #define CE_REG_PU_SIGN__A 0x1810020 | 3220 | #define CE_REG_PU_SIGN__A 0x1810020 |
| 3221 | #define CE_REG_PU_SIGN__W 1 | 3221 | #define CE_REG_PU_SIGN__W 1 |
| 3222 | #define CE_REG_PU_SIGN__M 0x1 | 3222 | #define CE_REG_PU_SIGN__M 0x1 |
| 3223 | #define CE_REG_PU_SIGN_INIT 0x0 | 3223 | #define CE_REG_PU_SIGN_INIT 0x0 |
| 3224 | 3224 | ||
| 3225 | #define CE_REG_PU_MIX__A 0x1810021 | 3225 | #define CE_REG_PU_MIX__A 0x1810021 |
| 3226 | #define CE_REG_PU_MIX__W 7 | 3226 | #define CE_REG_PU_MIX__W 7 |
| 3227 | #define CE_REG_PU_MIX__M 0x7F | 3227 | #define CE_REG_PU_MIX__M 0x7F |
| 3228 | #define CE_REG_PU_MIX_INIT 0x0 | 3228 | #define CE_REG_PU_MIX_INIT 0x0 |
| 3229 | 3229 | ||
| 3230 | #define CE_REG_PB_PILOT_REQ__A 0x1810030 | 3230 | #define CE_REG_PB_PILOT_REQ__A 0x1810030 |
| 3231 | #define CE_REG_PB_PILOT_REQ__W 15 | 3231 | #define CE_REG_PB_PILOT_REQ__W 15 |
| 3232 | #define CE_REG_PB_PILOT_REQ__M 0x7FFF | 3232 | #define CE_REG_PB_PILOT_REQ__M 0x7FFF |
| 3233 | #define CE_REG_PB_PILOT_REQ_INIT 0x0 | 3233 | #define CE_REG_PB_PILOT_REQ_INIT 0x0 |
| 3234 | #define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 | 3234 | #define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 |
| 3235 | #define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 | 3235 | #define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 |
| 3236 | #define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 | 3236 | #define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 |
| 3237 | #define CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 | 3237 | #define CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 |
| 3238 | #define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 | 3238 | #define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 |
| 3239 | #define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF | 3239 | #define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF |
| 3240 | 3240 | ||
| 3241 | #define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 | 3241 | #define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 |
| 3242 | #define CE_REG_PB_PILOT_REQ_VALID__W 1 | 3242 | #define CE_REG_PB_PILOT_REQ_VALID__W 1 |
| 3243 | #define CE_REG_PB_PILOT_REQ_VALID__M 0x1 | 3243 | #define CE_REG_PB_PILOT_REQ_VALID__M 0x1 |
| 3244 | #define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 | 3244 | #define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 |
| 3245 | 3245 | ||
| 3246 | #define CE_REG_PB_FREEZE__A 0x1810032 | 3246 | #define CE_REG_PB_FREEZE__A 0x1810032 |
| 3247 | #define CE_REG_PB_FREEZE__W 1 | 3247 | #define CE_REG_PB_FREEZE__W 1 |
| 3248 | #define CE_REG_PB_FREEZE__M 0x1 | 3248 | #define CE_REG_PB_FREEZE__M 0x1 |
| 3249 | #define CE_REG_PB_FREEZE_INIT 0x0 | 3249 | #define CE_REG_PB_FREEZE_INIT 0x0 |
| 3250 | 3250 | ||
| 3251 | #define CE_REG_PB_PILOT_EXP__A 0x1810038 | 3251 | #define CE_REG_PB_PILOT_EXP__A 0x1810038 |
| 3252 | #define CE_REG_PB_PILOT_EXP__W 4 | 3252 | #define CE_REG_PB_PILOT_EXP__W 4 |
| 3253 | #define CE_REG_PB_PILOT_EXP__M 0xF | 3253 | #define CE_REG_PB_PILOT_EXP__M 0xF |
| 3254 | #define CE_REG_PB_PILOT_EXP_INIT 0x0 | 3254 | #define CE_REG_PB_PILOT_EXP_INIT 0x0 |
| 3255 | 3255 | ||
| 3256 | #define CE_REG_PB_PILOT_REAL__A 0x1810039 | 3256 | #define CE_REG_PB_PILOT_REAL__A 0x1810039 |
| 3257 | #define CE_REG_PB_PILOT_REAL__W 10 | 3257 | #define CE_REG_PB_PILOT_REAL__W 10 |
| 3258 | #define CE_REG_PB_PILOT_REAL__M 0x3FF | 3258 | #define CE_REG_PB_PILOT_REAL__M 0x3FF |
| 3259 | #define CE_REG_PB_PILOT_REAL_INIT 0x0 | 3259 | #define CE_REG_PB_PILOT_REAL_INIT 0x0 |
| 3260 | 3260 | ||
| 3261 | #define CE_REG_PB_PILOT_IMAG__A 0x181003A | 3261 | #define CE_REG_PB_PILOT_IMAG__A 0x181003A |
| 3262 | #define CE_REG_PB_PILOT_IMAG__W 10 | 3262 | #define CE_REG_PB_PILOT_IMAG__W 10 |
| 3263 | #define CE_REG_PB_PILOT_IMAG__M 0x3FF | 3263 | #define CE_REG_PB_PILOT_IMAG__M 0x3FF |
| 3264 | #define CE_REG_PB_PILOT_IMAG_INIT 0x0 | 3264 | #define CE_REG_PB_PILOT_IMAG_INIT 0x0 |
| 3265 | 3265 | ||
| 3266 | #define CE_REG_PB_SMBNR__A 0x181003B | 3266 | #define CE_REG_PB_SMBNR__A 0x181003B |
| 3267 | #define CE_REG_PB_SMBNR__W 5 | 3267 | #define CE_REG_PB_SMBNR__W 5 |
| 3268 | #define CE_REG_PB_SMBNR__M 0x1F | 3268 | #define CE_REG_PB_SMBNR__M 0x1F |
| 3269 | #define CE_REG_PB_SMBNR_INIT 0x0 | 3269 | #define CE_REG_PB_SMBNR_INIT 0x0 |
| 3270 | 3270 | ||
| 3271 | #define CE_REG_NE_PILOT_REQ__A 0x1810040 | 3271 | #define CE_REG_NE_PILOT_REQ__A 0x1810040 |
| 3272 | #define CE_REG_NE_PILOT_REQ__W 12 | 3272 | #define CE_REG_NE_PILOT_REQ__W 12 |
| 3273 | #define CE_REG_NE_PILOT_REQ__M 0xFFF | 3273 | #define CE_REG_NE_PILOT_REQ__M 0xFFF |
| 3274 | #define CE_REG_NE_PILOT_REQ_INIT 0x0 | 3274 | #define CE_REG_NE_PILOT_REQ_INIT 0x0 |
| 3275 | 3275 | ||
| 3276 | #define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 | 3276 | #define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 |
| 3277 | #define CE_REG_NE_PILOT_REQ_VALID__W 2 | 3277 | #define CE_REG_NE_PILOT_REQ_VALID__W 2 |
| 3278 | #define CE_REG_NE_PILOT_REQ_VALID__M 0x3 | 3278 | #define CE_REG_NE_PILOT_REQ_VALID__M 0x3 |
| 3279 | #define CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 | 3279 | #define CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 |
| 3280 | #define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 | 3280 | #define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 |
| 3281 | #define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 | 3281 | #define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 |
| 3282 | #define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 | 3282 | #define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 |
| 3283 | #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 | 3283 | #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 |
| 3284 | #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 | 3284 | #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 |
| 3285 | #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 | 3285 | #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 |
| 3286 | 3286 | ||
| 3287 | #define CE_REG_NE_PILOT_DATA__A 0x1810042 | 3287 | #define CE_REG_NE_PILOT_DATA__A 0x1810042 |
| 3288 | #define CE_REG_NE_PILOT_DATA__W 10 | 3288 | #define CE_REG_NE_PILOT_DATA__W 10 |
| 3289 | #define CE_REG_NE_PILOT_DATA__M 0x3FF | 3289 | #define CE_REG_NE_PILOT_DATA__M 0x3FF |
| 3290 | #define CE_REG_NE_PILOT_DATA_INIT 0x0 | 3290 | #define CE_REG_NE_PILOT_DATA_INIT 0x0 |
| 3291 | 3291 | ||
| 3292 | #define CE_REG_NE_ERR_SELECT__A 0x1810043 | 3292 | #define CE_REG_NE_ERR_SELECT__A 0x1810043 |
| 3293 | #define CE_REG_NE_ERR_SELECT__W 3 | 3293 | #define CE_REG_NE_ERR_SELECT__W 3 |
| 3294 | #define CE_REG_NE_ERR_SELECT__M 0x7 | 3294 | #define CE_REG_NE_ERR_SELECT__M 0x7 |
| 3295 | #define CE_REG_NE_ERR_SELECT_INIT 0x0 | 3295 | #define CE_REG_NE_ERR_SELECT_INIT 0x0 |
| 3296 | 3296 | ||
| 3297 | #define CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 | 3297 | #define CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 |
| 3298 | #define CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 | 3298 | #define CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 |
| 3299 | #define CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 | 3299 | #define CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 |
| 3300 | 3300 | ||
| 3301 | #define CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 | 3301 | #define CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 |
| 3302 | #define CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 | 3302 | #define CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 |
| 3303 | #define CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 | 3303 | #define CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 |
| 3304 | 3304 | ||
| 3305 | #define CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 | 3305 | #define CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 |
| 3306 | #define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 | 3306 | #define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 |
| 3307 | #define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 | 3307 | #define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 |
| 3308 | 3308 | ||
| 3309 | #define CE_REG_NE_TD_CAL__A 0x1810044 | 3309 | #define CE_REG_NE_TD_CAL__A 0x1810044 |
| 3310 | #define CE_REG_NE_TD_CAL__W 9 | 3310 | #define CE_REG_NE_TD_CAL__W 9 |
| 3311 | #define CE_REG_NE_TD_CAL__M 0x1FF | 3311 | #define CE_REG_NE_TD_CAL__M 0x1FF |
| 3312 | #define CE_REG_NE_TD_CAL_INIT 0x0 | 3312 | #define CE_REG_NE_TD_CAL_INIT 0x0 |
| 3313 | 3313 | ||
| 3314 | #define CE_REG_NE_FD_CAL__A 0x1810045 | 3314 | #define CE_REG_NE_FD_CAL__A 0x1810045 |
| 3315 | #define CE_REG_NE_FD_CAL__W 9 | 3315 | #define CE_REG_NE_FD_CAL__W 9 |
| 3316 | #define CE_REG_NE_FD_CAL__M 0x1FF | 3316 | #define CE_REG_NE_FD_CAL__M 0x1FF |
| 3317 | #define CE_REG_NE_FD_CAL_INIT 0x0 | 3317 | #define CE_REG_NE_FD_CAL_INIT 0x0 |
| 3318 | 3318 | ||
| 3319 | #define CE_REG_NE_MIXAVG__A 0x1810046 | 3319 | #define CE_REG_NE_MIXAVG__A 0x1810046 |
| 3320 | #define CE_REG_NE_MIXAVG__W 3 | 3320 | #define CE_REG_NE_MIXAVG__W 3 |
| 3321 | #define CE_REG_NE_MIXAVG__M 0x7 | 3321 | #define CE_REG_NE_MIXAVG__M 0x7 |
| 3322 | #define CE_REG_NE_MIXAVG_INIT 0x0 | 3322 | #define CE_REG_NE_MIXAVG_INIT 0x0 |
| 3323 | 3323 | ||
| 3324 | #define CE_REG_NE_NUPD_OFS__A 0x1810047 | 3324 | #define CE_REG_NE_NUPD_OFS__A 0x1810047 |
| 3325 | #define CE_REG_NE_NUPD_OFS__W 7 | 3325 | #define CE_REG_NE_NUPD_OFS__W 7 |
| 3326 | #define CE_REG_NE_NUPD_OFS__M 0x7F | 3326 | #define CE_REG_NE_NUPD_OFS__M 0x7F |
| 3327 | #define CE_REG_NE_NUPD_OFS_INIT 0x0 | 3327 | #define CE_REG_NE_NUPD_OFS_INIT 0x0 |
| 3328 | 3328 | ||
| 3329 | #define CE_REG_NE_TD_POW__A 0x1810048 | 3329 | #define CE_REG_NE_TD_POW__A 0x1810048 |
| 3330 | #define CE_REG_NE_TD_POW__W 15 | 3330 | #define CE_REG_NE_TD_POW__W 15 |
| 3331 | #define CE_REG_NE_TD_POW__M 0x7FFF | 3331 | #define CE_REG_NE_TD_POW__M 0x7FFF |
| 3332 | #define CE_REG_NE_TD_POW_INIT 0x0 | 3332 | #define CE_REG_NE_TD_POW_INIT 0x0 |
| 3333 | 3333 | ||
| 3334 | #define CE_REG_NE_TD_POW_EXPONENT__B 10 | 3334 | #define CE_REG_NE_TD_POW_EXPONENT__B 10 |
| 3335 | #define CE_REG_NE_TD_POW_EXPONENT__W 5 | 3335 | #define CE_REG_NE_TD_POW_EXPONENT__W 5 |
| 3336 | #define CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 | 3336 | #define CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 |
| 3337 | 3337 | ||
| 3338 | #define CE_REG_NE_TD_POW_MANTISSA__B 0 | 3338 | #define CE_REG_NE_TD_POW_MANTISSA__B 0 |
| 3339 | #define CE_REG_NE_TD_POW_MANTISSA__W 10 | 3339 | #define CE_REG_NE_TD_POW_MANTISSA__W 10 |
| 3340 | #define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF | 3340 | #define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF |
| 3341 | 3341 | ||
| 3342 | #define CE_REG_NE_FD_POW__A 0x1810049 | 3342 | #define CE_REG_NE_FD_POW__A 0x1810049 |
| 3343 | #define CE_REG_NE_FD_POW__W 15 | 3343 | #define CE_REG_NE_FD_POW__W 15 |
| 3344 | #define CE_REG_NE_FD_POW__M 0x7FFF | 3344 | #define CE_REG_NE_FD_POW__M 0x7FFF |
| 3345 | #define CE_REG_NE_FD_POW_INIT 0x0 | 3345 | #define CE_REG_NE_FD_POW_INIT 0x0 |
| 3346 | 3346 | ||
| 3347 | #define CE_REG_NE_FD_POW_EXPONENT__B 10 | 3347 | #define CE_REG_NE_FD_POW_EXPONENT__B 10 |
| 3348 | #define CE_REG_NE_FD_POW_EXPONENT__W 5 | 3348 | #define CE_REG_NE_FD_POW_EXPONENT__W 5 |
| 3349 | #define CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 | 3349 | #define CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 |
| 3350 | 3350 | ||
| 3351 | #define CE_REG_NE_FD_POW_MANTISSA__B 0 | 3351 | #define CE_REG_NE_FD_POW_MANTISSA__B 0 |
| 3352 | #define CE_REG_NE_FD_POW_MANTISSA__W 10 | 3352 | #define CE_REG_NE_FD_POW_MANTISSA__W 10 |
| 3353 | #define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF | 3353 | #define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF |
| 3354 | 3354 | ||
| 3355 | #define CE_REG_NE_NEXP_AVG__A 0x181004A | 3355 | #define CE_REG_NE_NEXP_AVG__A 0x181004A |
| 3356 | #define CE_REG_NE_NEXP_AVG__W 8 | 3356 | #define CE_REG_NE_NEXP_AVG__W 8 |
| 3357 | #define CE_REG_NE_NEXP_AVG__M 0xFF | 3357 | #define CE_REG_NE_NEXP_AVG__M 0xFF |
| 3358 | #define CE_REG_NE_NEXP_AVG_INIT 0x0 | 3358 | #define CE_REG_NE_NEXP_AVG_INIT 0x0 |
| 3359 | 3359 | ||
| 3360 | #define CE_REG_NE_OFFSET__A 0x181004B | 3360 | #define CE_REG_NE_OFFSET__A 0x181004B |
| 3361 | #define CE_REG_NE_OFFSET__W 9 | 3361 | #define CE_REG_NE_OFFSET__W 9 |
| 3362 | #define CE_REG_NE_OFFSET__M 0x1FF | 3362 | #define CE_REG_NE_OFFSET__M 0x1FF |
| 3363 | #define CE_REG_NE_OFFSET_INIT 0x0 | 3363 | #define CE_REG_NE_OFFSET_INIT 0x0 |
| 3364 | 3364 | ||
| 3365 | #define CE_REG_PE_NEXP_OFFS__A 0x1810050 | 3365 | #define CE_REG_PE_NEXP_OFFS__A 0x1810050 |
| 3366 | #define CE_REG_PE_NEXP_OFFS__W 8 | 3366 | #define CE_REG_PE_NEXP_OFFS__W 8 |
| 3367 | #define CE_REG_PE_NEXP_OFFS__M 0xFF | 3367 | #define CE_REG_PE_NEXP_OFFS__M 0xFF |
| 3368 | #define CE_REG_PE_NEXP_OFFS_INIT 0x0 | 3368 | #define CE_REG_PE_NEXP_OFFS_INIT 0x0 |
| 3369 | 3369 | ||
| 3370 | #define CE_REG_PE_TIMESHIFT__A 0x1810051 | 3370 | #define CE_REG_PE_TIMESHIFT__A 0x1810051 |
| 3371 | #define CE_REG_PE_TIMESHIFT__W 14 | 3371 | #define CE_REG_PE_TIMESHIFT__W 14 |
| 3372 | #define CE_REG_PE_TIMESHIFT__M 0x3FFF | 3372 | #define CE_REG_PE_TIMESHIFT__M 0x3FFF |
| 3373 | #define CE_REG_PE_TIMESHIFT_INIT 0x0 | 3373 | #define CE_REG_PE_TIMESHIFT_INIT 0x0 |
| 3374 | 3374 | ||
| 3375 | #define CE_REG_PE_DIF_REAL_L__A 0x1810052 | 3375 | #define CE_REG_PE_DIF_REAL_L__A 0x1810052 |
| 3376 | #define CE_REG_PE_DIF_REAL_L__W 16 | 3376 | #define CE_REG_PE_DIF_REAL_L__W 16 |
| 3377 | #define CE_REG_PE_DIF_REAL_L__M 0xFFFF | 3377 | #define CE_REG_PE_DIF_REAL_L__M 0xFFFF |
| 3378 | #define CE_REG_PE_DIF_REAL_L_INIT 0x0 | 3378 | #define CE_REG_PE_DIF_REAL_L_INIT 0x0 |
| 3379 | 3379 | ||
| 3380 | #define CE_REG_PE_DIF_IMAG_L__A 0x1810053 | 3380 | #define CE_REG_PE_DIF_IMAG_L__A 0x1810053 |
| 3381 | #define CE_REG_PE_DIF_IMAG_L__W 16 | 3381 | #define CE_REG_PE_DIF_IMAG_L__W 16 |
| 3382 | #define CE_REG_PE_DIF_IMAG_L__M 0xFFFF | 3382 | #define CE_REG_PE_DIF_IMAG_L__M 0xFFFF |
| 3383 | #define CE_REG_PE_DIF_IMAG_L_INIT 0x0 | 3383 | #define CE_REG_PE_DIF_IMAG_L_INIT 0x0 |
| 3384 | 3384 | ||
| 3385 | #define CE_REG_PE_DIF_REAL_R__A 0x1810054 | 3385 | #define CE_REG_PE_DIF_REAL_R__A 0x1810054 |
| 3386 | #define CE_REG_PE_DIF_REAL_R__W 16 | 3386 | #define CE_REG_PE_DIF_REAL_R__W 16 |
| 3387 | #define CE_REG_PE_DIF_REAL_R__M 0xFFFF | 3387 | #define CE_REG_PE_DIF_REAL_R__M 0xFFFF |
| 3388 | #define CE_REG_PE_DIF_REAL_R_INIT 0x0 | 3388 | #define CE_REG_PE_DIF_REAL_R_INIT 0x0 |
| 3389 | 3389 | ||
| 3390 | #define CE_REG_PE_DIF_IMAG_R__A 0x1810055 | 3390 | #define CE_REG_PE_DIF_IMAG_R__A 0x1810055 |
| 3391 | #define CE_REG_PE_DIF_IMAG_R__W 16 | 3391 | #define CE_REG_PE_DIF_IMAG_R__W 16 |
| 3392 | #define CE_REG_PE_DIF_IMAG_R__M 0xFFFF | 3392 | #define CE_REG_PE_DIF_IMAG_R__M 0xFFFF |
| 3393 | #define CE_REG_PE_DIF_IMAG_R_INIT 0x0 | 3393 | #define CE_REG_PE_DIF_IMAG_R_INIT 0x0 |
| 3394 | 3394 | ||
| 3395 | #define CE_REG_PE_ABS_REAL_L__A 0x1810056 | 3395 | #define CE_REG_PE_ABS_REAL_L__A 0x1810056 |
| 3396 | #define CE_REG_PE_ABS_REAL_L__W 16 | 3396 | #define CE_REG_PE_ABS_REAL_L__W 16 |
| 3397 | #define CE_REG_PE_ABS_REAL_L__M 0xFFFF | 3397 | #define CE_REG_PE_ABS_REAL_L__M 0xFFFF |
| 3398 | #define CE_REG_PE_ABS_REAL_L_INIT 0x0 | 3398 | #define CE_REG_PE_ABS_REAL_L_INIT 0x0 |
| 3399 | 3399 | ||
| 3400 | #define CE_REG_PE_ABS_IMAG_L__A 0x1810057 | 3400 | #define CE_REG_PE_ABS_IMAG_L__A 0x1810057 |
| 3401 | #define CE_REG_PE_ABS_IMAG_L__W 16 | 3401 | #define CE_REG_PE_ABS_IMAG_L__W 16 |
| 3402 | #define CE_REG_PE_ABS_IMAG_L__M 0xFFFF | 3402 | #define CE_REG_PE_ABS_IMAG_L__M 0xFFFF |
| 3403 | #define CE_REG_PE_ABS_IMAG_L_INIT 0x0 | 3403 | #define CE_REG_PE_ABS_IMAG_L_INIT 0x0 |
| 3404 | 3404 | ||
| 3405 | #define CE_REG_PE_ABS_REAL_R__A 0x1810058 | 3405 | #define CE_REG_PE_ABS_REAL_R__A 0x1810058 |
| 3406 | #define CE_REG_PE_ABS_REAL_R__W 16 | 3406 | #define CE_REG_PE_ABS_REAL_R__W 16 |
| 3407 | #define CE_REG_PE_ABS_REAL_R__M 0xFFFF | 3407 | #define CE_REG_PE_ABS_REAL_R__M 0xFFFF |
| 3408 | #define CE_REG_PE_ABS_REAL_R_INIT 0x0 | 3408 | #define CE_REG_PE_ABS_REAL_R_INIT 0x0 |
| 3409 | 3409 | ||
| 3410 | #define CE_REG_PE_ABS_IMAG_R__A 0x1810059 | 3410 | #define CE_REG_PE_ABS_IMAG_R__A 0x1810059 |
| 3411 | #define CE_REG_PE_ABS_IMAG_R__W 16 | 3411 | #define CE_REG_PE_ABS_IMAG_R__W 16 |
| 3412 | #define CE_REG_PE_ABS_IMAG_R__M 0xFFFF | 3412 | #define CE_REG_PE_ABS_IMAG_R__M 0xFFFF |
| 3413 | #define CE_REG_PE_ABS_IMAG_R_INIT 0x0 | 3413 | #define CE_REG_PE_ABS_IMAG_R_INIT 0x0 |
| 3414 | 3414 | ||
| 3415 | #define CE_REG_PE_ABS_EXP_L__A 0x181005A | 3415 | #define CE_REG_PE_ABS_EXP_L__A 0x181005A |
| 3416 | #define CE_REG_PE_ABS_EXP_L__W 5 | 3416 | #define CE_REG_PE_ABS_EXP_L__W 5 |
| 3417 | #define CE_REG_PE_ABS_EXP_L__M 0x1F | 3417 | #define CE_REG_PE_ABS_EXP_L__M 0x1F |
| 3418 | #define CE_REG_PE_ABS_EXP_L_INIT 0x0 | 3418 | #define CE_REG_PE_ABS_EXP_L_INIT 0x0 |
| 3419 | 3419 | ||
| 3420 | #define CE_REG_PE_ABS_EXP_R__A 0x181005B | 3420 | #define CE_REG_PE_ABS_EXP_R__A 0x181005B |
| 3421 | #define CE_REG_PE_ABS_EXP_R__W 5 | 3421 | #define CE_REG_PE_ABS_EXP_R__W 5 |
| 3422 | #define CE_REG_PE_ABS_EXP_R__M 0x1F | 3422 | #define CE_REG_PE_ABS_EXP_R__M 0x1F |
| 3423 | #define CE_REG_PE_ABS_EXP_R_INIT 0x0 | 3423 | #define CE_REG_PE_ABS_EXP_R_INIT 0x0 |
| 3424 | 3424 | ||
| 3425 | #define CE_REG_TP_UPDATE_MODE__A 0x1810060 | 3425 | #define CE_REG_TP_UPDATE_MODE__A 0x1810060 |
| 3426 | #define CE_REG_TP_UPDATE_MODE__W 1 | 3426 | #define CE_REG_TP_UPDATE_MODE__W 1 |
| 3427 | #define CE_REG_TP_UPDATE_MODE__M 0x1 | 3427 | #define CE_REG_TP_UPDATE_MODE__M 0x1 |
| 3428 | #define CE_REG_TP_UPDATE_MODE_INIT 0x0 | 3428 | #define CE_REG_TP_UPDATE_MODE_INIT 0x0 |
| 3429 | 3429 | ||
| 3430 | #define CE_REG_TP_LMS_TAP_ON__A 0x1810061 | 3430 | #define CE_REG_TP_LMS_TAP_ON__A 0x1810061 |
| 3431 | #define CE_REG_TP_LMS_TAP_ON__W 1 | 3431 | #define CE_REG_TP_LMS_TAP_ON__W 1 |
| 3432 | #define CE_REG_TP_LMS_TAP_ON__M 0x1 | 3432 | #define CE_REG_TP_LMS_TAP_ON__M 0x1 |
| 3433 | 3433 | ||
| 3434 | #define CE_REG_TP_A0_TAP_NEW__A 0x1810064 | 3434 | #define CE_REG_TP_A0_TAP_NEW__A 0x1810064 |
| 3435 | #define CE_REG_TP_A0_TAP_NEW__W 10 | 3435 | #define CE_REG_TP_A0_TAP_NEW__W 10 |
| 3436 | #define CE_REG_TP_A0_TAP_NEW__M 0x3FF | 3436 | #define CE_REG_TP_A0_TAP_NEW__M 0x3FF |
| 3437 | 3437 | ||
| 3438 | #define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 | 3438 | #define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 |
| 3439 | #define CE_REG_TP_A0_TAP_NEW_VALID__W 1 | 3439 | #define CE_REG_TP_A0_TAP_NEW_VALID__W 1 |
| 3440 | #define CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 | 3440 | #define CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 |
| 3441 | 3441 | ||
| 3442 | #define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 | 3442 | #define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 |
| 3443 | #define CE_REG_TP_A0_MU_LMS_STEP__W 5 | 3443 | #define CE_REG_TP_A0_MU_LMS_STEP__W 5 |
| 3444 | #define CE_REG_TP_A0_MU_LMS_STEP__M 0x1F | 3444 | #define CE_REG_TP_A0_MU_LMS_STEP__M 0x1F |
| 3445 | 3445 | ||
| 3446 | #define CE_REG_TP_A0_TAP_CURR__A 0x1810067 | 3446 | #define CE_REG_TP_A0_TAP_CURR__A 0x1810067 |
| 3447 | #define CE_REG_TP_A0_TAP_CURR__W 10 | 3447 | #define CE_REG_TP_A0_TAP_CURR__W 10 |
| 3448 | #define CE_REG_TP_A0_TAP_CURR__M 0x3FF | 3448 | #define CE_REG_TP_A0_TAP_CURR__M 0x3FF |
| 3449 | 3449 | ||
| 3450 | #define CE_REG_TP_A1_TAP_NEW__A 0x1810068 | 3450 | #define CE_REG_TP_A1_TAP_NEW__A 0x1810068 |
| 3451 | #define CE_REG_TP_A1_TAP_NEW__W 10 | 3451 | #define CE_REG_TP_A1_TAP_NEW__W 10 |
| 3452 | #define CE_REG_TP_A1_TAP_NEW__M 0x3FF | 3452 | #define CE_REG_TP_A1_TAP_NEW__M 0x3FF |
| 3453 | 3453 | ||
| 3454 | #define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 | 3454 | #define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 |
| 3455 | #define CE_REG_TP_A1_TAP_NEW_VALID__W 1 | 3455 | #define CE_REG_TP_A1_TAP_NEW_VALID__W 1 |
| 3456 | #define CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 | 3456 | #define CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 |
| 3457 | 3457 | ||
| 3458 | #define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A | 3458 | #define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A |
| 3459 | #define CE_REG_TP_A1_MU_LMS_STEP__W 5 | 3459 | #define CE_REG_TP_A1_MU_LMS_STEP__W 5 |
| 3460 | #define CE_REG_TP_A1_MU_LMS_STEP__M 0x1F | 3460 | #define CE_REG_TP_A1_MU_LMS_STEP__M 0x1F |
| 3461 | 3461 | ||
| 3462 | #define CE_REG_TP_A1_TAP_CURR__A 0x181006B | 3462 | #define CE_REG_TP_A1_TAP_CURR__A 0x181006B |
| 3463 | #define CE_REG_TP_A1_TAP_CURR__W 10 | 3463 | #define CE_REG_TP_A1_TAP_CURR__W 10 |
| 3464 | #define CE_REG_TP_A1_TAP_CURR__M 0x3FF | 3464 | #define CE_REG_TP_A1_TAP_CURR__M 0x3FF |
| 3465 | 3465 | ||
| 3466 | #define CE_REG_TP_DOPP_ENERGY__A 0x181006C | 3466 | #define CE_REG_TP_DOPP_ENERGY__A 0x181006C |
| 3467 | #define CE_REG_TP_DOPP_ENERGY__W 15 | 3467 | #define CE_REG_TP_DOPP_ENERGY__W 15 |
| 3468 | #define CE_REG_TP_DOPP_ENERGY__M 0x7FFF | 3468 | #define CE_REG_TP_DOPP_ENERGY__M 0x7FFF |
| 3469 | #define CE_REG_TP_DOPP_ENERGY_INIT 0x0 | 3469 | #define CE_REG_TP_DOPP_ENERGY_INIT 0x0 |
| 3470 | 3470 | ||
| 3471 | #define CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 | 3471 | #define CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 |
| 3472 | #define CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 | 3472 | #define CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 |
| 3473 | #define CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 | 3473 | #define CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 |
| 3474 | 3474 | ||
| 3475 | #define CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 | 3475 | #define CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 |
| 3476 | #define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 | 3476 | #define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 |
| 3477 | #define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF | 3477 | #define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF |
| 3478 | 3478 | ||
| 3479 | #define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D | 3479 | #define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D |
| 3480 | #define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 | 3480 | #define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 |
| 3481 | #define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF | 3481 | #define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF |
| 3482 | #define CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 | 3482 | #define CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 |
| 3483 | 3483 | ||
| 3484 | #define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 | 3484 | #define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 |
| 3485 | #define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 | 3485 | #define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 |
| 3486 | #define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 | 3486 | #define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 |
| 3487 | 3487 | ||
| 3488 | #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 | 3488 | #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 |
| 3489 | #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 | 3489 | #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 |
| 3490 | #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF | 3490 | #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF |
| 3491 | 3491 | ||
| 3492 | #define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E | 3492 | #define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E |
| 3493 | #define CE_REG_TP_A0_TAP_ENERGY__W 15 | 3493 | #define CE_REG_TP_A0_TAP_ENERGY__W 15 |
| 3494 | #define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF | 3494 | #define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF |
| 3495 | #define CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 | 3495 | #define CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 |
| 3496 | 3496 | ||
| 3497 | #define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 | 3497 | #define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 |
| 3498 | #define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 | 3498 | #define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 |
| 3499 | #define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 | 3499 | #define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 |
| 3500 | 3500 | ||
| 3501 | #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 | 3501 | #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 |
| 3502 | #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 | 3502 | #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 |
| 3503 | #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF | 3503 | #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF |
| 3504 | 3504 | ||
| 3505 | #define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F | 3505 | #define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F |
| 3506 | #define CE_REG_TP_A1_TAP_ENERGY__W 15 | 3506 | #define CE_REG_TP_A1_TAP_ENERGY__W 15 |
| 3507 | #define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF | 3507 | #define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF |
| 3508 | #define CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 | 3508 | #define CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 |
| 3509 | 3509 | ||
| 3510 | #define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 | 3510 | #define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 |
| 3511 | #define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 | 3511 | #define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 |
| 3512 | #define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 | 3512 | #define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 |
| 3513 | 3513 | ||
| 3514 | #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 | 3514 | #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 |
| 3515 | #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 | 3515 | #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 |
| 3516 | #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF | 3516 | #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF |
| 3517 | 3517 | ||
| 3518 | #define CE_REG_TI_NEXP_OFFS__A 0x1810070 | 3518 | #define CE_REG_TI_NEXP_OFFS__A 0x1810070 |
| 3519 | #define CE_REG_TI_NEXP_OFFS__W 8 | 3519 | #define CE_REG_TI_NEXP_OFFS__W 8 |
| 3520 | #define CE_REG_TI_NEXP_OFFS__M 0xFF | 3520 | #define CE_REG_TI_NEXP_OFFS__M 0xFF |
| 3521 | #define CE_REG_TI_NEXP_OFFS_INIT 0x0 | 3521 | #define CE_REG_TI_NEXP_OFFS_INIT 0x0 |
| 3522 | 3522 | ||
| 3523 | #define CE_REG_TI_PEAK__A 0x1810071 | 3523 | #define CE_REG_TI_PEAK__A 0x1810071 |
| 3524 | #define CE_REG_TI_PEAK__W 8 | 3524 | #define CE_REG_TI_PEAK__W 8 |
| 3525 | #define CE_REG_TI_PEAK__M 0xFF | 3525 | #define CE_REG_TI_PEAK__M 0xFF |
| 3526 | #define CE_REG_TI_PEAK_INIT 0x0 | 3526 | #define CE_REG_TI_PEAK_INIT 0x0 |
| 3527 | 3527 | ||
| 3528 | #define CE_REG_FI_SHT_INCR__A 0x1810090 | 3528 | #define CE_REG_FI_SHT_INCR__A 0x1810090 |
| 3529 | #define CE_REG_FI_SHT_INCR__W 7 | 3529 | #define CE_REG_FI_SHT_INCR__W 7 |
| 3530 | #define CE_REG_FI_SHT_INCR__M 0x7F | 3530 | #define CE_REG_FI_SHT_INCR__M 0x7F |
| 3531 | #define CE_REG_FI_SHT_INCR_INIT 0x9 | 3531 | #define CE_REG_FI_SHT_INCR_INIT 0x9 |
| 3532 | 3532 | ||
| 3533 | #define CE_REG_FI_EXP_NORM__A 0x1810091 | 3533 | #define CE_REG_FI_EXP_NORM__A 0x1810091 |
| 3534 | #define CE_REG_FI_EXP_NORM__W 4 | 3534 | #define CE_REG_FI_EXP_NORM__W 4 |
| 3535 | #define CE_REG_FI_EXP_NORM__M 0xF | 3535 | #define CE_REG_FI_EXP_NORM__M 0xF |
| 3536 | #define CE_REG_FI_EXP_NORM_INIT 0x4 | 3536 | #define CE_REG_FI_EXP_NORM_INIT 0x4 |
| 3537 | 3537 | ||
| 3538 | #define CE_REG_FI_SUPR_VAL__A 0x1810092 | 3538 | #define CE_REG_FI_SUPR_VAL__A 0x1810092 |
| 3539 | #define CE_REG_FI_SUPR_VAL__W 1 | 3539 | #define CE_REG_FI_SUPR_VAL__W 1 |
| 3540 | #define CE_REG_FI_SUPR_VAL__M 0x1 | 3540 | #define CE_REG_FI_SUPR_VAL__M 0x1 |
| 3541 | #define CE_REG_FI_SUPR_VAL_INIT 0x1 | 3541 | #define CE_REG_FI_SUPR_VAL_INIT 0x1 |
| 3542 | 3542 | ||
| 3543 | #define CE_REG_IR_INPUTSEL__A 0x18100A0 | 3543 | #define CE_REG_IR_INPUTSEL__A 0x18100A0 |
| 3544 | #define CE_REG_IR_INPUTSEL__W 1 | 3544 | #define CE_REG_IR_INPUTSEL__W 1 |
| 3545 | #define CE_REG_IR_INPUTSEL__M 0x1 | 3545 | #define CE_REG_IR_INPUTSEL__M 0x1 |
| 3546 | #define CE_REG_IR_INPUTSEL_INIT 0x0 | 3546 | #define CE_REG_IR_INPUTSEL_INIT 0x0 |
| 3547 | 3547 | ||
| 3548 | #define CE_REG_IR_STARTPOS__A 0x18100A1 | 3548 | #define CE_REG_IR_STARTPOS__A 0x18100A1 |
| 3549 | #define CE_REG_IR_STARTPOS__W 8 | 3549 | #define CE_REG_IR_STARTPOS__W 8 |
| 3550 | #define CE_REG_IR_STARTPOS__M 0xFF | 3550 | #define CE_REG_IR_STARTPOS__M 0xFF |
| 3551 | #define CE_REG_IR_STARTPOS_INIT 0x0 | 3551 | #define CE_REG_IR_STARTPOS_INIT 0x0 |
| 3552 | 3552 | ||
| 3553 | #define CE_REG_IR_NEXP_THRES__A 0x18100A2 | 3553 | #define CE_REG_IR_NEXP_THRES__A 0x18100A2 |
| 3554 | #define CE_REG_IR_NEXP_THRES__W 8 | 3554 | #define CE_REG_IR_NEXP_THRES__W 8 |
| 3555 | #define CE_REG_IR_NEXP_THRES__M 0xFF | 3555 | #define CE_REG_IR_NEXP_THRES__M 0xFF |
| 3556 | #define CE_REG_IR_NEXP_THRES_INIT 0x0 | 3556 | #define CE_REG_IR_NEXP_THRES_INIT 0x0 |
| 3557 | 3557 | ||
| 3558 | #define CE_REG_IR_LENGTH__A 0x18100A3 | 3558 | #define CE_REG_IR_LENGTH__A 0x18100A3 |
| 3559 | #define CE_REG_IR_LENGTH__W 4 | 3559 | #define CE_REG_IR_LENGTH__W 4 |
| 3560 | #define CE_REG_IR_LENGTH__M 0xF | 3560 | #define CE_REG_IR_LENGTH__M 0xF |
| 3561 | #define CE_REG_IR_LENGTH_INIT 0x0 | 3561 | #define CE_REG_IR_LENGTH_INIT 0x0 |
| 3562 | 3562 | ||
| 3563 | #define CE_REG_IR_FREQ__A 0x18100A4 | 3563 | #define CE_REG_IR_FREQ__A 0x18100A4 |
| 3564 | #define CE_REG_IR_FREQ__W 11 | 3564 | #define CE_REG_IR_FREQ__W 11 |
| 3565 | #define CE_REG_IR_FREQ__M 0x7FF | 3565 | #define CE_REG_IR_FREQ__M 0x7FF |
| 3566 | #define CE_REG_IR_FREQ_INIT 0x0 | 3566 | #define CE_REG_IR_FREQ_INIT 0x0 |
| 3567 | 3567 | ||
| 3568 | #define CE_REG_IR_FREQINC__A 0x18100A5 | 3568 | #define CE_REG_IR_FREQINC__A 0x18100A5 |
| 3569 | #define CE_REG_IR_FREQINC__W 11 | 3569 | #define CE_REG_IR_FREQINC__W 11 |
| 3570 | #define CE_REG_IR_FREQINC__M 0x7FF | 3570 | #define CE_REG_IR_FREQINC__M 0x7FF |
| 3571 | #define CE_REG_IR_FREQINC_INIT 0x0 | 3571 | #define CE_REG_IR_FREQINC_INIT 0x0 |
| 3572 | 3572 | ||
| 3573 | #define CE_REG_IR_KAISINC__A 0x18100A6 | 3573 | #define CE_REG_IR_KAISINC__A 0x18100A6 |
| 3574 | #define CE_REG_IR_KAISINC__W 15 | 3574 | #define CE_REG_IR_KAISINC__W 15 |
| 3575 | #define CE_REG_IR_KAISINC__M 0x7FFF | 3575 | #define CE_REG_IR_KAISINC__M 0x7FFF |
| 3576 | #define CE_REG_IR_KAISINC_INIT 0x0 | 3576 | #define CE_REG_IR_KAISINC_INIT 0x0 |
| 3577 | 3577 | ||
| 3578 | #define CE_REG_IR_CTL__A 0x18100A7 | 3578 | #define CE_REG_IR_CTL__A 0x18100A7 |
| 3579 | #define CE_REG_IR_CTL__W 3 | 3579 | #define CE_REG_IR_CTL__W 3 |
| 3580 | #define CE_REG_IR_CTL__M 0x7 | 3580 | #define CE_REG_IR_CTL__M 0x7 |
| 3581 | #define CE_REG_IR_CTL_INIT 0x0 | 3581 | #define CE_REG_IR_CTL_INIT 0x0 |
| 3582 | 3582 | ||
| 3583 | #define CE_REG_IR_REAL__A 0x18100A8 | 3583 | #define CE_REG_IR_REAL__A 0x18100A8 |
| 3584 | #define CE_REG_IR_REAL__W 16 | 3584 | #define CE_REG_IR_REAL__W 16 |
| 3585 | #define CE_REG_IR_REAL__M 0xFFFF | 3585 | #define CE_REG_IR_REAL__M 0xFFFF |
| 3586 | #define CE_REG_IR_REAL_INIT 0x0 | 3586 | #define CE_REG_IR_REAL_INIT 0x0 |
| 3587 | 3587 | ||
| 3588 | #define CE_REG_IR_IMAG__A 0x18100A9 | 3588 | #define CE_REG_IR_IMAG__A 0x18100A9 |
| 3589 | #define CE_REG_IR_IMAG__W 16 | 3589 | #define CE_REG_IR_IMAG__W 16 |
| 3590 | #define CE_REG_IR_IMAG__M 0xFFFF | 3590 | #define CE_REG_IR_IMAG__M 0xFFFF |
| 3591 | #define CE_REG_IR_IMAG_INIT 0x0 | 3591 | #define CE_REG_IR_IMAG_INIT 0x0 |
| 3592 | 3592 | ||
| 3593 | #define CE_REG_IR_INDEX__A 0x18100AA | 3593 | #define CE_REG_IR_INDEX__A 0x18100AA |
| 3594 | #define CE_REG_IR_INDEX__W 12 | 3594 | #define CE_REG_IR_INDEX__W 12 |
| 3595 | #define CE_REG_IR_INDEX__M 0xFFF | 3595 | #define CE_REG_IR_INDEX__M 0xFFF |
| 3596 | #define CE_REG_IR_INDEX_INIT 0x0 | 3596 | #define CE_REG_IR_INDEX_INIT 0x0 |
| 3597 | 3597 | ||
| 3598 | #define CE_REG_FR_TREAL00__A 0x1820010 | 3598 | #define CE_REG_FR_TREAL00__A 0x1820010 |
| 3599 | #define CE_REG_FR_TREAL00__W 11 | 3599 | #define CE_REG_FR_TREAL00__W 11 |
| 3600 | #define CE_REG_FR_TREAL00__M 0x7FF | 3600 | #define CE_REG_FR_TREAL00__M 0x7FF |
| 3601 | #define CE_REG_FR_TREAL00_INIT 0x52 | 3601 | #define CE_REG_FR_TREAL00_INIT 0x52 |
| 3602 | 3602 | ||
| 3603 | #define CE_REG_FR_TIMAG00__A 0x1820011 | 3603 | #define CE_REG_FR_TIMAG00__A 0x1820011 |
| 3604 | #define CE_REG_FR_TIMAG00__W 11 | 3604 | #define CE_REG_FR_TIMAG00__W 11 |
| 3605 | #define CE_REG_FR_TIMAG00__M 0x7FF | 3605 | #define CE_REG_FR_TIMAG00__M 0x7FF |
| 3606 | #define CE_REG_FR_TIMAG00_INIT 0x0 | 3606 | #define CE_REG_FR_TIMAG00_INIT 0x0 |
| 3607 | 3607 | ||
| 3608 | #define CE_REG_FR_TREAL01__A 0x1820012 | 3608 | #define CE_REG_FR_TREAL01__A 0x1820012 |
| 3609 | #define CE_REG_FR_TREAL01__W 11 | 3609 | #define CE_REG_FR_TREAL01__W 11 |
| 3610 | #define CE_REG_FR_TREAL01__M 0x7FF | 3610 | #define CE_REG_FR_TREAL01__M 0x7FF |
| 3611 | #define CE_REG_FR_TREAL01_INIT 0x52 | 3611 | #define CE_REG_FR_TREAL01_INIT 0x52 |
| 3612 | 3612 | ||
| 3613 | #define CE_REG_FR_TIMAG01__A 0x1820013 | 3613 | #define CE_REG_FR_TIMAG01__A 0x1820013 |
| 3614 | #define CE_REG_FR_TIMAG01__W 11 | 3614 | #define CE_REG_FR_TIMAG01__W 11 |
| 3615 | #define CE_REG_FR_TIMAG01__M 0x7FF | 3615 | #define CE_REG_FR_TIMAG01__M 0x7FF |
| 3616 | #define CE_REG_FR_TIMAG01_INIT 0x0 | 3616 | #define CE_REG_FR_TIMAG01_INIT 0x0 |
| 3617 | 3617 | ||
| 3618 | #define CE_REG_FR_TREAL02__A 0x1820014 | 3618 | #define CE_REG_FR_TREAL02__A 0x1820014 |
| 3619 | #define CE_REG_FR_TREAL02__W 11 | 3619 | #define CE_REG_FR_TREAL02__W 11 |
| 3620 | #define CE_REG_FR_TREAL02__M 0x7FF | 3620 | #define CE_REG_FR_TREAL02__M 0x7FF |
| 3621 | #define CE_REG_FR_TREAL02_INIT 0x52 | 3621 | #define CE_REG_FR_TREAL02_INIT 0x52 |
| 3622 | 3622 | ||
| 3623 | #define CE_REG_FR_TIMAG02__A 0x1820015 | 3623 | #define CE_REG_FR_TIMAG02__A 0x1820015 |
| 3624 | #define CE_REG_FR_TIMAG02__W 11 | 3624 | #define CE_REG_FR_TIMAG02__W 11 |
| 3625 | #define CE_REG_FR_TIMAG02__M 0x7FF | 3625 | #define CE_REG_FR_TIMAG02__M 0x7FF |
| 3626 | #define CE_REG_FR_TIMAG02_INIT 0x0 | 3626 | #define CE_REG_FR_TIMAG02_INIT 0x0 |
| 3627 | 3627 | ||
| 3628 | #define CE_REG_FR_TREAL03__A 0x1820016 | 3628 | #define CE_REG_FR_TREAL03__A 0x1820016 |
| 3629 | #define CE_REG_FR_TREAL03__W 11 | 3629 | #define CE_REG_FR_TREAL03__W 11 |
| 3630 | #define CE_REG_FR_TREAL03__M 0x7FF | 3630 | #define CE_REG_FR_TREAL03__M 0x7FF |
| 3631 | #define CE_REG_FR_TREAL03_INIT 0x52 | 3631 | #define CE_REG_FR_TREAL03_INIT 0x52 |
| 3632 | 3632 | ||
| 3633 | #define CE_REG_FR_TIMAG03__A 0x1820017 | 3633 | #define CE_REG_FR_TIMAG03__A 0x1820017 |
| 3634 | #define CE_REG_FR_TIMAG03__W 11 | 3634 | #define CE_REG_FR_TIMAG03__W 11 |
| 3635 | #define CE_REG_FR_TIMAG03__M 0x7FF | 3635 | #define CE_REG_FR_TIMAG03__M 0x7FF |
| 3636 | #define CE_REG_FR_TIMAG03_INIT 0x0 | 3636 | #define CE_REG_FR_TIMAG03_INIT 0x0 |
| 3637 | 3637 | ||
| 3638 | #define CE_REG_FR_TREAL04__A 0x1820018 | 3638 | #define CE_REG_FR_TREAL04__A 0x1820018 |
| 3639 | #define CE_REG_FR_TREAL04__W 11 | 3639 | #define CE_REG_FR_TREAL04__W 11 |
| 3640 | #define CE_REG_FR_TREAL04__M 0x7FF | 3640 | #define CE_REG_FR_TREAL04__M 0x7FF |
| 3641 | #define CE_REG_FR_TREAL04_INIT 0x52 | 3641 | #define CE_REG_FR_TREAL04_INIT 0x52 |
| 3642 | 3642 | ||
| 3643 | #define CE_REG_FR_TIMAG04__A 0x1820019 | 3643 | #define CE_REG_FR_TIMAG04__A 0x1820019 |
| 3644 | #define CE_REG_FR_TIMAG04__W 11 | 3644 | #define CE_REG_FR_TIMAG04__W 11 |
| 3645 | #define CE_REG_FR_TIMAG04__M 0x7FF | 3645 | #define CE_REG_FR_TIMAG04__M 0x7FF |
| 3646 | #define CE_REG_FR_TIMAG04_INIT 0x0 | 3646 | #define CE_REG_FR_TIMAG04_INIT 0x0 |
| 3647 | 3647 | ||
| 3648 | #define CE_REG_FR_TREAL05__A 0x182001A | 3648 | #define CE_REG_FR_TREAL05__A 0x182001A |
| 3649 | #define CE_REG_FR_TREAL05__W 11 | 3649 | #define CE_REG_FR_TREAL05__W 11 |
| 3650 | #define CE_REG_FR_TREAL05__M 0x7FF | 3650 | #define CE_REG_FR_TREAL05__M 0x7FF |
| 3651 | #define CE_REG_FR_TREAL05_INIT 0x52 | 3651 | #define CE_REG_FR_TREAL05_INIT 0x52 |
| 3652 | 3652 | ||
| 3653 | #define CE_REG_FR_TIMAG05__A 0x182001B | 3653 | #define CE_REG_FR_TIMAG05__A 0x182001B |
| 3654 | #define CE_REG_FR_TIMAG05__W 11 | 3654 | #define CE_REG_FR_TIMAG05__W 11 |
| 3655 | #define CE_REG_FR_TIMAG05__M 0x7FF | 3655 | #define CE_REG_FR_TIMAG05__M 0x7FF |
| 3656 | #define CE_REG_FR_TIMAG05_INIT 0x0 | 3656 | #define CE_REG_FR_TIMAG05_INIT 0x0 |
| 3657 | 3657 | ||
| 3658 | #define CE_REG_FR_TREAL06__A 0x182001C | 3658 | #define CE_REG_FR_TREAL06__A 0x182001C |
| 3659 | #define CE_REG_FR_TREAL06__W 11 | 3659 | #define CE_REG_FR_TREAL06__W 11 |
| 3660 | #define CE_REG_FR_TREAL06__M 0x7FF | 3660 | #define CE_REG_FR_TREAL06__M 0x7FF |
| 3661 | #define CE_REG_FR_TREAL06_INIT 0x52 | 3661 | #define CE_REG_FR_TREAL06_INIT 0x52 |
| 3662 | 3662 | ||
| 3663 | #define CE_REG_FR_TIMAG06__A 0x182001D | 3663 | #define CE_REG_FR_TIMAG06__A 0x182001D |
| 3664 | #define CE_REG_FR_TIMAG06__W 11 | 3664 | #define CE_REG_FR_TIMAG06__W 11 |
| 3665 | #define CE_REG_FR_TIMAG06__M 0x7FF | 3665 | #define CE_REG_FR_TIMAG06__M 0x7FF |
| 3666 | #define CE_REG_FR_TIMAG06_INIT 0x0 | 3666 | #define CE_REG_FR_TIMAG06_INIT 0x0 |
| 3667 | 3667 | ||
| 3668 | #define CE_REG_FR_TREAL07__A 0x182001E | 3668 | #define CE_REG_FR_TREAL07__A 0x182001E |
| 3669 | #define CE_REG_FR_TREAL07__W 11 | 3669 | #define CE_REG_FR_TREAL07__W 11 |
| 3670 | #define CE_REG_FR_TREAL07__M 0x7FF | 3670 | #define CE_REG_FR_TREAL07__M 0x7FF |
| 3671 | #define CE_REG_FR_TREAL07_INIT 0x52 | 3671 | #define CE_REG_FR_TREAL07_INIT 0x52 |
| 3672 | 3672 | ||
| 3673 | #define CE_REG_FR_TIMAG07__A 0x182001F | 3673 | #define CE_REG_FR_TIMAG07__A 0x182001F |
| 3674 | #define CE_REG_FR_TIMAG07__W 11 | 3674 | #define CE_REG_FR_TIMAG07__W 11 |
| 3675 | #define CE_REG_FR_TIMAG07__M 0x7FF | 3675 | #define CE_REG_FR_TIMAG07__M 0x7FF |
| 3676 | #define CE_REG_FR_TIMAG07_INIT 0x0 | 3676 | #define CE_REG_FR_TIMAG07_INIT 0x0 |
| 3677 | 3677 | ||
| 3678 | #define CE_REG_FR_TREAL08__A 0x1820020 | 3678 | #define CE_REG_FR_TREAL08__A 0x1820020 |
| 3679 | #define CE_REG_FR_TREAL08__W 11 | 3679 | #define CE_REG_FR_TREAL08__W 11 |
| 3680 | #define CE_REG_FR_TREAL08__M 0x7FF | 3680 | #define CE_REG_FR_TREAL08__M 0x7FF |
| 3681 | #define CE_REG_FR_TREAL08_INIT 0x52 | 3681 | #define CE_REG_FR_TREAL08_INIT 0x52 |
| 3682 | 3682 | ||
| 3683 | #define CE_REG_FR_TIMAG08__A 0x1820021 | 3683 | #define CE_REG_FR_TIMAG08__A 0x1820021 |
| 3684 | #define CE_REG_FR_TIMAG08__W 11 | 3684 | #define CE_REG_FR_TIMAG08__W 11 |
| 3685 | #define CE_REG_FR_TIMAG08__M 0x7FF | 3685 | #define CE_REG_FR_TIMAG08__M 0x7FF |
| 3686 | #define CE_REG_FR_TIMAG08_INIT 0x0 | 3686 | #define CE_REG_FR_TIMAG08_INIT 0x0 |
| 3687 | 3687 | ||
| 3688 | #define CE_REG_FR_TREAL09__A 0x1820022 | 3688 | #define CE_REG_FR_TREAL09__A 0x1820022 |
| 3689 | #define CE_REG_FR_TREAL09__W 11 | 3689 | #define CE_REG_FR_TREAL09__W 11 |
| 3690 | #define CE_REG_FR_TREAL09__M 0x7FF | 3690 | #define CE_REG_FR_TREAL09__M 0x7FF |
| 3691 | #define CE_REG_FR_TREAL09_INIT 0x52 | 3691 | #define CE_REG_FR_TREAL09_INIT 0x52 |
| 3692 | 3692 | ||
| 3693 | #define CE_REG_FR_TIMAG09__A 0x1820023 | 3693 | #define CE_REG_FR_TIMAG09__A 0x1820023 |
| 3694 | #define CE_REG_FR_TIMAG09__W 11 | 3694 | #define CE_REG_FR_TIMAG09__W 11 |
| 3695 | #define CE_REG_FR_TIMAG09__M 0x7FF | 3695 | #define CE_REG_FR_TIMAG09__M 0x7FF |
| 3696 | #define CE_REG_FR_TIMAG09_INIT 0x0 | 3696 | #define CE_REG_FR_TIMAG09_INIT 0x0 |
| 3697 | 3697 | ||
| 3698 | #define CE_REG_FR_TREAL10__A 0x1820024 | 3698 | #define CE_REG_FR_TREAL10__A 0x1820024 |
| 3699 | #define CE_REG_FR_TREAL10__W 11 | 3699 | #define CE_REG_FR_TREAL10__W 11 |
| 3700 | #define CE_REG_FR_TREAL10__M 0x7FF | 3700 | #define CE_REG_FR_TREAL10__M 0x7FF |
| 3701 | #define CE_REG_FR_TREAL10_INIT 0x52 | 3701 | #define CE_REG_FR_TREAL10_INIT 0x52 |
| 3702 | 3702 | ||
| 3703 | #define CE_REG_FR_TIMAG10__A 0x1820025 | 3703 | #define CE_REG_FR_TIMAG10__A 0x1820025 |
| 3704 | #define CE_REG_FR_TIMAG10__W 11 | 3704 | #define CE_REG_FR_TIMAG10__W 11 |
| 3705 | #define CE_REG_FR_TIMAG10__M 0x7FF | 3705 | #define CE_REG_FR_TIMAG10__M 0x7FF |
| 3706 | #define CE_REG_FR_TIMAG10_INIT 0x0 | 3706 | #define CE_REG_FR_TIMAG10_INIT 0x0 |
| 3707 | 3707 | ||
| 3708 | #define CE_REG_FR_TREAL11__A 0x1820026 | 3708 | #define CE_REG_FR_TREAL11__A 0x1820026 |
| 3709 | #define CE_REG_FR_TREAL11__W 11 | 3709 | #define CE_REG_FR_TREAL11__W 11 |
| 3710 | #define CE_REG_FR_TREAL11__M 0x7FF | 3710 | #define CE_REG_FR_TREAL11__M 0x7FF |
| 3711 | #define CE_REG_FR_TREAL11_INIT 0x52 | 3711 | #define CE_REG_FR_TREAL11_INIT 0x52 |
| 3712 | 3712 | ||
| 3713 | #define CE_REG_FR_TIMAG11__A 0x1820027 | 3713 | #define CE_REG_FR_TIMAG11__A 0x1820027 |
| 3714 | #define CE_REG_FR_TIMAG11__W 11 | 3714 | #define CE_REG_FR_TIMAG11__W 11 |
| 3715 | #define CE_REG_FR_TIMAG11__M 0x7FF | 3715 | #define CE_REG_FR_TIMAG11__M 0x7FF |
| 3716 | #define CE_REG_FR_TIMAG11_INIT 0x0 | 3716 | #define CE_REG_FR_TIMAG11_INIT 0x0 |
| 3717 | 3717 | ||
| 3718 | #define CE_REG_FR_MID_TAP__A 0x1820028 | 3718 | #define CE_REG_FR_MID_TAP__A 0x1820028 |
| 3719 | #define CE_REG_FR_MID_TAP__W 11 | 3719 | #define CE_REG_FR_MID_TAP__W 11 |
| 3720 | #define CE_REG_FR_MID_TAP__M 0x7FF | 3720 | #define CE_REG_FR_MID_TAP__M 0x7FF |
| 3721 | #define CE_REG_FR_MID_TAP_INIT 0x51 | 3721 | #define CE_REG_FR_MID_TAP_INIT 0x51 |
| 3722 | 3722 | ||
| 3723 | #define CE_REG_FR_SQS_G00__A 0x1820029 | 3723 | #define CE_REG_FR_SQS_G00__A 0x1820029 |
| 3724 | #define CE_REG_FR_SQS_G00__W 8 | 3724 | #define CE_REG_FR_SQS_G00__W 8 |
| 3725 | #define CE_REG_FR_SQS_G00__M 0xFF | 3725 | #define CE_REG_FR_SQS_G00__M 0xFF |
| 3726 | #define CE_REG_FR_SQS_G00_INIT 0xB | 3726 | #define CE_REG_FR_SQS_G00_INIT 0xB |
| 3727 | 3727 | ||
| 3728 | #define CE_REG_FR_SQS_G01__A 0x182002A | 3728 | #define CE_REG_FR_SQS_G01__A 0x182002A |
| 3729 | #define CE_REG_FR_SQS_G01__W 8 | 3729 | #define CE_REG_FR_SQS_G01__W 8 |
| 3730 | #define CE_REG_FR_SQS_G01__M 0xFF | 3730 | #define CE_REG_FR_SQS_G01__M 0xFF |
| 3731 | #define CE_REG_FR_SQS_G01_INIT 0xB | 3731 | #define CE_REG_FR_SQS_G01_INIT 0xB |
| 3732 | 3732 | ||
| 3733 | #define CE_REG_FR_SQS_G02__A 0x182002B | 3733 | #define CE_REG_FR_SQS_G02__A 0x182002B |
| 3734 | #define CE_REG_FR_SQS_G02__W 8 | 3734 | #define CE_REG_FR_SQS_G02__W 8 |
| 3735 | #define CE_REG_FR_SQS_G02__M 0xFF | 3735 | #define CE_REG_FR_SQS_G02__M 0xFF |
| 3736 | #define CE_REG_FR_SQS_G02_INIT 0xB | 3736 | #define CE_REG_FR_SQS_G02_INIT 0xB |
| 3737 | 3737 | ||
| 3738 | #define CE_REG_FR_SQS_G03__A 0x182002C | 3738 | #define CE_REG_FR_SQS_G03__A 0x182002C |
| 3739 | #define CE_REG_FR_SQS_G03__W 8 | 3739 | #define CE_REG_FR_SQS_G03__W 8 |
| 3740 | #define CE_REG_FR_SQS_G03__M 0xFF | 3740 | #define CE_REG_FR_SQS_G03__M 0xFF |
| 3741 | #define CE_REG_FR_SQS_G03_INIT 0xB | 3741 | #define CE_REG_FR_SQS_G03_INIT 0xB |
| 3742 | 3742 | ||
| 3743 | #define CE_REG_FR_SQS_G04__A 0x182002D | 3743 | #define CE_REG_FR_SQS_G04__A 0x182002D |
| 3744 | #define CE_REG_FR_SQS_G04__W 8 | 3744 | #define CE_REG_FR_SQS_G04__W 8 |
| 3745 | #define CE_REG_FR_SQS_G04__M 0xFF | 3745 | #define CE_REG_FR_SQS_G04__M 0xFF |
| 3746 | #define CE_REG_FR_SQS_G04_INIT 0xB | 3746 | #define CE_REG_FR_SQS_G04_INIT 0xB |
| 3747 | 3747 | ||
| 3748 | #define CE_REG_FR_SQS_G05__A 0x182002E | 3748 | #define CE_REG_FR_SQS_G05__A 0x182002E |
| 3749 | #define CE_REG_FR_SQS_G05__W 8 | 3749 | #define CE_REG_FR_SQS_G05__W 8 |
| 3750 | #define CE_REG_FR_SQS_G05__M 0xFF | 3750 | #define CE_REG_FR_SQS_G05__M 0xFF |
| 3751 | #define CE_REG_FR_SQS_G05_INIT 0xB | 3751 | #define CE_REG_FR_SQS_G05_INIT 0xB |
| 3752 | 3752 | ||
| 3753 | #define CE_REG_FR_SQS_G06__A 0x182002F | 3753 | #define CE_REG_FR_SQS_G06__A 0x182002F |
| 3754 | #define CE_REG_FR_SQS_G06__W 8 | 3754 | #define CE_REG_FR_SQS_G06__W 8 |
| 3755 | #define CE_REG_FR_SQS_G06__M 0xFF | 3755 | #define CE_REG_FR_SQS_G06__M 0xFF |
| 3756 | #define CE_REG_FR_SQS_G06_INIT 0xB | 3756 | #define CE_REG_FR_SQS_G06_INIT 0xB |
| 3757 | 3757 | ||
| 3758 | #define CE_REG_FR_SQS_G07__A 0x1820030 | 3758 | #define CE_REG_FR_SQS_G07__A 0x1820030 |
| 3759 | #define CE_REG_FR_SQS_G07__W 8 | 3759 | #define CE_REG_FR_SQS_G07__W 8 |
| 3760 | #define CE_REG_FR_SQS_G07__M 0xFF | 3760 | #define CE_REG_FR_SQS_G07__M 0xFF |
| 3761 | #define CE_REG_FR_SQS_G07_INIT 0xB | 3761 | #define CE_REG_FR_SQS_G07_INIT 0xB |
| 3762 | 3762 | ||
| 3763 | #define CE_REG_FR_SQS_G08__A 0x1820031 | 3763 | #define CE_REG_FR_SQS_G08__A 0x1820031 |
| 3764 | #define CE_REG_FR_SQS_G08__W 8 | 3764 | #define CE_REG_FR_SQS_G08__W 8 |
| 3765 | #define CE_REG_FR_SQS_G08__M 0xFF | 3765 | #define CE_REG_FR_SQS_G08__M 0xFF |
| 3766 | #define CE_REG_FR_SQS_G08_INIT 0xB | 3766 | #define CE_REG_FR_SQS_G08_INIT 0xB |
| 3767 | 3767 | ||
| 3768 | #define CE_REG_FR_SQS_G09__A 0x1820032 | 3768 | #define CE_REG_FR_SQS_G09__A 0x1820032 |
| 3769 | #define CE_REG_FR_SQS_G09__W 8 | 3769 | #define CE_REG_FR_SQS_G09__W 8 |
| 3770 | #define CE_REG_FR_SQS_G09__M 0xFF | 3770 | #define CE_REG_FR_SQS_G09__M 0xFF |
| 3771 | #define CE_REG_FR_SQS_G09_INIT 0xB | 3771 | #define CE_REG_FR_SQS_G09_INIT 0xB |
| 3772 | 3772 | ||
| 3773 | #define CE_REG_FR_SQS_G10__A 0x1820033 | 3773 | #define CE_REG_FR_SQS_G10__A 0x1820033 |
| 3774 | #define CE_REG_FR_SQS_G10__W 8 | 3774 | #define CE_REG_FR_SQS_G10__W 8 |
| 3775 | #define CE_REG_FR_SQS_G10__M 0xFF | 3775 | #define CE_REG_FR_SQS_G10__M 0xFF |
| 3776 | #define CE_REG_FR_SQS_G10_INIT 0xB | 3776 | #define CE_REG_FR_SQS_G10_INIT 0xB |
| 3777 | 3777 | ||
| 3778 | #define CE_REG_FR_SQS_G11__A 0x1820034 | 3778 | #define CE_REG_FR_SQS_G11__A 0x1820034 |
| 3779 | #define CE_REG_FR_SQS_G11__W 8 | 3779 | #define CE_REG_FR_SQS_G11__W 8 |
| 3780 | #define CE_REG_FR_SQS_G11__M 0xFF | 3780 | #define CE_REG_FR_SQS_G11__M 0xFF |
| 3781 | #define CE_REG_FR_SQS_G11_INIT 0xB | 3781 | #define CE_REG_FR_SQS_G11_INIT 0xB |
| 3782 | 3782 | ||
| 3783 | #define CE_REG_FR_SQS_G12__A 0x1820035 | 3783 | #define CE_REG_FR_SQS_G12__A 0x1820035 |
| 3784 | #define CE_REG_FR_SQS_G12__W 8 | 3784 | #define CE_REG_FR_SQS_G12__W 8 |
| 3785 | #define CE_REG_FR_SQS_G12__M 0xFF | 3785 | #define CE_REG_FR_SQS_G12__M 0xFF |
| 3786 | #define CE_REG_FR_SQS_G12_INIT 0x5 | 3786 | #define CE_REG_FR_SQS_G12_INIT 0x5 |
| 3787 | 3787 | ||
| 3788 | #define CE_REG_FR_RIO_G00__A 0x1820036 | 3788 | #define CE_REG_FR_RIO_G00__A 0x1820036 |
| 3789 | #define CE_REG_FR_RIO_G00__W 9 | 3789 | #define CE_REG_FR_RIO_G00__W 9 |
| 3790 | #define CE_REG_FR_RIO_G00__M 0x1FF | 3790 | #define CE_REG_FR_RIO_G00__M 0x1FF |
| 3791 | #define CE_REG_FR_RIO_G00_INIT 0x1FF | 3791 | #define CE_REG_FR_RIO_G00_INIT 0x1FF |
| 3792 | 3792 | ||
| 3793 | #define CE_REG_FR_RIO_G01__A 0x1820037 | 3793 | #define CE_REG_FR_RIO_G01__A 0x1820037 |
| 3794 | #define CE_REG_FR_RIO_G01__W 9 | 3794 | #define CE_REG_FR_RIO_G01__W 9 |
| 3795 | #define CE_REG_FR_RIO_G01__M 0x1FF | 3795 | #define CE_REG_FR_RIO_G01__M 0x1FF |
| 3796 | #define CE_REG_FR_RIO_G01_INIT 0x190 | 3796 | #define CE_REG_FR_RIO_G01_INIT 0x190 |
| 3797 | 3797 | ||
| 3798 | #define CE_REG_FR_RIO_G02__A 0x1820038 | 3798 | #define CE_REG_FR_RIO_G02__A 0x1820038 |
| 3799 | #define CE_REG_FR_RIO_G02__W 9 | 3799 | #define CE_REG_FR_RIO_G02__W 9 |
| 3800 | #define CE_REG_FR_RIO_G02__M 0x1FF | 3800 | #define CE_REG_FR_RIO_G02__M 0x1FF |
| 3801 | #define CE_REG_FR_RIO_G02_INIT 0x10B | 3801 | #define CE_REG_FR_RIO_G02_INIT 0x10B |
| 3802 | 3802 | ||
| 3803 | #define CE_REG_FR_RIO_G03__A 0x1820039 | 3803 | #define CE_REG_FR_RIO_G03__A 0x1820039 |
| 3804 | #define CE_REG_FR_RIO_G03__W 9 | 3804 | #define CE_REG_FR_RIO_G03__W 9 |
| 3805 | #define CE_REG_FR_RIO_G03__M 0x1FF | 3805 | #define CE_REG_FR_RIO_G03__M 0x1FF |
| 3806 | #define CE_REG_FR_RIO_G03_INIT 0xC8 | 3806 | #define CE_REG_FR_RIO_G03_INIT 0xC8 |
| 3807 | 3807 | ||
| 3808 | #define CE_REG_FR_RIO_G04__A 0x182003A | 3808 | #define CE_REG_FR_RIO_G04__A 0x182003A |
| 3809 | #define CE_REG_FR_RIO_G04__W 9 | 3809 | #define CE_REG_FR_RIO_G04__W 9 |
| 3810 | #define CE_REG_FR_RIO_G04__M 0x1FF | 3810 | #define CE_REG_FR_RIO_G04__M 0x1FF |
| 3811 | #define CE_REG_FR_RIO_G04_INIT 0xA0 | 3811 | #define CE_REG_FR_RIO_G04_INIT 0xA0 |
| 3812 | 3812 | ||
| 3813 | #define CE_REG_FR_RIO_G05__A 0x182003B | 3813 | #define CE_REG_FR_RIO_G05__A 0x182003B |
| 3814 | #define CE_REG_FR_RIO_G05__W 9 | 3814 | #define CE_REG_FR_RIO_G05__W 9 |
| 3815 | #define CE_REG_FR_RIO_G05__M 0x1FF | 3815 | #define CE_REG_FR_RIO_G05__M 0x1FF |
| 3816 | #define CE_REG_FR_RIO_G05_INIT 0x85 | 3816 | #define CE_REG_FR_RIO_G05_INIT 0x85 |
| 3817 | 3817 | ||
| 3818 | #define CE_REG_FR_RIO_G06__A 0x182003C | 3818 | #define CE_REG_FR_RIO_G06__A 0x182003C |
| 3819 | #define CE_REG_FR_RIO_G06__W 9 | 3819 | #define CE_REG_FR_RIO_G06__W 9 |
| 3820 | #define CE_REG_FR_RIO_G06__M 0x1FF | 3820 | #define CE_REG_FR_RIO_G06__M 0x1FF |
| 3821 | #define CE_REG_FR_RIO_G06_INIT 0x72 | 3821 | #define CE_REG_FR_RIO_G06_INIT 0x72 |
| 3822 | 3822 | ||
| 3823 | #define CE_REG_FR_RIO_G07__A 0x182003D | 3823 | #define CE_REG_FR_RIO_G07__A 0x182003D |
| 3824 | #define CE_REG_FR_RIO_G07__W 9 | 3824 | #define CE_REG_FR_RIO_G07__W 9 |
| 3825 | #define CE_REG_FR_RIO_G07__M 0x1FF | 3825 | #define CE_REG_FR_RIO_G07__M 0x1FF |
| 3826 | #define CE_REG_FR_RIO_G07_INIT 0x64 | 3826 | #define CE_REG_FR_RIO_G07_INIT 0x64 |
| 3827 | 3827 | ||
| 3828 | #define CE_REG_FR_RIO_G08__A 0x182003E | 3828 | #define CE_REG_FR_RIO_G08__A 0x182003E |
| 3829 | #define CE_REG_FR_RIO_G08__W 9 | 3829 | #define CE_REG_FR_RIO_G08__W 9 |
| 3830 | #define CE_REG_FR_RIO_G08__M 0x1FF | 3830 | #define CE_REG_FR_RIO_G08__M 0x1FF |
| 3831 | #define CE_REG_FR_RIO_G08_INIT 0x59 | 3831 | #define CE_REG_FR_RIO_G08_INIT 0x59 |
| 3832 | 3832 | ||
| 3833 | #define CE_REG_FR_RIO_G09__A 0x182003F | 3833 | #define CE_REG_FR_RIO_G09__A 0x182003F |
| 3834 | #define CE_REG_FR_RIO_G09__W 9 | 3834 | #define CE_REG_FR_RIO_G09__W 9 |
| 3835 | #define CE_REG_FR_RIO_G09__M 0x1FF | 3835 | #define CE_REG_FR_RIO_G09__M 0x1FF |
| 3836 | #define CE_REG_FR_RIO_G09_INIT 0x50 | 3836 | #define CE_REG_FR_RIO_G09_INIT 0x50 |
| 3837 | 3837 | ||
| 3838 | #define CE_REG_FR_RIO_G10__A 0x1820040 | 3838 | #define CE_REG_FR_RIO_G10__A 0x1820040 |
| 3839 | #define CE_REG_FR_RIO_G10__W 9 | 3839 | #define CE_REG_FR_RIO_G10__W 9 |
| 3840 | #define CE_REG_FR_RIO_G10__M 0x1FF | 3840 | #define CE_REG_FR_RIO_G10__M 0x1FF |
| 3841 | #define CE_REG_FR_RIO_G10_INIT 0x49 | 3841 | #define CE_REG_FR_RIO_G10_INIT 0x49 |
| 3842 | 3842 | ||
| 3843 | #define CE_REG_FR_MODE__A 0x1820041 | 3843 | #define CE_REG_FR_MODE__A 0x1820041 |
| 3844 | #define CE_REG_FR_MODE__W 6 | 3844 | #define CE_REG_FR_MODE__W 6 |
| 3845 | #define CE_REG_FR_MODE__M 0x3F | 3845 | #define CE_REG_FR_MODE__M 0x3F |
| 3846 | 3846 | ||
| 3847 | #define CE_REG_FR_MODE_UPDATE_ENABLE__B 0 | 3847 | #define CE_REG_FR_MODE_UPDATE_ENABLE__B 0 |
| 3848 | #define CE_REG_FR_MODE_UPDATE_ENABLE__W 1 | 3848 | #define CE_REG_FR_MODE_UPDATE_ENABLE__W 1 |
| 3849 | #define CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 | 3849 | #define CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 |
| 3850 | 3850 | ||
| 3851 | #define CE_REG_FR_MODE_ERROR_SHIFT__B 1 | 3851 | #define CE_REG_FR_MODE_ERROR_SHIFT__B 1 |
| 3852 | #define CE_REG_FR_MODE_ERROR_SHIFT__W 1 | 3852 | #define CE_REG_FR_MODE_ERROR_SHIFT__W 1 |
| 3853 | #define CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 | 3853 | #define CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 |
| 3854 | 3854 | ||
| 3855 | #define CE_REG_FR_MODE_NEXP_UPDATE__B 2 | 3855 | #define CE_REG_FR_MODE_NEXP_UPDATE__B 2 |
| 3856 | #define CE_REG_FR_MODE_NEXP_UPDATE__W 1 | 3856 | #define CE_REG_FR_MODE_NEXP_UPDATE__W 1 |
| 3857 | #define CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 | 3857 | #define CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 |
| 3858 | 3858 | ||
| 3859 | #define CE_REG_FR_MODE_MANUAL_SHIFT__B 3 | 3859 | #define CE_REG_FR_MODE_MANUAL_SHIFT__B 3 |
| 3860 | #define CE_REG_FR_MODE_MANUAL_SHIFT__W 1 | 3860 | #define CE_REG_FR_MODE_MANUAL_SHIFT__W 1 |
| 3861 | #define CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 | 3861 | #define CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 |
| 3862 | 3862 | ||
| 3863 | #define CE_REG_FR_MODE_SQUASH_MODE__B 4 | 3863 | #define CE_REG_FR_MODE_SQUASH_MODE__B 4 |
| 3864 | #define CE_REG_FR_MODE_SQUASH_MODE__W 1 | 3864 | #define CE_REG_FR_MODE_SQUASH_MODE__W 1 |
| 3865 | #define CE_REG_FR_MODE_SQUASH_MODE__M 0x10 | 3865 | #define CE_REG_FR_MODE_SQUASH_MODE__M 0x10 |
| 3866 | 3866 | ||
| 3867 | #define CE_REG_FR_MODE_UPDATE_MODE__B 5 | 3867 | #define CE_REG_FR_MODE_UPDATE_MODE__B 5 |
| 3868 | #define CE_REG_FR_MODE_UPDATE_MODE__W 1 | 3868 | #define CE_REG_FR_MODE_UPDATE_MODE__W 1 |
| 3869 | #define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 | 3869 | #define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 |
| 3870 | #define CE_REG_FR_MODE_INIT 0x3E | 3870 | #define CE_REG_FR_MODE_INIT 0x3E |
| 3871 | 3871 | ||
| 3872 | #define CE_REG_FR_SQS_TRH__A 0x1820042 | 3872 | #define CE_REG_FR_SQS_TRH__A 0x1820042 |
| 3873 | #define CE_REG_FR_SQS_TRH__W 8 | 3873 | #define CE_REG_FR_SQS_TRH__W 8 |
| 3874 | #define CE_REG_FR_SQS_TRH__M 0xFF | 3874 | #define CE_REG_FR_SQS_TRH__M 0xFF |
| 3875 | #define CE_REG_FR_SQS_TRH_INIT 0x80 | 3875 | #define CE_REG_FR_SQS_TRH_INIT 0x80 |
| 3876 | 3876 | ||
| 3877 | #define CE_REG_FR_RIO_GAIN__A 0x1820043 | 3877 | #define CE_REG_FR_RIO_GAIN__A 0x1820043 |
| 3878 | #define CE_REG_FR_RIO_GAIN__W 3 | 3878 | #define CE_REG_FR_RIO_GAIN__W 3 |
| 3879 | #define CE_REG_FR_RIO_GAIN__M 0x7 | 3879 | #define CE_REG_FR_RIO_GAIN__M 0x7 |
| 3880 | #define CE_REG_FR_RIO_GAIN_INIT 0x2 | 3880 | #define CE_REG_FR_RIO_GAIN_INIT 0x2 |
| 3881 | 3881 | ||
| 3882 | #define CE_REG_FR_BYPASS__A 0x1820044 | 3882 | #define CE_REG_FR_BYPASS__A 0x1820044 |
| 3883 | #define CE_REG_FR_BYPASS__W 10 | 3883 | #define CE_REG_FR_BYPASS__W 10 |
| 3884 | #define CE_REG_FR_BYPASS__M 0x3FF | 3884 | #define CE_REG_FR_BYPASS__M 0x3FF |
| 3885 | 3885 | ||
| 3886 | #define CE_REG_FR_BYPASS_RUN_IN__B 0 | 3886 | #define CE_REG_FR_BYPASS_RUN_IN__B 0 |
| 3887 | #define CE_REG_FR_BYPASS_RUN_IN__W 4 | 3887 | #define CE_REG_FR_BYPASS_RUN_IN__W 4 |
| 3888 | #define CE_REG_FR_BYPASS_RUN_IN__M 0xF | 3888 | #define CE_REG_FR_BYPASS_RUN_IN__M 0xF |
| 3889 | 3889 | ||
| 3890 | #define CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 | 3890 | #define CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 |
| 3891 | #define CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 | 3891 | #define CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 |
| 3892 | #define CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 | 3892 | #define CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 |
| 3893 | 3893 | ||
| 3894 | #define CE_REG_FR_BYPASS_TOTAL__B 9 | 3894 | #define CE_REG_FR_BYPASS_TOTAL__B 9 |
| 3895 | #define CE_REG_FR_BYPASS_TOTAL__W 1 | 3895 | #define CE_REG_FR_BYPASS_TOTAL__W 1 |
| 3896 | #define CE_REG_FR_BYPASS_TOTAL__M 0x200 | 3896 | #define CE_REG_FR_BYPASS_TOTAL__M 0x200 |
| 3897 | #define CE_REG_FR_BYPASS_INIT 0x13B | 3897 | #define CE_REG_FR_BYPASS_INIT 0x13B |
| 3898 | 3898 | ||
| 3899 | #define CE_REG_FR_PM_SET__A 0x1820045 | 3899 | #define CE_REG_FR_PM_SET__A 0x1820045 |
| 3900 | #define CE_REG_FR_PM_SET__W 4 | 3900 | #define CE_REG_FR_PM_SET__W 4 |
| 3901 | #define CE_REG_FR_PM_SET__M 0xF | 3901 | #define CE_REG_FR_PM_SET__M 0xF |
| 3902 | #define CE_REG_FR_PM_SET_INIT 0x4 | 3902 | #define CE_REG_FR_PM_SET_INIT 0x4 |
| 3903 | 3903 | ||
| 3904 | #define CE_REG_FR_ERR_SH__A 0x1820046 | 3904 | #define CE_REG_FR_ERR_SH__A 0x1820046 |
| 3905 | #define CE_REG_FR_ERR_SH__W 4 | 3905 | #define CE_REG_FR_ERR_SH__W 4 |
| 3906 | #define CE_REG_FR_ERR_SH__M 0xF | 3906 | #define CE_REG_FR_ERR_SH__M 0xF |
| 3907 | #define CE_REG_FR_ERR_SH_INIT 0x4 | 3907 | #define CE_REG_FR_ERR_SH_INIT 0x4 |
| 3908 | 3908 | ||
| 3909 | #define CE_REG_FR_MAN_SH__A 0x1820047 | 3909 | #define CE_REG_FR_MAN_SH__A 0x1820047 |
| 3910 | #define CE_REG_FR_MAN_SH__W 4 | 3910 | #define CE_REG_FR_MAN_SH__W 4 |
| 3911 | #define CE_REG_FR_MAN_SH__M 0xF | 3911 | #define CE_REG_FR_MAN_SH__M 0xF |
| 3912 | #define CE_REG_FR_MAN_SH_INIT 0x7 | 3912 | #define CE_REG_FR_MAN_SH_INIT 0x7 |
| 3913 | 3913 | ||
| 3914 | #define CE_REG_FR_TAP_SH__A 0x1820048 | 3914 | #define CE_REG_FR_TAP_SH__A 0x1820048 |
| 3915 | #define CE_REG_FR_TAP_SH__W 3 | 3915 | #define CE_REG_FR_TAP_SH__W 3 |
| 3916 | #define CE_REG_FR_TAP_SH__M 0x7 | 3916 | #define CE_REG_FR_TAP_SH__M 0x7 |
| 3917 | #define CE_REG_FR_TAP_SH_INIT 0x3 | 3917 | #define CE_REG_FR_TAP_SH_INIT 0x3 |
| 3918 | 3918 | ||
| 3919 | #define CE_REG_FR_CLIP__A 0x1820049 | 3919 | #define CE_REG_FR_CLIP__A 0x1820049 |
| 3920 | #define CE_REG_FR_CLIP__W 9 | 3920 | #define CE_REG_FR_CLIP__W 9 |
| 3921 | #define CE_REG_FR_CLIP__M 0x1FF | 3921 | #define CE_REG_FR_CLIP__M 0x1FF |
| 3922 | #define CE_REG_FR_CLIP_INIT 0x49 | 3922 | #define CE_REG_FR_CLIP_INIT 0x49 |
| 3923 | 3923 | ||
| 3924 | #define CE_PB_RAM__A 0x1830000 | 3924 | #define CE_PB_RAM__A 0x1830000 |
| 3925 | 3925 | ||
| 3926 | #define CE_NE_RAM__A 0x1840000 | 3926 | #define CE_NE_RAM__A 0x1840000 |
| 3927 | 3927 | ||
| 3928 | #define EQ_SID 0xE | 3928 | #define EQ_SID 0xE |
| 3929 | 3929 | ||
| 3930 | #define EQ_COMM_EXEC__A 0x1C00000 | 3930 | #define EQ_COMM_EXEC__A 0x1C00000 |
| 3931 | #define EQ_COMM_EXEC__W 3 | 3931 | #define EQ_COMM_EXEC__W 3 |
| 3932 | #define EQ_COMM_EXEC__M 0x7 | 3932 | #define EQ_COMM_EXEC__M 0x7 |
| 3933 | #define EQ_COMM_EXEC_CTL__B 0 | 3933 | #define EQ_COMM_EXEC_CTL__B 0 |
| 3934 | #define EQ_COMM_EXEC_CTL__W 3 | 3934 | #define EQ_COMM_EXEC_CTL__W 3 |
| 3935 | #define EQ_COMM_EXEC_CTL__M 0x7 | 3935 | #define EQ_COMM_EXEC_CTL__M 0x7 |
| 3936 | #define EQ_COMM_EXEC_CTL_STOP 0x0 | 3936 | #define EQ_COMM_EXEC_CTL_STOP 0x0 |
| 3937 | #define EQ_COMM_EXEC_CTL_ACTIVE 0x1 | 3937 | #define EQ_COMM_EXEC_CTL_ACTIVE 0x1 |
| 3938 | #define EQ_COMM_EXEC_CTL_HOLD 0x2 | 3938 | #define EQ_COMM_EXEC_CTL_HOLD 0x2 |
| 3939 | #define EQ_COMM_EXEC_CTL_STEP 0x3 | 3939 | #define EQ_COMM_EXEC_CTL_STEP 0x3 |
| 3940 | #define EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 3940 | #define EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 3941 | #define EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 3941 | #define EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 3942 | 3942 | ||
| 3943 | #define EQ_COMM_STATE__A 0x1C00001 | 3943 | #define EQ_COMM_STATE__A 0x1C00001 |
| 3944 | #define EQ_COMM_STATE__W 16 | 3944 | #define EQ_COMM_STATE__W 16 |
| 3945 | #define EQ_COMM_STATE__M 0xFFFF | 3945 | #define EQ_COMM_STATE__M 0xFFFF |
| 3946 | #define EQ_COMM_MB__A 0x1C00002 | 3946 | #define EQ_COMM_MB__A 0x1C00002 |
| 3947 | #define EQ_COMM_MB__W 16 | 3947 | #define EQ_COMM_MB__W 16 |
| 3948 | #define EQ_COMM_MB__M 0xFFFF | 3948 | #define EQ_COMM_MB__M 0xFFFF |
| 3949 | #define EQ_COMM_SERVICE0__A 0x1C00003 | 3949 | #define EQ_COMM_SERVICE0__A 0x1C00003 |
| 3950 | #define EQ_COMM_SERVICE0__W 16 | 3950 | #define EQ_COMM_SERVICE0__W 16 |
| 3951 | #define EQ_COMM_SERVICE0__M 0xFFFF | 3951 | #define EQ_COMM_SERVICE0__M 0xFFFF |
| 3952 | #define EQ_COMM_SERVICE1__A 0x1C00004 | 3952 | #define EQ_COMM_SERVICE1__A 0x1C00004 |
| 3953 | #define EQ_COMM_SERVICE1__W 16 | 3953 | #define EQ_COMM_SERVICE1__W 16 |
| 3954 | #define EQ_COMM_SERVICE1__M 0xFFFF | 3954 | #define EQ_COMM_SERVICE1__M 0xFFFF |
| 3955 | #define EQ_COMM_INT_STA__A 0x1C00007 | 3955 | #define EQ_COMM_INT_STA__A 0x1C00007 |
| 3956 | #define EQ_COMM_INT_STA__W 16 | 3956 | #define EQ_COMM_INT_STA__W 16 |
| 3957 | #define EQ_COMM_INT_STA__M 0xFFFF | 3957 | #define EQ_COMM_INT_STA__M 0xFFFF |
| 3958 | #define EQ_COMM_INT_MSK__A 0x1C00008 | 3958 | #define EQ_COMM_INT_MSK__A 0x1C00008 |
| 3959 | #define EQ_COMM_INT_MSK__W 16 | 3959 | #define EQ_COMM_INT_MSK__W 16 |
| 3960 | #define EQ_COMM_INT_MSK__M 0xFFFF | 3960 | #define EQ_COMM_INT_MSK__M 0xFFFF |
| 3961 | 3961 | ||
| 3962 | #define EQ_REG_COMM_EXEC__A 0x1C10000 | 3962 | #define EQ_REG_COMM_EXEC__A 0x1C10000 |
| 3963 | #define EQ_REG_COMM_EXEC__W 3 | 3963 | #define EQ_REG_COMM_EXEC__W 3 |
| 3964 | #define EQ_REG_COMM_EXEC__M 0x7 | 3964 | #define EQ_REG_COMM_EXEC__M 0x7 |
| 3965 | #define EQ_REG_COMM_EXEC_CTL__B 0 | 3965 | #define EQ_REG_COMM_EXEC_CTL__B 0 |
| 3966 | #define EQ_REG_COMM_EXEC_CTL__W 3 | 3966 | #define EQ_REG_COMM_EXEC_CTL__W 3 |
| 3967 | #define EQ_REG_COMM_EXEC_CTL__M 0x7 | 3967 | #define EQ_REG_COMM_EXEC_CTL__M 0x7 |
| 3968 | #define EQ_REG_COMM_EXEC_CTL_STOP 0x0 | 3968 | #define EQ_REG_COMM_EXEC_CTL_STOP 0x0 |
| 3969 | #define EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 3969 | #define EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 3970 | #define EQ_REG_COMM_EXEC_CTL_HOLD 0x2 | 3970 | #define EQ_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 3971 | #define EQ_REG_COMM_EXEC_CTL_STEP 0x3 | 3971 | #define EQ_REG_COMM_EXEC_CTL_STEP 0x3 |
| 3972 | 3972 | ||
| 3973 | #define EQ_REG_COMM_STATE__A 0x1C10001 | 3973 | #define EQ_REG_COMM_STATE__A 0x1C10001 |
| 3974 | #define EQ_REG_COMM_STATE__W 4 | 3974 | #define EQ_REG_COMM_STATE__W 4 |
| 3975 | #define EQ_REG_COMM_STATE__M 0xF | 3975 | #define EQ_REG_COMM_STATE__M 0xF |
| 3976 | 3976 | ||
| 3977 | #define EQ_REG_COMM_MB__A 0x1C10002 | 3977 | #define EQ_REG_COMM_MB__A 0x1C10002 |
| 3978 | #define EQ_REG_COMM_MB__W 6 | 3978 | #define EQ_REG_COMM_MB__W 6 |
| 3979 | #define EQ_REG_COMM_MB__M 0x3F | 3979 | #define EQ_REG_COMM_MB__M 0x3F |
| 3980 | #define EQ_REG_COMM_MB_CTR__B 0 | 3980 | #define EQ_REG_COMM_MB_CTR__B 0 |
| 3981 | #define EQ_REG_COMM_MB_CTR__W 1 | 3981 | #define EQ_REG_COMM_MB_CTR__W 1 |
| 3982 | #define EQ_REG_COMM_MB_CTR__M 0x1 | 3982 | #define EQ_REG_COMM_MB_CTR__M 0x1 |
| 3983 | #define EQ_REG_COMM_MB_CTR_OFF 0x0 | 3983 | #define EQ_REG_COMM_MB_CTR_OFF 0x0 |
| 3984 | #define EQ_REG_COMM_MB_CTR_ON 0x1 | 3984 | #define EQ_REG_COMM_MB_CTR_ON 0x1 |
| 3985 | #define EQ_REG_COMM_MB_OBS__B 1 | 3985 | #define EQ_REG_COMM_MB_OBS__B 1 |
| 3986 | #define EQ_REG_COMM_MB_OBS__W 1 | 3986 | #define EQ_REG_COMM_MB_OBS__W 1 |
| 3987 | #define EQ_REG_COMM_MB_OBS__M 0x2 | 3987 | #define EQ_REG_COMM_MB_OBS__M 0x2 |
| 3988 | #define EQ_REG_COMM_MB_OBS_OFF 0x0 | 3988 | #define EQ_REG_COMM_MB_OBS_OFF 0x0 |
| 3989 | #define EQ_REG_COMM_MB_OBS_ON 0x2 | 3989 | #define EQ_REG_COMM_MB_OBS_ON 0x2 |
| 3990 | #define EQ_REG_COMM_MB_CTR_MUX__B 2 | 3990 | #define EQ_REG_COMM_MB_CTR_MUX__B 2 |
| 3991 | #define EQ_REG_COMM_MB_CTR_MUX__W 2 | 3991 | #define EQ_REG_COMM_MB_CTR_MUX__W 2 |
| 3992 | #define EQ_REG_COMM_MB_CTR_MUX__M 0xC | 3992 | #define EQ_REG_COMM_MB_CTR_MUX__M 0xC |
| 3993 | #define EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 | 3993 | #define EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 |
| 3994 | #define EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 | 3994 | #define EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 |
| 3995 | #define EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 | 3995 | #define EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 |
| 3996 | #define EQ_REG_COMM_MB_OBS_MUX__B 4 | 3996 | #define EQ_REG_COMM_MB_OBS_MUX__B 4 |
| 3997 | #define EQ_REG_COMM_MB_OBS_MUX__W 2 | 3997 | #define EQ_REG_COMM_MB_OBS_MUX__W 2 |
| 3998 | #define EQ_REG_COMM_MB_OBS_MUX__M 0x30 | 3998 | #define EQ_REG_COMM_MB_OBS_MUX__M 0x30 |
| 3999 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 | 3999 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 |
| 4000 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 | 4000 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 |
| 4001 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 | 4001 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 |
| 4002 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 | 4002 | #define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 |
| 4003 | 4003 | ||
| 4004 | #define EQ_REG_COMM_SERVICE0__A 0x1C10003 | 4004 | #define EQ_REG_COMM_SERVICE0__A 0x1C10003 |
| 4005 | #define EQ_REG_COMM_SERVICE0__W 10 | 4005 | #define EQ_REG_COMM_SERVICE0__W 10 |
| 4006 | #define EQ_REG_COMM_SERVICE0__M 0x3FF | 4006 | #define EQ_REG_COMM_SERVICE0__M 0x3FF |
| 4007 | 4007 | ||
| 4008 | #define EQ_REG_COMM_SERVICE1__A 0x1C10004 | 4008 | #define EQ_REG_COMM_SERVICE1__A 0x1C10004 |
| 4009 | #define EQ_REG_COMM_SERVICE1__W 11 | 4009 | #define EQ_REG_COMM_SERVICE1__W 11 |
| 4010 | #define EQ_REG_COMM_SERVICE1__M 0x7FF | 4010 | #define EQ_REG_COMM_SERVICE1__M 0x7FF |
| 4011 | 4011 | ||
| 4012 | #define EQ_REG_COMM_INT_STA__A 0x1C10007 | 4012 | #define EQ_REG_COMM_INT_STA__A 0x1C10007 |
| 4013 | #define EQ_REG_COMM_INT_STA__W 2 | 4013 | #define EQ_REG_COMM_INT_STA__W 2 |
| 4014 | #define EQ_REG_COMM_INT_STA__M 0x3 | 4014 | #define EQ_REG_COMM_INT_STA__M 0x3 |
| 4015 | #define EQ_REG_COMM_INT_STA_TPS_RDY__B 0 | 4015 | #define EQ_REG_COMM_INT_STA_TPS_RDY__B 0 |
| 4016 | #define EQ_REG_COMM_INT_STA_TPS_RDY__W 1 | 4016 | #define EQ_REG_COMM_INT_STA_TPS_RDY__W 1 |
| 4017 | #define EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 | 4017 | #define EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 |
| 4018 | #define EQ_REG_COMM_INT_STA_ERR_RDY__B 1 | 4018 | #define EQ_REG_COMM_INT_STA_ERR_RDY__B 1 |
| 4019 | #define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 | 4019 | #define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 |
| 4020 | #define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 | 4020 | #define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 |
| 4021 | 4021 | ||
| 4022 | #define EQ_REG_COMM_INT_MSK__A 0x1C10008 | 4022 | #define EQ_REG_COMM_INT_MSK__A 0x1C10008 |
| 4023 | #define EQ_REG_COMM_INT_MSK__W 2 | 4023 | #define EQ_REG_COMM_INT_MSK__W 2 |
| 4024 | #define EQ_REG_COMM_INT_MSK__M 0x3 | 4024 | #define EQ_REG_COMM_INT_MSK__M 0x3 |
| 4025 | #define EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 | 4025 | #define EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 |
| 4026 | #define EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 | 4026 | #define EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 |
| 4027 | #define EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 | 4027 | #define EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 |
| 4028 | #define EQ_REG_COMM_INT_MSK_MER_RDY__B 1 | 4028 | #define EQ_REG_COMM_INT_MSK_MER_RDY__B 1 |
| 4029 | #define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 | 4029 | #define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 |
| 4030 | #define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 | 4030 | #define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 |
| 4031 | 4031 | ||
| 4032 | #define EQ_REG_IS_MODE__A 0x1C10014 | 4032 | #define EQ_REG_IS_MODE__A 0x1C10014 |
| 4033 | #define EQ_REG_IS_MODE__W 4 | 4033 | #define EQ_REG_IS_MODE__W 4 |
| 4034 | #define EQ_REG_IS_MODE__M 0xF | 4034 | #define EQ_REG_IS_MODE__M 0xF |
| 4035 | #define EQ_REG_IS_MODE_INIT 0x0 | 4035 | #define EQ_REG_IS_MODE_INIT 0x0 |
| 4036 | 4036 | ||
| 4037 | #define EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 | 4037 | #define EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 |
| 4038 | #define EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 | 4038 | #define EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 |
| 4039 | #define EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 | 4039 | #define EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 |
| 4040 | #define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 | 4040 | #define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 |
| 4041 | #define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 | 4041 | #define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 |
| 4042 | 4042 | ||
| 4043 | #define EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 | 4043 | #define EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 |
| 4044 | #define EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 | 4044 | #define EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 |
| 4045 | #define EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 | 4045 | #define EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 |
| 4046 | #define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 | 4046 | #define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 |
| 4047 | #define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 | 4047 | #define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 |
| 4048 | 4048 | ||
| 4049 | #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 | 4049 | #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 |
| 4050 | #define EQ_REG_IS_GAIN_MAN__W 10 | 4050 | #define EQ_REG_IS_GAIN_MAN__W 10 |
| 4051 | #define EQ_REG_IS_GAIN_MAN__M 0x3FF | 4051 | #define EQ_REG_IS_GAIN_MAN__M 0x3FF |
| 4052 | #define EQ_REG_IS_GAIN_MAN_INIT 0x0 | 4052 | #define EQ_REG_IS_GAIN_MAN_INIT 0x0 |
| 4053 | 4053 | ||
| 4054 | #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 | 4054 | #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 |
| 4055 | #define EQ_REG_IS_GAIN_EXP__W 5 | 4055 | #define EQ_REG_IS_GAIN_EXP__W 5 |
| 4056 | #define EQ_REG_IS_GAIN_EXP__M 0x1F | 4056 | #define EQ_REG_IS_GAIN_EXP__M 0x1F |
| 4057 | #define EQ_REG_IS_GAIN_EXP_INIT 0x0 | 4057 | #define EQ_REG_IS_GAIN_EXP_INIT 0x0 |
| 4058 | 4058 | ||
| 4059 | #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 | 4059 | #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 |
| 4060 | #define EQ_REG_IS_CLIP_EXP__W 5 | 4060 | #define EQ_REG_IS_CLIP_EXP__W 5 |
| 4061 | #define EQ_REG_IS_CLIP_EXP__M 0x1F | 4061 | #define EQ_REG_IS_CLIP_EXP__M 0x1F |
| 4062 | #define EQ_REG_IS_CLIP_EXP_INIT 0x0 | 4062 | #define EQ_REG_IS_CLIP_EXP_INIT 0x0 |
| 4063 | 4063 | ||
| 4064 | #define EQ_REG_DV_MODE__A 0x1C1001E | 4064 | #define EQ_REG_DV_MODE__A 0x1C1001E |
| 4065 | #define EQ_REG_DV_MODE__W 4 | 4065 | #define EQ_REG_DV_MODE__W 4 |
| 4066 | #define EQ_REG_DV_MODE__M 0xF | 4066 | #define EQ_REG_DV_MODE__M 0xF |
| 4067 | #define EQ_REG_DV_MODE_INIT 0x0 | 4067 | #define EQ_REG_DV_MODE_INIT 0x0 |
| 4068 | 4068 | ||
| 4069 | #define EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 | 4069 | #define EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 |
| 4070 | #define EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 | 4070 | #define EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 |
| 4071 | #define EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 | 4071 | #define EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 |
| 4072 | #define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 | 4072 | #define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 |
| 4073 | #define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 | 4073 | #define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 |
| 4074 | 4074 | ||
| 4075 | #define EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 | 4075 | #define EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 |
| 4076 | #define EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 | 4076 | #define EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 |
| 4077 | #define EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 | 4077 | #define EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 |
| 4078 | #define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 | 4078 | #define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 |
| 4079 | #define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 | 4079 | #define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 |
| 4080 | 4080 | ||
| 4081 | #define EQ_REG_DV_MODE_CLP_REA_ENA__B 2 | 4081 | #define EQ_REG_DV_MODE_CLP_REA_ENA__B 2 |
| 4082 | #define EQ_REG_DV_MODE_CLP_REA_ENA__W 1 | 4082 | #define EQ_REG_DV_MODE_CLP_REA_ENA__W 1 |
| 4083 | #define EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 | 4083 | #define EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 |
| 4084 | #define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 | 4084 | #define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 |
| 4085 | #define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 | 4085 | #define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 |
| 4086 | 4086 | ||
| 4087 | #define EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 | 4087 | #define EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 |
| 4088 | #define EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 | 4088 | #define EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 |
| 4089 | #define EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 | 4089 | #define EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 |
| 4090 | #define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 | 4090 | #define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 |
| 4091 | #define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 | 4091 | #define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 |
| 4092 | 4092 | ||
| 4093 | #define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F | 4093 | #define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F |
| 4094 | #define EQ_REG_DV_POS_CLIP_DAT__W 16 | 4094 | #define EQ_REG_DV_POS_CLIP_DAT__W 16 |
| 4095 | #define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF | 4095 | #define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF |
| 4096 | 4096 | ||
| 4097 | #define EQ_REG_SN_MODE__A 0x1C10028 | 4097 | #define EQ_REG_SN_MODE__A 0x1C10028 |
| 4098 | #define EQ_REG_SN_MODE__W 8 | 4098 | #define EQ_REG_SN_MODE__W 8 |
| 4099 | #define EQ_REG_SN_MODE__M 0xFF | 4099 | #define EQ_REG_SN_MODE__M 0xFF |
| 4100 | #define EQ_REG_SN_MODE_INIT 0x0 | 4100 | #define EQ_REG_SN_MODE_INIT 0x0 |
| 4101 | 4101 | ||
| 4102 | #define EQ_REG_SN_MODE_MODE_0__B 0 | 4102 | #define EQ_REG_SN_MODE_MODE_0__B 0 |
| 4103 | #define EQ_REG_SN_MODE_MODE_0__W 1 | 4103 | #define EQ_REG_SN_MODE_MODE_0__W 1 |
| 4104 | #define EQ_REG_SN_MODE_MODE_0__M 0x1 | 4104 | #define EQ_REG_SN_MODE_MODE_0__M 0x1 |
| 4105 | #define EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 | 4105 | #define EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 |
| 4106 | #define EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 | 4106 | #define EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 |
| 4107 | 4107 | ||
| 4108 | #define EQ_REG_SN_MODE_MODE_1__B 1 | 4108 | #define EQ_REG_SN_MODE_MODE_1__B 1 |
| 4109 | #define EQ_REG_SN_MODE_MODE_1__W 1 | 4109 | #define EQ_REG_SN_MODE_MODE_1__W 1 |
| 4110 | #define EQ_REG_SN_MODE_MODE_1__M 0x2 | 4110 | #define EQ_REG_SN_MODE_MODE_1__M 0x2 |
| 4111 | #define EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 | 4111 | #define EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 |
| 4112 | #define EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 | 4112 | #define EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 |
| 4113 | 4113 | ||
| 4114 | #define EQ_REG_SN_MODE_MODE_2__B 2 | 4114 | #define EQ_REG_SN_MODE_MODE_2__B 2 |
| 4115 | #define EQ_REG_SN_MODE_MODE_2__W 1 | 4115 | #define EQ_REG_SN_MODE_MODE_2__W 1 |
| 4116 | #define EQ_REG_SN_MODE_MODE_2__M 0x4 | 4116 | #define EQ_REG_SN_MODE_MODE_2__M 0x4 |
| 4117 | #define EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 | 4117 | #define EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 |
| 4118 | #define EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 | 4118 | #define EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 |
| 4119 | 4119 | ||
| 4120 | #define EQ_REG_SN_MODE_MODE_3__B 3 | 4120 | #define EQ_REG_SN_MODE_MODE_3__B 3 |
| 4121 | #define EQ_REG_SN_MODE_MODE_3__W 1 | 4121 | #define EQ_REG_SN_MODE_MODE_3__W 1 |
| 4122 | #define EQ_REG_SN_MODE_MODE_3__M 0x8 | 4122 | #define EQ_REG_SN_MODE_MODE_3__M 0x8 |
| 4123 | #define EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 | 4123 | #define EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 |
| 4124 | #define EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 | 4124 | #define EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 |
| 4125 | 4125 | ||
| 4126 | #define EQ_REG_SN_MODE_MODE_4__B 4 | 4126 | #define EQ_REG_SN_MODE_MODE_4__B 4 |
| 4127 | #define EQ_REG_SN_MODE_MODE_4__W 1 | 4127 | #define EQ_REG_SN_MODE_MODE_4__W 1 |
| 4128 | #define EQ_REG_SN_MODE_MODE_4__M 0x10 | 4128 | #define EQ_REG_SN_MODE_MODE_4__M 0x10 |
| 4129 | #define EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 | 4129 | #define EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 |
| 4130 | #define EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 | 4130 | #define EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 |
| 4131 | 4131 | ||
| 4132 | #define EQ_REG_SN_MODE_MODE_5__B 5 | 4132 | #define EQ_REG_SN_MODE_MODE_5__B 5 |
| 4133 | #define EQ_REG_SN_MODE_MODE_5__W 1 | 4133 | #define EQ_REG_SN_MODE_MODE_5__W 1 |
| 4134 | #define EQ_REG_SN_MODE_MODE_5__M 0x20 | 4134 | #define EQ_REG_SN_MODE_MODE_5__M 0x20 |
| 4135 | #define EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 | 4135 | #define EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 |
| 4136 | #define EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 | 4136 | #define EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 |
| 4137 | 4137 | ||
| 4138 | #define EQ_REG_SN_MODE_MODE_6__B 6 | 4138 | #define EQ_REG_SN_MODE_MODE_6__B 6 |
| 4139 | #define EQ_REG_SN_MODE_MODE_6__W 1 | 4139 | #define EQ_REG_SN_MODE_MODE_6__W 1 |
| 4140 | #define EQ_REG_SN_MODE_MODE_6__M 0x40 | 4140 | #define EQ_REG_SN_MODE_MODE_6__M 0x40 |
| 4141 | #define EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 | 4141 | #define EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 |
| 4142 | #define EQ_REG_SN_MODE_MODE_6_STATIC 0x40 | 4142 | #define EQ_REG_SN_MODE_MODE_6_STATIC 0x40 |
| 4143 | 4143 | ||
| 4144 | #define EQ_REG_SN_MODE_MODE_7__B 7 | 4144 | #define EQ_REG_SN_MODE_MODE_7__B 7 |
| 4145 | #define EQ_REG_SN_MODE_MODE_7__W 1 | 4145 | #define EQ_REG_SN_MODE_MODE_7__W 1 |
| 4146 | #define EQ_REG_SN_MODE_MODE_7__M 0x80 | 4146 | #define EQ_REG_SN_MODE_MODE_7__M 0x80 |
| 4147 | #define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 | 4147 | #define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 |
| 4148 | #define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 | 4148 | #define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 |
| 4149 | 4149 | ||
| 4150 | #define EQ_REG_SN_PFIX__A 0x1C10029 | 4150 | #define EQ_REG_SN_PFIX__A 0x1C10029 |
| 4151 | #define EQ_REG_SN_PFIX__W 8 | 4151 | #define EQ_REG_SN_PFIX__W 8 |
| 4152 | #define EQ_REG_SN_PFIX__M 0xFF | 4152 | #define EQ_REG_SN_PFIX__M 0xFF |
| 4153 | #define EQ_REG_SN_PFIX_INIT 0x0 | 4153 | #define EQ_REG_SN_PFIX_INIT 0x0 |
| 4154 | 4154 | ||
| 4155 | #define EQ_REG_SN_CEGAIN__A 0x1C1002A | 4155 | #define EQ_REG_SN_CEGAIN__A 0x1C1002A |
| 4156 | #define EQ_REG_SN_CEGAIN__W 8 | 4156 | #define EQ_REG_SN_CEGAIN__W 8 |
| 4157 | #define EQ_REG_SN_CEGAIN__M 0xFF | 4157 | #define EQ_REG_SN_CEGAIN__M 0xFF |
| 4158 | #define EQ_REG_SN_CEGAIN_INIT 0x0 | 4158 | #define EQ_REG_SN_CEGAIN_INIT 0x0 |
| 4159 | 4159 | ||
| 4160 | #define EQ_REG_SN_OFFSET__A 0x1C1002B | 4160 | #define EQ_REG_SN_OFFSET__A 0x1C1002B |
| 4161 | #define EQ_REG_SN_OFFSET__W 6 | 4161 | #define EQ_REG_SN_OFFSET__W 6 |
| 4162 | #define EQ_REG_SN_OFFSET__M 0x3F | 4162 | #define EQ_REG_SN_OFFSET__M 0x3F |
| 4163 | #define EQ_REG_SN_OFFSET_INIT 0x0 | 4163 | #define EQ_REG_SN_OFFSET_INIT 0x0 |
| 4164 | 4164 | ||
| 4165 | #define EQ_REG_SN_NULLIFY__A 0x1C1002C | 4165 | #define EQ_REG_SN_NULLIFY__A 0x1C1002C |
| 4166 | #define EQ_REG_SN_NULLIFY__W 6 | 4166 | #define EQ_REG_SN_NULLIFY__W 6 |
| 4167 | #define EQ_REG_SN_NULLIFY__M 0x3F | 4167 | #define EQ_REG_SN_NULLIFY__M 0x3F |
| 4168 | #define EQ_REG_SN_NULLIFY_INIT 0x0 | 4168 | #define EQ_REG_SN_NULLIFY_INIT 0x0 |
| 4169 | 4169 | ||
| 4170 | #define EQ_REG_SN_SQUASH__A 0x1C1002D | 4170 | #define EQ_REG_SN_SQUASH__A 0x1C1002D |
| 4171 | #define EQ_REG_SN_SQUASH__W 10 | 4171 | #define EQ_REG_SN_SQUASH__W 10 |
| 4172 | #define EQ_REG_SN_SQUASH__M 0x3FF | 4172 | #define EQ_REG_SN_SQUASH__M 0x3FF |
| 4173 | #define EQ_REG_SN_SQUASH_INIT 0x0 | 4173 | #define EQ_REG_SN_SQUASH_INIT 0x0 |
| 4174 | 4174 | ||
| 4175 | #define EQ_REG_SN_SQUASH_MAN__B 0 | 4175 | #define EQ_REG_SN_SQUASH_MAN__B 0 |
| 4176 | #define EQ_REG_SN_SQUASH_MAN__W 6 | 4176 | #define EQ_REG_SN_SQUASH_MAN__W 6 |
| 4177 | #define EQ_REG_SN_SQUASH_MAN__M 0x3F | 4177 | #define EQ_REG_SN_SQUASH_MAN__M 0x3F |
| 4178 | 4178 | ||
| 4179 | #define EQ_REG_SN_SQUASH_EXP__B 6 | 4179 | #define EQ_REG_SN_SQUASH_EXP__B 6 |
| 4180 | #define EQ_REG_SN_SQUASH_EXP__W 4 | 4180 | #define EQ_REG_SN_SQUASH_EXP__W 4 |
| 4181 | #define EQ_REG_SN_SQUASH_EXP__M 0x3C0 | 4181 | #define EQ_REG_SN_SQUASH_EXP__M 0x3C0 |
| 4182 | 4182 | ||
| 4183 | #define EQ_REG_RC_SEL_CAR__A 0x1C10032 | 4183 | #define EQ_REG_RC_SEL_CAR__A 0x1C10032 |
| 4184 | #define EQ_REG_RC_SEL_CAR__W 6 | 4184 | #define EQ_REG_RC_SEL_CAR__W 6 |
| 4185 | #define EQ_REG_RC_SEL_CAR__M 0x3F | 4185 | #define EQ_REG_RC_SEL_CAR__M 0x3F |
| 4186 | #define EQ_REG_RC_SEL_CAR_INIT 0x0 | 4186 | #define EQ_REG_RC_SEL_CAR_INIT 0x0 |
| 4187 | #define EQ_REG_RC_SEL_CAR_DIV__B 0 | 4187 | #define EQ_REG_RC_SEL_CAR_DIV__B 0 |
| 4188 | #define EQ_REG_RC_SEL_CAR_DIV__W 1 | 4188 | #define EQ_REG_RC_SEL_CAR_DIV__W 1 |
| 4189 | #define EQ_REG_RC_SEL_CAR_DIV__M 0x1 | 4189 | #define EQ_REG_RC_SEL_CAR_DIV__M 0x1 |
| 4190 | #define EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 | 4190 | #define EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 |
| 4191 | #define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 | 4191 | #define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 |
| 4192 | 4192 | ||
| 4193 | #define EQ_REG_RC_SEL_CAR_PASS__B 1 | 4193 | #define EQ_REG_RC_SEL_CAR_PASS__B 1 |
| 4194 | #define EQ_REG_RC_SEL_CAR_PASS__W 2 | 4194 | #define EQ_REG_RC_SEL_CAR_PASS__W 2 |
| 4195 | #define EQ_REG_RC_SEL_CAR_PASS__M 0x6 | 4195 | #define EQ_REG_RC_SEL_CAR_PASS__M 0x6 |
| 4196 | #define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 | 4196 | #define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 |
| 4197 | #define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 | 4197 | #define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 |
| 4198 | #define EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 | 4198 | #define EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 |
| 4199 | #define EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 | 4199 | #define EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 |
| 4200 | 4200 | ||
| 4201 | #define EQ_REG_RC_SEL_CAR_LOCAL__B 3 | 4201 | #define EQ_REG_RC_SEL_CAR_LOCAL__B 3 |
| 4202 | #define EQ_REG_RC_SEL_CAR_LOCAL__W 2 | 4202 | #define EQ_REG_RC_SEL_CAR_LOCAL__W 2 |
| 4203 | #define EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 | 4203 | #define EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 |
| 4204 | #define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 | 4204 | #define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 |
| 4205 | #define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 | 4205 | #define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 |
| 4206 | #define EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 | 4206 | #define EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 |
| 4207 | #define EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 | 4207 | #define EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 |
| 4208 | 4208 | ||
| 4209 | #define EQ_REG_RC_SEL_CAR_MEAS__B 5 | 4209 | #define EQ_REG_RC_SEL_CAR_MEAS__B 5 |
| 4210 | #define EQ_REG_RC_SEL_CAR_MEAS__W 1 | 4210 | #define EQ_REG_RC_SEL_CAR_MEAS__W 1 |
| 4211 | #define EQ_REG_RC_SEL_CAR_MEAS__M 0x20 | 4211 | #define EQ_REG_RC_SEL_CAR_MEAS__M 0x20 |
| 4212 | #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 | 4212 | #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 |
| 4213 | #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 | 4213 | #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 |
| 4214 | 4214 | ||
| 4215 | #define EQ_REG_RC_STS__A 0x1C10033 | 4215 | #define EQ_REG_RC_STS__A 0x1C10033 |
| 4216 | #define EQ_REG_RC_STS__W 12 | 4216 | #define EQ_REG_RC_STS__W 12 |
| 4217 | #define EQ_REG_RC_STS__M 0xFFF | 4217 | #define EQ_REG_RC_STS__M 0xFFF |
| 4218 | 4218 | ||
| 4219 | #define EQ_REG_RC_STS_DIFF__B 0 | 4219 | #define EQ_REG_RC_STS_DIFF__B 0 |
| 4220 | #define EQ_REG_RC_STS_DIFF__W 9 | 4220 | #define EQ_REG_RC_STS_DIFF__W 9 |
| 4221 | #define EQ_REG_RC_STS_DIFF__M 0x1FF | 4221 | #define EQ_REG_RC_STS_DIFF__M 0x1FF |
| 4222 | 4222 | ||
| 4223 | #define EQ_REG_RC_STS_FIRST__B 9 | 4223 | #define EQ_REG_RC_STS_FIRST__B 9 |
| 4224 | #define EQ_REG_RC_STS_FIRST__W 1 | 4224 | #define EQ_REG_RC_STS_FIRST__W 1 |
| 4225 | #define EQ_REG_RC_STS_FIRST__M 0x200 | 4225 | #define EQ_REG_RC_STS_FIRST__M 0x200 |
| 4226 | #define EQ_REG_RC_STS_FIRST_A_CE 0x0 | 4226 | #define EQ_REG_RC_STS_FIRST_A_CE 0x0 |
| 4227 | #define EQ_REG_RC_STS_FIRST_B_DRI 0x200 | 4227 | #define EQ_REG_RC_STS_FIRST_B_DRI 0x200 |
| 4228 | 4228 | ||
| 4229 | #define EQ_REG_RC_STS_SELEC__B 10 | 4229 | #define EQ_REG_RC_STS_SELEC__B 10 |
| 4230 | #define EQ_REG_RC_STS_SELEC__W 1 | 4230 | #define EQ_REG_RC_STS_SELEC__W 1 |
| 4231 | #define EQ_REG_RC_STS_SELEC__M 0x400 | 4231 | #define EQ_REG_RC_STS_SELEC__M 0x400 |
| 4232 | #define EQ_REG_RC_STS_SELEC_A_CE 0x0 | 4232 | #define EQ_REG_RC_STS_SELEC_A_CE 0x0 |
| 4233 | #define EQ_REG_RC_STS_SELEC_B_DRI 0x400 | 4233 | #define EQ_REG_RC_STS_SELEC_B_DRI 0x400 |
| 4234 | 4234 | ||
| 4235 | #define EQ_REG_RC_STS_OVERFLOW__B 11 | 4235 | #define EQ_REG_RC_STS_OVERFLOW__B 11 |
| 4236 | #define EQ_REG_RC_STS_OVERFLOW__W 1 | 4236 | #define EQ_REG_RC_STS_OVERFLOW__W 1 |
| 4237 | #define EQ_REG_RC_STS_OVERFLOW__M 0x800 | 4237 | #define EQ_REG_RC_STS_OVERFLOW__M 0x800 |
| 4238 | #define EQ_REG_RC_STS_OVERFLOW_NO 0x0 | 4238 | #define EQ_REG_RC_STS_OVERFLOW_NO 0x0 |
| 4239 | #define EQ_REG_RC_STS_OVERFLOW_YES 0x800 | 4239 | #define EQ_REG_RC_STS_OVERFLOW_YES 0x800 |
| 4240 | 4240 | ||
| 4241 | #define EQ_REG_OT_CONST__A 0x1C10046 | 4241 | #define EQ_REG_OT_CONST__A 0x1C10046 |
| 4242 | #define EQ_REG_OT_CONST__W 2 | 4242 | #define EQ_REG_OT_CONST__W 2 |
| 4243 | #define EQ_REG_OT_CONST__M 0x3 | 4243 | #define EQ_REG_OT_CONST__M 0x3 |
| 4244 | #define EQ_REG_OT_CONST_INIT 0x0 | 4244 | #define EQ_REG_OT_CONST_INIT 0x0 |
| 4245 | 4245 | ||
| 4246 | #define EQ_REG_OT_ALPHA__A 0x1C10047 | 4246 | #define EQ_REG_OT_ALPHA__A 0x1C10047 |
| 4247 | #define EQ_REG_OT_ALPHA__W 2 | 4247 | #define EQ_REG_OT_ALPHA__W 2 |
| 4248 | #define EQ_REG_OT_ALPHA__M 0x3 | 4248 | #define EQ_REG_OT_ALPHA__M 0x3 |
| 4249 | #define EQ_REG_OT_ALPHA_INIT 0x0 | 4249 | #define EQ_REG_OT_ALPHA_INIT 0x0 |
| 4250 | 4250 | ||
| 4251 | #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 | 4251 | #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 |
| 4252 | #define EQ_REG_OT_QNT_THRES0__W 5 | 4252 | #define EQ_REG_OT_QNT_THRES0__W 5 |
| 4253 | #define EQ_REG_OT_QNT_THRES0__M 0x1F | 4253 | #define EQ_REG_OT_QNT_THRES0__M 0x1F |
| 4254 | #define EQ_REG_OT_QNT_THRES0_INIT 0x0 | 4254 | #define EQ_REG_OT_QNT_THRES0_INIT 0x0 |
| 4255 | 4255 | ||
| 4256 | #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 | 4256 | #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 |
| 4257 | #define EQ_REG_OT_QNT_THRES1__W 5 | 4257 | #define EQ_REG_OT_QNT_THRES1__W 5 |
| 4258 | #define EQ_REG_OT_QNT_THRES1__M 0x1F | 4258 | #define EQ_REG_OT_QNT_THRES1__M 0x1F |
| 4259 | #define EQ_REG_OT_QNT_THRES1_INIT 0x0 | 4259 | #define EQ_REG_OT_QNT_THRES1_INIT 0x0 |
| 4260 | 4260 | ||
| 4261 | #define EQ_REG_OT_CSI_STEP__A 0x1C1004A | 4261 | #define EQ_REG_OT_CSI_STEP__A 0x1C1004A |
| 4262 | #define EQ_REG_OT_CSI_STEP__W 4 | 4262 | #define EQ_REG_OT_CSI_STEP__W 4 |
| 4263 | #define EQ_REG_OT_CSI_STEP__M 0xF | 4263 | #define EQ_REG_OT_CSI_STEP__M 0xF |
| 4264 | #define EQ_REG_OT_CSI_STEP_INIT 0x0 | 4264 | #define EQ_REG_OT_CSI_STEP_INIT 0x0 |
| 4265 | 4265 | ||
| 4266 | #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B | 4266 | #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B |
| 4267 | #define EQ_REG_OT_CSI_OFFSET__W 7 | 4267 | #define EQ_REG_OT_CSI_OFFSET__W 7 |
| 4268 | #define EQ_REG_OT_CSI_OFFSET__M 0x7F | 4268 | #define EQ_REG_OT_CSI_OFFSET__M 0x7F |
| 4269 | #define EQ_REG_OT_CSI_OFFSET_INIT 0x0 | 4269 | #define EQ_REG_OT_CSI_OFFSET_INIT 0x0 |
| 4270 | 4270 | ||
| 4271 | #define EQ_REG_TD_TPS_INIT__A 0x1C10050 | 4271 | #define EQ_REG_TD_TPS_INIT__A 0x1C10050 |
| 4272 | #define EQ_REG_TD_TPS_INIT__W 1 | 4272 | #define EQ_REG_TD_TPS_INIT__W 1 |
| 4273 | #define EQ_REG_TD_TPS_INIT__M 0x1 | 4273 | #define EQ_REG_TD_TPS_INIT__M 0x1 |
| 4274 | #define EQ_REG_TD_TPS_INIT_INIT 0x0 | 4274 | #define EQ_REG_TD_TPS_INIT_INIT 0x0 |
| 4275 | #define EQ_REG_TD_TPS_INIT_POS 0x0 | 4275 | #define EQ_REG_TD_TPS_INIT_POS 0x0 |
| 4276 | #define EQ_REG_TD_TPS_INIT_NEG 0x1 | 4276 | #define EQ_REG_TD_TPS_INIT_NEG 0x1 |
| 4277 | 4277 | ||
| 4278 | #define EQ_REG_TD_TPS_SYNC__A 0x1C10051 | 4278 | #define EQ_REG_TD_TPS_SYNC__A 0x1C10051 |
| 4279 | #define EQ_REG_TD_TPS_SYNC__W 16 | 4279 | #define EQ_REG_TD_TPS_SYNC__W 16 |
| 4280 | #define EQ_REG_TD_TPS_SYNC__M 0xFFFF | 4280 | #define EQ_REG_TD_TPS_SYNC__M 0xFFFF |
| 4281 | #define EQ_REG_TD_TPS_SYNC_INIT 0x0 | 4281 | #define EQ_REG_TD_TPS_SYNC_INIT 0x0 |
| 4282 | #define EQ_REG_TD_TPS_SYNC_ODD 0x35EE | 4282 | #define EQ_REG_TD_TPS_SYNC_ODD 0x35EE |
| 4283 | #define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 | 4283 | #define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 |
| 4284 | 4284 | ||
| 4285 | #define EQ_REG_TD_TPS_LEN__A 0x1C10052 | 4285 | #define EQ_REG_TD_TPS_LEN__A 0x1C10052 |
| 4286 | #define EQ_REG_TD_TPS_LEN__W 6 | 4286 | #define EQ_REG_TD_TPS_LEN__W 6 |
| 4287 | #define EQ_REG_TD_TPS_LEN__M 0x3F | 4287 | #define EQ_REG_TD_TPS_LEN__M 0x3F |
| 4288 | #define EQ_REG_TD_TPS_LEN_INIT 0x0 | 4288 | #define EQ_REG_TD_TPS_LEN_INIT 0x0 |
| 4289 | #define EQ_REG_TD_TPS_LEN_DEF 0x17 | 4289 | #define EQ_REG_TD_TPS_LEN_DEF 0x17 |
| 4290 | #define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F | 4290 | #define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F |
| 4291 | 4291 | ||
| 4292 | #define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 | 4292 | #define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 |
| 4293 | #define EQ_REG_TD_TPS_FRM_NMB__W 2 | 4293 | #define EQ_REG_TD_TPS_FRM_NMB__W 2 |
| 4294 | #define EQ_REG_TD_TPS_FRM_NMB__M 0x3 | 4294 | #define EQ_REG_TD_TPS_FRM_NMB__M 0x3 |
| 4295 | #define EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 | 4295 | #define EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 |
| 4296 | #define EQ_REG_TD_TPS_FRM_NMB_1 0x0 | 4296 | #define EQ_REG_TD_TPS_FRM_NMB_1 0x0 |
| 4297 | #define EQ_REG_TD_TPS_FRM_NMB_2 0x1 | 4297 | #define EQ_REG_TD_TPS_FRM_NMB_2 0x1 |
| 4298 | #define EQ_REG_TD_TPS_FRM_NMB_3 0x2 | 4298 | #define EQ_REG_TD_TPS_FRM_NMB_3 0x2 |
| 4299 | #define EQ_REG_TD_TPS_FRM_NMB_4 0x3 | 4299 | #define EQ_REG_TD_TPS_FRM_NMB_4 0x3 |
| 4300 | 4300 | ||
| 4301 | #define EQ_REG_TD_TPS_CONST__A 0x1C10054 | 4301 | #define EQ_REG_TD_TPS_CONST__A 0x1C10054 |
| 4302 | #define EQ_REG_TD_TPS_CONST__W 2 | 4302 | #define EQ_REG_TD_TPS_CONST__W 2 |
| 4303 | #define EQ_REG_TD_TPS_CONST__M 0x3 | 4303 | #define EQ_REG_TD_TPS_CONST__M 0x3 |
| 4304 | #define EQ_REG_TD_TPS_CONST_INIT 0x0 | 4304 | #define EQ_REG_TD_TPS_CONST_INIT 0x0 |
| 4305 | #define EQ_REG_TD_TPS_CONST_QPSK 0x0 | 4305 | #define EQ_REG_TD_TPS_CONST_QPSK 0x0 |
| 4306 | #define EQ_REG_TD_TPS_CONST_16QAM 0x1 | 4306 | #define EQ_REG_TD_TPS_CONST_16QAM 0x1 |
| 4307 | #define EQ_REG_TD_TPS_CONST_64QAM 0x2 | 4307 | #define EQ_REG_TD_TPS_CONST_64QAM 0x2 |
| 4308 | 4308 | ||
| 4309 | #define EQ_REG_TD_TPS_HINFO__A 0x1C10055 | 4309 | #define EQ_REG_TD_TPS_HINFO__A 0x1C10055 |
| 4310 | #define EQ_REG_TD_TPS_HINFO__W 3 | 4310 | #define EQ_REG_TD_TPS_HINFO__W 3 |
| 4311 | #define EQ_REG_TD_TPS_HINFO__M 0x7 | 4311 | #define EQ_REG_TD_TPS_HINFO__M 0x7 |
| 4312 | #define EQ_REG_TD_TPS_HINFO_INIT 0x0 | 4312 | #define EQ_REG_TD_TPS_HINFO_INIT 0x0 |
| 4313 | #define EQ_REG_TD_TPS_HINFO_NH 0x0 | 4313 | #define EQ_REG_TD_TPS_HINFO_NH 0x0 |
| 4314 | #define EQ_REG_TD_TPS_HINFO_H1 0x1 | 4314 | #define EQ_REG_TD_TPS_HINFO_H1 0x1 |
| 4315 | #define EQ_REG_TD_TPS_HINFO_H2 0x2 | 4315 | #define EQ_REG_TD_TPS_HINFO_H2 0x2 |
| 4316 | #define EQ_REG_TD_TPS_HINFO_H4 0x3 | 4316 | #define EQ_REG_TD_TPS_HINFO_H4 0x3 |
| 4317 | 4317 | ||
| 4318 | #define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 | 4318 | #define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 |
| 4319 | #define EQ_REG_TD_TPS_CODE_HP__W 3 | 4319 | #define EQ_REG_TD_TPS_CODE_HP__W 3 |
| 4320 | #define EQ_REG_TD_TPS_CODE_HP__M 0x7 | 4320 | #define EQ_REG_TD_TPS_CODE_HP__M 0x7 |
| 4321 | #define EQ_REG_TD_TPS_CODE_HP_INIT 0x0 | 4321 | #define EQ_REG_TD_TPS_CODE_HP_INIT 0x0 |
| 4322 | #define EQ_REG_TD_TPS_CODE_HP_1_2 0x0 | 4322 | #define EQ_REG_TD_TPS_CODE_HP_1_2 0x0 |
| 4323 | #define EQ_REG_TD_TPS_CODE_HP_2_3 0x1 | 4323 | #define EQ_REG_TD_TPS_CODE_HP_2_3 0x1 |
| 4324 | #define EQ_REG_TD_TPS_CODE_HP_3_4 0x2 | 4324 | #define EQ_REG_TD_TPS_CODE_HP_3_4 0x2 |
| 4325 | #define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 | 4325 | #define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 |
| 4326 | #define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 | 4326 | #define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 |
| 4327 | 4327 | ||
| 4328 | #define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 | 4328 | #define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 |
| 4329 | #define EQ_REG_TD_TPS_CODE_LP__W 3 | 4329 | #define EQ_REG_TD_TPS_CODE_LP__W 3 |
| 4330 | #define EQ_REG_TD_TPS_CODE_LP__M 0x7 | 4330 | #define EQ_REG_TD_TPS_CODE_LP__M 0x7 |
| 4331 | #define EQ_REG_TD_TPS_CODE_LP_INIT 0x0 | 4331 | #define EQ_REG_TD_TPS_CODE_LP_INIT 0x0 |
| 4332 | #define EQ_REG_TD_TPS_CODE_LP_1_2 0x0 | 4332 | #define EQ_REG_TD_TPS_CODE_LP_1_2 0x0 |
| 4333 | #define EQ_REG_TD_TPS_CODE_LP_2_3 0x1 | 4333 | #define EQ_REG_TD_TPS_CODE_LP_2_3 0x1 |
| 4334 | #define EQ_REG_TD_TPS_CODE_LP_3_4 0x2 | 4334 | #define EQ_REG_TD_TPS_CODE_LP_3_4 0x2 |
| 4335 | #define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 | 4335 | #define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 |
| 4336 | #define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 | 4336 | #define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 |
| 4337 | 4337 | ||
| 4338 | #define EQ_REG_TD_TPS_GUARD__A 0x1C10058 | 4338 | #define EQ_REG_TD_TPS_GUARD__A 0x1C10058 |
| 4339 | #define EQ_REG_TD_TPS_GUARD__W 2 | 4339 | #define EQ_REG_TD_TPS_GUARD__W 2 |
| 4340 | #define EQ_REG_TD_TPS_GUARD__M 0x3 | 4340 | #define EQ_REG_TD_TPS_GUARD__M 0x3 |
| 4341 | #define EQ_REG_TD_TPS_GUARD_INIT 0x0 | 4341 | #define EQ_REG_TD_TPS_GUARD_INIT 0x0 |
| 4342 | #define EQ_REG_TD_TPS_GUARD_32 0x0 | 4342 | #define EQ_REG_TD_TPS_GUARD_32 0x0 |
| 4343 | #define EQ_REG_TD_TPS_GUARD_16 0x1 | 4343 | #define EQ_REG_TD_TPS_GUARD_16 0x1 |
| 4344 | #define EQ_REG_TD_TPS_GUARD_08 0x2 | 4344 | #define EQ_REG_TD_TPS_GUARD_08 0x2 |
| 4345 | #define EQ_REG_TD_TPS_GUARD_04 0x3 | 4345 | #define EQ_REG_TD_TPS_GUARD_04 0x3 |
| 4346 | 4346 | ||
| 4347 | #define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 | 4347 | #define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 |
| 4348 | #define EQ_REG_TD_TPS_TR_MODE__W 2 | 4348 | #define EQ_REG_TD_TPS_TR_MODE__W 2 |
| 4349 | #define EQ_REG_TD_TPS_TR_MODE__M 0x3 | 4349 | #define EQ_REG_TD_TPS_TR_MODE__M 0x3 |
| 4350 | #define EQ_REG_TD_TPS_TR_MODE_INIT 0x0 | 4350 | #define EQ_REG_TD_TPS_TR_MODE_INIT 0x0 |
| 4351 | #define EQ_REG_TD_TPS_TR_MODE_2K 0x0 | 4351 | #define EQ_REG_TD_TPS_TR_MODE_2K 0x0 |
| 4352 | #define EQ_REG_TD_TPS_TR_MODE_8K 0x1 | 4352 | #define EQ_REG_TD_TPS_TR_MODE_8K 0x1 |
| 4353 | 4353 | ||
| 4354 | #define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A | 4354 | #define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A |
| 4355 | #define EQ_REG_TD_TPS_CELL_ID_HI__W 8 | 4355 | #define EQ_REG_TD_TPS_CELL_ID_HI__W 8 |
| 4356 | #define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF | 4356 | #define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF |
| 4357 | #define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 | 4357 | #define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 |
| 4358 | 4358 | ||
| 4359 | #define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B | 4359 | #define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B |
| 4360 | #define EQ_REG_TD_TPS_CELL_ID_LO__W 8 | 4360 | #define EQ_REG_TD_TPS_CELL_ID_LO__W 8 |
| 4361 | #define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF | 4361 | #define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF |
| 4362 | #define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 | 4362 | #define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 |
| 4363 | 4363 | ||
| 4364 | #define EQ_REG_TD_TPS_RSV__A 0x1C1005C | 4364 | #define EQ_REG_TD_TPS_RSV__A 0x1C1005C |
| 4365 | #define EQ_REG_TD_TPS_RSV__W 6 | 4365 | #define EQ_REG_TD_TPS_RSV__W 6 |
| 4366 | #define EQ_REG_TD_TPS_RSV__M 0x3F | 4366 | #define EQ_REG_TD_TPS_RSV__M 0x3F |
| 4367 | #define EQ_REG_TD_TPS_RSV_INIT 0x0 | 4367 | #define EQ_REG_TD_TPS_RSV_INIT 0x0 |
| 4368 | 4368 | ||
| 4369 | #define EQ_REG_TD_TPS_BCH__A 0x1C1005D | 4369 | #define EQ_REG_TD_TPS_BCH__A 0x1C1005D |
| 4370 | #define EQ_REG_TD_TPS_BCH__W 14 | 4370 | #define EQ_REG_TD_TPS_BCH__W 14 |
| 4371 | #define EQ_REG_TD_TPS_BCH__M 0x3FFF | 4371 | #define EQ_REG_TD_TPS_BCH__M 0x3FFF |
| 4372 | #define EQ_REG_TD_TPS_BCH_INIT 0x0 | 4372 | #define EQ_REG_TD_TPS_BCH_INIT 0x0 |
| 4373 | 4373 | ||
| 4374 | #define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E | 4374 | #define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E |
| 4375 | #define EQ_REG_TD_SQR_ERR_I__W 16 | 4375 | #define EQ_REG_TD_SQR_ERR_I__W 16 |
| 4376 | #define EQ_REG_TD_SQR_ERR_I__M 0xFFFF | 4376 | #define EQ_REG_TD_SQR_ERR_I__M 0xFFFF |
| 4377 | #define EQ_REG_TD_SQR_ERR_I_INIT 0x0 | 4377 | #define EQ_REG_TD_SQR_ERR_I_INIT 0x0 |
| 4378 | 4378 | ||
| 4379 | #define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F | 4379 | #define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F |
| 4380 | #define EQ_REG_TD_SQR_ERR_Q__W 16 | 4380 | #define EQ_REG_TD_SQR_ERR_Q__W 16 |
| 4381 | #define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF | 4381 | #define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF |
| 4382 | #define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 | 4382 | #define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 |
| 4383 | 4383 | ||
| 4384 | #define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 | 4384 | #define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 |
| 4385 | #define EQ_REG_TD_SQR_ERR_EXP__W 4 | 4385 | #define EQ_REG_TD_SQR_ERR_EXP__W 4 |
| 4386 | #define EQ_REG_TD_SQR_ERR_EXP__M 0xF | 4386 | #define EQ_REG_TD_SQR_ERR_EXP__M 0xF |
| 4387 | #define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 | 4387 | #define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 |
| 4388 | 4388 | ||
| 4389 | #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 | 4389 | #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 |
| 4390 | #define EQ_REG_TD_REQ_SMB_CNT__W 16 | 4390 | #define EQ_REG_TD_REQ_SMB_CNT__W 16 |
| 4391 | #define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF | 4391 | #define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF |
| 4392 | #define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 | 4392 | #define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 |
| 4393 | 4393 | ||
| 4394 | #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 | 4394 | #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 |
| 4395 | #define EQ_REG_TD_TPS_PWR_OFS__W 16 | 4395 | #define EQ_REG_TD_TPS_PWR_OFS__W 16 |
| 4396 | #define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF | 4396 | #define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF |
| 4397 | #define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 | 4397 | #define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 |
| 4398 | 4398 | ||
| 4399 | #define EC_COMM_EXEC__A 0x2000000 | 4399 | #define EC_COMM_EXEC__A 0x2000000 |
| 4400 | #define EC_COMM_EXEC__W 3 | 4400 | #define EC_COMM_EXEC__W 3 |
| 4401 | #define EC_COMM_EXEC__M 0x7 | 4401 | #define EC_COMM_EXEC__M 0x7 |
| 4402 | #define EC_COMM_EXEC_CTL__B 0 | 4402 | #define EC_COMM_EXEC_CTL__B 0 |
| 4403 | #define EC_COMM_EXEC_CTL__W 3 | 4403 | #define EC_COMM_EXEC_CTL__W 3 |
| 4404 | #define EC_COMM_EXEC_CTL__M 0x7 | 4404 | #define EC_COMM_EXEC_CTL__M 0x7 |
| 4405 | #define EC_COMM_EXEC_CTL_STOP 0x0 | 4405 | #define EC_COMM_EXEC_CTL_STOP 0x0 |
| 4406 | #define EC_COMM_EXEC_CTL_ACTIVE 0x1 | 4406 | #define EC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 4407 | #define EC_COMM_EXEC_CTL_HOLD 0x2 | 4407 | #define EC_COMM_EXEC_CTL_HOLD 0x2 |
| 4408 | #define EC_COMM_EXEC_CTL_STEP 0x3 | 4408 | #define EC_COMM_EXEC_CTL_STEP 0x3 |
| 4409 | #define EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 4409 | #define EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 4410 | #define EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 4410 | #define EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 4411 | 4411 | ||
| 4412 | #define EC_COMM_STATE__A 0x2000001 | 4412 | #define EC_COMM_STATE__A 0x2000001 |
| 4413 | #define EC_COMM_STATE__W 16 | 4413 | #define EC_COMM_STATE__W 16 |
| 4414 | #define EC_COMM_STATE__M 0xFFFF | 4414 | #define EC_COMM_STATE__M 0xFFFF |
| 4415 | #define EC_COMM_MB__A 0x2000002 | 4415 | #define EC_COMM_MB__A 0x2000002 |
| 4416 | #define EC_COMM_MB__W 16 | 4416 | #define EC_COMM_MB__W 16 |
| 4417 | #define EC_COMM_MB__M 0xFFFF | 4417 | #define EC_COMM_MB__M 0xFFFF |
| 4418 | #define EC_COMM_SERVICE0__A 0x2000003 | 4418 | #define EC_COMM_SERVICE0__A 0x2000003 |
| 4419 | #define EC_COMM_SERVICE0__W 16 | 4419 | #define EC_COMM_SERVICE0__W 16 |
| 4420 | #define EC_COMM_SERVICE0__M 0xFFFF | 4420 | #define EC_COMM_SERVICE0__M 0xFFFF |
| 4421 | #define EC_COMM_SERVICE1__A 0x2000004 | 4421 | #define EC_COMM_SERVICE1__A 0x2000004 |
| 4422 | #define EC_COMM_SERVICE1__W 16 | 4422 | #define EC_COMM_SERVICE1__W 16 |
| 4423 | #define EC_COMM_SERVICE1__M 0xFFFF | 4423 | #define EC_COMM_SERVICE1__M 0xFFFF |
| 4424 | #define EC_COMM_INT_STA__A 0x2000007 | 4424 | #define EC_COMM_INT_STA__A 0x2000007 |
| 4425 | #define EC_COMM_INT_STA__W 16 | 4425 | #define EC_COMM_INT_STA__W 16 |
| 4426 | #define EC_COMM_INT_STA__M 0xFFFF | 4426 | #define EC_COMM_INT_STA__M 0xFFFF |
| 4427 | #define EC_COMM_INT_MSK__A 0x2000008 | 4427 | #define EC_COMM_INT_MSK__A 0x2000008 |
| 4428 | #define EC_COMM_INT_MSK__W 16 | 4428 | #define EC_COMM_INT_MSK__W 16 |
| 4429 | #define EC_COMM_INT_MSK__M 0xFFFF | 4429 | #define EC_COMM_INT_MSK__M 0xFFFF |
| 4430 | 4430 | ||
| 4431 | #define EC_SB_SID 0x16 | 4431 | #define EC_SB_SID 0x16 |
| 4432 | 4432 | ||
| 4433 | #define EC_SB_REG_COMM_EXEC__A 0x2010000 | 4433 | #define EC_SB_REG_COMM_EXEC__A 0x2010000 |
| 4434 | #define EC_SB_REG_COMM_EXEC__W 3 | 4434 | #define EC_SB_REG_COMM_EXEC__W 3 |
| 4435 | #define EC_SB_REG_COMM_EXEC__M 0x7 | 4435 | #define EC_SB_REG_COMM_EXEC__M 0x7 |
| 4436 | #define EC_SB_REG_COMM_EXEC_CTL__B 0 | 4436 | #define EC_SB_REG_COMM_EXEC_CTL__B 0 |
| 4437 | #define EC_SB_REG_COMM_EXEC_CTL__W 3 | 4437 | #define EC_SB_REG_COMM_EXEC_CTL__W 3 |
| 4438 | #define EC_SB_REG_COMM_EXEC_CTL__M 0x7 | 4438 | #define EC_SB_REG_COMM_EXEC_CTL__M 0x7 |
| 4439 | #define EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 | 4439 | #define EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 |
| 4440 | #define EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 4440 | #define EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 4441 | #define EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 | 4441 | #define EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 4442 | 4442 | ||
| 4443 | #define EC_SB_REG_COMM_STATE__A 0x2010001 | 4443 | #define EC_SB_REG_COMM_STATE__A 0x2010001 |
| 4444 | #define EC_SB_REG_COMM_STATE__W 4 | 4444 | #define EC_SB_REG_COMM_STATE__W 4 |
| 4445 | #define EC_SB_REG_COMM_STATE__M 0xF | 4445 | #define EC_SB_REG_COMM_STATE__M 0xF |
| 4446 | #define EC_SB_REG_COMM_MB__A 0x2010002 | 4446 | #define EC_SB_REG_COMM_MB__A 0x2010002 |
| 4447 | #define EC_SB_REG_COMM_MB__W 2 | 4447 | #define EC_SB_REG_COMM_MB__W 2 |
| 4448 | #define EC_SB_REG_COMM_MB__M 0x3 | 4448 | #define EC_SB_REG_COMM_MB__M 0x3 |
| 4449 | #define EC_SB_REG_COMM_MB_CTR__B 0 | 4449 | #define EC_SB_REG_COMM_MB_CTR__B 0 |
| 4450 | #define EC_SB_REG_COMM_MB_CTR__W 1 | 4450 | #define EC_SB_REG_COMM_MB_CTR__W 1 |
| 4451 | #define EC_SB_REG_COMM_MB_CTR__M 0x1 | 4451 | #define EC_SB_REG_COMM_MB_CTR__M 0x1 |
| 4452 | #define EC_SB_REG_COMM_MB_CTR_OFF 0x0 | 4452 | #define EC_SB_REG_COMM_MB_CTR_OFF 0x0 |
| 4453 | #define EC_SB_REG_COMM_MB_CTR_ON 0x1 | 4453 | #define EC_SB_REG_COMM_MB_CTR_ON 0x1 |
| 4454 | #define EC_SB_REG_COMM_MB_OBS__B 1 | 4454 | #define EC_SB_REG_COMM_MB_OBS__B 1 |
| 4455 | #define EC_SB_REG_COMM_MB_OBS__W 1 | 4455 | #define EC_SB_REG_COMM_MB_OBS__W 1 |
| 4456 | #define EC_SB_REG_COMM_MB_OBS__M 0x2 | 4456 | #define EC_SB_REG_COMM_MB_OBS__M 0x2 |
| 4457 | #define EC_SB_REG_COMM_MB_OBS_OFF 0x0 | 4457 | #define EC_SB_REG_COMM_MB_OBS_OFF 0x0 |
| 4458 | #define EC_SB_REG_COMM_MB_OBS_ON 0x2 | 4458 | #define EC_SB_REG_COMM_MB_OBS_ON 0x2 |
| 4459 | 4459 | ||
| 4460 | #define EC_SB_REG_TR_MODE__A 0x2010010 | 4460 | #define EC_SB_REG_TR_MODE__A 0x2010010 |
| 4461 | #define EC_SB_REG_TR_MODE__W 1 | 4461 | #define EC_SB_REG_TR_MODE__W 1 |
| 4462 | #define EC_SB_REG_TR_MODE__M 0x1 | 4462 | #define EC_SB_REG_TR_MODE__M 0x1 |
| 4463 | #define EC_SB_REG_TR_MODE_INIT 0x0 | 4463 | #define EC_SB_REG_TR_MODE_INIT 0x0 |
| 4464 | #define EC_SB_REG_TR_MODE_8K 0x0 | 4464 | #define EC_SB_REG_TR_MODE_8K 0x0 |
| 4465 | #define EC_SB_REG_TR_MODE_2K 0x1 | 4465 | #define EC_SB_REG_TR_MODE_2K 0x1 |
| 4466 | 4466 | ||
| 4467 | #define EC_SB_REG_CONST__A 0x2010011 | 4467 | #define EC_SB_REG_CONST__A 0x2010011 |
| 4468 | #define EC_SB_REG_CONST__W 2 | 4468 | #define EC_SB_REG_CONST__W 2 |
| 4469 | #define EC_SB_REG_CONST__M 0x3 | 4469 | #define EC_SB_REG_CONST__M 0x3 |
| 4470 | #define EC_SB_REG_CONST_INIT 0x2 | 4470 | #define EC_SB_REG_CONST_INIT 0x2 |
| 4471 | #define EC_SB_REG_CONST_QPSK 0x0 | 4471 | #define EC_SB_REG_CONST_QPSK 0x0 |
| 4472 | #define EC_SB_REG_CONST_16QAM 0x1 | 4472 | #define EC_SB_REG_CONST_16QAM 0x1 |
| 4473 | #define EC_SB_REG_CONST_64QAM 0x2 | 4473 | #define EC_SB_REG_CONST_64QAM 0x2 |
| 4474 | 4474 | ||
| 4475 | #define EC_SB_REG_ALPHA__A 0x2010012 | 4475 | #define EC_SB_REG_ALPHA__A 0x2010012 |
| 4476 | #define EC_SB_REG_ALPHA__W 3 | 4476 | #define EC_SB_REG_ALPHA__W 3 |
| 4477 | #define EC_SB_REG_ALPHA__M 0x7 | 4477 | #define EC_SB_REG_ALPHA__M 0x7 |
| 4478 | 4478 | ||
| 4479 | #define EC_SB_REG_ALPHA_INIT 0x0 | 4479 | #define EC_SB_REG_ALPHA_INIT 0x0 |
| 4480 | 4480 | ||
| 4481 | #define EC_SB_REG_ALPHA_NH 0x0 | 4481 | #define EC_SB_REG_ALPHA_NH 0x0 |
| 4482 | 4482 | ||
| 4483 | #define EC_SB_REG_ALPHA_H1 0x1 | 4483 | #define EC_SB_REG_ALPHA_H1 0x1 |
| 4484 | 4484 | ||
| 4485 | #define EC_SB_REG_ALPHA_H2 0x2 | 4485 | #define EC_SB_REG_ALPHA_H2 0x2 |
| 4486 | 4486 | ||
| 4487 | #define EC_SB_REG_ALPHA_H4 0x3 | 4487 | #define EC_SB_REG_ALPHA_H4 0x3 |
| 4488 | 4488 | ||
| 4489 | #define EC_SB_REG_PRIOR__A 0x2010013 | 4489 | #define EC_SB_REG_PRIOR__A 0x2010013 |
| 4490 | #define EC_SB_REG_PRIOR__W 1 | 4490 | #define EC_SB_REG_PRIOR__W 1 |
| 4491 | #define EC_SB_REG_PRIOR__M 0x1 | 4491 | #define EC_SB_REG_PRIOR__M 0x1 |
| 4492 | #define EC_SB_REG_PRIOR_INIT 0x0 | 4492 | #define EC_SB_REG_PRIOR_INIT 0x0 |
| 4493 | #define EC_SB_REG_PRIOR_HI 0x0 | 4493 | #define EC_SB_REG_PRIOR_HI 0x0 |
| 4494 | #define EC_SB_REG_PRIOR_LO 0x1 | 4494 | #define EC_SB_REG_PRIOR_LO 0x1 |
| 4495 | 4495 | ||
| 4496 | #define EC_SB_REG_CSI_HI__A 0x2010014 | 4496 | #define EC_SB_REG_CSI_HI__A 0x2010014 |
| 4497 | #define EC_SB_REG_CSI_HI__W 5 | 4497 | #define EC_SB_REG_CSI_HI__W 5 |
| 4498 | #define EC_SB_REG_CSI_HI__M 0x1F | 4498 | #define EC_SB_REG_CSI_HI__M 0x1F |
| 4499 | #define EC_SB_REG_CSI_HI_INIT 0x1F | 4499 | #define EC_SB_REG_CSI_HI_INIT 0x1F |
| 4500 | #define EC_SB_REG_CSI_HI_MAX 0x1F | 4500 | #define EC_SB_REG_CSI_HI_MAX 0x1F |
| 4501 | #define EC_SB_REG_CSI_HI_MIN 0x0 | 4501 | #define EC_SB_REG_CSI_HI_MIN 0x0 |
| 4502 | #define EC_SB_REG_CSI_HI_TAG 0x0 | 4502 | #define EC_SB_REG_CSI_HI_TAG 0x0 |
| 4503 | 4503 | ||
| 4504 | #define EC_SB_REG_CSI_LO__A 0x2010015 | 4504 | #define EC_SB_REG_CSI_LO__A 0x2010015 |
| 4505 | #define EC_SB_REG_CSI_LO__W 5 | 4505 | #define EC_SB_REG_CSI_LO__W 5 |
| 4506 | #define EC_SB_REG_CSI_LO__M 0x1F | 4506 | #define EC_SB_REG_CSI_LO__M 0x1F |
| 4507 | #define EC_SB_REG_CSI_LO_INIT 0x1F | 4507 | #define EC_SB_REG_CSI_LO_INIT 0x1F |
| 4508 | #define EC_SB_REG_CSI_LO_MAX 0x1F | 4508 | #define EC_SB_REG_CSI_LO_MAX 0x1F |
| 4509 | #define EC_SB_REG_CSI_LO_MIN 0x0 | 4509 | #define EC_SB_REG_CSI_LO_MIN 0x0 |
| 4510 | #define EC_SB_REG_CSI_LO_TAG 0x0 | 4510 | #define EC_SB_REG_CSI_LO_TAG 0x0 |
| 4511 | 4511 | ||
| 4512 | #define EC_SB_REG_SMB_TGL__A 0x2010016 | 4512 | #define EC_SB_REG_SMB_TGL__A 0x2010016 |
| 4513 | #define EC_SB_REG_SMB_TGL__W 1 | 4513 | #define EC_SB_REG_SMB_TGL__W 1 |
| 4514 | #define EC_SB_REG_SMB_TGL__M 0x1 | 4514 | #define EC_SB_REG_SMB_TGL__M 0x1 |
| 4515 | #define EC_SB_REG_SMB_TGL_OFF 0x0 | 4515 | #define EC_SB_REG_SMB_TGL_OFF 0x0 |
| 4516 | #define EC_SB_REG_SMB_TGL_ON 0x1 | 4516 | #define EC_SB_REG_SMB_TGL_ON 0x1 |
| 4517 | 4517 | ||
| 4518 | #define EC_SB_REG_SNR_HI__A 0x2010017 | 4518 | #define EC_SB_REG_SNR_HI__A 0x2010017 |
| 4519 | #define EC_SB_REG_SNR_HI__W 8 | 4519 | #define EC_SB_REG_SNR_HI__W 8 |
| 4520 | #define EC_SB_REG_SNR_HI__M 0xFF | 4520 | #define EC_SB_REG_SNR_HI__M 0xFF |
| 4521 | #define EC_SB_REG_SNR_HI_INIT 0xFF | 4521 | #define EC_SB_REG_SNR_HI_INIT 0xFF |
| 4522 | #define EC_SB_REG_SNR_HI_MAX 0xFF | 4522 | #define EC_SB_REG_SNR_HI_MAX 0xFF |
| 4523 | #define EC_SB_REG_SNR_HI_MIN 0x0 | 4523 | #define EC_SB_REG_SNR_HI_MIN 0x0 |
| 4524 | #define EC_SB_REG_SNR_HI_TAG 0x0 | 4524 | #define EC_SB_REG_SNR_HI_TAG 0x0 |
| 4525 | 4525 | ||
| 4526 | #define EC_SB_REG_SNR_MID__A 0x2010018 | 4526 | #define EC_SB_REG_SNR_MID__A 0x2010018 |
| 4527 | #define EC_SB_REG_SNR_MID__W 8 | 4527 | #define EC_SB_REG_SNR_MID__W 8 |
| 4528 | #define EC_SB_REG_SNR_MID__M 0xFF | 4528 | #define EC_SB_REG_SNR_MID__M 0xFF |
| 4529 | #define EC_SB_REG_SNR_MID_INIT 0xFF | 4529 | #define EC_SB_REG_SNR_MID_INIT 0xFF |
| 4530 | #define EC_SB_REG_SNR_MID_MAX 0xFF | 4530 | #define EC_SB_REG_SNR_MID_MAX 0xFF |
| 4531 | #define EC_SB_REG_SNR_MID_MIN 0x0 | 4531 | #define EC_SB_REG_SNR_MID_MIN 0x0 |
| 4532 | #define EC_SB_REG_SNR_MID_TAG 0x0 | 4532 | #define EC_SB_REG_SNR_MID_TAG 0x0 |
| 4533 | 4533 | ||
| 4534 | #define EC_SB_REG_SNR_LO__A 0x2010019 | 4534 | #define EC_SB_REG_SNR_LO__A 0x2010019 |
| 4535 | #define EC_SB_REG_SNR_LO__W 8 | 4535 | #define EC_SB_REG_SNR_LO__W 8 |
| 4536 | #define EC_SB_REG_SNR_LO__M 0xFF | 4536 | #define EC_SB_REG_SNR_LO__M 0xFF |
| 4537 | #define EC_SB_REG_SNR_LO_INIT 0xFF | 4537 | #define EC_SB_REG_SNR_LO_INIT 0xFF |
| 4538 | #define EC_SB_REG_SNR_LO_MAX 0xFF | 4538 | #define EC_SB_REG_SNR_LO_MAX 0xFF |
| 4539 | #define EC_SB_REG_SNR_LO_MIN 0x0 | 4539 | #define EC_SB_REG_SNR_LO_MIN 0x0 |
| 4540 | #define EC_SB_REG_SNR_LO_TAG 0x0 | 4540 | #define EC_SB_REG_SNR_LO_TAG 0x0 |
| 4541 | 4541 | ||
| 4542 | #define EC_SB_REG_SCALE_MSB__A 0x201001A | 4542 | #define EC_SB_REG_SCALE_MSB__A 0x201001A |
| 4543 | #define EC_SB_REG_SCALE_MSB__W 6 | 4543 | #define EC_SB_REG_SCALE_MSB__W 6 |
| 4544 | #define EC_SB_REG_SCALE_MSB__M 0x3F | 4544 | #define EC_SB_REG_SCALE_MSB__M 0x3F |
| 4545 | #define EC_SB_REG_SCALE_MSB_INIT 0x30 | 4545 | #define EC_SB_REG_SCALE_MSB_INIT 0x30 |
| 4546 | #define EC_SB_REG_SCALE_MSB_MAX 0x3F | 4546 | #define EC_SB_REG_SCALE_MSB_MAX 0x3F |
| 4547 | 4547 | ||
| 4548 | #define EC_SB_REG_SCALE_BIT2__A 0x201001B | 4548 | #define EC_SB_REG_SCALE_BIT2__A 0x201001B |
| 4549 | #define EC_SB_REG_SCALE_BIT2__W 6 | 4549 | #define EC_SB_REG_SCALE_BIT2__W 6 |
| 4550 | #define EC_SB_REG_SCALE_BIT2__M 0x3F | 4550 | #define EC_SB_REG_SCALE_BIT2__M 0x3F |
| 4551 | #define EC_SB_REG_SCALE_BIT2_INIT 0x20 | 4551 | #define EC_SB_REG_SCALE_BIT2_INIT 0x20 |
| 4552 | #define EC_SB_REG_SCALE_BIT2_MAX 0x3F | 4552 | #define EC_SB_REG_SCALE_BIT2_MAX 0x3F |
| 4553 | 4553 | ||
| 4554 | #define EC_SB_REG_SCALE_LSB__A 0x201001C | 4554 | #define EC_SB_REG_SCALE_LSB__A 0x201001C |
| 4555 | #define EC_SB_REG_SCALE_LSB__W 6 | 4555 | #define EC_SB_REG_SCALE_LSB__W 6 |
| 4556 | #define EC_SB_REG_SCALE_LSB__M 0x3F | 4556 | #define EC_SB_REG_SCALE_LSB__M 0x3F |
| 4557 | #define EC_SB_REG_SCALE_LSB_INIT 0x10 | 4557 | #define EC_SB_REG_SCALE_LSB_INIT 0x10 |
| 4558 | #define EC_SB_REG_SCALE_LSB_MAX 0x3F | 4558 | #define EC_SB_REG_SCALE_LSB_MAX 0x3F |
| 4559 | 4559 | ||
| 4560 | #define EC_SB_REG_CSI_OFS__A 0x201001D | 4560 | #define EC_SB_REG_CSI_OFS__A 0x201001D |
| 4561 | #define EC_SB_REG_CSI_OFS__W 4 | 4561 | #define EC_SB_REG_CSI_OFS__W 4 |
| 4562 | #define EC_SB_REG_CSI_OFS__M 0xF | 4562 | #define EC_SB_REG_CSI_OFS__M 0xF |
| 4563 | #define EC_SB_REG_CSI_OFS_INIT 0x1 | 4563 | #define EC_SB_REG_CSI_OFS_INIT 0x1 |
| 4564 | #define EC_SB_REG_CSI_OFS_ADD__B 0 | 4564 | #define EC_SB_REG_CSI_OFS_ADD__B 0 |
| 4565 | #define EC_SB_REG_CSI_OFS_ADD__W 3 | 4565 | #define EC_SB_REG_CSI_OFS_ADD__W 3 |
| 4566 | #define EC_SB_REG_CSI_OFS_ADD__M 0x7 | 4566 | #define EC_SB_REG_CSI_OFS_ADD__M 0x7 |
| 4567 | #define EC_SB_REG_CSI_OFS_DIS__B 3 | 4567 | #define EC_SB_REG_CSI_OFS_DIS__B 3 |
| 4568 | #define EC_SB_REG_CSI_OFS_DIS__W 1 | 4568 | #define EC_SB_REG_CSI_OFS_DIS__W 1 |
| 4569 | #define EC_SB_REG_CSI_OFS_DIS__M 0x8 | 4569 | #define EC_SB_REG_CSI_OFS_DIS__M 0x8 |
| 4570 | #define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 | 4570 | #define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 |
| 4571 | #define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 | 4571 | #define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 |
| 4572 | 4572 | ||
| 4573 | #define EC_SB_SD_RAM__A 0x2020000 | 4573 | #define EC_SB_SD_RAM__A 0x2020000 |
| 4574 | 4574 | ||
| 4575 | #define EC_SB_BD0_RAM__A 0x2030000 | 4575 | #define EC_SB_BD0_RAM__A 0x2030000 |
| 4576 | 4576 | ||
| 4577 | #define EC_SB_BD1_RAM__A 0x2040000 | 4577 | #define EC_SB_BD1_RAM__A 0x2040000 |
| 4578 | 4578 | ||
| 4579 | #define EC_VD_SID 0x17 | 4579 | #define EC_VD_SID 0x17 |
| 4580 | 4580 | ||
| 4581 | #define EC_VD_REG_COMM_EXEC__A 0x2090000 | 4581 | #define EC_VD_REG_COMM_EXEC__A 0x2090000 |
| 4582 | #define EC_VD_REG_COMM_EXEC__W 3 | 4582 | #define EC_VD_REG_COMM_EXEC__W 3 |
| 4583 | #define EC_VD_REG_COMM_EXEC__M 0x7 | 4583 | #define EC_VD_REG_COMM_EXEC__M 0x7 |
| 4584 | #define EC_VD_REG_COMM_EXEC_CTL__B 0 | 4584 | #define EC_VD_REG_COMM_EXEC_CTL__B 0 |
| 4585 | #define EC_VD_REG_COMM_EXEC_CTL__W 3 | 4585 | #define EC_VD_REG_COMM_EXEC_CTL__W 3 |
| 4586 | #define EC_VD_REG_COMM_EXEC_CTL__M 0x7 | 4586 | #define EC_VD_REG_COMM_EXEC_CTL__M 0x7 |
| 4587 | #define EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 | 4587 | #define EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 4588 | #define EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 4588 | #define EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 4589 | #define EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 | 4589 | #define EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 4590 | 4590 | ||
| 4591 | #define EC_VD_REG_COMM_STATE__A 0x2090001 | 4591 | #define EC_VD_REG_COMM_STATE__A 0x2090001 |
| 4592 | #define EC_VD_REG_COMM_STATE__W 4 | 4592 | #define EC_VD_REG_COMM_STATE__W 4 |
| 4593 | #define EC_VD_REG_COMM_STATE__M 0xF | 4593 | #define EC_VD_REG_COMM_STATE__M 0xF |
| 4594 | #define EC_VD_REG_COMM_MB__A 0x2090002 | 4594 | #define EC_VD_REG_COMM_MB__A 0x2090002 |
| 4595 | #define EC_VD_REG_COMM_MB__W 2 | 4595 | #define EC_VD_REG_COMM_MB__W 2 |
| 4596 | #define EC_VD_REG_COMM_MB__M 0x3 | 4596 | #define EC_VD_REG_COMM_MB__M 0x3 |
| 4597 | #define EC_VD_REG_COMM_MB_CTR__B 0 | 4597 | #define EC_VD_REG_COMM_MB_CTR__B 0 |
| 4598 | #define EC_VD_REG_COMM_MB_CTR__W 1 | 4598 | #define EC_VD_REG_COMM_MB_CTR__W 1 |
| 4599 | #define EC_VD_REG_COMM_MB_CTR__M 0x1 | 4599 | #define EC_VD_REG_COMM_MB_CTR__M 0x1 |
| 4600 | #define EC_VD_REG_COMM_MB_CTR_OFF 0x0 | 4600 | #define EC_VD_REG_COMM_MB_CTR_OFF 0x0 |
| 4601 | #define EC_VD_REG_COMM_MB_CTR_ON 0x1 | 4601 | #define EC_VD_REG_COMM_MB_CTR_ON 0x1 |
| 4602 | #define EC_VD_REG_COMM_MB_OBS__B 1 | 4602 | #define EC_VD_REG_COMM_MB_OBS__B 1 |
| 4603 | #define EC_VD_REG_COMM_MB_OBS__W 1 | 4603 | #define EC_VD_REG_COMM_MB_OBS__W 1 |
| 4604 | #define EC_VD_REG_COMM_MB_OBS__M 0x2 | 4604 | #define EC_VD_REG_COMM_MB_OBS__M 0x2 |
| 4605 | #define EC_VD_REG_COMM_MB_OBS_OFF 0x0 | 4605 | #define EC_VD_REG_COMM_MB_OBS_OFF 0x0 |
| 4606 | #define EC_VD_REG_COMM_MB_OBS_ON 0x2 | 4606 | #define EC_VD_REG_COMM_MB_OBS_ON 0x2 |
| 4607 | 4607 | ||
| 4608 | #define EC_VD_REG_COMM_SERVICE0__A 0x2090003 | 4608 | #define EC_VD_REG_COMM_SERVICE0__A 0x2090003 |
| 4609 | #define EC_VD_REG_COMM_SERVICE0__W 16 | 4609 | #define EC_VD_REG_COMM_SERVICE0__W 16 |
| 4610 | #define EC_VD_REG_COMM_SERVICE0__M 0xFFFF | 4610 | #define EC_VD_REG_COMM_SERVICE0__M 0xFFFF |
| 4611 | #define EC_VD_REG_COMM_SERVICE1__A 0x2090004 | 4611 | #define EC_VD_REG_COMM_SERVICE1__A 0x2090004 |
| 4612 | #define EC_VD_REG_COMM_SERVICE1__W 16 | 4612 | #define EC_VD_REG_COMM_SERVICE1__W 16 |
| 4613 | #define EC_VD_REG_COMM_SERVICE1__M 0xFFFF | 4613 | #define EC_VD_REG_COMM_SERVICE1__M 0xFFFF |
| 4614 | #define EC_VD_REG_COMM_INT_STA__A 0x2090007 | 4614 | #define EC_VD_REG_COMM_INT_STA__A 0x2090007 |
| 4615 | #define EC_VD_REG_COMM_INT_STA__W 1 | 4615 | #define EC_VD_REG_COMM_INT_STA__W 1 |
| 4616 | #define EC_VD_REG_COMM_INT_STA__M 0x1 | 4616 | #define EC_VD_REG_COMM_INT_STA__M 0x1 |
| 4617 | #define EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 | 4617 | #define EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 |
| 4618 | #define EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 | 4618 | #define EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 |
| 4619 | #define EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 | 4619 | #define EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 |
| 4620 | 4620 | ||
| 4621 | #define EC_VD_REG_COMM_INT_MSK__A 0x2090008 | 4621 | #define EC_VD_REG_COMM_INT_MSK__A 0x2090008 |
| 4622 | #define EC_VD_REG_COMM_INT_MSK__W 1 | 4622 | #define EC_VD_REG_COMM_INT_MSK__W 1 |
| 4623 | #define EC_VD_REG_COMM_INT_MSK__M 0x1 | 4623 | #define EC_VD_REG_COMM_INT_MSK__M 0x1 |
| 4624 | #define EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 | 4624 | #define EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 |
| 4625 | #define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 | 4625 | #define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 |
| 4626 | #define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 | 4626 | #define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 |
| 4627 | 4627 | ||
| 4628 | #define EC_VD_REG_FORCE__A 0x2090010 | 4628 | #define EC_VD_REG_FORCE__A 0x2090010 |
| 4629 | #define EC_VD_REG_FORCE__W 2 | 4629 | #define EC_VD_REG_FORCE__W 2 |
| 4630 | #define EC_VD_REG_FORCE__M 0x3 | 4630 | #define EC_VD_REG_FORCE__M 0x3 |
| 4631 | #define EC_VD_REG_FORCE_INIT 0x0 | 4631 | #define EC_VD_REG_FORCE_INIT 0x0 |
| 4632 | #define EC_VD_REG_FORCE_FREE 0x0 | 4632 | #define EC_VD_REG_FORCE_FREE 0x0 |
| 4633 | #define EC_VD_REG_FORCE_PROP 0x1 | 4633 | #define EC_VD_REG_FORCE_PROP 0x1 |
| 4634 | #define EC_VD_REG_FORCE_FORCED 0x2 | 4634 | #define EC_VD_REG_FORCE_FORCED 0x2 |
| 4635 | #define EC_VD_REG_FORCE_FIXED 0x3 | 4635 | #define EC_VD_REG_FORCE_FIXED 0x3 |
| 4636 | 4636 | ||
| 4637 | #define EC_VD_REG_SET_CODERATE__A 0x2090011 | 4637 | #define EC_VD_REG_SET_CODERATE__A 0x2090011 |
| 4638 | #define EC_VD_REG_SET_CODERATE__W 3 | 4638 | #define EC_VD_REG_SET_CODERATE__W 3 |
| 4639 | #define EC_VD_REG_SET_CODERATE__M 0x7 | 4639 | #define EC_VD_REG_SET_CODERATE__M 0x7 |
| 4640 | #define EC_VD_REG_SET_CODERATE_INIT 0x0 | 4640 | #define EC_VD_REG_SET_CODERATE_INIT 0x0 |
| 4641 | #define EC_VD_REG_SET_CODERATE_C1_2 0x0 | 4641 | #define EC_VD_REG_SET_CODERATE_C1_2 0x0 |
| 4642 | #define EC_VD_REG_SET_CODERATE_C2_3 0x1 | 4642 | #define EC_VD_REG_SET_CODERATE_C2_3 0x1 |
| 4643 | #define EC_VD_REG_SET_CODERATE_C3_4 0x2 | 4643 | #define EC_VD_REG_SET_CODERATE_C3_4 0x2 |
| 4644 | #define EC_VD_REG_SET_CODERATE_C5_6 0x3 | 4644 | #define EC_VD_REG_SET_CODERATE_C5_6 0x3 |
| 4645 | #define EC_VD_REG_SET_CODERATE_C7_8 0x4 | 4645 | #define EC_VD_REG_SET_CODERATE_C7_8 0x4 |
| 4646 | 4646 | ||
| 4647 | #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 | 4647 | #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 |
| 4648 | #define EC_VD_REG_REQ_SMB_CNT__W 16 | 4648 | #define EC_VD_REG_REQ_SMB_CNT__W 16 |
| 4649 | #define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF | 4649 | #define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF |
| 4650 | #define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 | 4650 | #define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 |
| 4651 | 4651 | ||
| 4652 | #define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 | 4652 | #define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 |
| 4653 | #define EC_VD_REG_REQ_BIT_CNT__W 16 | 4653 | #define EC_VD_REG_REQ_BIT_CNT__W 16 |
| 4654 | #define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF | 4654 | #define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF |
| 4655 | #define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF | 4655 | #define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF |
| 4656 | 4656 | ||
| 4657 | #define EC_VD_REG_RLK_ENA__A 0x2090014 | 4657 | #define EC_VD_REG_RLK_ENA__A 0x2090014 |
| 4658 | #define EC_VD_REG_RLK_ENA__W 1 | 4658 | #define EC_VD_REG_RLK_ENA__W 1 |
| 4659 | #define EC_VD_REG_RLK_ENA__M 0x1 | 4659 | #define EC_VD_REG_RLK_ENA__M 0x1 |
| 4660 | #define EC_VD_REG_RLK_ENA_INIT 0x0 | 4660 | #define EC_VD_REG_RLK_ENA_INIT 0x0 |
| 4661 | #define EC_VD_REG_RLK_ENA_OFF 0x0 | 4661 | #define EC_VD_REG_RLK_ENA_OFF 0x0 |
| 4662 | #define EC_VD_REG_RLK_ENA_ON 0x1 | 4662 | #define EC_VD_REG_RLK_ENA_ON 0x1 |
| 4663 | 4663 | ||
| 4664 | #define EC_VD_REG_VAL__A 0x2090015 | 4664 | #define EC_VD_REG_VAL__A 0x2090015 |
| 4665 | #define EC_VD_REG_VAL__W 2 | 4665 | #define EC_VD_REG_VAL__W 2 |
| 4666 | #define EC_VD_REG_VAL__M 0x3 | 4666 | #define EC_VD_REG_VAL__M 0x3 |
| 4667 | #define EC_VD_REG_VAL_INIT 0x0 | 4667 | #define EC_VD_REG_VAL_INIT 0x0 |
| 4668 | #define EC_VD_REG_VAL_CODE 0x1 | 4668 | #define EC_VD_REG_VAL_CODE 0x1 |
| 4669 | #define EC_VD_REG_VAL_CNT 0x2 | 4669 | #define EC_VD_REG_VAL_CNT 0x2 |
| 4670 | 4670 | ||
| 4671 | #define EC_VD_REG_GET_CODERATE__A 0x2090016 | 4671 | #define EC_VD_REG_GET_CODERATE__A 0x2090016 |
| 4672 | #define EC_VD_REG_GET_CODERATE__W 3 | 4672 | #define EC_VD_REG_GET_CODERATE__W 3 |
| 4673 | #define EC_VD_REG_GET_CODERATE__M 0x7 | 4673 | #define EC_VD_REG_GET_CODERATE__M 0x7 |
| 4674 | #define EC_VD_REG_GET_CODERATE_INIT 0x0 | 4674 | #define EC_VD_REG_GET_CODERATE_INIT 0x0 |
| 4675 | #define EC_VD_REG_GET_CODERATE_C1_2 0x0 | 4675 | #define EC_VD_REG_GET_CODERATE_C1_2 0x0 |
| 4676 | #define EC_VD_REG_GET_CODERATE_C2_3 0x1 | 4676 | #define EC_VD_REG_GET_CODERATE_C2_3 0x1 |
| 4677 | #define EC_VD_REG_GET_CODERATE_C3_4 0x2 | 4677 | #define EC_VD_REG_GET_CODERATE_C3_4 0x2 |
| 4678 | #define EC_VD_REG_GET_CODERATE_C5_6 0x3 | 4678 | #define EC_VD_REG_GET_CODERATE_C5_6 0x3 |
| 4679 | #define EC_VD_REG_GET_CODERATE_C7_8 0x4 | 4679 | #define EC_VD_REG_GET_CODERATE_C7_8 0x4 |
| 4680 | 4680 | ||
| 4681 | #define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 | 4681 | #define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 |
| 4682 | #define EC_VD_REG_ERR_BIT_CNT__W 16 | 4682 | #define EC_VD_REG_ERR_BIT_CNT__W 16 |
| 4683 | #define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF | 4683 | #define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF |
| 4684 | #define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF | 4684 | #define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF |
| 4685 | 4685 | ||
| 4686 | #define EC_VD_REG_IN_BIT_CNT__A 0x2090018 | 4686 | #define EC_VD_REG_IN_BIT_CNT__A 0x2090018 |
| 4687 | #define EC_VD_REG_IN_BIT_CNT__W 16 | 4687 | #define EC_VD_REG_IN_BIT_CNT__W 16 |
| 4688 | #define EC_VD_REG_IN_BIT_CNT__M 0xFFFF | 4688 | #define EC_VD_REG_IN_BIT_CNT__M 0xFFFF |
| 4689 | #define EC_VD_REG_IN_BIT_CNT_INIT 0x0 | 4689 | #define EC_VD_REG_IN_BIT_CNT_INIT 0x0 |
| 4690 | 4690 | ||
| 4691 | #define EC_VD_REG_STS__A 0x2090019 | 4691 | #define EC_VD_REG_STS__A 0x2090019 |
| 4692 | #define EC_VD_REG_STS__W 1 | 4692 | #define EC_VD_REG_STS__W 1 |
| 4693 | #define EC_VD_REG_STS__M 0x1 | 4693 | #define EC_VD_REG_STS__M 0x1 |
| 4694 | #define EC_VD_REG_STS_INIT 0x0 | 4694 | #define EC_VD_REG_STS_INIT 0x0 |
| 4695 | #define EC_VD_REG_STS_NO_LOCK 0x0 | 4695 | #define EC_VD_REG_STS_NO_LOCK 0x0 |
| 4696 | #define EC_VD_REG_STS_IN_LOCK 0x1 | 4696 | #define EC_VD_REG_STS_IN_LOCK 0x1 |
| 4697 | 4697 | ||
| 4698 | #define EC_VD_REG_RLK_CNT__A 0x209001A | 4698 | #define EC_VD_REG_RLK_CNT__A 0x209001A |
| 4699 | #define EC_VD_REG_RLK_CNT__W 16 | 4699 | #define EC_VD_REG_RLK_CNT__W 16 |
| 4700 | #define EC_VD_REG_RLK_CNT__M 0xFFFF | 4700 | #define EC_VD_REG_RLK_CNT__M 0xFFFF |
| 4701 | #define EC_VD_REG_RLK_CNT_INIT 0x0 | 4701 | #define EC_VD_REG_RLK_CNT_INIT 0x0 |
| 4702 | 4702 | ||
| 4703 | #define EC_VD_TB0_RAM__A 0x20A0000 | 4703 | #define EC_VD_TB0_RAM__A 0x20A0000 |
| 4704 | 4704 | ||
| 4705 | #define EC_VD_TB1_RAM__A 0x20B0000 | 4705 | #define EC_VD_TB1_RAM__A 0x20B0000 |
| 4706 | 4706 | ||
| 4707 | #define EC_VD_TB2_RAM__A 0x20C0000 | 4707 | #define EC_VD_TB2_RAM__A 0x20C0000 |
| 4708 | 4708 | ||
| 4709 | #define EC_VD_TB3_RAM__A 0x20D0000 | 4709 | #define EC_VD_TB3_RAM__A 0x20D0000 |
| 4710 | 4710 | ||
| 4711 | #define EC_VD_RE_RAM__A 0x2100000 | 4711 | #define EC_VD_RE_RAM__A 0x2100000 |
| 4712 | 4712 | ||
| 4713 | #define EC_OD_SID 0x18 | 4713 | #define EC_OD_SID 0x18 |
| 4714 | 4714 | ||
| 4715 | #define EC_OD_REG_COMM_EXEC__A 0x2110000 | 4715 | #define EC_OD_REG_COMM_EXEC__A 0x2110000 |
| 4716 | #define EC_OD_REG_COMM_EXEC__W 3 | 4716 | #define EC_OD_REG_COMM_EXEC__W 3 |
| 4717 | #define EC_OD_REG_COMM_EXEC__M 0x7 | 4717 | #define EC_OD_REG_COMM_EXEC__M 0x7 |
| 4718 | #define EC_OD_REG_COMM_EXEC_CTL__B 0 | 4718 | #define EC_OD_REG_COMM_EXEC_CTL__B 0 |
| 4719 | #define EC_OD_REG_COMM_EXEC_CTL__W 3 | 4719 | #define EC_OD_REG_COMM_EXEC_CTL__W 3 |
| 4720 | #define EC_OD_REG_COMM_EXEC_CTL__M 0x7 | 4720 | #define EC_OD_REG_COMM_EXEC_CTL__M 0x7 |
| 4721 | #define EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 | 4721 | #define EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 4722 | #define EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 4722 | #define EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 4723 | #define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 | 4723 | #define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 4724 | #define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 | 4724 | #define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 |
| 4725 | 4725 | ||
| 4726 | #define EC_OD_REG_COMM_MB__A 0x2110002 | 4726 | #define EC_OD_REG_COMM_MB__A 0x2110002 |
| 4727 | #define EC_OD_REG_COMM_MB__W 3 | 4727 | #define EC_OD_REG_COMM_MB__W 3 |
| 4728 | #define EC_OD_REG_COMM_MB__M 0x7 | 4728 | #define EC_OD_REG_COMM_MB__M 0x7 |
| 4729 | #define EC_OD_REG_COMM_MB_CTR__B 0 | 4729 | #define EC_OD_REG_COMM_MB_CTR__B 0 |
| 4730 | #define EC_OD_REG_COMM_MB_CTR__W 1 | 4730 | #define EC_OD_REG_COMM_MB_CTR__W 1 |
| 4731 | #define EC_OD_REG_COMM_MB_CTR__M 0x1 | 4731 | #define EC_OD_REG_COMM_MB_CTR__M 0x1 |
| 4732 | #define EC_OD_REG_COMM_MB_CTR_OFF 0x0 | 4732 | #define EC_OD_REG_COMM_MB_CTR_OFF 0x0 |
| 4733 | #define EC_OD_REG_COMM_MB_CTR_ON 0x1 | 4733 | #define EC_OD_REG_COMM_MB_CTR_ON 0x1 |
| 4734 | #define EC_OD_REG_COMM_MB_OBS__B 1 | 4734 | #define EC_OD_REG_COMM_MB_OBS__B 1 |
| 4735 | #define EC_OD_REG_COMM_MB_OBS__W 1 | 4735 | #define EC_OD_REG_COMM_MB_OBS__W 1 |
| 4736 | #define EC_OD_REG_COMM_MB_OBS__M 0x2 | 4736 | #define EC_OD_REG_COMM_MB_OBS__M 0x2 |
| 4737 | #define EC_OD_REG_COMM_MB_OBS_OFF 0x0 | 4737 | #define EC_OD_REG_COMM_MB_OBS_OFF 0x0 |
| 4738 | #define EC_OD_REG_COMM_MB_OBS_ON 0x2 | 4738 | #define EC_OD_REG_COMM_MB_OBS_ON 0x2 |
| 4739 | 4739 | ||
| 4740 | #define EC_OD_REG_COMM_SERVICE0__A 0x2110003 | 4740 | #define EC_OD_REG_COMM_SERVICE0__A 0x2110003 |
| 4741 | #define EC_OD_REG_COMM_SERVICE0__W 10 | 4741 | #define EC_OD_REG_COMM_SERVICE0__W 10 |
| 4742 | #define EC_OD_REG_COMM_SERVICE0__M 0x3FF | 4742 | #define EC_OD_REG_COMM_SERVICE0__M 0x3FF |
| 4743 | #define EC_OD_REG_COMM_SERVICE1__A 0x2110004 | 4743 | #define EC_OD_REG_COMM_SERVICE1__A 0x2110004 |
| 4744 | #define EC_OD_REG_COMM_SERVICE1__W 11 | 4744 | #define EC_OD_REG_COMM_SERVICE1__W 11 |
| 4745 | #define EC_OD_REG_COMM_SERVICE1__M 0x7FF | 4745 | #define EC_OD_REG_COMM_SERVICE1__M 0x7FF |
| 4746 | 4746 | ||
| 4747 | #define EC_OD_REG_COMM_ACTIVATE__A 0x2110005 | 4747 | #define EC_OD_REG_COMM_ACTIVATE__A 0x2110005 |
| 4748 | #define EC_OD_REG_COMM_ACTIVATE__W 2 | 4748 | #define EC_OD_REG_COMM_ACTIVATE__W 2 |
| 4749 | #define EC_OD_REG_COMM_ACTIVATE__M 0x3 | 4749 | #define EC_OD_REG_COMM_ACTIVATE__M 0x3 |
| 4750 | 4750 | ||
| 4751 | #define EC_OD_REG_COMM_COUNT__A 0x2110006 | 4751 | #define EC_OD_REG_COMM_COUNT__A 0x2110006 |
| 4752 | #define EC_OD_REG_COMM_COUNT__W 16 | 4752 | #define EC_OD_REG_COMM_COUNT__W 16 |
| 4753 | #define EC_OD_REG_COMM_COUNT__M 0xFFFF | 4753 | #define EC_OD_REG_COMM_COUNT__M 0xFFFF |
| 4754 | 4754 | ||
| 4755 | #define EC_OD_REG_COMM_INT_STA__A 0x2110007 | 4755 | #define EC_OD_REG_COMM_INT_STA__A 0x2110007 |
| 4756 | #define EC_OD_REG_COMM_INT_STA__W 2 | 4756 | #define EC_OD_REG_COMM_INT_STA__W 2 |
| 4757 | #define EC_OD_REG_COMM_INT_STA__M 0x3 | 4757 | #define EC_OD_REG_COMM_INT_STA__M 0x3 |
| 4758 | #define EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 | 4758 | #define EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 |
| 4759 | #define EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 | 4759 | #define EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 |
| 4760 | #define EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 | 4760 | #define EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 |
| 4761 | #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 | 4761 | #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 |
| 4762 | #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 | 4762 | #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 |
| 4763 | #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 | 4763 | #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 |
| 4764 | 4764 | ||
| 4765 | #define EC_OD_REG_COMM_INT_MSK__A 0x2110008 | 4765 | #define EC_OD_REG_COMM_INT_MSK__A 0x2110008 |
| 4766 | #define EC_OD_REG_COMM_INT_MSK__W 2 | 4766 | #define EC_OD_REG_COMM_INT_MSK__W 2 |
| 4767 | #define EC_OD_REG_COMM_INT_MSK__M 0x3 | 4767 | #define EC_OD_REG_COMM_INT_MSK__M 0x3 |
| 4768 | #define EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 | 4768 | #define EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 |
| 4769 | #define EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 | 4769 | #define EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 |
| 4770 | #define EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 | 4770 | #define EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 |
| 4771 | #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 | 4771 | #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 |
| 4772 | #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 | 4772 | #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 |
| 4773 | #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 | 4773 | #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 |
| 4774 | 4774 | ||
| 4775 | #define EC_OD_REG_SYNC__A 0x2110010 | 4775 | #define EC_OD_REG_SYNC__A 0x2110010 |
| 4776 | #define EC_OD_REG_SYNC__W 12 | 4776 | #define EC_OD_REG_SYNC__W 12 |
| 4777 | #define EC_OD_REG_SYNC__M 0xFFF | 4777 | #define EC_OD_REG_SYNC__M 0xFFF |
| 4778 | #define EC_OD_REG_SYNC_NR_SYNC__B 0 | 4778 | #define EC_OD_REG_SYNC_NR_SYNC__B 0 |
| 4779 | #define EC_OD_REG_SYNC_NR_SYNC__W 5 | 4779 | #define EC_OD_REG_SYNC_NR_SYNC__W 5 |
| 4780 | #define EC_OD_REG_SYNC_NR_SYNC__M 0x1F | 4780 | #define EC_OD_REG_SYNC_NR_SYNC__M 0x1F |
| 4781 | #define EC_OD_REG_SYNC_IN_SYNC__B 5 | 4781 | #define EC_OD_REG_SYNC_IN_SYNC__B 5 |
| 4782 | #define EC_OD_REG_SYNC_IN_SYNC__W 4 | 4782 | #define EC_OD_REG_SYNC_IN_SYNC__W 4 |
| 4783 | #define EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 | 4783 | #define EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 |
| 4784 | #define EC_OD_REG_SYNC_OUT_SYNC__B 9 | 4784 | #define EC_OD_REG_SYNC_OUT_SYNC__B 9 |
| 4785 | #define EC_OD_REG_SYNC_OUT_SYNC__W 3 | 4785 | #define EC_OD_REG_SYNC_OUT_SYNC__W 3 |
| 4786 | #define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 | 4786 | #define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 |
| 4787 | 4787 | ||
| 4788 | #define EC_OD_REG_NOSYNC__A 0x2110011 | 4788 | #define EC_OD_REG_NOSYNC__A 0x2110011 |
| 4789 | #define EC_OD_REG_NOSYNC__W 8 | 4789 | #define EC_OD_REG_NOSYNC__W 8 |
| 4790 | #define EC_OD_REG_NOSYNC__M 0xFF | 4790 | #define EC_OD_REG_NOSYNC__M 0xFF |
| 4791 | 4791 | ||
| 4792 | #define EC_OD_DEINT_RAM__A 0x2120000 | 4792 | #define EC_OD_DEINT_RAM__A 0x2120000 |
| 4793 | 4793 | ||
| 4794 | #define EC_RS_SID 0x19 | 4794 | #define EC_RS_SID 0x19 |
| 4795 | 4795 | ||
| 4796 | #define EC_RS_REG_COMM_EXEC__A 0x2130000 | 4796 | #define EC_RS_REG_COMM_EXEC__A 0x2130000 |
| 4797 | #define EC_RS_REG_COMM_EXEC__W 3 | 4797 | #define EC_RS_REG_COMM_EXEC__W 3 |
| 4798 | #define EC_RS_REG_COMM_EXEC__M 0x7 | 4798 | #define EC_RS_REG_COMM_EXEC__M 0x7 |
| 4799 | #define EC_RS_REG_COMM_EXEC_CTL__B 0 | 4799 | #define EC_RS_REG_COMM_EXEC_CTL__B 0 |
| 4800 | #define EC_RS_REG_COMM_EXEC_CTL__W 3 | 4800 | #define EC_RS_REG_COMM_EXEC_CTL__W 3 |
| 4801 | #define EC_RS_REG_COMM_EXEC_CTL__M 0x7 | 4801 | #define EC_RS_REG_COMM_EXEC_CTL__M 0x7 |
| 4802 | #define EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 | 4802 | #define EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 |
| 4803 | #define EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 4803 | #define EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 4804 | #define EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 | 4804 | #define EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 4805 | 4805 | ||
| 4806 | #define EC_RS_REG_COMM_STATE__A 0x2130001 | 4806 | #define EC_RS_REG_COMM_STATE__A 0x2130001 |
| 4807 | #define EC_RS_REG_COMM_STATE__W 4 | 4807 | #define EC_RS_REG_COMM_STATE__W 4 |
| 4808 | #define EC_RS_REG_COMM_STATE__M 0xF | 4808 | #define EC_RS_REG_COMM_STATE__M 0xF |
| 4809 | #define EC_RS_REG_COMM_MB__A 0x2130002 | 4809 | #define EC_RS_REG_COMM_MB__A 0x2130002 |
| 4810 | #define EC_RS_REG_COMM_MB__W 2 | 4810 | #define EC_RS_REG_COMM_MB__W 2 |
| 4811 | #define EC_RS_REG_COMM_MB__M 0x3 | 4811 | #define EC_RS_REG_COMM_MB__M 0x3 |
| 4812 | #define EC_RS_REG_COMM_MB_CTR__B 0 | 4812 | #define EC_RS_REG_COMM_MB_CTR__B 0 |
| 4813 | #define EC_RS_REG_COMM_MB_CTR__W 1 | 4813 | #define EC_RS_REG_COMM_MB_CTR__W 1 |
| 4814 | #define EC_RS_REG_COMM_MB_CTR__M 0x1 | 4814 | #define EC_RS_REG_COMM_MB_CTR__M 0x1 |
| 4815 | #define EC_RS_REG_COMM_MB_CTR_OFF 0x0 | 4815 | #define EC_RS_REG_COMM_MB_CTR_OFF 0x0 |
| 4816 | #define EC_RS_REG_COMM_MB_CTR_ON 0x1 | 4816 | #define EC_RS_REG_COMM_MB_CTR_ON 0x1 |
| 4817 | #define EC_RS_REG_COMM_MB_OBS__B 1 | 4817 | #define EC_RS_REG_COMM_MB_OBS__B 1 |
| 4818 | #define EC_RS_REG_COMM_MB_OBS__W 1 | 4818 | #define EC_RS_REG_COMM_MB_OBS__W 1 |
| 4819 | #define EC_RS_REG_COMM_MB_OBS__M 0x2 | 4819 | #define EC_RS_REG_COMM_MB_OBS__M 0x2 |
| 4820 | #define EC_RS_REG_COMM_MB_OBS_OFF 0x0 | 4820 | #define EC_RS_REG_COMM_MB_OBS_OFF 0x0 |
| 4821 | #define EC_RS_REG_COMM_MB_OBS_ON 0x2 | 4821 | #define EC_RS_REG_COMM_MB_OBS_ON 0x2 |
| 4822 | 4822 | ||
| 4823 | #define EC_RS_REG_COMM_SERVICE0__A 0x2130003 | 4823 | #define EC_RS_REG_COMM_SERVICE0__A 0x2130003 |
| 4824 | #define EC_RS_REG_COMM_SERVICE0__W 16 | 4824 | #define EC_RS_REG_COMM_SERVICE0__W 16 |
| 4825 | #define EC_RS_REG_COMM_SERVICE0__M 0xFFFF | 4825 | #define EC_RS_REG_COMM_SERVICE0__M 0xFFFF |
| 4826 | #define EC_RS_REG_COMM_SERVICE1__A 0x2130004 | 4826 | #define EC_RS_REG_COMM_SERVICE1__A 0x2130004 |
| 4827 | #define EC_RS_REG_COMM_SERVICE1__W 16 | 4827 | #define EC_RS_REG_COMM_SERVICE1__W 16 |
| 4828 | #define EC_RS_REG_COMM_SERVICE1__M 0xFFFF | 4828 | #define EC_RS_REG_COMM_SERVICE1__M 0xFFFF |
| 4829 | #define EC_RS_REG_COMM_INT_STA__A 0x2130007 | 4829 | #define EC_RS_REG_COMM_INT_STA__A 0x2130007 |
| 4830 | #define EC_RS_REG_COMM_INT_STA__W 1 | 4830 | #define EC_RS_REG_COMM_INT_STA__W 1 |
| 4831 | #define EC_RS_REG_COMM_INT_STA__M 0x1 | 4831 | #define EC_RS_REG_COMM_INT_STA__M 0x1 |
| 4832 | #define EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 | 4832 | #define EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 |
| 4833 | #define EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 | 4833 | #define EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 |
| 4834 | #define EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 | 4834 | #define EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 |
| 4835 | 4835 | ||
| 4836 | #define EC_RS_REG_COMM_INT_MSK__A 0x2130008 | 4836 | #define EC_RS_REG_COMM_INT_MSK__A 0x2130008 |
| 4837 | #define EC_RS_REG_COMM_INT_MSK__W 1 | 4837 | #define EC_RS_REG_COMM_INT_MSK__W 1 |
| 4838 | #define EC_RS_REG_COMM_INT_MSK__M 0x1 | 4838 | #define EC_RS_REG_COMM_INT_MSK__M 0x1 |
| 4839 | #define EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 | 4839 | #define EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 |
| 4840 | #define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 | 4840 | #define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 |
| 4841 | #define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 | 4841 | #define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 |
| 4842 | 4842 | ||
| 4843 | #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 | 4843 | #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 |
| 4844 | #define EC_RS_REG_REQ_PCK_CNT__W 16 | 4844 | #define EC_RS_REG_REQ_PCK_CNT__W 16 |
| 4845 | #define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF | 4845 | #define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF |
| 4846 | #define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF | 4846 | #define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF |
| 4847 | 4847 | ||
| 4848 | #define EC_RS_REG_VAL__A 0x2130011 | 4848 | #define EC_RS_REG_VAL__A 0x2130011 |
| 4849 | #define EC_RS_REG_VAL__W 1 | 4849 | #define EC_RS_REG_VAL__W 1 |
| 4850 | #define EC_RS_REG_VAL__M 0x1 | 4850 | #define EC_RS_REG_VAL__M 0x1 |
| 4851 | #define EC_RS_REG_VAL_INIT 0x0 | 4851 | #define EC_RS_REG_VAL_INIT 0x0 |
| 4852 | #define EC_RS_REG_VAL_PCK 0x1 | 4852 | #define EC_RS_REG_VAL_PCK 0x1 |
| 4853 | 4853 | ||
| 4854 | #define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 | 4854 | #define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 |
| 4855 | #define EC_RS_REG_ERR_PCK_CNT__W 16 | 4855 | #define EC_RS_REG_ERR_PCK_CNT__W 16 |
| 4856 | #define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF | 4856 | #define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF |
| 4857 | #define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF | 4857 | #define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF |
| 4858 | 4858 | ||
| 4859 | #define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 | 4859 | #define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 |
| 4860 | #define EC_RS_REG_ERR_SMB_CNT__W 16 | 4860 | #define EC_RS_REG_ERR_SMB_CNT__W 16 |
| 4861 | #define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF | 4861 | #define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF |
| 4862 | #define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF | 4862 | #define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF |
| 4863 | 4863 | ||
| 4864 | #define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 | 4864 | #define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 |
| 4865 | #define EC_RS_REG_ERR_BIT_CNT__W 16 | 4865 | #define EC_RS_REG_ERR_BIT_CNT__W 16 |
| 4866 | #define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF | 4866 | #define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF |
| 4867 | #define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF | 4867 | #define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF |
| 4868 | 4868 | ||
| 4869 | #define EC_RS_REG_IN_PCK_CNT__A 0x2130015 | 4869 | #define EC_RS_REG_IN_PCK_CNT__A 0x2130015 |
| 4870 | #define EC_RS_REG_IN_PCK_CNT__W 16 | 4870 | #define EC_RS_REG_IN_PCK_CNT__W 16 |
| 4871 | #define EC_RS_REG_IN_PCK_CNT__M 0xFFFF | 4871 | #define EC_RS_REG_IN_PCK_CNT__M 0xFFFF |
| 4872 | #define EC_RS_REG_IN_PCK_CNT_INIT 0x0 | 4872 | #define EC_RS_REG_IN_PCK_CNT_INIT 0x0 |
| 4873 | 4873 | ||
| 4874 | #define EC_RS_EC_RAM__A 0x2140000 | 4874 | #define EC_RS_EC_RAM__A 0x2140000 |
| 4875 | 4875 | ||
| 4876 | #define EC_OC_SID 0x1A | 4876 | #define EC_OC_SID 0x1A |
| 4877 | 4877 | ||
| 4878 | #define EC_OC_REG_COMM_EXEC__A 0x2150000 | 4878 | #define EC_OC_REG_COMM_EXEC__A 0x2150000 |
| 4879 | #define EC_OC_REG_COMM_EXEC__W 3 | 4879 | #define EC_OC_REG_COMM_EXEC__W 3 |
| 4880 | #define EC_OC_REG_COMM_EXEC__M 0x7 | 4880 | #define EC_OC_REG_COMM_EXEC__M 0x7 |
| 4881 | #define EC_OC_REG_COMM_EXEC_CTL__B 0 | 4881 | #define EC_OC_REG_COMM_EXEC_CTL__B 0 |
| 4882 | #define EC_OC_REG_COMM_EXEC_CTL__W 3 | 4882 | #define EC_OC_REG_COMM_EXEC_CTL__W 3 |
| 4883 | #define EC_OC_REG_COMM_EXEC_CTL__M 0x7 | 4883 | #define EC_OC_REG_COMM_EXEC_CTL__M 0x7 |
| 4884 | #define EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 | 4884 | #define EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 |
| 4885 | #define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 4885 | #define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 4886 | #define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 | 4886 | #define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 4887 | #define EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 | 4887 | #define EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 |
| 4888 | 4888 | ||
| 4889 | #define EC_OC_REG_COMM_STATE__A 0x2150001 | 4889 | #define EC_OC_REG_COMM_STATE__A 0x2150001 |
| 4890 | #define EC_OC_REG_COMM_STATE__W 4 | 4890 | #define EC_OC_REG_COMM_STATE__W 4 |
| 4891 | #define EC_OC_REG_COMM_STATE__M 0xF | 4891 | #define EC_OC_REG_COMM_STATE__M 0xF |
| 4892 | 4892 | ||
| 4893 | #define EC_OC_REG_COMM_MB__A 0x2150002 | 4893 | #define EC_OC_REG_COMM_MB__A 0x2150002 |
| 4894 | #define EC_OC_REG_COMM_MB__W 2 | 4894 | #define EC_OC_REG_COMM_MB__W 2 |
| 4895 | #define EC_OC_REG_COMM_MB__M 0x3 | 4895 | #define EC_OC_REG_COMM_MB__M 0x3 |
| 4896 | #define EC_OC_REG_COMM_MB_CTR__B 0 | 4896 | #define EC_OC_REG_COMM_MB_CTR__B 0 |
| 4897 | #define EC_OC_REG_COMM_MB_CTR__W 1 | 4897 | #define EC_OC_REG_COMM_MB_CTR__W 1 |
| 4898 | #define EC_OC_REG_COMM_MB_CTR__M 0x1 | 4898 | #define EC_OC_REG_COMM_MB_CTR__M 0x1 |
| 4899 | #define EC_OC_REG_COMM_MB_CTR_OFF 0x0 | 4899 | #define EC_OC_REG_COMM_MB_CTR_OFF 0x0 |
| 4900 | #define EC_OC_REG_COMM_MB_CTR_ON 0x1 | 4900 | #define EC_OC_REG_COMM_MB_CTR_ON 0x1 |
| 4901 | #define EC_OC_REG_COMM_MB_OBS__B 1 | 4901 | #define EC_OC_REG_COMM_MB_OBS__B 1 |
| 4902 | #define EC_OC_REG_COMM_MB_OBS__W 1 | 4902 | #define EC_OC_REG_COMM_MB_OBS__W 1 |
| 4903 | #define EC_OC_REG_COMM_MB_OBS__M 0x2 | 4903 | #define EC_OC_REG_COMM_MB_OBS__M 0x2 |
| 4904 | #define EC_OC_REG_COMM_MB_OBS_OFF 0x0 | 4904 | #define EC_OC_REG_COMM_MB_OBS_OFF 0x0 |
| 4905 | #define EC_OC_REG_COMM_MB_OBS_ON 0x2 | 4905 | #define EC_OC_REG_COMM_MB_OBS_ON 0x2 |
| 4906 | 4906 | ||
| 4907 | #define EC_OC_REG_COMM_SERVICE0__A 0x2150003 | 4907 | #define EC_OC_REG_COMM_SERVICE0__A 0x2150003 |
| 4908 | #define EC_OC_REG_COMM_SERVICE0__W 10 | 4908 | #define EC_OC_REG_COMM_SERVICE0__W 10 |
| 4909 | #define EC_OC_REG_COMM_SERVICE0__M 0x3FF | 4909 | #define EC_OC_REG_COMM_SERVICE0__M 0x3FF |
| 4910 | 4910 | ||
| 4911 | #define EC_OC_REG_COMM_SERVICE1__A 0x2150004 | 4911 | #define EC_OC_REG_COMM_SERVICE1__A 0x2150004 |
| 4912 | #define EC_OC_REG_COMM_SERVICE1__W 11 | 4912 | #define EC_OC_REG_COMM_SERVICE1__W 11 |
| 4913 | #define EC_OC_REG_COMM_SERVICE1__M 0x7FF | 4913 | #define EC_OC_REG_COMM_SERVICE1__M 0x7FF |
| 4914 | 4914 | ||
| 4915 | #define EC_OC_REG_COMM_INT_STA__A 0x2150007 | 4915 | #define EC_OC_REG_COMM_INT_STA__A 0x2150007 |
| 4916 | #define EC_OC_REG_COMM_INT_STA__W 6 | 4916 | #define EC_OC_REG_COMM_INT_STA__W 6 |
| 4917 | #define EC_OC_REG_COMM_INT_STA__M 0x3F | 4917 | #define EC_OC_REG_COMM_INT_STA__M 0x3F |
| 4918 | #define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 | 4918 | #define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 |
| 4919 | #define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 | 4919 | #define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 |
| 4920 | #define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 | 4920 | #define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 |
| 4921 | #define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 | 4921 | #define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 |
| 4922 | #define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 | 4922 | #define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 |
| 4923 | #define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 | 4923 | #define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 |
| 4924 | #define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 | 4924 | #define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 |
| 4925 | #define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 | 4925 | #define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 |
| 4926 | #define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 | 4926 | #define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 |
| 4927 | #define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 | 4927 | #define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 |
| 4928 | #define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 | 4928 | #define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 |
| 4929 | #define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 | 4929 | #define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 |
| 4930 | #define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 | 4930 | #define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 |
| 4931 | #define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 | 4931 | #define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 |
| 4932 | #define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 | 4932 | #define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 |
| 4933 | #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 | 4933 | #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 |
| 4934 | #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 | 4934 | #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 |
| 4935 | #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 | 4935 | #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 |
| 4936 | 4936 | ||
| 4937 | #define EC_OC_REG_COMM_INT_MSK__A 0x2150008 | 4937 | #define EC_OC_REG_COMM_INT_MSK__A 0x2150008 |
| 4938 | #define EC_OC_REG_COMM_INT_MSK__W 6 | 4938 | #define EC_OC_REG_COMM_INT_MSK__W 6 |
| 4939 | #define EC_OC_REG_COMM_INT_MSK__M 0x3F | 4939 | #define EC_OC_REG_COMM_INT_MSK__M 0x3F |
| 4940 | #define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 | 4940 | #define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 |
| 4941 | #define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 | 4941 | #define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 |
| 4942 | #define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 | 4942 | #define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 |
| 4943 | #define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 | 4943 | #define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 |
| 4944 | #define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 | 4944 | #define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 |
| 4945 | #define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 | 4945 | #define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 |
| 4946 | #define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 | 4946 | #define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 |
| 4947 | #define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 | 4947 | #define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 |
| 4948 | #define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 | 4948 | #define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 |
| 4949 | #define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 | 4949 | #define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 |
| 4950 | #define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 | 4950 | #define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 |
| 4951 | #define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 | 4951 | #define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 |
| 4952 | #define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 | 4952 | #define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 |
| 4953 | #define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 | 4953 | #define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 |
| 4954 | #define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 | 4954 | #define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 |
| 4955 | #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 | 4955 | #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 |
| 4956 | #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 | 4956 | #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 |
| 4957 | #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 | 4957 | #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 |
| 4958 | 4958 | ||
| 4959 | #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 | 4959 | #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 |
| 4960 | #define EC_OC_REG_OC_MODE_LOP__W 16 | 4960 | #define EC_OC_REG_OC_MODE_LOP__W 16 |
| 4961 | #define EC_OC_REG_OC_MODE_LOP__M 0xFFFF | 4961 | #define EC_OC_REG_OC_MODE_LOP__M 0xFFFF |
| 4962 | #define EC_OC_REG_OC_MODE_LOP_INIT 0x0 | 4962 | #define EC_OC_REG_OC_MODE_LOP_INIT 0x0 |
| 4963 | 4963 | ||
| 4964 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 | 4964 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 |
| 4965 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 | 4965 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 |
| 4966 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 | 4966 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 |
| 4967 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 | 4967 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 |
| 4968 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 | 4968 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 |
| 4969 | 4969 | ||
| 4970 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 | 4970 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 |
| 4971 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 | 4971 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 |
| 4972 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 | 4972 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 |
| 4973 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 | 4973 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 |
| 4974 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 | 4974 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 |
| 4975 | 4975 | ||
| 4976 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 | 4976 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 |
| 4977 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 | 4977 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 |
| 4978 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 | 4978 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 |
| 4979 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 | 4979 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 |
| 4980 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 | 4980 | #define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 |
| 4981 | 4981 | ||
| 4982 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 | 4982 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 |
| 4983 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 | 4983 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 |
| 4984 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 | 4984 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 |
| 4985 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 | 4985 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 |
| 4986 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 | 4986 | #define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 |
| 4987 | 4987 | ||
| 4988 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 | 4988 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 |
| 4989 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 | 4989 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 |
| 4990 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 | 4990 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 |
| 4991 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 | 4991 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 |
| 4992 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 | 4992 | #define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 |
| 4993 | 4993 | ||
| 4994 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 | 4994 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 |
| 4995 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 | 4995 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 |
| 4996 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 | 4996 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 |
| 4997 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 | 4997 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 |
| 4998 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 | 4998 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 |
| 4999 | 4999 | ||
| 5000 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 | 5000 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 |
| 5001 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 | 5001 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 |
| 5002 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 | 5002 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 |
| 5003 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 | 5003 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 |
| 5004 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 | 5004 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 |
| 5005 | 5005 | ||
| 5006 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 | 5006 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 |
| 5007 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 | 5007 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 |
| 5008 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 | 5008 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 |
| 5009 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 | 5009 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 |
| 5010 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 | 5010 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 |
| 5011 | 5011 | ||
| 5012 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 | 5012 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 |
| 5013 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 | 5013 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 |
| 5014 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 | 5014 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 |
| 5015 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 | 5015 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 |
| 5016 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 | 5016 | #define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 |
| 5017 | 5017 | ||
| 5018 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 | 5018 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 |
| 5019 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 | 5019 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 |
| 5020 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 | 5020 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 |
| 5021 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 | 5021 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 |
| 5022 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 | 5022 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 |
| 5023 | 5023 | ||
| 5024 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 | 5024 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 |
| 5025 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 | 5025 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 |
| 5026 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 | 5026 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 |
| 5027 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 | 5027 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 |
| 5028 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 | 5028 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 |
| 5029 | 5029 | ||
| 5030 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 | 5030 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 |
| 5031 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 | 5031 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 |
| 5032 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 | 5032 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 |
| 5033 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 | 5033 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 |
| 5034 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 | 5034 | #define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 |
| 5035 | 5035 | ||
| 5036 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 | 5036 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 |
| 5037 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 | 5037 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 |
| 5038 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 | 5038 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 |
| 5039 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 | 5039 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 |
| 5040 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 | 5040 | #define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 |
| 5041 | 5041 | ||
| 5042 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 | 5042 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 |
| 5043 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 | 5043 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 |
| 5044 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 | 5044 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 |
| 5045 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 | 5045 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 |
| 5046 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 | 5046 | #define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 |
| 5047 | 5047 | ||
| 5048 | #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 | 5048 | #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 |
| 5049 | #define EC_OC_REG_OC_MODE_HIP__W 14 | 5049 | #define EC_OC_REG_OC_MODE_HIP__W 14 |
| 5050 | #define EC_OC_REG_OC_MODE_HIP__M 0x3FFF | 5050 | #define EC_OC_REG_OC_MODE_HIP__M 0x3FFF |
| 5051 | #define EC_OC_REG_OC_MODE_HIP_INIT 0x0 | 5051 | #define EC_OC_REG_OC_MODE_HIP_INIT 0x0 |
| 5052 | 5052 | ||
| 5053 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 | 5053 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 |
| 5054 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 | 5054 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 |
| 5055 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 | 5055 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 |
| 5056 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 | 5056 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 |
| 5057 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 | 5057 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 |
| 5058 | 5058 | ||
| 5059 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 | 5059 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 |
| 5060 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 | 5060 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 |
| 5061 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 | 5061 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 |
| 5062 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 | 5062 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 |
| 5063 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 | 5063 | #define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 |
| 5064 | 5064 | ||
| 5065 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 | 5065 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 |
| 5066 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 | 5066 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 |
| 5067 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 | 5067 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 |
| 5068 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 | 5068 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 |
| 5069 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 | 5069 | #define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 |
| 5070 | 5070 | ||
| 5071 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 | 5071 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 |
| 5072 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 | 5072 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 |
| 5073 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 | 5073 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 |
| 5074 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 | 5074 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 |
| 5075 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 | 5075 | #define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 |
| 5076 | 5076 | ||
| 5077 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 | 5077 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 |
| 5078 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 | 5078 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 |
| 5079 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 | 5079 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 |
| 5080 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 | 5080 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 |
| 5081 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 | 5081 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 |
| 5082 | 5082 | ||
| 5083 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 | 5083 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 |
| 5084 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 | 5084 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 |
| 5085 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 | 5085 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 |
| 5086 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 | 5086 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 |
| 5087 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 | 5087 | #define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 |
| 5088 | 5088 | ||
| 5089 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 | 5089 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 |
| 5090 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 | 5090 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 |
| 5091 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 | 5091 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 |
| 5092 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 | 5092 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 |
| 5093 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 | 5093 | #define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 |
| 5094 | 5094 | ||
| 5095 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 | 5095 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 |
| 5096 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 | 5096 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 |
| 5097 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 | 5097 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 |
| 5098 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 | 5098 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 |
| 5099 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 | 5099 | #define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 |
| 5100 | 5100 | ||
| 5101 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 | 5101 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 |
| 5102 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 | 5102 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 |
| 5103 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 | 5103 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 |
| 5104 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 | 5104 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 |
| 5105 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 | 5105 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 |
| 5106 | 5106 | ||
| 5107 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 | 5107 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 |
| 5108 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 | 5108 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 |
| 5109 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 | 5109 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 |
| 5110 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 | 5110 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 |
| 5111 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 | 5111 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 |
| 5112 | 5112 | ||
| 5113 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 | 5113 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 |
| 5114 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 | 5114 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 |
| 5115 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 | 5115 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 |
| 5116 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 | 5116 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 |
| 5117 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 | 5117 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 |
| 5118 | 5118 | ||
| 5119 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 | 5119 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 |
| 5120 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 | 5120 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 |
| 5121 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 | 5121 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 |
| 5122 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 | 5122 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 |
| 5123 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 | 5123 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 |
| 5124 | 5124 | ||
| 5125 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 | 5125 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 |
| 5126 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 | 5126 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 |
| 5127 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 | 5127 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 |
| 5128 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 | 5128 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 |
| 5129 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 | 5129 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 |
| 5130 | 5130 | ||
| 5131 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 | 5131 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 |
| 5132 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 | 5132 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 |
| 5133 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 | 5133 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 |
| 5134 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 | 5134 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 |
| 5135 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 | 5135 | #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 |
| 5136 | 5136 | ||
| 5137 | #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 | 5137 | #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 |
| 5138 | #define EC_OC_REG_OC_MPG_SIO__W 12 | 5138 | #define EC_OC_REG_OC_MPG_SIO__W 12 |
| 5139 | #define EC_OC_REG_OC_MPG_SIO__M 0xFFF | 5139 | #define EC_OC_REG_OC_MPG_SIO__M 0xFFF |
| 5140 | #define EC_OC_REG_OC_MPG_SIO_INIT 0xFFF | 5140 | #define EC_OC_REG_OC_MPG_SIO_INIT 0xFFF |
| 5141 | 5141 | ||
| 5142 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 | 5142 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 |
| 5143 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 | 5143 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 |
| 5144 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 | 5144 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 |
| 5145 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 | 5145 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 |
| 5146 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 | 5146 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 |
| 5147 | 5147 | ||
| 5148 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 | 5148 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 |
| 5149 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 | 5149 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 |
| 5150 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 | 5150 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 |
| 5151 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 | 5151 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 |
| 5152 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 | 5152 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 |
| 5153 | 5153 | ||
| 5154 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 | 5154 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 |
| 5155 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 | 5155 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 |
| 5156 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 | 5156 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 |
| 5157 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 | 5157 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 |
| 5158 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 | 5158 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 |
| 5159 | 5159 | ||
| 5160 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 | 5160 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 |
| 5161 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 | 5161 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 |
| 5162 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 | 5162 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 |
| 5163 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 | 5163 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 |
| 5164 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 | 5164 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 |
| 5165 | 5165 | ||
| 5166 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 | 5166 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 |
| 5167 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 | 5167 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 |
| 5168 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 | 5168 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 |
| 5169 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 | 5169 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 |
| 5170 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 | 5170 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 |
| 5171 | 5171 | ||
| 5172 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 | 5172 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 |
| 5173 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 | 5173 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 |
| 5174 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 | 5174 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 |
| 5175 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 | 5175 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 |
| 5176 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 | 5176 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 |
| 5177 | 5177 | ||
| 5178 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 | 5178 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 |
| 5179 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 | 5179 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 |
| 5180 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 | 5180 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 |
| 5181 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 | 5181 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 |
| 5182 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 | 5182 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 |
| 5183 | 5183 | ||
| 5184 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 | 5184 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 |
| 5185 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 | 5185 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 |
| 5186 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 | 5186 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 |
| 5187 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 | 5187 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 |
| 5188 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 | 5188 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 |
| 5189 | 5189 | ||
| 5190 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 | 5190 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 |
| 5191 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 | 5191 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 |
| 5192 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 | 5192 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 |
| 5193 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 | 5193 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 |
| 5194 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 | 5194 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 |
| 5195 | 5195 | ||
| 5196 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 | 5196 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 |
| 5197 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 | 5197 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 |
| 5198 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 | 5198 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 |
| 5199 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 | 5199 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 |
| 5200 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 | 5200 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 |
| 5201 | 5201 | ||
| 5202 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 | 5202 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 |
| 5203 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 | 5203 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 |
| 5204 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 | 5204 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 |
| 5205 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 | 5205 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 |
| 5206 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 | 5206 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 |
| 5207 | 5207 | ||
| 5208 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 | 5208 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 |
| 5209 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 | 5209 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 |
| 5210 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 | 5210 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 |
| 5211 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 | 5211 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 |
| 5212 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 | 5212 | #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 |
| 5213 | 5213 | ||
| 5214 | #define EC_OC_REG_OC_MON_SIO__A 0x2150013 | 5214 | #define EC_OC_REG_OC_MON_SIO__A 0x2150013 |
| 5215 | #define EC_OC_REG_OC_MON_SIO__W 12 | 5215 | #define EC_OC_REG_OC_MON_SIO__W 12 |
| 5216 | #define EC_OC_REG_OC_MON_SIO__M 0xFFF | 5216 | #define EC_OC_REG_OC_MON_SIO__M 0xFFF |
| 5217 | #define EC_OC_REG_OC_MON_SIO_INIT 0xFFF | 5217 | #define EC_OC_REG_OC_MON_SIO_INIT 0xFFF |
| 5218 | 5218 | ||
| 5219 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0__B 0 | 5219 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0__B 0 |
| 5220 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0__W 1 | 5220 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0__W 1 |
| 5221 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0__M 0x1 | 5221 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0__M 0x1 |
| 5222 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0_OUTPUT 0x0 | 5222 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0_OUTPUT 0x0 |
| 5223 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0_INPUT 0x1 | 5223 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_0_INPUT 0x1 |
| 5224 | 5224 | ||
| 5225 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1__B 1 | 5225 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1__B 1 |
| 5226 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1__W 1 | 5226 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1__W 1 |
| 5227 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1__M 0x2 | 5227 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1__M 0x2 |
| 5228 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1_OUTPUT 0x0 | 5228 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1_OUTPUT 0x0 |
| 5229 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1_INPUT 0x2 | 5229 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_1_INPUT 0x2 |
| 5230 | 5230 | ||
| 5231 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2__B 2 | 5231 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2__B 2 |
| 5232 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2__W 1 | 5232 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2__W 1 |
| 5233 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2__M 0x4 | 5233 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2__M 0x4 |
| 5234 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2_OUTPUT 0x0 | 5234 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2_OUTPUT 0x0 |
| 5235 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2_INPUT 0x4 | 5235 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_2_INPUT 0x4 |
| 5236 | 5236 | ||
| 5237 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3__B 3 | 5237 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3__B 3 |
| 5238 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3__W 1 | 5238 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3__W 1 |
| 5239 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3__M 0x8 | 5239 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3__M 0x8 |
| 5240 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3_OUTPUT 0x0 | 5240 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3_OUTPUT 0x0 |
| 5241 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3_INPUT 0x8 | 5241 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_3_INPUT 0x8 |
| 5242 | 5242 | ||
| 5243 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4__B 4 | 5243 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4__B 4 |
| 5244 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4__W 1 | 5244 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4__W 1 |
| 5245 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4__M 0x10 | 5245 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4__M 0x10 |
| 5246 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4_OUTPUT 0x0 | 5246 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4_OUTPUT 0x0 |
| 5247 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4_INPUT 0x10 | 5247 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_4_INPUT 0x10 |
| 5248 | 5248 | ||
| 5249 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5__B 5 | 5249 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5__B 5 |
| 5250 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5__W 1 | 5250 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5__W 1 |
| 5251 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5__M 0x20 | 5251 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5__M 0x20 |
| 5252 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5_OUTPUT 0x0 | 5252 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5_OUTPUT 0x0 |
| 5253 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5_INPUT 0x20 | 5253 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_5_INPUT 0x20 |
| 5254 | 5254 | ||
| 5255 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6__B 6 | 5255 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6__B 6 |
| 5256 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6__W 1 | 5256 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6__W 1 |
| 5257 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6__M 0x40 | 5257 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6__M 0x40 |
| 5258 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6_OUTPUT 0x0 | 5258 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6_OUTPUT 0x0 |
| 5259 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6_INPUT 0x40 | 5259 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_6_INPUT 0x40 |
| 5260 | 5260 | ||
| 5261 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7__B 7 | 5261 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7__B 7 |
| 5262 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7__W 1 | 5262 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7__W 1 |
| 5263 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7__M 0x80 | 5263 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7__M 0x80 |
| 5264 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7_OUTPUT 0x0 | 5264 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7_OUTPUT 0x0 |
| 5265 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7_INPUT 0x80 | 5265 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_7_INPUT 0x80 |
| 5266 | 5266 | ||
| 5267 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8__B 8 | 5267 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8__B 8 |
| 5268 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8__W 1 | 5268 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8__W 1 |
| 5269 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8__M 0x100 | 5269 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8__M 0x100 |
| 5270 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8_OUTPUT 0x0 | 5270 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8_OUTPUT 0x0 |
| 5271 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8_INPUT 0x100 | 5271 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_8_INPUT 0x100 |
| 5272 | 5272 | ||
| 5273 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9__B 9 | 5273 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9__B 9 |
| 5274 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9__W 1 | 5274 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9__W 1 |
| 5275 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9__M 0x200 | 5275 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9__M 0x200 |
| 5276 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9_OUTPUT 0x0 | 5276 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9_OUTPUT 0x0 |
| 5277 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9_INPUT 0x200 | 5277 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_9_INPUT 0x200 |
| 5278 | 5278 | ||
| 5279 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10__B 10 | 5279 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10__B 10 |
| 5280 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10__W 1 | 5280 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10__W 1 |
| 5281 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10__M 0x400 | 5281 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10__M 0x400 |
| 5282 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10_OUTPUT 0x0 | 5282 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10_OUTPUT 0x0 |
| 5283 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10_INPUT 0x400 | 5283 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_10_INPUT 0x400 |
| 5284 | 5284 | ||
| 5285 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11__B 11 | 5285 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11__B 11 |
| 5286 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11__W 1 | 5286 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11__W 1 |
| 5287 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11__M 0x800 | 5287 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11__M 0x800 |
| 5288 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 | 5288 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 |
| 5289 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 | 5289 | #define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 |
| 5290 | 5290 | ||
| 5291 | #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 | 5291 | #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 |
| 5292 | #define EC_OC_REG_DTO_INC_LOP__W 16 | 5292 | #define EC_OC_REG_DTO_INC_LOP__W 16 |
| 5293 | #define EC_OC_REG_DTO_INC_LOP__M 0xFFFF | 5293 | #define EC_OC_REG_DTO_INC_LOP__M 0xFFFF |
| 5294 | #define EC_OC_REG_DTO_INC_LOP_INIT 0x0 | 5294 | #define EC_OC_REG_DTO_INC_LOP_INIT 0x0 |
| 5295 | 5295 | ||
| 5296 | #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 | 5296 | #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 |
| 5297 | #define EC_OC_REG_DTO_INC_HIP__W 8 | 5297 | #define EC_OC_REG_DTO_INC_HIP__W 8 |
| 5298 | #define EC_OC_REG_DTO_INC_HIP__M 0xFF | 5298 | #define EC_OC_REG_DTO_INC_HIP__M 0xFF |
| 5299 | #define EC_OC_REG_DTO_INC_HIP_INIT 0x0 | 5299 | #define EC_OC_REG_DTO_INC_HIP_INIT 0x0 |
| 5300 | 5300 | ||
| 5301 | #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 | 5301 | #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 |
| 5302 | #define EC_OC_REG_SNC_ISC_LVL__W 12 | 5302 | #define EC_OC_REG_SNC_ISC_LVL__W 12 |
| 5303 | #define EC_OC_REG_SNC_ISC_LVL__M 0xFFF | 5303 | #define EC_OC_REG_SNC_ISC_LVL__M 0xFFF |
| 5304 | #define EC_OC_REG_SNC_ISC_LVL_INIT 0x0 | 5304 | #define EC_OC_REG_SNC_ISC_LVL_INIT 0x0 |
| 5305 | 5305 | ||
| 5306 | #define EC_OC_REG_SNC_ISC_LVL_ISC__B 0 | 5306 | #define EC_OC_REG_SNC_ISC_LVL_ISC__B 0 |
| 5307 | #define EC_OC_REG_SNC_ISC_LVL_ISC__W 4 | 5307 | #define EC_OC_REG_SNC_ISC_LVL_ISC__W 4 |
| 5308 | #define EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF | 5308 | #define EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF |
| 5309 | 5309 | ||
| 5310 | #define EC_OC_REG_SNC_ISC_LVL_OSC__B 4 | 5310 | #define EC_OC_REG_SNC_ISC_LVL_OSC__B 4 |
| 5311 | #define EC_OC_REG_SNC_ISC_LVL_OSC__W 4 | 5311 | #define EC_OC_REG_SNC_ISC_LVL_OSC__W 4 |
| 5312 | #define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 | 5312 | #define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 |
| 5313 | 5313 | ||
| 5314 | #define EC_OC_REG_SNC_ISC_LVL_NSC__B 8 | 5314 | #define EC_OC_REG_SNC_ISC_LVL_NSC__B 8 |
| 5315 | #define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 | 5315 | #define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 |
| 5316 | #define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 | 5316 | #define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 |
| 5317 | 5317 | ||
| 5318 | #define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 | 5318 | #define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 |
| 5319 | #define EC_OC_REG_SNC_NSC_LVL__W 8 | 5319 | #define EC_OC_REG_SNC_NSC_LVL__W 8 |
| 5320 | #define EC_OC_REG_SNC_NSC_LVL__M 0xFF | 5320 | #define EC_OC_REG_SNC_NSC_LVL__M 0xFF |
| 5321 | #define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 | 5321 | #define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 |
| 5322 | 5322 | ||
| 5323 | #define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 | 5323 | #define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 |
| 5324 | #define EC_OC_REG_SNC_SNC_MODE__W 2 | 5324 | #define EC_OC_REG_SNC_SNC_MODE__W 2 |
| 5325 | #define EC_OC_REG_SNC_SNC_MODE__M 0x3 | 5325 | #define EC_OC_REG_SNC_SNC_MODE__M 0x3 |
| 5326 | #define EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 | 5326 | #define EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 |
| 5327 | #define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 | 5327 | #define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 |
| 5328 | #define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 | 5328 | #define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 |
| 5329 | 5329 | ||
| 5330 | #define EC_OC_REG_SNC_PCK_NMB__A 0x215001A | 5330 | #define EC_OC_REG_SNC_PCK_NMB__A 0x215001A |
| 5331 | #define EC_OC_REG_SNC_PCK_NMB__W 16 | 5331 | #define EC_OC_REG_SNC_PCK_NMB__W 16 |
| 5332 | #define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF | 5332 | #define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF |
| 5333 | 5333 | ||
| 5334 | #define EC_OC_REG_SNC_PCK_CNT__A 0x215001B | 5334 | #define EC_OC_REG_SNC_PCK_CNT__A 0x215001B |
| 5335 | #define EC_OC_REG_SNC_PCK_CNT__W 16 | 5335 | #define EC_OC_REG_SNC_PCK_CNT__W 16 |
| 5336 | #define EC_OC_REG_SNC_PCK_CNT__M 0xFFFF | 5336 | #define EC_OC_REG_SNC_PCK_CNT__M 0xFFFF |
| 5337 | 5337 | ||
| 5338 | #define EC_OC_REG_SNC_PCK_ERR__A 0x215001C | 5338 | #define EC_OC_REG_SNC_PCK_ERR__A 0x215001C |
| 5339 | #define EC_OC_REG_SNC_PCK_ERR__W 16 | 5339 | #define EC_OC_REG_SNC_PCK_ERR__W 16 |
| 5340 | #define EC_OC_REG_SNC_PCK_ERR__M 0xFFFF | 5340 | #define EC_OC_REG_SNC_PCK_ERR__M 0xFFFF |
| 5341 | 5341 | ||
| 5342 | #define EC_OC_REG_TMD_TOP_MODE__A 0x215001D | 5342 | #define EC_OC_REG_TMD_TOP_MODE__A 0x215001D |
| 5343 | #define EC_OC_REG_TMD_TOP_MODE__W 2 | 5343 | #define EC_OC_REG_TMD_TOP_MODE__W 2 |
| 5344 | #define EC_OC_REG_TMD_TOP_MODE__M 0x3 | 5344 | #define EC_OC_REG_TMD_TOP_MODE__M 0x3 |
| 5345 | #define EC_OC_REG_TMD_TOP_MODE_INIT 0x0 | 5345 | #define EC_OC_REG_TMD_TOP_MODE_INIT 0x0 |
| 5346 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 | 5346 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 |
| 5347 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 | 5347 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 |
| 5348 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 | 5348 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 |
| 5349 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 | 5349 | #define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 |
| 5350 | 5350 | ||
| 5351 | #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E | 5351 | #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E |
| 5352 | #define EC_OC_REG_TMD_TOP_CNT__W 10 | 5352 | #define EC_OC_REG_TMD_TOP_CNT__W 10 |
| 5353 | #define EC_OC_REG_TMD_TOP_CNT__M 0x3FF | 5353 | #define EC_OC_REG_TMD_TOP_CNT__M 0x3FF |
| 5354 | #define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 | 5354 | #define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 |
| 5355 | 5355 | ||
| 5356 | #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F | 5356 | #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F |
| 5357 | #define EC_OC_REG_TMD_HIL_MAR__W 10 | 5357 | #define EC_OC_REG_TMD_HIL_MAR__W 10 |
| 5358 | #define EC_OC_REG_TMD_HIL_MAR__M 0x3FF | 5358 | #define EC_OC_REG_TMD_HIL_MAR__M 0x3FF |
| 5359 | #define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 | 5359 | #define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 |
| 5360 | 5360 | ||
| 5361 | #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 | 5361 | #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 |
| 5362 | #define EC_OC_REG_TMD_LOL_MAR__W 10 | 5362 | #define EC_OC_REG_TMD_LOL_MAR__W 10 |
| 5363 | #define EC_OC_REG_TMD_LOL_MAR__M 0x3FF | 5363 | #define EC_OC_REG_TMD_LOL_MAR__M 0x3FF |
| 5364 | #define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 | 5364 | #define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 |
| 5365 | 5365 | ||
| 5366 | #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 | 5366 | #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 |
| 5367 | #define EC_OC_REG_TMD_CUR_CNT__W 4 | 5367 | #define EC_OC_REG_TMD_CUR_CNT__W 4 |
| 5368 | #define EC_OC_REG_TMD_CUR_CNT__M 0xF | 5368 | #define EC_OC_REG_TMD_CUR_CNT__M 0xF |
| 5369 | #define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 | 5369 | #define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 |
| 5370 | 5370 | ||
| 5371 | #define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 | 5371 | #define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 |
| 5372 | #define EC_OC_REG_TMD_IUR_CNT__W 4 | 5372 | #define EC_OC_REG_TMD_IUR_CNT__W 4 |
| 5373 | #define EC_OC_REG_TMD_IUR_CNT__M 0xF | 5373 | #define EC_OC_REG_TMD_IUR_CNT__M 0xF |
| 5374 | #define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 | 5374 | #define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 |
| 5375 | 5375 | ||
| 5376 | #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 | 5376 | #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 |
| 5377 | #define EC_OC_REG_AVR_ASH_CNT__W 4 | 5377 | #define EC_OC_REG_AVR_ASH_CNT__W 4 |
| 5378 | #define EC_OC_REG_AVR_ASH_CNT__M 0xF | 5378 | #define EC_OC_REG_AVR_ASH_CNT__M 0xF |
| 5379 | #define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 | 5379 | #define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 |
| 5380 | 5380 | ||
| 5381 | #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 | 5381 | #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 |
| 5382 | #define EC_OC_REG_AVR_BSH_CNT__W 4 | 5382 | #define EC_OC_REG_AVR_BSH_CNT__W 4 |
| 5383 | #define EC_OC_REG_AVR_BSH_CNT__M 0xF | 5383 | #define EC_OC_REG_AVR_BSH_CNT__M 0xF |
| 5384 | #define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 | 5384 | #define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 |
| 5385 | 5385 | ||
| 5386 | #define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 | 5386 | #define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 |
| 5387 | #define EC_OC_REG_AVR_AVE_LOP__W 16 | 5387 | #define EC_OC_REG_AVR_AVE_LOP__W 16 |
| 5388 | #define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF | 5388 | #define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF |
| 5389 | 5389 | ||
| 5390 | #define EC_OC_REG_AVR_AVE_HIP__A 0x2150026 | 5390 | #define EC_OC_REG_AVR_AVE_HIP__A 0x2150026 |
| 5391 | #define EC_OC_REG_AVR_AVE_HIP__W 5 | 5391 | #define EC_OC_REG_AVR_AVE_HIP__W 5 |
| 5392 | #define EC_OC_REG_AVR_AVE_HIP__M 0x1F | 5392 | #define EC_OC_REG_AVR_AVE_HIP__M 0x1F |
| 5393 | 5393 | ||
| 5394 | #define EC_OC_REG_RCN_MODE__A 0x2150027 | 5394 | #define EC_OC_REG_RCN_MODE__A 0x2150027 |
| 5395 | #define EC_OC_REG_RCN_MODE__W 3 | 5395 | #define EC_OC_REG_RCN_MODE__W 3 |
| 5396 | #define EC_OC_REG_RCN_MODE__M 0x7 | 5396 | #define EC_OC_REG_RCN_MODE__M 0x7 |
| 5397 | #define EC_OC_REG_RCN_MODE_INIT 0x0 | 5397 | #define EC_OC_REG_RCN_MODE_INIT 0x0 |
| 5398 | 5398 | ||
| 5399 | #define EC_OC_REG_RCN_MODE_MODE_0__B 0 | 5399 | #define EC_OC_REG_RCN_MODE_MODE_0__B 0 |
| 5400 | #define EC_OC_REG_RCN_MODE_MODE_0__W 1 | 5400 | #define EC_OC_REG_RCN_MODE_MODE_0__W 1 |
| 5401 | #define EC_OC_REG_RCN_MODE_MODE_0__M 0x1 | 5401 | #define EC_OC_REG_RCN_MODE_MODE_0__M 0x1 |
| 5402 | #define EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 | 5402 | #define EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 |
| 5403 | #define EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 | 5403 | #define EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 |
| 5404 | 5404 | ||
| 5405 | #define EC_OC_REG_RCN_MODE_MODE_1__B 1 | 5405 | #define EC_OC_REG_RCN_MODE_MODE_1__B 1 |
| 5406 | #define EC_OC_REG_RCN_MODE_MODE_1__W 1 | 5406 | #define EC_OC_REG_RCN_MODE_MODE_1__W 1 |
| 5407 | #define EC_OC_REG_RCN_MODE_MODE_1__M 0x2 | 5407 | #define EC_OC_REG_RCN_MODE_MODE_1__M 0x2 |
| 5408 | #define EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 | 5408 | #define EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 |
| 5409 | #define EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 | 5409 | #define EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 |
| 5410 | 5410 | ||
| 5411 | #define EC_OC_REG_RCN_MODE_MODE_2__B 2 | 5411 | #define EC_OC_REG_RCN_MODE_MODE_2__B 2 |
| 5412 | #define EC_OC_REG_RCN_MODE_MODE_2__W 1 | 5412 | #define EC_OC_REG_RCN_MODE_MODE_2__W 1 |
| 5413 | #define EC_OC_REG_RCN_MODE_MODE_2__M 0x4 | 5413 | #define EC_OC_REG_RCN_MODE_MODE_2__M 0x4 |
| 5414 | #define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 | 5414 | #define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 |
| 5415 | #define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 | 5415 | #define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 |
| 5416 | 5416 | ||
| 5417 | #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 | 5417 | #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 |
| 5418 | #define EC_OC_REG_RCN_CRA_LOP__W 16 | 5418 | #define EC_OC_REG_RCN_CRA_LOP__W 16 |
| 5419 | #define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF | 5419 | #define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF |
| 5420 | #define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 | 5420 | #define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 |
| 5421 | 5421 | ||
| 5422 | #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 | 5422 | #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 |
| 5423 | #define EC_OC_REG_RCN_CRA_HIP__W 8 | 5423 | #define EC_OC_REG_RCN_CRA_HIP__W 8 |
| 5424 | #define EC_OC_REG_RCN_CRA_HIP__M 0xFF | 5424 | #define EC_OC_REG_RCN_CRA_HIP__M 0xFF |
| 5425 | #define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 | 5425 | #define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 |
| 5426 | 5426 | ||
| 5427 | #define EC_OC_REG_RCN_CST_LOP__A 0x215002A | 5427 | #define EC_OC_REG_RCN_CST_LOP__A 0x215002A |
| 5428 | #define EC_OC_REG_RCN_CST_LOP__W 16 | 5428 | #define EC_OC_REG_RCN_CST_LOP__W 16 |
| 5429 | #define EC_OC_REG_RCN_CST_LOP__M 0xFFFF | 5429 | #define EC_OC_REG_RCN_CST_LOP__M 0xFFFF |
| 5430 | #define EC_OC_REG_RCN_CST_LOP_INIT 0x0 | 5430 | #define EC_OC_REG_RCN_CST_LOP_INIT 0x0 |
| 5431 | 5431 | ||
| 5432 | #define EC_OC_REG_RCN_CST_HIP__A 0x215002B | 5432 | #define EC_OC_REG_RCN_CST_HIP__A 0x215002B |
| 5433 | #define EC_OC_REG_RCN_CST_HIP__W 8 | 5433 | #define EC_OC_REG_RCN_CST_HIP__W 8 |
| 5434 | #define EC_OC_REG_RCN_CST_HIP__M 0xFF | 5434 | #define EC_OC_REG_RCN_CST_HIP__M 0xFF |
| 5435 | #define EC_OC_REG_RCN_CST_HIP_INIT 0x0 | 5435 | #define EC_OC_REG_RCN_CST_HIP_INIT 0x0 |
| 5436 | 5436 | ||
| 5437 | #define EC_OC_REG_RCN_SET_LVL__A 0x215002C | 5437 | #define EC_OC_REG_RCN_SET_LVL__A 0x215002C |
| 5438 | #define EC_OC_REG_RCN_SET_LVL__W 9 | 5438 | #define EC_OC_REG_RCN_SET_LVL__W 9 |
| 5439 | #define EC_OC_REG_RCN_SET_LVL__M 0x1FF | 5439 | #define EC_OC_REG_RCN_SET_LVL__M 0x1FF |
| 5440 | #define EC_OC_REG_RCN_SET_LVL_INIT 0x0 | 5440 | #define EC_OC_REG_RCN_SET_LVL_INIT 0x0 |
| 5441 | 5441 | ||
| 5442 | #define EC_OC_REG_RCN_GAI_LVL__A 0x215002D | 5442 | #define EC_OC_REG_RCN_GAI_LVL__A 0x215002D |
| 5443 | #define EC_OC_REG_RCN_GAI_LVL__W 4 | 5443 | #define EC_OC_REG_RCN_GAI_LVL__W 4 |
| 5444 | #define EC_OC_REG_RCN_GAI_LVL__M 0xF | 5444 | #define EC_OC_REG_RCN_GAI_LVL__M 0xF |
| 5445 | #define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 | 5445 | #define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 |
| 5446 | 5446 | ||
| 5447 | #define EC_OC_REG_RCN_DRA_LOP__A 0x215002E | 5447 | #define EC_OC_REG_RCN_DRA_LOP__A 0x215002E |
| 5448 | #define EC_OC_REG_RCN_DRA_LOP__W 16 | 5448 | #define EC_OC_REG_RCN_DRA_LOP__W 16 |
| 5449 | #define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF | 5449 | #define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF |
| 5450 | 5450 | ||
| 5451 | #define EC_OC_REG_RCN_DRA_HIP__A 0x215002F | 5451 | #define EC_OC_REG_RCN_DRA_HIP__A 0x215002F |
| 5452 | #define EC_OC_REG_RCN_DRA_HIP__W 8 | 5452 | #define EC_OC_REG_RCN_DRA_HIP__W 8 |
| 5453 | #define EC_OC_REG_RCN_DRA_HIP__M 0xFF | 5453 | #define EC_OC_REG_RCN_DRA_HIP__M 0xFF |
| 5454 | 5454 | ||
| 5455 | #define EC_OC_REG_RCN_DOF_LOP__A 0x2150030 | 5455 | #define EC_OC_REG_RCN_DOF_LOP__A 0x2150030 |
| 5456 | #define EC_OC_REG_RCN_DOF_LOP__W 16 | 5456 | #define EC_OC_REG_RCN_DOF_LOP__W 16 |
| 5457 | #define EC_OC_REG_RCN_DOF_LOP__M 0xFFFF | 5457 | #define EC_OC_REG_RCN_DOF_LOP__M 0xFFFF |
| 5458 | 5458 | ||
| 5459 | #define EC_OC_REG_RCN_DOF_HIP__A 0x2150031 | 5459 | #define EC_OC_REG_RCN_DOF_HIP__A 0x2150031 |
| 5460 | #define EC_OC_REG_RCN_DOF_HIP__W 8 | 5460 | #define EC_OC_REG_RCN_DOF_HIP__W 8 |
| 5461 | #define EC_OC_REG_RCN_DOF_HIP__M 0xFF | 5461 | #define EC_OC_REG_RCN_DOF_HIP__M 0xFF |
| 5462 | 5462 | ||
| 5463 | #define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 | 5463 | #define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 |
| 5464 | #define EC_OC_REG_RCN_CLP_LOP__W 16 | 5464 | #define EC_OC_REG_RCN_CLP_LOP__W 16 |
| 5465 | #define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF | 5465 | #define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF |
| 5466 | #define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF | 5466 | #define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF |
| 5467 | 5467 | ||
| 5468 | #define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 | 5468 | #define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 |
| 5469 | #define EC_OC_REG_RCN_CLP_HIP__W 8 | 5469 | #define EC_OC_REG_RCN_CLP_HIP__W 8 |
| 5470 | #define EC_OC_REG_RCN_CLP_HIP__M 0xFF | 5470 | #define EC_OC_REG_RCN_CLP_HIP__M 0xFF |
| 5471 | #define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF | 5471 | #define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF |
| 5472 | 5472 | ||
| 5473 | #define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 | 5473 | #define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 |
| 5474 | #define EC_OC_REG_RCN_MAP_LOP__W 16 | 5474 | #define EC_OC_REG_RCN_MAP_LOP__W 16 |
| 5475 | #define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF | 5475 | #define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF |
| 5476 | 5476 | ||
| 5477 | #define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 | 5477 | #define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 |
| 5478 | #define EC_OC_REG_RCN_MAP_HIP__W 8 | 5478 | #define EC_OC_REG_RCN_MAP_HIP__W 8 |
| 5479 | #define EC_OC_REG_RCN_MAP_HIP__M 0xFF | 5479 | #define EC_OC_REG_RCN_MAP_HIP__M 0xFF |
| 5480 | 5480 | ||
| 5481 | #define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 | 5481 | #define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 |
| 5482 | #define EC_OC_REG_OCR_MPG_UOS__W 12 | 5482 | #define EC_OC_REG_OCR_MPG_UOS__W 12 |
| 5483 | #define EC_OC_REG_OCR_MPG_UOS__M 0xFFF | 5483 | #define EC_OC_REG_OCR_MPG_UOS__M 0xFFF |
| 5484 | #define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 | 5484 | #define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 |
| 5485 | 5485 | ||
| 5486 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 | 5486 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 |
| 5487 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 | 5487 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 |
| 5488 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 | 5488 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 |
| 5489 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 | 5489 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 |
| 5490 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 | 5490 | #define EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 |
| 5491 | 5491 | ||
| 5492 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 | 5492 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 |
| 5493 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 | 5493 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 |
| 5494 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 | 5494 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 |
| 5495 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 | 5495 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 |
| 5496 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 | 5496 | #define EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 |
| 5497 | 5497 | ||
| 5498 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 | 5498 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 |
| 5499 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 | 5499 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 |
| 5500 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 | 5500 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 |
| 5501 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 | 5501 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 |
| 5502 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 | 5502 | #define EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 |
| 5503 | 5503 | ||
| 5504 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 | 5504 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 |
| 5505 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 | 5505 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 |
| 5506 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 | 5506 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 |
| 5507 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 | 5507 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 |
| 5508 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 | 5508 | #define EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 |
| 5509 | 5509 | ||
| 5510 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 | 5510 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 |
| 5511 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 | 5511 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 |
| 5512 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 | 5512 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 |
| 5513 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 | 5513 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 |
| 5514 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 | 5514 | #define EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 |
| 5515 | 5515 | ||
| 5516 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 | 5516 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 |
| 5517 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 | 5517 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 |
| 5518 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 | 5518 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 |
| 5519 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 | 5519 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 |
| 5520 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 | 5520 | #define EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 |
| 5521 | 5521 | ||
| 5522 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 | 5522 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 |
| 5523 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 | 5523 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 |
| 5524 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 | 5524 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 |
| 5525 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 | 5525 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 |
| 5526 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 | 5526 | #define EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 |
| 5527 | 5527 | ||
| 5528 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 | 5528 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 |
| 5529 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 | 5529 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 |
| 5530 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 | 5530 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 |
| 5531 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 | 5531 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 |
| 5532 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 | 5532 | #define EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 |
| 5533 | 5533 | ||
| 5534 | #define EC_OC_REG_OCR_MPG_UOS_ERR__B 8 | 5534 | #define EC_OC_REG_OCR_MPG_UOS_ERR__B 8 |
| 5535 | #define EC_OC_REG_OCR_MPG_UOS_ERR__W 1 | 5535 | #define EC_OC_REG_OCR_MPG_UOS_ERR__W 1 |
| 5536 | #define EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 | 5536 | #define EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 |
| 5537 | #define EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 | 5537 | #define EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 |
| 5538 | #define EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 | 5538 | #define EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 |
| 5539 | 5539 | ||
| 5540 | #define EC_OC_REG_OCR_MPG_UOS_STR__B 9 | 5540 | #define EC_OC_REG_OCR_MPG_UOS_STR__B 9 |
| 5541 | #define EC_OC_REG_OCR_MPG_UOS_STR__W 1 | 5541 | #define EC_OC_REG_OCR_MPG_UOS_STR__W 1 |
| 5542 | #define EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 | 5542 | #define EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 |
| 5543 | #define EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 | 5543 | #define EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 |
| 5544 | #define EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 | 5544 | #define EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 |
| 5545 | 5545 | ||
| 5546 | #define EC_OC_REG_OCR_MPG_UOS_VAL__B 10 | 5546 | #define EC_OC_REG_OCR_MPG_UOS_VAL__B 10 |
| 5547 | #define EC_OC_REG_OCR_MPG_UOS_VAL__W 1 | 5547 | #define EC_OC_REG_OCR_MPG_UOS_VAL__W 1 |
| 5548 | #define EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 | 5548 | #define EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 |
| 5549 | #define EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 | 5549 | #define EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 |
| 5550 | #define EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 | 5550 | #define EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 |
| 5551 | 5551 | ||
| 5552 | #define EC_OC_REG_OCR_MPG_UOS_CLK__B 11 | 5552 | #define EC_OC_REG_OCR_MPG_UOS_CLK__B 11 |
| 5553 | #define EC_OC_REG_OCR_MPG_UOS_CLK__W 1 | 5553 | #define EC_OC_REG_OCR_MPG_UOS_CLK__W 1 |
| 5554 | #define EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 | 5554 | #define EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 |
| 5555 | #define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 | 5555 | #define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 |
| 5556 | #define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 | 5556 | #define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 |
| 5557 | 5557 | ||
| 5558 | #define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 | 5558 | #define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 |
| 5559 | #define EC_OC_REG_OCR_MPG_WRI__W 12 | 5559 | #define EC_OC_REG_OCR_MPG_WRI__W 12 |
| 5560 | #define EC_OC_REG_OCR_MPG_WRI__M 0xFFF | 5560 | #define EC_OC_REG_OCR_MPG_WRI__M 0xFFF |
| 5561 | #define EC_OC_REG_OCR_MPG_WRI_INIT 0x0 | 5561 | #define EC_OC_REG_OCR_MPG_WRI_INIT 0x0 |
| 5562 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 | 5562 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 |
| 5563 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 | 5563 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 |
| 5564 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 | 5564 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 |
| 5565 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 | 5565 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 |
| 5566 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 | 5566 | #define EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 |
| 5567 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 | 5567 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 |
| 5568 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 | 5568 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 |
| 5569 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 | 5569 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 |
| 5570 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 | 5570 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 |
| 5571 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 | 5571 | #define EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 |
| 5572 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 | 5572 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 |
| 5573 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 | 5573 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 |
| 5574 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 | 5574 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 |
| 5575 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 | 5575 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 |
| 5576 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 | 5576 | #define EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 |
| 5577 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 | 5577 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 |
| 5578 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 | 5578 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 |
| 5579 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 | 5579 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 |
| 5580 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 | 5580 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 |
| 5581 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 | 5581 | #define EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 |
| 5582 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 | 5582 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 |
| 5583 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 | 5583 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 |
| 5584 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 | 5584 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 |
| 5585 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 | 5585 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 |
| 5586 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 | 5586 | #define EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 |
| 5587 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 | 5587 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 |
| 5588 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 | 5588 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 |
| 5589 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 | 5589 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 |
| 5590 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 | 5590 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 |
| 5591 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 | 5591 | #define EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 |
| 5592 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 | 5592 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 |
| 5593 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 | 5593 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 |
| 5594 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 | 5594 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 |
| 5595 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 | 5595 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 |
| 5596 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 | 5596 | #define EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 |
| 5597 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 | 5597 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 |
| 5598 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 | 5598 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 |
| 5599 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 | 5599 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 |
| 5600 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 | 5600 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 |
| 5601 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 | 5601 | #define EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 |
| 5602 | #define EC_OC_REG_OCR_MPG_WRI_ERR__B 8 | 5602 | #define EC_OC_REG_OCR_MPG_WRI_ERR__B 8 |
| 5603 | #define EC_OC_REG_OCR_MPG_WRI_ERR__W 1 | 5603 | #define EC_OC_REG_OCR_MPG_WRI_ERR__W 1 |
| 5604 | #define EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 | 5604 | #define EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 |
| 5605 | #define EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 | 5605 | #define EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 |
| 5606 | #define EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 | 5606 | #define EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 |
| 5607 | #define EC_OC_REG_OCR_MPG_WRI_STR__B 9 | 5607 | #define EC_OC_REG_OCR_MPG_WRI_STR__B 9 |
| 5608 | #define EC_OC_REG_OCR_MPG_WRI_STR__W 1 | 5608 | #define EC_OC_REG_OCR_MPG_WRI_STR__W 1 |
| 5609 | #define EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 | 5609 | #define EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 |
| 5610 | #define EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 | 5610 | #define EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 |
| 5611 | #define EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 | 5611 | #define EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 |
| 5612 | #define EC_OC_REG_OCR_MPG_WRI_VAL__B 10 | 5612 | #define EC_OC_REG_OCR_MPG_WRI_VAL__B 10 |
| 5613 | #define EC_OC_REG_OCR_MPG_WRI_VAL__W 1 | 5613 | #define EC_OC_REG_OCR_MPG_WRI_VAL__W 1 |
| 5614 | #define EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 | 5614 | #define EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 |
| 5615 | #define EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 | 5615 | #define EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 |
| 5616 | #define EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 | 5616 | #define EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 |
| 5617 | #define EC_OC_REG_OCR_MPG_WRI_CLK__B 11 | 5617 | #define EC_OC_REG_OCR_MPG_WRI_CLK__B 11 |
| 5618 | #define EC_OC_REG_OCR_MPG_WRI_CLK__W 1 | 5618 | #define EC_OC_REG_OCR_MPG_WRI_CLK__W 1 |
| 5619 | #define EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 | 5619 | #define EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 |
| 5620 | #define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 | 5620 | #define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 |
| 5621 | #define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 | 5621 | #define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 |
| 5622 | 5622 | ||
| 5623 | #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 | 5623 | #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 |
| 5624 | #define EC_OC_REG_OCR_MPG_USR_DAT__W 12 | 5624 | #define EC_OC_REG_OCR_MPG_USR_DAT__W 12 |
| 5625 | #define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF | 5625 | #define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF |
| 5626 | 5626 | ||
| 5627 | #define EC_OC_REG_OCR_MON_UOS__A 0x2150039 | 5627 | #define EC_OC_REG_OCR_MON_UOS__A 0x2150039 |
| 5628 | #define EC_OC_REG_OCR_MON_UOS__W 12 | 5628 | #define EC_OC_REG_OCR_MON_UOS__W 12 |
| 5629 | #define EC_OC_REG_OCR_MON_UOS__M 0xFFF | 5629 | #define EC_OC_REG_OCR_MON_UOS__M 0xFFF |
| 5630 | #define EC_OC_REG_OCR_MON_UOS_INIT 0x0 | 5630 | #define EC_OC_REG_OCR_MON_UOS_INIT 0x0 |
| 5631 | 5631 | ||
| 5632 | #define EC_OC_REG_OCR_MON_UOS_DAT_0__B 0 | 5632 | #define EC_OC_REG_OCR_MON_UOS_DAT_0__B 0 |
| 5633 | #define EC_OC_REG_OCR_MON_UOS_DAT_0__W 1 | 5633 | #define EC_OC_REG_OCR_MON_UOS_DAT_0__W 1 |
| 5634 | #define EC_OC_REG_OCR_MON_UOS_DAT_0__M 0x1 | 5634 | #define EC_OC_REG_OCR_MON_UOS_DAT_0__M 0x1 |
| 5635 | #define EC_OC_REG_OCR_MON_UOS_DAT_0_DISABLE 0x0 | 5635 | #define EC_OC_REG_OCR_MON_UOS_DAT_0_DISABLE 0x0 |
| 5636 | #define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 | 5636 | #define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 |
| 5637 | 5637 | ||
| 5638 | #define EC_OC_REG_OCR_MON_UOS_DAT_1__B 1 | 5638 | #define EC_OC_REG_OCR_MON_UOS_DAT_1__B 1 |
| 5639 | #define EC_OC_REG_OCR_MON_UOS_DAT_1__W 1 | 5639 | #define EC_OC_REG_OCR_MON_UOS_DAT_1__W 1 |
| 5640 | #define EC_OC_REG_OCR_MON_UOS_DAT_1__M 0x2 | 5640 | #define EC_OC_REG_OCR_MON_UOS_DAT_1__M 0x2 |
| 5641 | #define EC_OC_REG_OCR_MON_UOS_DAT_1_DISABLE 0x0 | 5641 | #define EC_OC_REG_OCR_MON_UOS_DAT_1_DISABLE 0x0 |
| 5642 | #define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 | 5642 | #define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 |
| 5643 | 5643 | ||
| 5644 | #define EC_OC_REG_OCR_MON_UOS_DAT_2__B 2 | 5644 | #define EC_OC_REG_OCR_MON_UOS_DAT_2__B 2 |
| 5645 | #define EC_OC_REG_OCR_MON_UOS_DAT_2__W 1 | 5645 | #define EC_OC_REG_OCR_MON_UOS_DAT_2__W 1 |
| 5646 | #define EC_OC_REG_OCR_MON_UOS_DAT_2__M 0x4 | 5646 | #define EC_OC_REG_OCR_MON_UOS_DAT_2__M 0x4 |
| 5647 | #define EC_OC_REG_OCR_MON_UOS_DAT_2_DISABLE 0x0 | 5647 | #define EC_OC_REG_OCR_MON_UOS_DAT_2_DISABLE 0x0 |
| 5648 | #define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 | 5648 | #define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 |
| 5649 | 5649 | ||
| 5650 | #define EC_OC_REG_OCR_MON_UOS_DAT_3__B 3 | 5650 | #define EC_OC_REG_OCR_MON_UOS_DAT_3__B 3 |
| 5651 | #define EC_OC_REG_OCR_MON_UOS_DAT_3__W 1 | 5651 | #define EC_OC_REG_OCR_MON_UOS_DAT_3__W 1 |
| 5652 | #define EC_OC_REG_OCR_MON_UOS_DAT_3__M 0x8 | 5652 | #define EC_OC_REG_OCR_MON_UOS_DAT_3__M 0x8 |
| 5653 | #define EC_OC_REG_OCR_MON_UOS_DAT_3_DISABLE 0x0 | 5653 | #define EC_OC_REG_OCR_MON_UOS_DAT_3_DISABLE 0x0 |
| 5654 | #define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 | 5654 | #define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 |
| 5655 | 5655 | ||
| 5656 | #define EC_OC_REG_OCR_MON_UOS_DAT_4__B 4 | 5656 | #define EC_OC_REG_OCR_MON_UOS_DAT_4__B 4 |
| 5657 | #define EC_OC_REG_OCR_MON_UOS_DAT_4__W 1 | 5657 | #define EC_OC_REG_OCR_MON_UOS_DAT_4__W 1 |
| 5658 | #define EC_OC_REG_OCR_MON_UOS_DAT_4__M 0x10 | 5658 | #define EC_OC_REG_OCR_MON_UOS_DAT_4__M 0x10 |
| 5659 | #define EC_OC_REG_OCR_MON_UOS_DAT_4_DISABLE 0x0 | 5659 | #define EC_OC_REG_OCR_MON_UOS_DAT_4_DISABLE 0x0 |
| 5660 | #define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 | 5660 | #define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 |
| 5661 | 5661 | ||
| 5662 | #define EC_OC_REG_OCR_MON_UOS_DAT_5__B 5 | 5662 | #define EC_OC_REG_OCR_MON_UOS_DAT_5__B 5 |
| 5663 | #define EC_OC_REG_OCR_MON_UOS_DAT_5__W 1 | 5663 | #define EC_OC_REG_OCR_MON_UOS_DAT_5__W 1 |
| 5664 | #define EC_OC_REG_OCR_MON_UOS_DAT_5__M 0x20 | 5664 | #define EC_OC_REG_OCR_MON_UOS_DAT_5__M 0x20 |
| 5665 | #define EC_OC_REG_OCR_MON_UOS_DAT_5_DISABLE 0x0 | 5665 | #define EC_OC_REG_OCR_MON_UOS_DAT_5_DISABLE 0x0 |
| 5666 | #define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 | 5666 | #define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 |
| 5667 | 5667 | ||
| 5668 | #define EC_OC_REG_OCR_MON_UOS_DAT_6__B 6 | 5668 | #define EC_OC_REG_OCR_MON_UOS_DAT_6__B 6 |
| 5669 | #define EC_OC_REG_OCR_MON_UOS_DAT_6__W 1 | 5669 | #define EC_OC_REG_OCR_MON_UOS_DAT_6__W 1 |
| 5670 | #define EC_OC_REG_OCR_MON_UOS_DAT_6__M 0x40 | 5670 | #define EC_OC_REG_OCR_MON_UOS_DAT_6__M 0x40 |
| 5671 | #define EC_OC_REG_OCR_MON_UOS_DAT_6_DISABLE 0x0 | 5671 | #define EC_OC_REG_OCR_MON_UOS_DAT_6_DISABLE 0x0 |
| 5672 | #define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 | 5672 | #define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 |
| 5673 | 5673 | ||
| 5674 | #define EC_OC_REG_OCR_MON_UOS_DAT_7__B 7 | 5674 | #define EC_OC_REG_OCR_MON_UOS_DAT_7__B 7 |
| 5675 | #define EC_OC_REG_OCR_MON_UOS_DAT_7__W 1 | 5675 | #define EC_OC_REG_OCR_MON_UOS_DAT_7__W 1 |
| 5676 | #define EC_OC_REG_OCR_MON_UOS_DAT_7__M 0x80 | 5676 | #define EC_OC_REG_OCR_MON_UOS_DAT_7__M 0x80 |
| 5677 | #define EC_OC_REG_OCR_MON_UOS_DAT_7_DISABLE 0x0 | 5677 | #define EC_OC_REG_OCR_MON_UOS_DAT_7_DISABLE 0x0 |
| 5678 | #define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 | 5678 | #define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 |
| 5679 | 5679 | ||
| 5680 | #define EC_OC_REG_OCR_MON_UOS_DAT_8__B 8 | 5680 | #define EC_OC_REG_OCR_MON_UOS_DAT_8__B 8 |
| 5681 | #define EC_OC_REG_OCR_MON_UOS_DAT_8__W 1 | 5681 | #define EC_OC_REG_OCR_MON_UOS_DAT_8__W 1 |
| 5682 | #define EC_OC_REG_OCR_MON_UOS_DAT_8__M 0x100 | 5682 | #define EC_OC_REG_OCR_MON_UOS_DAT_8__M 0x100 |
| 5683 | #define EC_OC_REG_OCR_MON_UOS_DAT_8_DISABLE 0x0 | 5683 | #define EC_OC_REG_OCR_MON_UOS_DAT_8_DISABLE 0x0 |
| 5684 | #define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 | 5684 | #define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 |
| 5685 | 5685 | ||
| 5686 | #define EC_OC_REG_OCR_MON_UOS_DAT_9__B 9 | 5686 | #define EC_OC_REG_OCR_MON_UOS_DAT_9__B 9 |
| 5687 | #define EC_OC_REG_OCR_MON_UOS_DAT_9__W 1 | 5687 | #define EC_OC_REG_OCR_MON_UOS_DAT_9__W 1 |
| 5688 | #define EC_OC_REG_OCR_MON_UOS_DAT_9__M 0x200 | 5688 | #define EC_OC_REG_OCR_MON_UOS_DAT_9__M 0x200 |
| 5689 | #define EC_OC_REG_OCR_MON_UOS_DAT_9_DISABLE 0x0 | 5689 | #define EC_OC_REG_OCR_MON_UOS_DAT_9_DISABLE 0x0 |
| 5690 | #define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 | 5690 | #define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 |
| 5691 | 5691 | ||
| 5692 | #define EC_OC_REG_OCR_MON_UOS_VAL__B 10 | 5692 | #define EC_OC_REG_OCR_MON_UOS_VAL__B 10 |
| 5693 | #define EC_OC_REG_OCR_MON_UOS_VAL__W 1 | 5693 | #define EC_OC_REG_OCR_MON_UOS_VAL__W 1 |
| 5694 | #define EC_OC_REG_OCR_MON_UOS_VAL__M 0x400 | 5694 | #define EC_OC_REG_OCR_MON_UOS_VAL__M 0x400 |
| 5695 | #define EC_OC_REG_OCR_MON_UOS_VAL_DISABLE 0x0 | 5695 | #define EC_OC_REG_OCR_MON_UOS_VAL_DISABLE 0x0 |
| 5696 | #define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 | 5696 | #define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 |
| 5697 | 5697 | ||
| 5698 | #define EC_OC_REG_OCR_MON_UOS_CLK__B 11 | 5698 | #define EC_OC_REG_OCR_MON_UOS_CLK__B 11 |
| 5699 | #define EC_OC_REG_OCR_MON_UOS_CLK__W 1 | 5699 | #define EC_OC_REG_OCR_MON_UOS_CLK__W 1 |
| 5700 | #define EC_OC_REG_OCR_MON_UOS_CLK__M 0x800 | 5700 | #define EC_OC_REG_OCR_MON_UOS_CLK__M 0x800 |
| 5701 | #define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 | 5701 | #define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 |
| 5702 | #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 | 5702 | #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 |
| 5703 | 5703 | ||
| 5704 | #define EC_OC_REG_OCR_MON_WRI__A 0x215003A | 5704 | #define EC_OC_REG_OCR_MON_WRI__A 0x215003A |
| 5705 | #define EC_OC_REG_OCR_MON_WRI__W 12 | 5705 | #define EC_OC_REG_OCR_MON_WRI__W 12 |
| 5706 | #define EC_OC_REG_OCR_MON_WRI__M 0xFFF | 5706 | #define EC_OC_REG_OCR_MON_WRI__M 0xFFF |
| 5707 | #define EC_OC_REG_OCR_MON_WRI_INIT 0x0 | 5707 | #define EC_OC_REG_OCR_MON_WRI_INIT 0x0 |
| 5708 | #define EC_OC_REG_OCR_MON_WRI_DAT_0__B 0 | 5708 | #define EC_OC_REG_OCR_MON_WRI_DAT_0__B 0 |
| 5709 | #define EC_OC_REG_OCR_MON_WRI_DAT_0__W 1 | 5709 | #define EC_OC_REG_OCR_MON_WRI_DAT_0__W 1 |
| 5710 | #define EC_OC_REG_OCR_MON_WRI_DAT_0__M 0x1 | 5710 | #define EC_OC_REG_OCR_MON_WRI_DAT_0__M 0x1 |
| 5711 | #define EC_OC_REG_OCR_MON_WRI_DAT_0_DISABLE 0x0 | 5711 | #define EC_OC_REG_OCR_MON_WRI_DAT_0_DISABLE 0x0 |
| 5712 | #define EC_OC_REG_OCR_MON_WRI_DAT_0_ENABLE 0x1 | 5712 | #define EC_OC_REG_OCR_MON_WRI_DAT_0_ENABLE 0x1 |
| 5713 | #define EC_OC_REG_OCR_MON_WRI_DAT_1__B 1 | 5713 | #define EC_OC_REG_OCR_MON_WRI_DAT_1__B 1 |
| 5714 | #define EC_OC_REG_OCR_MON_WRI_DAT_1__W 1 | 5714 | #define EC_OC_REG_OCR_MON_WRI_DAT_1__W 1 |
| 5715 | #define EC_OC_REG_OCR_MON_WRI_DAT_1__M 0x2 | 5715 | #define EC_OC_REG_OCR_MON_WRI_DAT_1__M 0x2 |
| 5716 | #define EC_OC_REG_OCR_MON_WRI_DAT_1_DISABLE 0x0 | 5716 | #define EC_OC_REG_OCR_MON_WRI_DAT_1_DISABLE 0x0 |
| 5717 | #define EC_OC_REG_OCR_MON_WRI_DAT_1_ENABLE 0x2 | 5717 | #define EC_OC_REG_OCR_MON_WRI_DAT_1_ENABLE 0x2 |
| 5718 | #define EC_OC_REG_OCR_MON_WRI_DAT_2__B 2 | 5718 | #define EC_OC_REG_OCR_MON_WRI_DAT_2__B 2 |
| 5719 | #define EC_OC_REG_OCR_MON_WRI_DAT_2__W 1 | 5719 | #define EC_OC_REG_OCR_MON_WRI_DAT_2__W 1 |
| 5720 | #define EC_OC_REG_OCR_MON_WRI_DAT_2__M 0x4 | 5720 | #define EC_OC_REG_OCR_MON_WRI_DAT_2__M 0x4 |
| 5721 | #define EC_OC_REG_OCR_MON_WRI_DAT_2_DISABLE 0x0 | 5721 | #define EC_OC_REG_OCR_MON_WRI_DAT_2_DISABLE 0x0 |
| 5722 | #define EC_OC_REG_OCR_MON_WRI_DAT_2_ENABLE 0x4 | 5722 | #define EC_OC_REG_OCR_MON_WRI_DAT_2_ENABLE 0x4 |
| 5723 | #define EC_OC_REG_OCR_MON_WRI_DAT_3__B 3 | 5723 | #define EC_OC_REG_OCR_MON_WRI_DAT_3__B 3 |
| 5724 | #define EC_OC_REG_OCR_MON_WRI_DAT_3__W 1 | 5724 | #define EC_OC_REG_OCR_MON_WRI_DAT_3__W 1 |
| 5725 | #define EC_OC_REG_OCR_MON_WRI_DAT_3__M 0x8 | 5725 | #define EC_OC_REG_OCR_MON_WRI_DAT_3__M 0x8 |
| 5726 | #define EC_OC_REG_OCR_MON_WRI_DAT_3_DISABLE 0x0 | 5726 | #define EC_OC_REG_OCR_MON_WRI_DAT_3_DISABLE 0x0 |
| 5727 | #define EC_OC_REG_OCR_MON_WRI_DAT_3_ENABLE 0x8 | 5727 | #define EC_OC_REG_OCR_MON_WRI_DAT_3_ENABLE 0x8 |
| 5728 | #define EC_OC_REG_OCR_MON_WRI_DAT_4__B 4 | 5728 | #define EC_OC_REG_OCR_MON_WRI_DAT_4__B 4 |
| 5729 | #define EC_OC_REG_OCR_MON_WRI_DAT_4__W 1 | 5729 | #define EC_OC_REG_OCR_MON_WRI_DAT_4__W 1 |
| 5730 | #define EC_OC_REG_OCR_MON_WRI_DAT_4__M 0x10 | 5730 | #define EC_OC_REG_OCR_MON_WRI_DAT_4__M 0x10 |
| 5731 | #define EC_OC_REG_OCR_MON_WRI_DAT_4_DISABLE 0x0 | 5731 | #define EC_OC_REG_OCR_MON_WRI_DAT_4_DISABLE 0x0 |
| 5732 | #define EC_OC_REG_OCR_MON_WRI_DAT_4_ENABLE 0x10 | 5732 | #define EC_OC_REG_OCR_MON_WRI_DAT_4_ENABLE 0x10 |
| 5733 | #define EC_OC_REG_OCR_MON_WRI_DAT_5__B 5 | 5733 | #define EC_OC_REG_OCR_MON_WRI_DAT_5__B 5 |
| 5734 | #define EC_OC_REG_OCR_MON_WRI_DAT_5__W 1 | 5734 | #define EC_OC_REG_OCR_MON_WRI_DAT_5__W 1 |
| 5735 | #define EC_OC_REG_OCR_MON_WRI_DAT_5__M 0x20 | 5735 | #define EC_OC_REG_OCR_MON_WRI_DAT_5__M 0x20 |
| 5736 | #define EC_OC_REG_OCR_MON_WRI_DAT_5_DISABLE 0x0 | 5736 | #define EC_OC_REG_OCR_MON_WRI_DAT_5_DISABLE 0x0 |
| 5737 | #define EC_OC_REG_OCR_MON_WRI_DAT_5_ENABLE 0x20 | 5737 | #define EC_OC_REG_OCR_MON_WRI_DAT_5_ENABLE 0x20 |
| 5738 | #define EC_OC_REG_OCR_MON_WRI_DAT_6__B 6 | 5738 | #define EC_OC_REG_OCR_MON_WRI_DAT_6__B 6 |
| 5739 | #define EC_OC_REG_OCR_MON_WRI_DAT_6__W 1 | 5739 | #define EC_OC_REG_OCR_MON_WRI_DAT_6__W 1 |
| 5740 | #define EC_OC_REG_OCR_MON_WRI_DAT_6__M 0x40 | 5740 | #define EC_OC_REG_OCR_MON_WRI_DAT_6__M 0x40 |
| 5741 | #define EC_OC_REG_OCR_MON_WRI_DAT_6_DISABLE 0x0 | 5741 | #define EC_OC_REG_OCR_MON_WRI_DAT_6_DISABLE 0x0 |
| 5742 | #define EC_OC_REG_OCR_MON_WRI_DAT_6_ENABLE 0x40 | 5742 | #define EC_OC_REG_OCR_MON_WRI_DAT_6_ENABLE 0x40 |
| 5743 | #define EC_OC_REG_OCR_MON_WRI_DAT_7__B 7 | 5743 | #define EC_OC_REG_OCR_MON_WRI_DAT_7__B 7 |
| 5744 | #define EC_OC_REG_OCR_MON_WRI_DAT_7__W 1 | 5744 | #define EC_OC_REG_OCR_MON_WRI_DAT_7__W 1 |
| 5745 | #define EC_OC_REG_OCR_MON_WRI_DAT_7__M 0x80 | 5745 | #define EC_OC_REG_OCR_MON_WRI_DAT_7__M 0x80 |
| 5746 | #define EC_OC_REG_OCR_MON_WRI_DAT_7_DISABLE 0x0 | 5746 | #define EC_OC_REG_OCR_MON_WRI_DAT_7_DISABLE 0x0 |
| 5747 | #define EC_OC_REG_OCR_MON_WRI_DAT_7_ENABLE 0x80 | 5747 | #define EC_OC_REG_OCR_MON_WRI_DAT_7_ENABLE 0x80 |
| 5748 | #define EC_OC_REG_OCR_MON_WRI_DAT_8__B 8 | 5748 | #define EC_OC_REG_OCR_MON_WRI_DAT_8__B 8 |
| 5749 | #define EC_OC_REG_OCR_MON_WRI_DAT_8__W 1 | 5749 | #define EC_OC_REG_OCR_MON_WRI_DAT_8__W 1 |
| 5750 | #define EC_OC_REG_OCR_MON_WRI_DAT_8__M 0x100 | 5750 | #define EC_OC_REG_OCR_MON_WRI_DAT_8__M 0x100 |
| 5751 | #define EC_OC_REG_OCR_MON_WRI_DAT_8_DISABLE 0x0 | 5751 | #define EC_OC_REG_OCR_MON_WRI_DAT_8_DISABLE 0x0 |
| 5752 | #define EC_OC_REG_OCR_MON_WRI_DAT_8_ENABLE 0x100 | 5752 | #define EC_OC_REG_OCR_MON_WRI_DAT_8_ENABLE 0x100 |
| 5753 | #define EC_OC_REG_OCR_MON_WRI_DAT_9__B 9 | 5753 | #define EC_OC_REG_OCR_MON_WRI_DAT_9__B 9 |
| 5754 | #define EC_OC_REG_OCR_MON_WRI_DAT_9__W 1 | 5754 | #define EC_OC_REG_OCR_MON_WRI_DAT_9__W 1 |
| 5755 | #define EC_OC_REG_OCR_MON_WRI_DAT_9__M 0x200 | 5755 | #define EC_OC_REG_OCR_MON_WRI_DAT_9__M 0x200 |
| 5756 | #define EC_OC_REG_OCR_MON_WRI_DAT_9_DISABLE 0x0 | 5756 | #define EC_OC_REG_OCR_MON_WRI_DAT_9_DISABLE 0x0 |
| 5757 | #define EC_OC_REG_OCR_MON_WRI_DAT_9_ENABLE 0x200 | 5757 | #define EC_OC_REG_OCR_MON_WRI_DAT_9_ENABLE 0x200 |
| 5758 | #define EC_OC_REG_OCR_MON_WRI_VAL__B 10 | 5758 | #define EC_OC_REG_OCR_MON_WRI_VAL__B 10 |
| 5759 | #define EC_OC_REG_OCR_MON_WRI_VAL__W 1 | 5759 | #define EC_OC_REG_OCR_MON_WRI_VAL__W 1 |
| 5760 | #define EC_OC_REG_OCR_MON_WRI_VAL__M 0x400 | 5760 | #define EC_OC_REG_OCR_MON_WRI_VAL__M 0x400 |
| 5761 | #define EC_OC_REG_OCR_MON_WRI_VAL_DISABLE 0x0 | 5761 | #define EC_OC_REG_OCR_MON_WRI_VAL_DISABLE 0x0 |
| 5762 | #define EC_OC_REG_OCR_MON_WRI_VAL_ENABLE 0x400 | 5762 | #define EC_OC_REG_OCR_MON_WRI_VAL_ENABLE 0x400 |
| 5763 | #define EC_OC_REG_OCR_MON_WRI_CLK__B 11 | 5763 | #define EC_OC_REG_OCR_MON_WRI_CLK__B 11 |
| 5764 | #define EC_OC_REG_OCR_MON_WRI_CLK__W 1 | 5764 | #define EC_OC_REG_OCR_MON_WRI_CLK__W 1 |
| 5765 | #define EC_OC_REG_OCR_MON_WRI_CLK__M 0x800 | 5765 | #define EC_OC_REG_OCR_MON_WRI_CLK__M 0x800 |
| 5766 | #define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 | 5766 | #define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 |
| 5767 | #define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 | 5767 | #define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 |
| 5768 | 5768 | ||
| 5769 | #define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B | 5769 | #define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B |
| 5770 | #define EC_OC_REG_OCR_MON_USR_DAT__W 12 | 5770 | #define EC_OC_REG_OCR_MON_USR_DAT__W 12 |
| 5771 | #define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF | 5771 | #define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF |
| 5772 | 5772 | ||
| 5773 | #define EC_OC_REG_OCR_MON_CNT__A 0x215003C | 5773 | #define EC_OC_REG_OCR_MON_CNT__A 0x215003C |
| 5774 | #define EC_OC_REG_OCR_MON_CNT__W 14 | 5774 | #define EC_OC_REG_OCR_MON_CNT__W 14 |
| 5775 | #define EC_OC_REG_OCR_MON_CNT__M 0x3FFF | 5775 | #define EC_OC_REG_OCR_MON_CNT__M 0x3FFF |
| 5776 | #define EC_OC_REG_OCR_MON_CNT_INIT 0x0 | 5776 | #define EC_OC_REG_OCR_MON_CNT_INIT 0x0 |
| 5777 | 5777 | ||
| 5778 | #define EC_OC_REG_OCR_MON_RDX__A 0x215003D | 5778 | #define EC_OC_REG_OCR_MON_RDX__A 0x215003D |
| 5779 | #define EC_OC_REG_OCR_MON_RDX__W 1 | 5779 | #define EC_OC_REG_OCR_MON_RDX__W 1 |
| 5780 | #define EC_OC_REG_OCR_MON_RDX__M 0x1 | 5780 | #define EC_OC_REG_OCR_MON_RDX__M 0x1 |
| 5781 | #define EC_OC_REG_OCR_MON_RDX_INIT 0x0 | 5781 | #define EC_OC_REG_OCR_MON_RDX_INIT 0x0 |
| 5782 | 5782 | ||
| 5783 | #define EC_OC_REG_OCR_MON_RD0__A 0x215003E | 5783 | #define EC_OC_REG_OCR_MON_RD0__A 0x215003E |
| 5784 | #define EC_OC_REG_OCR_MON_RD0__W 10 | 5784 | #define EC_OC_REG_OCR_MON_RD0__W 10 |
| 5785 | #define EC_OC_REG_OCR_MON_RD0__M 0x3FF | 5785 | #define EC_OC_REG_OCR_MON_RD0__M 0x3FF |
| 5786 | 5786 | ||
| 5787 | #define EC_OC_REG_OCR_MON_RD1__A 0x215003F | 5787 | #define EC_OC_REG_OCR_MON_RD1__A 0x215003F |
| 5788 | #define EC_OC_REG_OCR_MON_RD1__W 10 | 5788 | #define EC_OC_REG_OCR_MON_RD1__W 10 |
| 5789 | #define EC_OC_REG_OCR_MON_RD1__M 0x3FF | 5789 | #define EC_OC_REG_OCR_MON_RD1__M 0x3FF |
| 5790 | 5790 | ||
| 5791 | #define EC_OC_REG_OCR_MON_RD2__A 0x2150040 | 5791 | #define EC_OC_REG_OCR_MON_RD2__A 0x2150040 |
| 5792 | #define EC_OC_REG_OCR_MON_RD2__W 10 | 5792 | #define EC_OC_REG_OCR_MON_RD2__W 10 |
| 5793 | #define EC_OC_REG_OCR_MON_RD2__M 0x3FF | 5793 | #define EC_OC_REG_OCR_MON_RD2__M 0x3FF |
| 5794 | 5794 | ||
| 5795 | #define EC_OC_REG_OCR_MON_RD3__A 0x2150041 | 5795 | #define EC_OC_REG_OCR_MON_RD3__A 0x2150041 |
| 5796 | #define EC_OC_REG_OCR_MON_RD3__W 10 | 5796 | #define EC_OC_REG_OCR_MON_RD3__W 10 |
| 5797 | #define EC_OC_REG_OCR_MON_RD3__M 0x3FF | 5797 | #define EC_OC_REG_OCR_MON_RD3__M 0x3FF |
| 5798 | 5798 | ||
| 5799 | #define EC_OC_REG_OCR_MON_RD4__A 0x2150042 | 5799 | #define EC_OC_REG_OCR_MON_RD4__A 0x2150042 |
| 5800 | #define EC_OC_REG_OCR_MON_RD4__W 10 | 5800 | #define EC_OC_REG_OCR_MON_RD4__W 10 |
| 5801 | #define EC_OC_REG_OCR_MON_RD4__M 0x3FF | 5801 | #define EC_OC_REG_OCR_MON_RD4__M 0x3FF |
| 5802 | 5802 | ||
| 5803 | #define EC_OC_REG_OCR_MON_RD5__A 0x2150043 | 5803 | #define EC_OC_REG_OCR_MON_RD5__A 0x2150043 |
| 5804 | #define EC_OC_REG_OCR_MON_RD5__W 10 | 5804 | #define EC_OC_REG_OCR_MON_RD5__W 10 |
| 5805 | #define EC_OC_REG_OCR_MON_RD5__M 0x3FF | 5805 | #define EC_OC_REG_OCR_MON_RD5__M 0x3FF |
| 5806 | 5806 | ||
| 5807 | #define EC_OC_REG_OCR_INV_MON__A 0x2150044 | 5807 | #define EC_OC_REG_OCR_INV_MON__A 0x2150044 |
| 5808 | #define EC_OC_REG_OCR_INV_MON__W 12 | 5808 | #define EC_OC_REG_OCR_INV_MON__W 12 |
| 5809 | #define EC_OC_REG_OCR_INV_MON__M 0xFFF | 5809 | #define EC_OC_REG_OCR_INV_MON__M 0xFFF |
| 5810 | #define EC_OC_REG_OCR_INV_MON_INIT 0x0 | 5810 | #define EC_OC_REG_OCR_INV_MON_INIT 0x0 |
| 5811 | 5811 | ||
| 5812 | #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 | 5812 | #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 |
| 5813 | #define EC_OC_REG_IPR_INV_MPG__W 12 | 5813 | #define EC_OC_REG_IPR_INV_MPG__W 12 |
| 5814 | #define EC_OC_REG_IPR_INV_MPG__M 0xFFF | 5814 | #define EC_OC_REG_IPR_INV_MPG__M 0xFFF |
| 5815 | #define EC_OC_REG_IPR_INV_MPG_INIT 0x0 | 5815 | #define EC_OC_REG_IPR_INV_MPG_INIT 0x0 |
| 5816 | 5816 | ||
| 5817 | #define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 | 5817 | #define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 |
| 5818 | #define EC_OC_REG_IPR_MSR_SNC__W 6 | 5818 | #define EC_OC_REG_IPR_MSR_SNC__W 6 |
| 5819 | #define EC_OC_REG_IPR_MSR_SNC__M 0x3F | 5819 | #define EC_OC_REG_IPR_MSR_SNC__M 0x3F |
| 5820 | #define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 | 5820 | #define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 |
| 5821 | 5821 | ||
| 5822 | #define EC_OC_RAM__A 0x2160000 | 5822 | #define EC_OC_RAM__A 0x2160000 |
| 5823 | 5823 | ||
| 5824 | #define CC_SID 0x1B | 5824 | #define CC_SID 0x1B |
| 5825 | 5825 | ||
| 5826 | #define CC_COMM_EXEC__A 0x2400000 | 5826 | #define CC_COMM_EXEC__A 0x2400000 |
| 5827 | #define CC_COMM_EXEC__W 3 | 5827 | #define CC_COMM_EXEC__W 3 |
| 5828 | #define CC_COMM_EXEC__M 0x7 | 5828 | #define CC_COMM_EXEC__M 0x7 |
| 5829 | #define CC_COMM_EXEC_CTL__B 0 | 5829 | #define CC_COMM_EXEC_CTL__B 0 |
| 5830 | #define CC_COMM_EXEC_CTL__W 3 | 5830 | #define CC_COMM_EXEC_CTL__W 3 |
| 5831 | #define CC_COMM_EXEC_CTL__M 0x7 | 5831 | #define CC_COMM_EXEC_CTL__M 0x7 |
| 5832 | #define CC_COMM_EXEC_CTL_STOP 0x0 | 5832 | #define CC_COMM_EXEC_CTL_STOP 0x0 |
| 5833 | #define CC_COMM_EXEC_CTL_ACTIVE 0x1 | 5833 | #define CC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 5834 | #define CC_COMM_EXEC_CTL_HOLD 0x2 | 5834 | #define CC_COMM_EXEC_CTL_HOLD 0x2 |
| 5835 | #define CC_COMM_EXEC_CTL_STEP 0x3 | 5835 | #define CC_COMM_EXEC_CTL_STEP 0x3 |
| 5836 | #define CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 5836 | #define CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 5837 | #define CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 5837 | #define CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 5838 | 5838 | ||
| 5839 | #define CC_COMM_STATE__A 0x2400001 | 5839 | #define CC_COMM_STATE__A 0x2400001 |
| 5840 | #define CC_COMM_STATE__W 16 | 5840 | #define CC_COMM_STATE__W 16 |
| 5841 | #define CC_COMM_STATE__M 0xFFFF | 5841 | #define CC_COMM_STATE__M 0xFFFF |
| 5842 | #define CC_COMM_MB__A 0x2400002 | 5842 | #define CC_COMM_MB__A 0x2400002 |
| 5843 | #define CC_COMM_MB__W 16 | 5843 | #define CC_COMM_MB__W 16 |
| 5844 | #define CC_COMM_MB__M 0xFFFF | 5844 | #define CC_COMM_MB__M 0xFFFF |
| 5845 | #define CC_COMM_SERVICE0__A 0x2400003 | 5845 | #define CC_COMM_SERVICE0__A 0x2400003 |
| 5846 | #define CC_COMM_SERVICE0__W 16 | 5846 | #define CC_COMM_SERVICE0__W 16 |
| 5847 | #define CC_COMM_SERVICE0__M 0xFFFF | 5847 | #define CC_COMM_SERVICE0__M 0xFFFF |
| 5848 | #define CC_COMM_SERVICE1__A 0x2400004 | 5848 | #define CC_COMM_SERVICE1__A 0x2400004 |
| 5849 | #define CC_COMM_SERVICE1__W 16 | 5849 | #define CC_COMM_SERVICE1__W 16 |
| 5850 | #define CC_COMM_SERVICE1__M 0xFFFF | 5850 | #define CC_COMM_SERVICE1__M 0xFFFF |
| 5851 | #define CC_COMM_INT_STA__A 0x2400007 | 5851 | #define CC_COMM_INT_STA__A 0x2400007 |
| 5852 | #define CC_COMM_INT_STA__W 16 | 5852 | #define CC_COMM_INT_STA__W 16 |
| 5853 | #define CC_COMM_INT_STA__M 0xFFFF | 5853 | #define CC_COMM_INT_STA__M 0xFFFF |
| 5854 | #define CC_COMM_INT_MSK__A 0x2400008 | 5854 | #define CC_COMM_INT_MSK__A 0x2400008 |
| 5855 | #define CC_COMM_INT_MSK__W 16 | 5855 | #define CC_COMM_INT_MSK__W 16 |
| 5856 | #define CC_COMM_INT_MSK__M 0xFFFF | 5856 | #define CC_COMM_INT_MSK__M 0xFFFF |
| 5857 | 5857 | ||
| 5858 | #define CC_REG_COMM_EXEC__A 0x2410000 | 5858 | #define CC_REG_COMM_EXEC__A 0x2410000 |
| 5859 | #define CC_REG_COMM_EXEC__W 3 | 5859 | #define CC_REG_COMM_EXEC__W 3 |
| 5860 | #define CC_REG_COMM_EXEC__M 0x7 | 5860 | #define CC_REG_COMM_EXEC__M 0x7 |
| 5861 | #define CC_REG_COMM_EXEC_CTL__B 0 | 5861 | #define CC_REG_COMM_EXEC_CTL__B 0 |
| 5862 | #define CC_REG_COMM_EXEC_CTL__W 3 | 5862 | #define CC_REG_COMM_EXEC_CTL__W 3 |
| 5863 | #define CC_REG_COMM_EXEC_CTL__M 0x7 | 5863 | #define CC_REG_COMM_EXEC_CTL__M 0x7 |
| 5864 | #define CC_REG_COMM_EXEC_CTL_STOP 0x0 | 5864 | #define CC_REG_COMM_EXEC_CTL_STOP 0x0 |
| 5865 | #define CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 5865 | #define CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 5866 | #define CC_REG_COMM_EXEC_CTL_HOLD 0x2 | 5866 | #define CC_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 5867 | #define CC_REG_COMM_EXEC_CTL_STEP 0x3 | 5867 | #define CC_REG_COMM_EXEC_CTL_STEP 0x3 |
| 5868 | #define CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 5868 | #define CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 5869 | #define CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 5869 | #define CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 5870 | 5870 | ||
| 5871 | #define CC_REG_COMM_STATE__A 0x2410001 | 5871 | #define CC_REG_COMM_STATE__A 0x2410001 |
| 5872 | #define CC_REG_COMM_STATE__W 16 | 5872 | #define CC_REG_COMM_STATE__W 16 |
| 5873 | #define CC_REG_COMM_STATE__M 0xFFFF | 5873 | #define CC_REG_COMM_STATE__M 0xFFFF |
| 5874 | #define CC_REG_COMM_MB__A 0x2410002 | 5874 | #define CC_REG_COMM_MB__A 0x2410002 |
| 5875 | #define CC_REG_COMM_MB__W 16 | 5875 | #define CC_REG_COMM_MB__W 16 |
| 5876 | #define CC_REG_COMM_MB__M 0xFFFF | 5876 | #define CC_REG_COMM_MB__M 0xFFFF |
| 5877 | #define CC_REG_COMM_SERVICE0__A 0x2410003 | 5877 | #define CC_REG_COMM_SERVICE0__A 0x2410003 |
| 5878 | #define CC_REG_COMM_SERVICE0__W 16 | 5878 | #define CC_REG_COMM_SERVICE0__W 16 |
| 5879 | #define CC_REG_COMM_SERVICE0__M 0xFFFF | 5879 | #define CC_REG_COMM_SERVICE0__M 0xFFFF |
| 5880 | #define CC_REG_COMM_SERVICE1__A 0x2410004 | 5880 | #define CC_REG_COMM_SERVICE1__A 0x2410004 |
| 5881 | #define CC_REG_COMM_SERVICE1__W 16 | 5881 | #define CC_REG_COMM_SERVICE1__W 16 |
| 5882 | #define CC_REG_COMM_SERVICE1__M 0xFFFF | 5882 | #define CC_REG_COMM_SERVICE1__M 0xFFFF |
| 5883 | #define CC_REG_COMM_INT_STA__A 0x2410007 | 5883 | #define CC_REG_COMM_INT_STA__A 0x2410007 |
| 5884 | #define CC_REG_COMM_INT_STA__W 16 | 5884 | #define CC_REG_COMM_INT_STA__W 16 |
| 5885 | #define CC_REG_COMM_INT_STA__M 0xFFFF | 5885 | #define CC_REG_COMM_INT_STA__M 0xFFFF |
| 5886 | #define CC_REG_COMM_INT_MSK__A 0x2410008 | 5886 | #define CC_REG_COMM_INT_MSK__A 0x2410008 |
| 5887 | #define CC_REG_COMM_INT_MSK__W 16 | 5887 | #define CC_REG_COMM_INT_MSK__W 16 |
| 5888 | #define CC_REG_COMM_INT_MSK__M 0xFFFF | 5888 | #define CC_REG_COMM_INT_MSK__M 0xFFFF |
| 5889 | 5889 | ||
| 5890 | #define CC_REG_OSC_MODE__A 0x2410010 | 5890 | #define CC_REG_OSC_MODE__A 0x2410010 |
| 5891 | #define CC_REG_OSC_MODE__W 2 | 5891 | #define CC_REG_OSC_MODE__W 2 |
| 5892 | #define CC_REG_OSC_MODE__M 0x3 | 5892 | #define CC_REG_OSC_MODE__M 0x3 |
| 5893 | #define CC_REG_OSC_MODE_OHW 0x0 | 5893 | #define CC_REG_OSC_MODE_OHW 0x0 |
| 5894 | #define CC_REG_OSC_MODE_M20 0x1 | 5894 | #define CC_REG_OSC_MODE_M20 0x1 |
| 5895 | #define CC_REG_OSC_MODE_M48 0x2 | 5895 | #define CC_REG_OSC_MODE_M48 0x2 |
| 5896 | 5896 | ||
| 5897 | #define CC_REG_PLL_MODE__A 0x2410011 | 5897 | #define CC_REG_PLL_MODE__A 0x2410011 |
| 5898 | #define CC_REG_PLL_MODE__W 6 | 5898 | #define CC_REG_PLL_MODE__W 6 |
| 5899 | #define CC_REG_PLL_MODE__M 0x3F | 5899 | #define CC_REG_PLL_MODE__M 0x3F |
| 5900 | #define CC_REG_PLL_MODE_INIT 0xC | 5900 | #define CC_REG_PLL_MODE_INIT 0xC |
| 5901 | #define CC_REG_PLL_MODE_BYPASS__B 0 | 5901 | #define CC_REG_PLL_MODE_BYPASS__B 0 |
| 5902 | #define CC_REG_PLL_MODE_BYPASS__W 2 | 5902 | #define CC_REG_PLL_MODE_BYPASS__W 2 |
| 5903 | #define CC_REG_PLL_MODE_BYPASS__M 0x3 | 5903 | #define CC_REG_PLL_MODE_BYPASS__M 0x3 |
| 5904 | #define CC_REG_PLL_MODE_BYPASS_OHW 0x0 | 5904 | #define CC_REG_PLL_MODE_BYPASS_OHW 0x0 |
| 5905 | #define CC_REG_PLL_MODE_BYPASS_PLL 0x1 | 5905 | #define CC_REG_PLL_MODE_BYPASS_PLL 0x1 |
| 5906 | #define CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 | 5906 | #define CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 |
| 5907 | #define CC_REG_PLL_MODE_PUMP__B 2 | 5907 | #define CC_REG_PLL_MODE_PUMP__B 2 |
| 5908 | #define CC_REG_PLL_MODE_PUMP__W 3 | 5908 | #define CC_REG_PLL_MODE_PUMP__W 3 |
| 5909 | #define CC_REG_PLL_MODE_PUMP__M 0x1C | 5909 | #define CC_REG_PLL_MODE_PUMP__M 0x1C |
| 5910 | #define CC_REG_PLL_MODE_PUMP_OFF 0x0 | 5910 | #define CC_REG_PLL_MODE_PUMP_OFF 0x0 |
| 5911 | #define CC_REG_PLL_MODE_PUMP_CUR_08 0x4 | 5911 | #define CC_REG_PLL_MODE_PUMP_CUR_08 0x4 |
| 5912 | #define CC_REG_PLL_MODE_PUMP_CUR_09 0x8 | 5912 | #define CC_REG_PLL_MODE_PUMP_CUR_09 0x8 |
| 5913 | #define CC_REG_PLL_MODE_PUMP_CUR_10 0xC | 5913 | #define CC_REG_PLL_MODE_PUMP_CUR_10 0xC |
| 5914 | #define CC_REG_PLL_MODE_PUMP_CUR_11 0x10 | 5914 | #define CC_REG_PLL_MODE_PUMP_CUR_11 0x10 |
| 5915 | #define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 | 5915 | #define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 |
| 5916 | #define CC_REG_PLL_MODE_OUT_EN__B 5 | 5916 | #define CC_REG_PLL_MODE_OUT_EN__B 5 |
| 5917 | #define CC_REG_PLL_MODE_OUT_EN__W 1 | 5917 | #define CC_REG_PLL_MODE_OUT_EN__W 1 |
| 5918 | #define CC_REG_PLL_MODE_OUT_EN__M 0x20 | 5918 | #define CC_REG_PLL_MODE_OUT_EN__M 0x20 |
| 5919 | #define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 | 5919 | #define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 |
| 5920 | #define CC_REG_PLL_MODE_OUT_EN_ON 0x20 | 5920 | #define CC_REG_PLL_MODE_OUT_EN_ON 0x20 |
| 5921 | 5921 | ||
| 5922 | #define CC_REG_REF_DIVIDE__A 0x2410012 | 5922 | #define CC_REG_REF_DIVIDE__A 0x2410012 |
| 5923 | #define CC_REG_REF_DIVIDE__W 4 | 5923 | #define CC_REG_REF_DIVIDE__W 4 |
| 5924 | #define CC_REG_REF_DIVIDE__M 0xF | 5924 | #define CC_REG_REF_DIVIDE__M 0xF |
| 5925 | #define CC_REG_REF_DIVIDE_INIT 0xA | 5925 | #define CC_REG_REF_DIVIDE_INIT 0xA |
| 5926 | #define CC_REG_REF_DIVIDE_OHW 0x0 | 5926 | #define CC_REG_REF_DIVIDE_OHW 0x0 |
| 5927 | #define CC_REG_REF_DIVIDE_D01 0x1 | 5927 | #define CC_REG_REF_DIVIDE_D01 0x1 |
| 5928 | #define CC_REG_REF_DIVIDE_D02 0x2 | 5928 | #define CC_REG_REF_DIVIDE_D02 0x2 |
| 5929 | #define CC_REG_REF_DIVIDE_D03 0x3 | 5929 | #define CC_REG_REF_DIVIDE_D03 0x3 |
| 5930 | #define CC_REG_REF_DIVIDE_D04 0x4 | 5930 | #define CC_REG_REF_DIVIDE_D04 0x4 |
| 5931 | #define CC_REG_REF_DIVIDE_D05 0x5 | 5931 | #define CC_REG_REF_DIVIDE_D05 0x5 |
| 5932 | #define CC_REG_REF_DIVIDE_D06 0x6 | 5932 | #define CC_REG_REF_DIVIDE_D06 0x6 |
| 5933 | #define CC_REG_REF_DIVIDE_D07 0x7 | 5933 | #define CC_REG_REF_DIVIDE_D07 0x7 |
| 5934 | #define CC_REG_REF_DIVIDE_D08 0x8 | 5934 | #define CC_REG_REF_DIVIDE_D08 0x8 |
| 5935 | #define CC_REG_REF_DIVIDE_D09 0x9 | 5935 | #define CC_REG_REF_DIVIDE_D09 0x9 |
| 5936 | #define CC_REG_REF_DIVIDE_D10 0xA | 5936 | #define CC_REG_REF_DIVIDE_D10 0xA |
| 5937 | 5937 | ||
| 5938 | #define CC_REG_REF_DELAY__A 0x2410013 | 5938 | #define CC_REG_REF_DELAY__A 0x2410013 |
| 5939 | #define CC_REG_REF_DELAY__W 3 | 5939 | #define CC_REG_REF_DELAY__W 3 |
| 5940 | #define CC_REG_REF_DELAY__M 0x7 | 5940 | #define CC_REG_REF_DELAY__M 0x7 |
| 5941 | #define CC_REG_REF_DELAY_EDGE__B 0 | 5941 | #define CC_REG_REF_DELAY_EDGE__B 0 |
| 5942 | #define CC_REG_REF_DELAY_EDGE__W 1 | 5942 | #define CC_REG_REF_DELAY_EDGE__W 1 |
| 5943 | #define CC_REG_REF_DELAY_EDGE__M 0x1 | 5943 | #define CC_REG_REF_DELAY_EDGE__M 0x1 |
| 5944 | #define CC_REG_REF_DELAY_EDGE_POS 0x0 | 5944 | #define CC_REG_REF_DELAY_EDGE_POS 0x0 |
| 5945 | #define CC_REG_REF_DELAY_EDGE_NEG 0x1 | 5945 | #define CC_REG_REF_DELAY_EDGE_NEG 0x1 |
| 5946 | #define CC_REG_REF_DELAY_DELAY__B 1 | 5946 | #define CC_REG_REF_DELAY_DELAY__B 1 |
| 5947 | #define CC_REG_REF_DELAY_DELAY__W 2 | 5947 | #define CC_REG_REF_DELAY_DELAY__W 2 |
| 5948 | #define CC_REG_REF_DELAY_DELAY__M 0x6 | 5948 | #define CC_REG_REF_DELAY_DELAY__M 0x6 |
| 5949 | #define CC_REG_REF_DELAY_DELAY_DEL_0 0x0 | 5949 | #define CC_REG_REF_DELAY_DELAY_DEL_0 0x0 |
| 5950 | #define CC_REG_REF_DELAY_DELAY_DEL_3 0x2 | 5950 | #define CC_REG_REF_DELAY_DELAY_DEL_3 0x2 |
| 5951 | #define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 | 5951 | #define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 |
| 5952 | #define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 | 5952 | #define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 |
| 5953 | 5953 | ||
| 5954 | #define CC_REG_CLK_DELAY__A 0x2410014 | 5954 | #define CC_REG_CLK_DELAY__A 0x2410014 |
| 5955 | #define CC_REG_CLK_DELAY__W 4 | 5955 | #define CC_REG_CLK_DELAY__W 4 |
| 5956 | #define CC_REG_CLK_DELAY__M 0xF | 5956 | #define CC_REG_CLK_DELAY__M 0xF |
| 5957 | #define CC_REG_CLK_DELAY_OFF 0x0 | 5957 | #define CC_REG_CLK_DELAY_OFF 0x0 |
| 5958 | 5958 | ||
| 5959 | #define CC_REG_PWD_MODE__A 0x2410015 | 5959 | #define CC_REG_PWD_MODE__A 0x2410015 |
| 5960 | #define CC_REG_PWD_MODE__W 2 | 5960 | #define CC_REG_PWD_MODE__W 2 |
| 5961 | #define CC_REG_PWD_MODE__M 0x3 | 5961 | #define CC_REG_PWD_MODE__M 0x3 |
| 5962 | #define CC_REG_PWD_MODE_UP 0x0 | 5962 | #define CC_REG_PWD_MODE_UP 0x0 |
| 5963 | #define CC_REG_PWD_MODE_DOWN_CLK 0x1 | 5963 | #define CC_REG_PWD_MODE_DOWN_CLK 0x1 |
| 5964 | #define CC_REG_PWD_MODE_DOWN_PLL 0x2 | 5964 | #define CC_REG_PWD_MODE_DOWN_PLL 0x2 |
| 5965 | #define CC_REG_PWD_MODE_DOWN_OSC 0x3 | 5965 | #define CC_REG_PWD_MODE_DOWN_OSC 0x3 |
| 5966 | 5966 | ||
| 5967 | #define CC_REG_SOFT_RST__A 0x2410016 | 5967 | #define CC_REG_SOFT_RST__A 0x2410016 |
| 5968 | #define CC_REG_SOFT_RST__W 2 | 5968 | #define CC_REG_SOFT_RST__W 2 |
| 5969 | #define CC_REG_SOFT_RST__M 0x3 | 5969 | #define CC_REG_SOFT_RST__M 0x3 |
| 5970 | #define CC_REG_SOFT_RST_SYS__B 0 | 5970 | #define CC_REG_SOFT_RST_SYS__B 0 |
| 5971 | #define CC_REG_SOFT_RST_SYS__W 1 | 5971 | #define CC_REG_SOFT_RST_SYS__W 1 |
| 5972 | #define CC_REG_SOFT_RST_SYS__M 0x1 | 5972 | #define CC_REG_SOFT_RST_SYS__M 0x1 |
| 5973 | #define CC_REG_SOFT_RST_OSC__B 1 | 5973 | #define CC_REG_SOFT_RST_OSC__B 1 |
| 5974 | #define CC_REG_SOFT_RST_OSC__W 1 | 5974 | #define CC_REG_SOFT_RST_OSC__W 1 |
| 5975 | #define CC_REG_SOFT_RST_OSC__M 0x2 | 5975 | #define CC_REG_SOFT_RST_OSC__M 0x2 |
| 5976 | 5976 | ||
| 5977 | #define CC_REG_UPDATE__A 0x2410017 | 5977 | #define CC_REG_UPDATE__A 0x2410017 |
| 5978 | #define CC_REG_UPDATE__W 16 | 5978 | #define CC_REG_UPDATE__W 16 |
| 5979 | #define CC_REG_UPDATE__M 0xFFFF | 5979 | #define CC_REG_UPDATE__M 0xFFFF |
| 5980 | #define CC_REG_UPDATE_KEY 0x3973 | 5980 | #define CC_REG_UPDATE_KEY 0x3973 |
| 5981 | 5981 | ||
| 5982 | #define CC_REG_PLL_LOCK__A 0x2410018 | 5982 | #define CC_REG_PLL_LOCK__A 0x2410018 |
| 5983 | #define CC_REG_PLL_LOCK__W 1 | 5983 | #define CC_REG_PLL_LOCK__W 1 |
| 5984 | #define CC_REG_PLL_LOCK__M 0x1 | 5984 | #define CC_REG_PLL_LOCK__M 0x1 |
| 5985 | #define CC_REG_PLL_LOCK_LOCK 0x1 | 5985 | #define CC_REG_PLL_LOCK_LOCK 0x1 |
| 5986 | 5986 | ||
| 5987 | #define CC_REG_JTAGID_L__A 0x2410019 | 5987 | #define CC_REG_JTAGID_L__A 0x2410019 |
| 5988 | #define CC_REG_JTAGID_L__W 16 | 5988 | #define CC_REG_JTAGID_L__W 16 |
| 5989 | #define CC_REG_JTAGID_L__M 0xFFFF | 5989 | #define CC_REG_JTAGID_L__M 0xFFFF |
| 5990 | #define CC_REG_JTAGID_L_INIT 0x0 | 5990 | #define CC_REG_JTAGID_L_INIT 0x0 |
| 5991 | 5991 | ||
| 5992 | #define CC_REG_JTAGID_H__A 0x241001A | 5992 | #define CC_REG_JTAGID_H__A 0x241001A |
| 5993 | #define CC_REG_JTAGID_H__W 16 | 5993 | #define CC_REG_JTAGID_H__W 16 |
| 5994 | #define CC_REG_JTAGID_H__M 0xFFFF | 5994 | #define CC_REG_JTAGID_H__M 0xFFFF |
| 5995 | #define CC_REG_JTAGID_H_INIT 0x0 | 5995 | #define CC_REG_JTAGID_H_INIT 0x0 |
| 5996 | 5996 | ||
| 5997 | #define LC_SID 0x1C | 5997 | #define LC_SID 0x1C |
| 5998 | 5998 | ||
| 5999 | #define LC_COMM_EXEC__A 0x2800000 | 5999 | #define LC_COMM_EXEC__A 0x2800000 |
| 6000 | #define LC_COMM_EXEC__W 3 | 6000 | #define LC_COMM_EXEC__W 3 |
| 6001 | #define LC_COMM_EXEC__M 0x7 | 6001 | #define LC_COMM_EXEC__M 0x7 |
| 6002 | #define LC_COMM_EXEC_CTL__B 0 | 6002 | #define LC_COMM_EXEC_CTL__B 0 |
| 6003 | #define LC_COMM_EXEC_CTL__W 3 | 6003 | #define LC_COMM_EXEC_CTL__W 3 |
| 6004 | #define LC_COMM_EXEC_CTL__M 0x7 | 6004 | #define LC_COMM_EXEC_CTL__M 0x7 |
| 6005 | #define LC_COMM_EXEC_CTL_STOP 0x0 | 6005 | #define LC_COMM_EXEC_CTL_STOP 0x0 |
| 6006 | #define LC_COMM_EXEC_CTL_ACTIVE 0x1 | 6006 | #define LC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 6007 | #define LC_COMM_EXEC_CTL_HOLD 0x2 | 6007 | #define LC_COMM_EXEC_CTL_HOLD 0x2 |
| 6008 | #define LC_COMM_EXEC_CTL_STEP 0x3 | 6008 | #define LC_COMM_EXEC_CTL_STEP 0x3 |
| 6009 | #define LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 6009 | #define LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 6010 | #define LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 6010 | #define LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 6011 | 6011 | ||
| 6012 | #define LC_COMM_STATE__A 0x2800001 | 6012 | #define LC_COMM_STATE__A 0x2800001 |
| 6013 | #define LC_COMM_STATE__W 16 | 6013 | #define LC_COMM_STATE__W 16 |
| 6014 | #define LC_COMM_STATE__M 0xFFFF | 6014 | #define LC_COMM_STATE__M 0xFFFF |
| 6015 | #define LC_COMM_MB__A 0x2800002 | 6015 | #define LC_COMM_MB__A 0x2800002 |
| 6016 | #define LC_COMM_MB__W 16 | 6016 | #define LC_COMM_MB__W 16 |
| 6017 | #define LC_COMM_MB__M 0xFFFF | 6017 | #define LC_COMM_MB__M 0xFFFF |
| 6018 | #define LC_COMM_SERVICE0__A 0x2800003 | 6018 | #define LC_COMM_SERVICE0__A 0x2800003 |
| 6019 | #define LC_COMM_SERVICE0__W 16 | 6019 | #define LC_COMM_SERVICE0__W 16 |
| 6020 | #define LC_COMM_SERVICE0__M 0xFFFF | 6020 | #define LC_COMM_SERVICE0__M 0xFFFF |
| 6021 | #define LC_COMM_SERVICE1__A 0x2800004 | 6021 | #define LC_COMM_SERVICE1__A 0x2800004 |
| 6022 | #define LC_COMM_SERVICE1__W 16 | 6022 | #define LC_COMM_SERVICE1__W 16 |
| 6023 | #define LC_COMM_SERVICE1__M 0xFFFF | 6023 | #define LC_COMM_SERVICE1__M 0xFFFF |
| 6024 | #define LC_COMM_INT_STA__A 0x2800007 | 6024 | #define LC_COMM_INT_STA__A 0x2800007 |
| 6025 | #define LC_COMM_INT_STA__W 16 | 6025 | #define LC_COMM_INT_STA__W 16 |
| 6026 | #define LC_COMM_INT_STA__M 0xFFFF | 6026 | #define LC_COMM_INT_STA__M 0xFFFF |
| 6027 | #define LC_COMM_INT_MSK__A 0x2800008 | 6027 | #define LC_COMM_INT_MSK__A 0x2800008 |
| 6028 | #define LC_COMM_INT_MSK__W 16 | 6028 | #define LC_COMM_INT_MSK__W 16 |
| 6029 | #define LC_COMM_INT_MSK__M 0xFFFF | 6029 | #define LC_COMM_INT_MSK__M 0xFFFF |
| 6030 | 6030 | ||
| 6031 | #define LC_CT_REG_COMM_EXEC__A 0x2810000 | 6031 | #define LC_CT_REG_COMM_EXEC__A 0x2810000 |
| 6032 | #define LC_CT_REG_COMM_EXEC__W 3 | 6032 | #define LC_CT_REG_COMM_EXEC__W 3 |
| 6033 | #define LC_CT_REG_COMM_EXEC__M 0x7 | 6033 | #define LC_CT_REG_COMM_EXEC__M 0x7 |
| 6034 | #define LC_CT_REG_COMM_EXEC_CTL__B 0 | 6034 | #define LC_CT_REG_COMM_EXEC_CTL__B 0 |
| 6035 | #define LC_CT_REG_COMM_EXEC_CTL__W 3 | 6035 | #define LC_CT_REG_COMM_EXEC_CTL__W 3 |
| 6036 | #define LC_CT_REG_COMM_EXEC_CTL__M 0x7 | 6036 | #define LC_CT_REG_COMM_EXEC_CTL__M 0x7 |
| 6037 | #define LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 | 6037 | #define LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 6038 | #define LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 6038 | #define LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 6039 | #define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 | 6039 | #define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 6040 | #define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 | 6040 | #define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 6041 | 6041 | ||
| 6042 | #define LC_CT_REG_COMM_STATE__A 0x2810001 | 6042 | #define LC_CT_REG_COMM_STATE__A 0x2810001 |
| 6043 | #define LC_CT_REG_COMM_STATE__W 10 | 6043 | #define LC_CT_REG_COMM_STATE__W 10 |
| 6044 | #define LC_CT_REG_COMM_STATE__M 0x3FF | 6044 | #define LC_CT_REG_COMM_STATE__M 0x3FF |
| 6045 | #define LC_CT_REG_COMM_SERVICE0__A 0x2810003 | 6045 | #define LC_CT_REG_COMM_SERVICE0__A 0x2810003 |
| 6046 | #define LC_CT_REG_COMM_SERVICE0__W 16 | 6046 | #define LC_CT_REG_COMM_SERVICE0__W 16 |
| 6047 | #define LC_CT_REG_COMM_SERVICE0__M 0xFFFF | 6047 | #define LC_CT_REG_COMM_SERVICE0__M 0xFFFF |
| 6048 | #define LC_CT_REG_COMM_SERVICE1__A 0x2810004 | 6048 | #define LC_CT_REG_COMM_SERVICE1__A 0x2810004 |
| 6049 | #define LC_CT_REG_COMM_SERVICE1__W 16 | 6049 | #define LC_CT_REG_COMM_SERVICE1__W 16 |
| 6050 | #define LC_CT_REG_COMM_SERVICE1__M 0xFFFF | 6050 | #define LC_CT_REG_COMM_SERVICE1__M 0xFFFF |
| 6051 | #define LC_CT_REG_COMM_SERVICE1_LC__B 12 | 6051 | #define LC_CT_REG_COMM_SERVICE1_LC__B 12 |
| 6052 | #define LC_CT_REG_COMM_SERVICE1_LC__W 1 | 6052 | #define LC_CT_REG_COMM_SERVICE1_LC__W 1 |
| 6053 | #define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 | 6053 | #define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 |
| 6054 | 6054 | ||
| 6055 | #define LC_CT_REG_COMM_INT_STA__A 0x2810007 | 6055 | #define LC_CT_REG_COMM_INT_STA__A 0x2810007 |
| 6056 | #define LC_CT_REG_COMM_INT_STA__W 1 | 6056 | #define LC_CT_REG_COMM_INT_STA__W 1 |
| 6057 | #define LC_CT_REG_COMM_INT_STA__M 0x1 | 6057 | #define LC_CT_REG_COMM_INT_STA__M 0x1 |
| 6058 | #define LC_CT_REG_COMM_INT_STA_REQUEST__B 0 | 6058 | #define LC_CT_REG_COMM_INT_STA_REQUEST__B 0 |
| 6059 | #define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 | 6059 | #define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 |
| 6060 | #define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 | 6060 | #define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 |
| 6061 | 6061 | ||
| 6062 | #define LC_CT_REG_COMM_INT_MSK__A 0x2810008 | 6062 | #define LC_CT_REG_COMM_INT_MSK__A 0x2810008 |
| 6063 | #define LC_CT_REG_COMM_INT_MSK__W 1 | 6063 | #define LC_CT_REG_COMM_INT_MSK__W 1 |
| 6064 | #define LC_CT_REG_COMM_INT_MSK__M 0x1 | 6064 | #define LC_CT_REG_COMM_INT_MSK__M 0x1 |
| 6065 | #define LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 | 6065 | #define LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 |
| 6066 | #define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 | 6066 | #define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 |
| 6067 | #define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 | 6067 | #define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 |
| 6068 | 6068 | ||
| 6069 | #define LC_CT_REG_CTL_STK__AX 0x2810010 | 6069 | #define LC_CT_REG_CTL_STK__AX 0x2810010 |
| 6070 | #define LC_CT_REG_CTL_STK__XSZ 4 | 6070 | #define LC_CT_REG_CTL_STK__XSZ 4 |
| 6071 | #define LC_CT_REG_CTL_STK__W 10 | 6071 | #define LC_CT_REG_CTL_STK__W 10 |
| 6072 | #define LC_CT_REG_CTL_STK__M 0x3FF | 6072 | #define LC_CT_REG_CTL_STK__M 0x3FF |
| 6073 | 6073 | ||
| 6074 | #define LC_CT_REG_CTL_BPT_IDX__A 0x281001F | 6074 | #define LC_CT_REG_CTL_BPT_IDX__A 0x281001F |
| 6075 | #define LC_CT_REG_CTL_BPT_IDX__W 1 | 6075 | #define LC_CT_REG_CTL_BPT_IDX__W 1 |
| 6076 | #define LC_CT_REG_CTL_BPT_IDX__M 0x1 | 6076 | #define LC_CT_REG_CTL_BPT_IDX__M 0x1 |
| 6077 | 6077 | ||
| 6078 | #define LC_CT_REG_CTL_BPT__A 0x2810020 | 6078 | #define LC_CT_REG_CTL_BPT__A 0x2810020 |
| 6079 | #define LC_CT_REG_CTL_BPT__W 10 | 6079 | #define LC_CT_REG_CTL_BPT__W 10 |
| 6080 | #define LC_CT_REG_CTL_BPT__M 0x3FF | 6080 | #define LC_CT_REG_CTL_BPT__M 0x3FF |
| 6081 | 6081 | ||
| 6082 | #define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 | 6082 | #define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 |
| 6083 | #define LC_RA_RAM_PROC_DELAY_IF__W 16 | 6083 | #define LC_RA_RAM_PROC_DELAY_IF__W 16 |
| 6084 | #define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF | 6084 | #define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF |
| 6085 | #define LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 | 6085 | #define LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 |
| 6086 | #define LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 | 6086 | #define LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 |
| 6087 | #define LC_RA_RAM_PROC_DELAY_FS__W 16 | 6087 | #define LC_RA_RAM_PROC_DELAY_FS__W 16 |
| 6088 | #define LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF | 6088 | #define LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF |
| 6089 | #define LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 | 6089 | #define LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 |
| 6090 | #define LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 | 6090 | #define LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 |
| 6091 | #define LC_RA_RAM_LOCK_TH_CRMM__W 16 | 6091 | #define LC_RA_RAM_LOCK_TH_CRMM__W 16 |
| 6092 | #define LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF | 6092 | #define LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF |
| 6093 | #define LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 | 6093 | #define LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 |
| 6094 | #define LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 | 6094 | #define LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 |
| 6095 | #define LC_RA_RAM_LOCK_TH_SRMM__W 16 | 6095 | #define LC_RA_RAM_LOCK_TH_SRMM__W 16 |
| 6096 | #define LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF | 6096 | #define LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF |
| 6097 | #define LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 | 6097 | #define LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 |
| 6098 | #define LC_RA_RAM_LOCK_COUNT__A 0x282000A | 6098 | #define LC_RA_RAM_LOCK_COUNT__A 0x282000A |
| 6099 | #define LC_RA_RAM_LOCK_COUNT__W 16 | 6099 | #define LC_RA_RAM_LOCK_COUNT__W 16 |
| 6100 | #define LC_RA_RAM_LOCK_COUNT__M 0xFFFF | 6100 | #define LC_RA_RAM_LOCK_COUNT__M 0xFFFF |
| 6101 | #define LC_RA_RAM_CPRTOFS_NOM__A 0x282000B | 6101 | #define LC_RA_RAM_CPRTOFS_NOM__A 0x282000B |
| 6102 | #define LC_RA_RAM_CPRTOFS_NOM__W 16 | 6102 | #define LC_RA_RAM_CPRTOFS_NOM__W 16 |
| 6103 | #define LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF | 6103 | #define LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF |
| 6104 | #define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C | 6104 | #define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C |
| 6105 | #define LC_RA_RAM_IFINCR_NOM_L__W 16 | 6105 | #define LC_RA_RAM_IFINCR_NOM_L__W 16 |
| 6106 | #define LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF | 6106 | #define LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF |
| 6107 | #define LC_RA_RAM_IFINCR_NOM_H__A 0x282000D | 6107 | #define LC_RA_RAM_IFINCR_NOM_H__A 0x282000D |
| 6108 | #define LC_RA_RAM_IFINCR_NOM_H__W 16 | 6108 | #define LC_RA_RAM_IFINCR_NOM_H__W 16 |
| 6109 | #define LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF | 6109 | #define LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF |
| 6110 | #define LC_RA_RAM_FSINCR_NOM_L__A 0x282000E | 6110 | #define LC_RA_RAM_FSINCR_NOM_L__A 0x282000E |
| 6111 | #define LC_RA_RAM_FSINCR_NOM_L__W 16 | 6111 | #define LC_RA_RAM_FSINCR_NOM_L__W 16 |
| 6112 | #define LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF | 6112 | #define LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF |
| 6113 | #define LC_RA_RAM_FSINCR_NOM_H__A 0x282000F | 6113 | #define LC_RA_RAM_FSINCR_NOM_H__A 0x282000F |
| 6114 | #define LC_RA_RAM_FSINCR_NOM_H__W 16 | 6114 | #define LC_RA_RAM_FSINCR_NOM_H__W 16 |
| 6115 | #define LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF | 6115 | #define LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF |
| 6116 | #define LC_RA_RAM_MODE_2K__A 0x2820010 | 6116 | #define LC_RA_RAM_MODE_2K__A 0x2820010 |
| 6117 | #define LC_RA_RAM_MODE_2K__W 16 | 6117 | #define LC_RA_RAM_MODE_2K__W 16 |
| 6118 | #define LC_RA_RAM_MODE_2K__M 0xFFFF | 6118 | #define LC_RA_RAM_MODE_2K__M 0xFFFF |
| 6119 | #define LC_RA_RAM_MODE_GUARD__A 0x2820011 | 6119 | #define LC_RA_RAM_MODE_GUARD__A 0x2820011 |
| 6120 | #define LC_RA_RAM_MODE_GUARD__W 16 | 6120 | #define LC_RA_RAM_MODE_GUARD__W 16 |
| 6121 | #define LC_RA_RAM_MODE_GUARD__M 0xFFFF | 6121 | #define LC_RA_RAM_MODE_GUARD__M 0xFFFF |
| 6122 | #define LC_RA_RAM_MODE_GUARD_32 0x0 | 6122 | #define LC_RA_RAM_MODE_GUARD_32 0x0 |
| 6123 | #define LC_RA_RAM_MODE_GUARD_16 0x1 | 6123 | #define LC_RA_RAM_MODE_GUARD_16 0x1 |
| 6124 | #define LC_RA_RAM_MODE_GUARD_8 0x2 | 6124 | #define LC_RA_RAM_MODE_GUARD_8 0x2 |
| 6125 | #define LC_RA_RAM_MODE_GUARD_4 0x3 | 6125 | #define LC_RA_RAM_MODE_GUARD_4 0x3 |
| 6126 | 6126 | ||
| 6127 | #define LC_RA_RAM_MODE_ADJUST__A 0x2820012 | 6127 | #define LC_RA_RAM_MODE_ADJUST__A 0x2820012 |
| 6128 | #define LC_RA_RAM_MODE_ADJUST__W 16 | 6128 | #define LC_RA_RAM_MODE_ADJUST__W 16 |
| 6129 | #define LC_RA_RAM_MODE_ADJUST__M 0xFFFF | 6129 | #define LC_RA_RAM_MODE_ADJUST__M 0xFFFF |
| 6130 | #define LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 | 6130 | #define LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 |
| 6131 | #define LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 | 6131 | #define LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 |
| 6132 | #define LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 | 6132 | #define LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 |
| 6133 | #define LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 | 6133 | #define LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 |
| 6134 | #define LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 | 6134 | #define LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 |
| 6135 | #define LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 | 6135 | #define LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 |
| 6136 | #define LC_RA_RAM_MODE_ADJUST_SRMM__B 2 | 6136 | #define LC_RA_RAM_MODE_ADJUST_SRMM__B 2 |
| 6137 | #define LC_RA_RAM_MODE_ADJUST_SRMM__W 1 | 6137 | #define LC_RA_RAM_MODE_ADJUST_SRMM__W 1 |
| 6138 | #define LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 | 6138 | #define LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 |
| 6139 | #define LC_RA_RAM_MODE_ADJUST_PHASE__B 3 | 6139 | #define LC_RA_RAM_MODE_ADJUST_PHASE__B 3 |
| 6140 | #define LC_RA_RAM_MODE_ADJUST_PHASE__W 1 | 6140 | #define LC_RA_RAM_MODE_ADJUST_PHASE__W 1 |
| 6141 | #define LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 | 6141 | #define LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 |
| 6142 | #define LC_RA_RAM_MODE_ADJUST_DELAY__B 4 | 6142 | #define LC_RA_RAM_MODE_ADJUST_DELAY__B 4 |
| 6143 | #define LC_RA_RAM_MODE_ADJUST_DELAY__W 1 | 6143 | #define LC_RA_RAM_MODE_ADJUST_DELAY__W 1 |
| 6144 | #define LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 | 6144 | #define LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 |
| 6145 | #define LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 | 6145 | #define LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 |
| 6146 | #define LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 | 6146 | #define LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 |
| 6147 | #define LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 | 6147 | #define LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 |
| 6148 | #define LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 | 6148 | #define LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 |
| 6149 | #define LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 | 6149 | #define LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 |
| 6150 | #define LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 | 6150 | #define LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 |
| 6151 | #define LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 | 6151 | #define LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 |
| 6152 | #define LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 | 6152 | #define LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 |
| 6153 | #define LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 | 6153 | #define LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 |
| 6154 | #define LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 | 6154 | #define LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 |
| 6155 | #define LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 | 6155 | #define LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 |
| 6156 | #define LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 | 6156 | #define LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 |
| 6157 | #define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 | 6157 | #define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 |
| 6158 | #define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 | 6158 | #define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 |
| 6159 | #define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 | 6159 | #define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 |
| 6160 | 6160 | ||
| 6161 | #define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A | 6161 | #define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A |
| 6162 | #define LC_RA_RAM_FILTER_SYM_SET__W 16 | 6162 | #define LC_RA_RAM_FILTER_SYM_SET__W 16 |
| 6163 | #define LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF | 6163 | #define LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF |
| 6164 | #define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 | 6164 | #define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 |
| 6165 | #define LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B | 6165 | #define LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B |
| 6166 | #define LC_RA_RAM_FILTER_SYM_CUR__W 16 | 6166 | #define LC_RA_RAM_FILTER_SYM_CUR__W 16 |
| 6167 | #define LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF | 6167 | #define LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF |
| 6168 | #define LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 | 6168 | #define LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 |
| 6169 | #define LC_RA_RAM_MAX_ABS_EXP__A 0x282001D | 6169 | #define LC_RA_RAM_MAX_ABS_EXP__A 0x282001D |
| 6170 | #define LC_RA_RAM_MAX_ABS_EXP__W 16 | 6170 | #define LC_RA_RAM_MAX_ABS_EXP__W 16 |
| 6171 | #define LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF | 6171 | #define LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF |
| 6172 | #define LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 | 6172 | #define LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 |
| 6173 | #define LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F | 6173 | #define LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F |
| 6174 | #define LC_RA_RAM_ACTUAL_CP_CRMM__W 16 | 6174 | #define LC_RA_RAM_ACTUAL_CP_CRMM__W 16 |
| 6175 | #define LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF | 6175 | #define LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF |
| 6176 | #define LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 | 6176 | #define LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 |
| 6177 | #define LC_RA_RAM_ACTUAL_CE_CRMM__W 16 | 6177 | #define LC_RA_RAM_ACTUAL_CE_CRMM__W 16 |
| 6178 | #define LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF | 6178 | #define LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF |
| 6179 | #define LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 | 6179 | #define LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 |
| 6180 | #define LC_RA_RAM_ACTUAL_CE_SRMM__W 16 | 6180 | #define LC_RA_RAM_ACTUAL_CE_SRMM__W 16 |
| 6181 | #define LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF | 6181 | #define LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF |
| 6182 | #define LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 | 6182 | #define LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 |
| 6183 | #define LC_RA_RAM_ACTUAL_PHASE__W 16 | 6183 | #define LC_RA_RAM_ACTUAL_PHASE__W 16 |
| 6184 | #define LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF | 6184 | #define LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF |
| 6185 | #define LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 | 6185 | #define LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 |
| 6186 | #define LC_RA_RAM_ACTUAL_DELAY__W 16 | 6186 | #define LC_RA_RAM_ACTUAL_DELAY__W 16 |
| 6187 | #define LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF | 6187 | #define LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF |
| 6188 | #define LC_RA_RAM_ADJUST_CRMM__A 0x2820024 | 6188 | #define LC_RA_RAM_ADJUST_CRMM__A 0x2820024 |
| 6189 | #define LC_RA_RAM_ADJUST_CRMM__W 16 | 6189 | #define LC_RA_RAM_ADJUST_CRMM__W 16 |
| 6190 | #define LC_RA_RAM_ADJUST_CRMM__M 0xFFFF | 6190 | #define LC_RA_RAM_ADJUST_CRMM__M 0xFFFF |
| 6191 | #define LC_RA_RAM_ADJUST_SRMM__A 0x2820025 | 6191 | #define LC_RA_RAM_ADJUST_SRMM__A 0x2820025 |
| 6192 | #define LC_RA_RAM_ADJUST_SRMM__W 16 | 6192 | #define LC_RA_RAM_ADJUST_SRMM__W 16 |
| 6193 | #define LC_RA_RAM_ADJUST_SRMM__M 0xFFFF | 6193 | #define LC_RA_RAM_ADJUST_SRMM__M 0xFFFF |
| 6194 | #define LC_RA_RAM_ADJUST_PHASE__A 0x2820026 | 6194 | #define LC_RA_RAM_ADJUST_PHASE__A 0x2820026 |
| 6195 | #define LC_RA_RAM_ADJUST_PHASE__W 16 | 6195 | #define LC_RA_RAM_ADJUST_PHASE__W 16 |
| 6196 | #define LC_RA_RAM_ADJUST_PHASE__M 0xFFFF | 6196 | #define LC_RA_RAM_ADJUST_PHASE__M 0xFFFF |
| 6197 | #define LC_RA_RAM_ADJUST_DELAY__A 0x2820027 | 6197 | #define LC_RA_RAM_ADJUST_DELAY__A 0x2820027 |
| 6198 | #define LC_RA_RAM_ADJUST_DELAY__W 16 | 6198 | #define LC_RA_RAM_ADJUST_DELAY__W 16 |
| 6199 | #define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF | 6199 | #define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF |
| 6200 | 6200 | ||
| 6201 | #define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 | 6201 | #define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 |
| 6202 | #define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 | 6202 | #define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 |
| 6203 | #define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF | 6203 | #define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF |
| 6204 | #define LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 | 6204 | #define LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 |
| 6205 | #define LC_RA_RAM_PIPE_CP_PHASE_1__W 16 | 6205 | #define LC_RA_RAM_PIPE_CP_PHASE_1__W 16 |
| 6206 | #define LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF | 6206 | #define LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF |
| 6207 | #define LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A | 6207 | #define LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A |
| 6208 | #define LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 | 6208 | #define LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 |
| 6209 | #define LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF | 6209 | #define LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF |
| 6210 | #define LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B | 6210 | #define LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B |
| 6211 | #define LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 | 6211 | #define LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 |
| 6212 | #define LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF | 6212 | #define LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF |
| 6213 | #define LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C | 6213 | #define LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C |
| 6214 | #define LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 | 6214 | #define LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 |
| 6215 | #define LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF | 6215 | #define LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF |
| 6216 | #define LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D | 6216 | #define LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D |
| 6217 | #define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 | 6217 | #define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 |
| 6218 | #define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF | 6218 | #define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF |
| 6219 | 6219 | ||
| 6220 | #define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 | 6220 | #define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 |
| 6221 | #define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 | 6221 | #define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 |
| 6222 | #define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF | 6222 | #define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF |
| 6223 | #define LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 | 6223 | #define LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 |
| 6224 | #define LC_RA_RAM_PIPE_CP_CRMM_1__W 16 | 6224 | #define LC_RA_RAM_PIPE_CP_CRMM_1__W 16 |
| 6225 | #define LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF | 6225 | #define LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF |
| 6226 | #define LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 | 6226 | #define LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 |
| 6227 | #define LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 | 6227 | #define LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 |
| 6228 | #define LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF | 6228 | #define LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF |
| 6229 | #define LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 | 6229 | #define LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 |
| 6230 | #define LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 | 6230 | #define LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 |
| 6231 | #define LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF | 6231 | #define LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF |
| 6232 | #define LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 | 6232 | #define LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 |
| 6233 | #define LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 | 6233 | #define LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 |
| 6234 | #define LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF | 6234 | #define LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF |
| 6235 | #define LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 | 6235 | #define LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 |
| 6236 | #define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 | 6236 | #define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 |
| 6237 | #define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF | 6237 | #define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF |
| 6238 | 6238 | ||
| 6239 | #define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 | 6239 | #define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 |
| 6240 | #define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 | 6240 | #define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 |
| 6241 | #define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF | 6241 | #define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF |
| 6242 | #define LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 | 6242 | #define LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 |
| 6243 | #define LC_RA_RAM_PIPE_CP_SRMM_1__W 16 | 6243 | #define LC_RA_RAM_PIPE_CP_SRMM_1__W 16 |
| 6244 | #define LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF | 6244 | #define LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF |
| 6245 | #define LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A | 6245 | #define LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A |
| 6246 | #define LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 | 6246 | #define LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 |
| 6247 | #define LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF | 6247 | #define LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF |
| 6248 | #define LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B | 6248 | #define LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B |
| 6249 | #define LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 | 6249 | #define LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 |
| 6250 | #define LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF | 6250 | #define LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF |
| 6251 | #define LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C | 6251 | #define LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C |
| 6252 | #define LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 | 6252 | #define LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 |
| 6253 | #define LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF | 6253 | #define LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF |
| 6254 | #define LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D | 6254 | #define LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D |
| 6255 | #define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 | 6255 | #define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 |
| 6256 | #define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF | 6256 | #define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF |
| 6257 | 6257 | ||
| 6258 | #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 | 6258 | #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 |
| 6259 | #define LC_RA_RAM_FILTER_CRMM_A__W 16 | 6259 | #define LC_RA_RAM_FILTER_CRMM_A__W 16 |
| 6260 | #define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF | 6260 | #define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF |
| 6261 | #define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 | 6261 | #define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 |
| 6262 | #define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 | 6262 | #define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 |
| 6263 | #define LC_RA_RAM_FILTER_CRMM_B__W 16 | 6263 | #define LC_RA_RAM_FILTER_CRMM_B__W 16 |
| 6264 | #define LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF | 6264 | #define LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF |
| 6265 | #define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 | 6265 | #define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 |
| 6266 | #define LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 | 6266 | #define LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 |
| 6267 | #define LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 | 6267 | #define LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 |
| 6268 | #define LC_RA_RAM_FILTER_CRMM_Z1__W 16 | 6268 | #define LC_RA_RAM_FILTER_CRMM_Z1__W 16 |
| 6269 | #define LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF | 6269 | #define LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF |
| 6270 | #define LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 | 6270 | #define LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 |
| 6271 | #define LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 | 6271 | #define LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 |
| 6272 | #define LC_RA_RAM_FILTER_CRMM_Z2__W 16 | 6272 | #define LC_RA_RAM_FILTER_CRMM_Z2__W 16 |
| 6273 | #define LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF | 6273 | #define LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF |
| 6274 | #define LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 | 6274 | #define LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 |
| 6275 | #define LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 | 6275 | #define LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 |
| 6276 | #define LC_RA_RAM_FILTER_CRMM_TMP__W 16 | 6276 | #define LC_RA_RAM_FILTER_CRMM_TMP__W 16 |
| 6277 | #define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF | 6277 | #define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF |
| 6278 | 6278 | ||
| 6279 | #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 | 6279 | #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 |
| 6280 | #define LC_RA_RAM_FILTER_SRMM_A__W 16 | 6280 | #define LC_RA_RAM_FILTER_SRMM_A__W 16 |
| 6281 | #define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF | 6281 | #define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF |
| 6282 | #define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 | 6282 | #define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 |
| 6283 | #define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 | 6283 | #define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 |
| 6284 | #define LC_RA_RAM_FILTER_SRMM_B__W 16 | 6284 | #define LC_RA_RAM_FILTER_SRMM_B__W 16 |
| 6285 | #define LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF | 6285 | #define LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF |
| 6286 | #define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 | 6286 | #define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 |
| 6287 | #define LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A | 6287 | #define LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A |
| 6288 | #define LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 | 6288 | #define LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 |
| 6289 | #define LC_RA_RAM_FILTER_SRMM_Z1__W 16 | 6289 | #define LC_RA_RAM_FILTER_SRMM_Z1__W 16 |
| 6290 | #define LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF | 6290 | #define LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF |
| 6291 | #define LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C | 6291 | #define LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C |
| 6292 | #define LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 | 6292 | #define LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 |
| 6293 | #define LC_RA_RAM_FILTER_SRMM_Z2__W 16 | 6293 | #define LC_RA_RAM_FILTER_SRMM_Z2__W 16 |
| 6294 | #define LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF | 6294 | #define LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF |
| 6295 | #define LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E | 6295 | #define LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E |
| 6296 | #define LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 | 6296 | #define LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 |
| 6297 | #define LC_RA_RAM_FILTER_SRMM_TMP__W 16 | 6297 | #define LC_RA_RAM_FILTER_SRMM_TMP__W 16 |
| 6298 | #define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF | 6298 | #define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF |
| 6299 | 6299 | ||
| 6300 | #define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 | 6300 | #define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 |
| 6301 | #define LC_RA_RAM_FILTER_PHASE_A__W 16 | 6301 | #define LC_RA_RAM_FILTER_PHASE_A__W 16 |
| 6302 | #define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF | 6302 | #define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF |
| 6303 | #define LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 | 6303 | #define LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 |
| 6304 | #define LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 | 6304 | #define LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 |
| 6305 | #define LC_RA_RAM_FILTER_PHASE_B__W 16 | 6305 | #define LC_RA_RAM_FILTER_PHASE_B__W 16 |
| 6306 | #define LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF | 6306 | #define LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF |
| 6307 | #define LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 | 6307 | #define LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 |
| 6308 | #define LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 | 6308 | #define LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 |
| 6309 | #define LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 | 6309 | #define LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 |
| 6310 | #define LC_RA_RAM_FILTER_PHASE_Z1__W 16 | 6310 | #define LC_RA_RAM_FILTER_PHASE_Z1__W 16 |
| 6311 | #define LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF | 6311 | #define LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF |
| 6312 | #define LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 | 6312 | #define LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 |
| 6313 | #define LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 | 6313 | #define LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 |
| 6314 | #define LC_RA_RAM_FILTER_PHASE_Z2__W 16 | 6314 | #define LC_RA_RAM_FILTER_PHASE_Z2__W 16 |
| 6315 | #define LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF | 6315 | #define LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF |
| 6316 | #define LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 | 6316 | #define LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 |
| 6317 | #define LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 | 6317 | #define LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 |
| 6318 | #define LC_RA_RAM_FILTER_PHASE_TMP__W 16 | 6318 | #define LC_RA_RAM_FILTER_PHASE_TMP__W 16 |
| 6319 | #define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF | 6319 | #define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF |
| 6320 | 6320 | ||
| 6321 | #define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 | 6321 | #define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 |
| 6322 | #define LC_RA_RAM_FILTER_DELAY_A__W 16 | 6322 | #define LC_RA_RAM_FILTER_DELAY_A__W 16 |
| 6323 | #define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF | 6323 | #define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF |
| 6324 | #define LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 | 6324 | #define LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 |
| 6325 | #define LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 | 6325 | #define LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 |
| 6326 | #define LC_RA_RAM_FILTER_DELAY_B__W 16 | 6326 | #define LC_RA_RAM_FILTER_DELAY_B__W 16 |
| 6327 | #define LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF | 6327 | #define LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF |
| 6328 | #define LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 | 6328 | #define LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 |
| 6329 | #define LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A | 6329 | #define LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A |
| 6330 | #define LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 | 6330 | #define LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 |
| 6331 | #define LC_RA_RAM_FILTER_DELAY_Z1__W 16 | 6331 | #define LC_RA_RAM_FILTER_DELAY_Z1__W 16 |
| 6332 | #define LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF | 6332 | #define LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF |
| 6333 | #define LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C | 6333 | #define LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C |
| 6334 | #define LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 | 6334 | #define LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 |
| 6335 | #define LC_RA_RAM_FILTER_DELAY_Z2__W 16 | 6335 | #define LC_RA_RAM_FILTER_DELAY_Z2__W 16 |
| 6336 | #define LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF | 6336 | #define LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF |
| 6337 | #define LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E | 6337 | #define LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E |
| 6338 | #define LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 | 6338 | #define LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 |
| 6339 | #define LC_RA_RAM_FILTER_DELAY_TMP__W 16 | 6339 | #define LC_RA_RAM_FILTER_DELAY_TMP__W 16 |
| 6340 | #define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF | 6340 | #define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF |
| 6341 | 6341 | ||
| 6342 | #define LC_IF_RAM_TRP_BPT0__AX 0x2830000 | 6342 | #define LC_IF_RAM_TRP_BPT0__AX 0x2830000 |
| 6343 | #define LC_IF_RAM_TRP_BPT0__XSZ 2 | 6343 | #define LC_IF_RAM_TRP_BPT0__XSZ 2 |
| 6344 | #define LC_IF_RAM_TRP_BPT0__W 12 | 6344 | #define LC_IF_RAM_TRP_BPT0__W 12 |
| 6345 | #define LC_IF_RAM_TRP_BPT0__M 0xFFF | 6345 | #define LC_IF_RAM_TRP_BPT0__M 0xFFF |
| 6346 | 6346 | ||
| 6347 | #define LC_IF_RAM_TRP_STKU__AX 0x2830002 | 6347 | #define LC_IF_RAM_TRP_STKU__AX 0x2830002 |
| 6348 | #define LC_IF_RAM_TRP_STKU__XSZ 2 | 6348 | #define LC_IF_RAM_TRP_STKU__XSZ 2 |
| 6349 | #define LC_IF_RAM_TRP_STKU__W 12 | 6349 | #define LC_IF_RAM_TRP_STKU__W 12 |
| 6350 | #define LC_IF_RAM_TRP_STKU__M 0xFFF | 6350 | #define LC_IF_RAM_TRP_STKU__M 0xFFF |
| 6351 | 6351 | ||
| 6352 | #define LC_IF_RAM_TRP_WARM__AX 0x2830006 | 6352 | #define LC_IF_RAM_TRP_WARM__AX 0x2830006 |
| 6353 | #define LC_IF_RAM_TRP_WARM__XSZ 2 | 6353 | #define LC_IF_RAM_TRP_WARM__XSZ 2 |
| 6354 | #define LC_IF_RAM_TRP_WARM__W 12 | 6354 | #define LC_IF_RAM_TRP_WARM__W 12 |
| 6355 | #define LC_IF_RAM_TRP_WARM__M 0xFFF | 6355 | #define LC_IF_RAM_TRP_WARM__M 0xFFF |
| 6356 | 6356 | ||
| 6357 | #define B_HI_SID 0x10 | 6357 | #define B_HI_SID 0x10 |
| 6358 | 6358 | ||
| 6359 | #define B_HI_COMM_EXEC__A 0x400000 | 6359 | #define B_HI_COMM_EXEC__A 0x400000 |
| 6360 | #define B_HI_COMM_EXEC__W 3 | 6360 | #define B_HI_COMM_EXEC__W 3 |
| 6361 | #define B_HI_COMM_EXEC__M 0x7 | 6361 | #define B_HI_COMM_EXEC__M 0x7 |
| 6362 | #define B_HI_COMM_EXEC_CTL__B 0 | 6362 | #define B_HI_COMM_EXEC_CTL__B 0 |
| 6363 | #define B_HI_COMM_EXEC_CTL__W 3 | 6363 | #define B_HI_COMM_EXEC_CTL__W 3 |
| 6364 | #define B_HI_COMM_EXEC_CTL__M 0x7 | 6364 | #define B_HI_COMM_EXEC_CTL__M 0x7 |
| 6365 | #define B_HI_COMM_EXEC_CTL_STOP 0x0 | 6365 | #define B_HI_COMM_EXEC_CTL_STOP 0x0 |
| 6366 | #define B_HI_COMM_EXEC_CTL_ACTIVE 0x1 | 6366 | #define B_HI_COMM_EXEC_CTL_ACTIVE 0x1 |
| 6367 | #define B_HI_COMM_EXEC_CTL_HOLD 0x2 | 6367 | #define B_HI_COMM_EXEC_CTL_HOLD 0x2 |
| 6368 | #define B_HI_COMM_EXEC_CTL_STEP 0x3 | 6368 | #define B_HI_COMM_EXEC_CTL_STEP 0x3 |
| 6369 | #define B_HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 6369 | #define B_HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 6370 | #define B_HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 6370 | #define B_HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 6371 | 6371 | ||
| 6372 | #define B_HI_COMM_STATE__A 0x400001 | 6372 | #define B_HI_COMM_STATE__A 0x400001 |
| 6373 | #define B_HI_COMM_STATE__W 16 | 6373 | #define B_HI_COMM_STATE__W 16 |
| 6374 | #define B_HI_COMM_STATE__M 0xFFFF | 6374 | #define B_HI_COMM_STATE__M 0xFFFF |
| 6375 | #define B_HI_COMM_MB__A 0x400002 | 6375 | #define B_HI_COMM_MB__A 0x400002 |
| 6376 | #define B_HI_COMM_MB__W 16 | 6376 | #define B_HI_COMM_MB__W 16 |
| 6377 | #define B_HI_COMM_MB__M 0xFFFF | 6377 | #define B_HI_COMM_MB__M 0xFFFF |
| 6378 | #define B_HI_COMM_SERVICE0__A 0x400003 | 6378 | #define B_HI_COMM_SERVICE0__A 0x400003 |
| 6379 | #define B_HI_COMM_SERVICE0__W 16 | 6379 | #define B_HI_COMM_SERVICE0__W 16 |
| 6380 | #define B_HI_COMM_SERVICE0__M 0xFFFF | 6380 | #define B_HI_COMM_SERVICE0__M 0xFFFF |
| 6381 | #define B_HI_COMM_SERVICE1__A 0x400004 | 6381 | #define B_HI_COMM_SERVICE1__A 0x400004 |
| 6382 | #define B_HI_COMM_SERVICE1__W 16 | 6382 | #define B_HI_COMM_SERVICE1__W 16 |
| 6383 | #define B_HI_COMM_SERVICE1__M 0xFFFF | 6383 | #define B_HI_COMM_SERVICE1__M 0xFFFF |
| 6384 | #define B_HI_COMM_INT_STA__A 0x400007 | 6384 | #define B_HI_COMM_INT_STA__A 0x400007 |
| 6385 | #define B_HI_COMM_INT_STA__W 16 | 6385 | #define B_HI_COMM_INT_STA__W 16 |
| 6386 | #define B_HI_COMM_INT_STA__M 0xFFFF | 6386 | #define B_HI_COMM_INT_STA__M 0xFFFF |
| 6387 | #define B_HI_COMM_INT_MSK__A 0x400008 | 6387 | #define B_HI_COMM_INT_MSK__A 0x400008 |
| 6388 | #define B_HI_COMM_INT_MSK__W 16 | 6388 | #define B_HI_COMM_INT_MSK__W 16 |
| 6389 | #define B_HI_COMM_INT_MSK__M 0xFFFF | 6389 | #define B_HI_COMM_INT_MSK__M 0xFFFF |
| 6390 | 6390 | ||
| 6391 | #define B_HI_CT_REG_COMM_EXEC__A 0x410000 | 6391 | #define B_HI_CT_REG_COMM_EXEC__A 0x410000 |
| 6392 | #define B_HI_CT_REG_COMM_EXEC__W 3 | 6392 | #define B_HI_CT_REG_COMM_EXEC__W 3 |
| 6393 | #define B_HI_CT_REG_COMM_EXEC__M 0x7 | 6393 | #define B_HI_CT_REG_COMM_EXEC__M 0x7 |
| 6394 | #define B_HI_CT_REG_COMM_EXEC_CTL__B 0 | 6394 | #define B_HI_CT_REG_COMM_EXEC_CTL__B 0 |
| 6395 | #define B_HI_CT_REG_COMM_EXEC_CTL__W 3 | 6395 | #define B_HI_CT_REG_COMM_EXEC_CTL__W 3 |
| 6396 | #define B_HI_CT_REG_COMM_EXEC_CTL__M 0x7 | 6396 | #define B_HI_CT_REG_COMM_EXEC_CTL__M 0x7 |
| 6397 | #define B_HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 | 6397 | #define B_HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 6398 | #define B_HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 6398 | #define B_HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 6399 | #define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 | 6399 | #define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 6400 | #define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 | 6400 | #define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 6401 | 6401 | ||
| 6402 | #define B_HI_CT_REG_COMM_STATE__A 0x410001 | 6402 | #define B_HI_CT_REG_COMM_STATE__A 0x410001 |
| 6403 | #define B_HI_CT_REG_COMM_STATE__W 10 | 6403 | #define B_HI_CT_REG_COMM_STATE__W 10 |
| 6404 | #define B_HI_CT_REG_COMM_STATE__M 0x3FF | 6404 | #define B_HI_CT_REG_COMM_STATE__M 0x3FF |
| 6405 | #define B_HI_CT_REG_COMM_SERVICE0__A 0x410003 | 6405 | #define B_HI_CT_REG_COMM_SERVICE0__A 0x410003 |
| 6406 | #define B_HI_CT_REG_COMM_SERVICE0__W 16 | 6406 | #define B_HI_CT_REG_COMM_SERVICE0__W 16 |
| 6407 | #define B_HI_CT_REG_COMM_SERVICE0__M 0xFFFF | 6407 | #define B_HI_CT_REG_COMM_SERVICE0__M 0xFFFF |
| 6408 | #define B_HI_CT_REG_COMM_SERVICE1__A 0x410004 | 6408 | #define B_HI_CT_REG_COMM_SERVICE1__A 0x410004 |
| 6409 | #define B_HI_CT_REG_COMM_SERVICE1__W 16 | 6409 | #define B_HI_CT_REG_COMM_SERVICE1__W 16 |
| 6410 | #define B_HI_CT_REG_COMM_SERVICE1__M 0xFFFF | 6410 | #define B_HI_CT_REG_COMM_SERVICE1__M 0xFFFF |
| 6411 | #define B_HI_CT_REG_COMM_SERVICE1_HI__B 0 | 6411 | #define B_HI_CT_REG_COMM_SERVICE1_HI__B 0 |
| 6412 | #define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 | 6412 | #define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 |
| 6413 | #define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 | 6413 | #define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 |
| 6414 | 6414 | ||
| 6415 | #define B_HI_CT_REG_COMM_INT_STA__A 0x410007 | 6415 | #define B_HI_CT_REG_COMM_INT_STA__A 0x410007 |
| 6416 | #define B_HI_CT_REG_COMM_INT_STA__W 1 | 6416 | #define B_HI_CT_REG_COMM_INT_STA__W 1 |
| 6417 | #define B_HI_CT_REG_COMM_INT_STA__M 0x1 | 6417 | #define B_HI_CT_REG_COMM_INT_STA__M 0x1 |
| 6418 | #define B_HI_CT_REG_COMM_INT_STA_REQUEST__B 0 | 6418 | #define B_HI_CT_REG_COMM_INT_STA_REQUEST__B 0 |
| 6419 | #define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 | 6419 | #define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 |
| 6420 | #define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 | 6420 | #define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 |
| 6421 | 6421 | ||
| 6422 | #define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 | 6422 | #define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 |
| 6423 | #define B_HI_CT_REG_COMM_INT_MSK__W 1 | 6423 | #define B_HI_CT_REG_COMM_INT_MSK__W 1 |
| 6424 | #define B_HI_CT_REG_COMM_INT_MSK__M 0x1 | 6424 | #define B_HI_CT_REG_COMM_INT_MSK__M 0x1 |
| 6425 | #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 | 6425 | #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 |
| 6426 | #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 | 6426 | #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 |
| 6427 | #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 | 6427 | #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 |
| 6428 | 6428 | ||
| 6429 | #define B_HI_CT_REG_CTL_STK__AX 0x410010 | 6429 | #define B_HI_CT_REG_CTL_STK__AX 0x410010 |
| 6430 | #define B_HI_CT_REG_CTL_STK__XSZ 4 | 6430 | #define B_HI_CT_REG_CTL_STK__XSZ 4 |
| 6431 | #define B_HI_CT_REG_CTL_STK__W 10 | 6431 | #define B_HI_CT_REG_CTL_STK__W 10 |
| 6432 | #define B_HI_CT_REG_CTL_STK__M 0x3FF | 6432 | #define B_HI_CT_REG_CTL_STK__M 0x3FF |
| 6433 | 6433 | ||
| 6434 | #define B_HI_CT_REG_CTL_BPT_IDX__A 0x41001F | 6434 | #define B_HI_CT_REG_CTL_BPT_IDX__A 0x41001F |
| 6435 | #define B_HI_CT_REG_CTL_BPT_IDX__W 1 | 6435 | #define B_HI_CT_REG_CTL_BPT_IDX__W 1 |
| 6436 | #define B_HI_CT_REG_CTL_BPT_IDX__M 0x1 | 6436 | #define B_HI_CT_REG_CTL_BPT_IDX__M 0x1 |
| 6437 | 6437 | ||
| 6438 | #define B_HI_CT_REG_CTL_BPT__A 0x410020 | 6438 | #define B_HI_CT_REG_CTL_BPT__A 0x410020 |
| 6439 | #define B_HI_CT_REG_CTL_BPT__W 10 | 6439 | #define B_HI_CT_REG_CTL_BPT__W 10 |
| 6440 | #define B_HI_CT_REG_CTL_BPT__M 0x3FF | 6440 | #define B_HI_CT_REG_CTL_BPT__M 0x3FF |
| 6441 | 6441 | ||
| 6442 | #define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 | 6442 | #define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 |
| 6443 | #define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 | 6443 | #define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 |
| 6444 | #define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 | 6444 | #define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 |
| 6445 | #define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 | 6445 | #define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 |
| 6446 | #define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 | 6446 | #define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 |
| 6447 | 6447 | ||
| 6448 | #define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 | 6448 | #define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 |
| 6449 | #define B_HI_RA_RAM_SLV0_DEV_ID__W 7 | 6449 | #define B_HI_RA_RAM_SLV0_DEV_ID__W 7 |
| 6450 | #define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F | 6450 | #define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F |
| 6451 | 6451 | ||
| 6452 | #define B_HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 | 6452 | #define B_HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 |
| 6453 | #define B_HI_RA_RAM_SLV0_FLG_CRC__W 1 | 6453 | #define B_HI_RA_RAM_SLV0_FLG_CRC__W 1 |
| 6454 | #define B_HI_RA_RAM_SLV0_FLG_CRC__M 0x1 | 6454 | #define B_HI_RA_RAM_SLV0_FLG_CRC__M 0x1 |
| 6455 | #define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 | 6455 | #define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 |
| 6456 | #define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 | 6456 | #define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 |
| 6457 | 6457 | ||
| 6458 | #define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 | 6458 | #define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 |
| 6459 | #define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 | 6459 | #define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 |
| 6460 | #define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 | 6460 | #define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 |
| 6461 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 | 6461 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 |
| 6462 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 | 6462 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 |
| 6463 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 | 6463 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 |
| 6464 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 | 6464 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 |
| 6465 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 | 6465 | #define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 |
| 6466 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 | 6466 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 |
| 6467 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 | 6467 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 |
| 6468 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 | 6468 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 |
| 6469 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 | 6469 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 |
| 6470 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 | 6470 | #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 |
| 6471 | 6471 | ||
| 6472 | #define B_HI_RA_RAM_SLV0_STATE__A 0x420014 | 6472 | #define B_HI_RA_RAM_SLV0_STATE__A 0x420014 |
| 6473 | #define B_HI_RA_RAM_SLV0_STATE__W 1 | 6473 | #define B_HI_RA_RAM_SLV0_STATE__W 1 |
| 6474 | #define B_HI_RA_RAM_SLV0_STATE__M 0x1 | 6474 | #define B_HI_RA_RAM_SLV0_STATE__M 0x1 |
| 6475 | #define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 | 6475 | #define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 |
| 6476 | #define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 | 6476 | #define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 |
| 6477 | 6477 | ||
| 6478 | #define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 | 6478 | #define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 |
| 6479 | #define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 | 6479 | #define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 |
| 6480 | #define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF | 6480 | #define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF |
| 6481 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 | 6481 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 |
| 6482 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 | 6482 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 |
| 6483 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F | 6483 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F |
| 6484 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 | 6484 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 |
| 6485 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 | 6485 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 |
| 6486 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 | 6486 | #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 |
| 6487 | 6487 | ||
| 6488 | #define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 | 6488 | #define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 |
| 6489 | #define B_HI_RA_RAM_SLV0_ADDR__W 16 | 6489 | #define B_HI_RA_RAM_SLV0_ADDR__W 16 |
| 6490 | #define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF | 6490 | #define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF |
| 6491 | 6491 | ||
| 6492 | #define B_HI_RA_RAM_SLV0_CRC__A 0x420017 | 6492 | #define B_HI_RA_RAM_SLV0_CRC__A 0x420017 |
| 6493 | #define B_HI_RA_RAM_SLV0_CRC__W 16 | 6493 | #define B_HI_RA_RAM_SLV0_CRC__W 16 |
| 6494 | #define B_HI_RA_RAM_SLV0_CRC__M 0xFFFF | 6494 | #define B_HI_RA_RAM_SLV0_CRC__M 0xFFFF |
| 6495 | 6495 | ||
| 6496 | #define B_HI_RA_RAM_SLV0_READBACK__A 0x420018 | 6496 | #define B_HI_RA_RAM_SLV0_READBACK__A 0x420018 |
| 6497 | #define B_HI_RA_RAM_SLV0_READBACK__W 16 | 6497 | #define B_HI_RA_RAM_SLV0_READBACK__W 16 |
| 6498 | #define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF | 6498 | #define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF |
| 6499 | 6499 | ||
| 6500 | #define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 | 6500 | #define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 |
| 6501 | #define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 | 6501 | #define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 |
| 6502 | #define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 | 6502 | #define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 |
| 6503 | #define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 | 6503 | #define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 |
| 6504 | #define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 | 6504 | #define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 |
| 6505 | 6505 | ||
| 6506 | #define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 | 6506 | #define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 |
| 6507 | #define B_HI_RA_RAM_SLV1_DEV_ID__W 7 | 6507 | #define B_HI_RA_RAM_SLV1_DEV_ID__W 7 |
| 6508 | #define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F | 6508 | #define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F |
| 6509 | 6509 | ||
| 6510 | #define B_HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 | 6510 | #define B_HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 |
| 6511 | #define B_HI_RA_RAM_SLV1_FLG_CRC__W 1 | 6511 | #define B_HI_RA_RAM_SLV1_FLG_CRC__W 1 |
| 6512 | #define B_HI_RA_RAM_SLV1_FLG_CRC__M 0x1 | 6512 | #define B_HI_RA_RAM_SLV1_FLG_CRC__M 0x1 |
| 6513 | #define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 | 6513 | #define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 |
| 6514 | #define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 | 6514 | #define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 |
| 6515 | 6515 | ||
| 6516 | #define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 | 6516 | #define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 |
| 6517 | #define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 | 6517 | #define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 |
| 6518 | #define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 | 6518 | #define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 |
| 6519 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 | 6519 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 |
| 6520 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 | 6520 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 |
| 6521 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 | 6521 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 |
| 6522 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 | 6522 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 |
| 6523 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 | 6523 | #define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 |
| 6524 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 | 6524 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 |
| 6525 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 | 6525 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 |
| 6526 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 | 6526 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 |
| 6527 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 | 6527 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 |
| 6528 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 | 6528 | #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 |
| 6529 | 6529 | ||
| 6530 | #define B_HI_RA_RAM_SLV1_STATE__A 0x420024 | 6530 | #define B_HI_RA_RAM_SLV1_STATE__A 0x420024 |
| 6531 | #define B_HI_RA_RAM_SLV1_STATE__W 1 | 6531 | #define B_HI_RA_RAM_SLV1_STATE__W 1 |
| 6532 | #define B_HI_RA_RAM_SLV1_STATE__M 0x1 | 6532 | #define B_HI_RA_RAM_SLV1_STATE__M 0x1 |
| 6533 | #define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 | 6533 | #define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 |
| 6534 | #define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 | 6534 | #define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 |
| 6535 | 6535 | ||
| 6536 | #define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 | 6536 | #define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 |
| 6537 | #define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 | 6537 | #define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 |
| 6538 | #define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF | 6538 | #define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF |
| 6539 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 | 6539 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 |
| 6540 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 | 6540 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 |
| 6541 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F | 6541 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F |
| 6542 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 | 6542 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 |
| 6543 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 | 6543 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 |
| 6544 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 | 6544 | #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 |
| 6545 | 6545 | ||
| 6546 | #define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 | 6546 | #define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 |
| 6547 | #define B_HI_RA_RAM_SLV1_ADDR__W 16 | 6547 | #define B_HI_RA_RAM_SLV1_ADDR__W 16 |
| 6548 | #define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF | 6548 | #define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF |
| 6549 | 6549 | ||
| 6550 | #define B_HI_RA_RAM_SLV1_CRC__A 0x420027 | 6550 | #define B_HI_RA_RAM_SLV1_CRC__A 0x420027 |
| 6551 | #define B_HI_RA_RAM_SLV1_CRC__W 16 | 6551 | #define B_HI_RA_RAM_SLV1_CRC__W 16 |
| 6552 | #define B_HI_RA_RAM_SLV1_CRC__M 0xFFFF | 6552 | #define B_HI_RA_RAM_SLV1_CRC__M 0xFFFF |
| 6553 | 6553 | ||
| 6554 | #define B_HI_RA_RAM_SLV1_READBACK__A 0x420028 | 6554 | #define B_HI_RA_RAM_SLV1_READBACK__A 0x420028 |
| 6555 | #define B_HI_RA_RAM_SLV1_READBACK__W 16 | 6555 | #define B_HI_RA_RAM_SLV1_READBACK__W 16 |
| 6556 | #define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF | 6556 | #define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF |
| 6557 | 6557 | ||
| 6558 | #define B_HI_RA_RAM_SRV_SEM__A 0x420030 | 6558 | #define B_HI_RA_RAM_SRV_SEM__A 0x420030 |
| 6559 | #define B_HI_RA_RAM_SRV_SEM__W 1 | 6559 | #define B_HI_RA_RAM_SRV_SEM__W 1 |
| 6560 | #define B_HI_RA_RAM_SRV_SEM__M 0x1 | 6560 | #define B_HI_RA_RAM_SRV_SEM__M 0x1 |
| 6561 | #define B_HI_RA_RAM_SRV_SEM_FREE 0x0 | 6561 | #define B_HI_RA_RAM_SRV_SEM_FREE 0x0 |
| 6562 | #define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 | 6562 | #define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 |
| 6563 | 6563 | ||
| 6564 | #define B_HI_RA_RAM_SRV_RES__A 0x420031 | 6564 | #define B_HI_RA_RAM_SRV_RES__A 0x420031 |
| 6565 | #define B_HI_RA_RAM_SRV_RES__W 3 | 6565 | #define B_HI_RA_RAM_SRV_RES__W 3 |
| 6566 | #define B_HI_RA_RAM_SRV_RES__M 0x7 | 6566 | #define B_HI_RA_RAM_SRV_RES__M 0x7 |
| 6567 | #define B_HI_RA_RAM_SRV_RES_OK 0x0 | 6567 | #define B_HI_RA_RAM_SRV_RES_OK 0x0 |
| 6568 | #define B_HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 | 6568 | #define B_HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 |
| 6569 | #define B_HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 | 6569 | #define B_HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 |
| 6570 | #define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 | 6570 | #define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 |
| 6571 | #define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 | 6571 | #define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 |
| 6572 | 6572 | ||
| 6573 | #define B_HI_RA_RAM_SRV_CMD__A 0x420032 | 6573 | #define B_HI_RA_RAM_SRV_CMD__A 0x420032 |
| 6574 | #define B_HI_RA_RAM_SRV_CMD__W 3 | 6574 | #define B_HI_RA_RAM_SRV_CMD__W 3 |
| 6575 | #define B_HI_RA_RAM_SRV_CMD__M 0x7 | 6575 | #define B_HI_RA_RAM_SRV_CMD__M 0x7 |
| 6576 | #define B_HI_RA_RAM_SRV_CMD_NULL 0x0 | 6576 | #define B_HI_RA_RAM_SRV_CMD_NULL 0x0 |
| 6577 | #define B_HI_RA_RAM_SRV_CMD_UIO 0x1 | 6577 | #define B_HI_RA_RAM_SRV_CMD_UIO 0x1 |
| 6578 | #define B_HI_RA_RAM_SRV_CMD_RESET 0x2 | 6578 | #define B_HI_RA_RAM_SRV_CMD_RESET 0x2 |
| 6579 | #define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 | 6579 | #define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 |
| 6580 | #define B_HI_RA_RAM_SRV_CMD_COPY 0x4 | 6580 | #define B_HI_RA_RAM_SRV_CMD_COPY 0x4 |
| 6581 | #define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 | 6581 | #define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 |
| 6582 | #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 | 6582 | #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 |
| 6583 | 6583 | ||
| 6584 | #define B_HI_RA_RAM_SRV_PAR__AX 0x420033 | 6584 | #define B_HI_RA_RAM_SRV_PAR__AX 0x420033 |
| 6585 | #define B_HI_RA_RAM_SRV_PAR__XSZ 5 | 6585 | #define B_HI_RA_RAM_SRV_PAR__XSZ 5 |
| 6586 | #define B_HI_RA_RAM_SRV_PAR__W 16 | 6586 | #define B_HI_RA_RAM_SRV_PAR__W 16 |
| 6587 | #define B_HI_RA_RAM_SRV_PAR__M 0xFFFF | 6587 | #define B_HI_RA_RAM_SRV_PAR__M 0xFFFF |
| 6588 | 6588 | ||
| 6589 | #define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 | 6589 | #define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 |
| 6590 | #define B_HI_RA_RAM_SRV_NOP_RES__W 3 | 6590 | #define B_HI_RA_RAM_SRV_NOP_RES__W 3 |
| 6591 | #define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 | 6591 | #define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 |
| 6592 | #define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 | 6592 | #define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 |
| 6593 | #define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 | 6593 | #define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 |
| 6594 | 6594 | ||
| 6595 | #define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 | 6595 | #define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 |
| 6596 | #define B_HI_RA_RAM_SRV_UIO_RES__W 3 | 6596 | #define B_HI_RA_RAM_SRV_UIO_RES__W 3 |
| 6597 | #define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 | 6597 | #define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 |
| 6598 | #define B_HI_RA_RAM_SRV_UIO_RES_LO 0x0 | 6598 | #define B_HI_RA_RAM_SRV_UIO_RES_LO 0x0 |
| 6599 | #define B_HI_RA_RAM_SRV_UIO_RES_HI 0x1 | 6599 | #define B_HI_RA_RAM_SRV_UIO_RES_HI 0x1 |
| 6600 | 6600 | ||
| 6601 | #define B_HI_RA_RAM_SRV_UIO_KEY__A 0x420033 | 6601 | #define B_HI_RA_RAM_SRV_UIO_KEY__A 0x420033 |
| 6602 | #define B_HI_RA_RAM_SRV_UIO_KEY__W 16 | 6602 | #define B_HI_RA_RAM_SRV_UIO_KEY__W 16 |
| 6603 | #define B_HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF | 6603 | #define B_HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF |
| 6604 | #define B_HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 | 6604 | #define B_HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 |
| 6605 | 6605 | ||
| 6606 | #define B_HI_RA_RAM_SRV_UIO_SEL__A 0x420034 | 6606 | #define B_HI_RA_RAM_SRV_UIO_SEL__A 0x420034 |
| 6607 | #define B_HI_RA_RAM_SRV_UIO_SEL__W 2 | 6607 | #define B_HI_RA_RAM_SRV_UIO_SEL__W 2 |
| 6608 | #define B_HI_RA_RAM_SRV_UIO_SEL__M 0x3 | 6608 | #define B_HI_RA_RAM_SRV_UIO_SEL__M 0x3 |
| 6609 | #define B_HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 | 6609 | #define B_HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 |
| 6610 | #define B_HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 | 6610 | #define B_HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 |
| 6611 | 6611 | ||
| 6612 | #define B_HI_RA_RAM_SRV_UIO_SET__A 0x420035 | 6612 | #define B_HI_RA_RAM_SRV_UIO_SET__A 0x420035 |
| 6613 | #define B_HI_RA_RAM_SRV_UIO_SET__W 2 | 6613 | #define B_HI_RA_RAM_SRV_UIO_SET__W 2 |
| 6614 | #define B_HI_RA_RAM_SRV_UIO_SET__M 0x3 | 6614 | #define B_HI_RA_RAM_SRV_UIO_SET__M 0x3 |
| 6615 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT__B 0 | 6615 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT__B 0 |
| 6616 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT__W 1 | 6616 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT__W 1 |
| 6617 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 | 6617 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 |
| 6618 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 | 6618 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 |
| 6619 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 | 6619 | #define B_HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 |
| 6620 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR__B 1 | 6620 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR__B 1 |
| 6621 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR__W 1 | 6621 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR__W 1 |
| 6622 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 | 6622 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 |
| 6623 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 | 6623 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 |
| 6624 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 | 6624 | #define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 |
| 6625 | 6625 | ||
| 6626 | #define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 | 6626 | #define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 |
| 6627 | #define B_HI_RA_RAM_SRV_RST_RES__W 1 | 6627 | #define B_HI_RA_RAM_SRV_RST_RES__W 1 |
| 6628 | #define B_HI_RA_RAM_SRV_RST_RES__M 0x1 | 6628 | #define B_HI_RA_RAM_SRV_RST_RES__M 0x1 |
| 6629 | #define B_HI_RA_RAM_SRV_RST_RES_OK 0x0 | 6629 | #define B_HI_RA_RAM_SRV_RST_RES_OK 0x0 |
| 6630 | #define B_HI_RA_RAM_SRV_RST_RES_ERROR 0x1 | 6630 | #define B_HI_RA_RAM_SRV_RST_RES_ERROR 0x1 |
| 6631 | 6631 | ||
| 6632 | #define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 | 6632 | #define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 |
| 6633 | #define B_HI_RA_RAM_SRV_RST_KEY__W 16 | 6633 | #define B_HI_RA_RAM_SRV_RST_KEY__W 16 |
| 6634 | #define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF | 6634 | #define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF |
| 6635 | #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 | 6635 | #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 |
| 6636 | 6636 | ||
| 6637 | #define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 | 6637 | #define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 |
| 6638 | #define B_HI_RA_RAM_SRV_CFG_RES__W 1 | 6638 | #define B_HI_RA_RAM_SRV_CFG_RES__W 1 |
| 6639 | #define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 | 6639 | #define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 |
| 6640 | #define B_HI_RA_RAM_SRV_CFG_RES_OK 0x0 | 6640 | #define B_HI_RA_RAM_SRV_CFG_RES_OK 0x0 |
| 6641 | #define B_HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 | 6641 | #define B_HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 |
| 6642 | 6642 | ||
| 6643 | #define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 | 6643 | #define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 |
| 6644 | #define B_HI_RA_RAM_SRV_CFG_KEY__W 16 | 6644 | #define B_HI_RA_RAM_SRV_CFG_KEY__W 16 |
| 6645 | #define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF | 6645 | #define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF |
| 6646 | #define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 | 6646 | #define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 |
| 6647 | 6647 | ||
| 6648 | #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 | 6648 | #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 |
| 6649 | #define B_HI_RA_RAM_SRV_CFG_DIV__W 5 | 6649 | #define B_HI_RA_RAM_SRV_CFG_DIV__W 5 |
| 6650 | #define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F | 6650 | #define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F |
| 6651 | 6651 | ||
| 6652 | #define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 | 6652 | #define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 |
| 6653 | #define B_HI_RA_RAM_SRV_CFG_BDL__W 6 | 6653 | #define B_HI_RA_RAM_SRV_CFG_BDL__W 6 |
| 6654 | #define B_HI_RA_RAM_SRV_CFG_BDL__M 0x3F | 6654 | #define B_HI_RA_RAM_SRV_CFG_BDL__M 0x3F |
| 6655 | 6655 | ||
| 6656 | #define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 | 6656 | #define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 |
| 6657 | #define B_HI_RA_RAM_SRV_CFG_WUP__W 8 | 6657 | #define B_HI_RA_RAM_SRV_CFG_WUP__W 8 |
| 6658 | #define B_HI_RA_RAM_SRV_CFG_WUP__M 0xFF | 6658 | #define B_HI_RA_RAM_SRV_CFG_WUP__M 0xFF |
| 6659 | 6659 | ||
| 6660 | #define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 | 6660 | #define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 |
| 6661 | #define B_HI_RA_RAM_SRV_CFG_ACT__W 4 | 6661 | #define B_HI_RA_RAM_SRV_CFG_ACT__W 4 |
| 6662 | #define B_HI_RA_RAM_SRV_CFG_ACT__M 0xF | 6662 | #define B_HI_RA_RAM_SRV_CFG_ACT__M 0xF |
| 6663 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 | 6663 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 |
| 6664 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 | 6664 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 |
| 6665 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 | 6665 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 |
| 6666 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 | 6666 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 |
| 6667 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 | 6667 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 |
| 6668 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 | 6668 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 |
| 6669 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 | 6669 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 |
| 6670 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 | 6670 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 |
| 6671 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 | 6671 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 |
| 6672 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 | 6672 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 |
| 6673 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 | 6673 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 |
| 6674 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 | 6674 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 |
| 6675 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 | 6675 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 |
| 6676 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 | 6676 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 |
| 6677 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 | 6677 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 |
| 6678 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 | 6678 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 |
| 6679 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 | 6679 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 |
| 6680 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 | 6680 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 |
| 6681 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 | 6681 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 |
| 6682 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 | 6682 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 |
| 6683 | 6683 | ||
| 6684 | #define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 | 6684 | #define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 |
| 6685 | #define B_HI_RA_RAM_SRV_CPY_RES__W 1 | 6685 | #define B_HI_RA_RAM_SRV_CPY_RES__W 1 |
| 6686 | #define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 | 6686 | #define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 |
| 6687 | #define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 | 6687 | #define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 |
| 6688 | #define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 | 6688 | #define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 |
| 6689 | 6689 | ||
| 6690 | #define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 | 6690 | #define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 |
| 6691 | #define B_HI_RA_RAM_SRV_CPY_SBB__W 12 | 6691 | #define B_HI_RA_RAM_SRV_CPY_SBB__W 12 |
| 6692 | #define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF | 6692 | #define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF |
| 6693 | #define B_HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 | 6693 | #define B_HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 |
| 6694 | #define B_HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 | 6694 | #define B_HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 |
| 6695 | #define B_HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F | 6695 | #define B_HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F |
| 6696 | #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 | 6696 | #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 |
| 6697 | #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 | 6697 | #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 |
| 6698 | #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 | 6698 | #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 |
| 6699 | 6699 | ||
| 6700 | #define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 | 6700 | #define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 |
| 6701 | #define B_HI_RA_RAM_SRV_CPY_SAD__W 16 | 6701 | #define B_HI_RA_RAM_SRV_CPY_SAD__W 16 |
| 6702 | #define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF | 6702 | #define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF |
| 6703 | 6703 | ||
| 6704 | #define B_HI_RA_RAM_SRV_CPY_LEN__A 0x420035 | 6704 | #define B_HI_RA_RAM_SRV_CPY_LEN__A 0x420035 |
| 6705 | #define B_HI_RA_RAM_SRV_CPY_LEN__W 16 | 6705 | #define B_HI_RA_RAM_SRV_CPY_LEN__W 16 |
| 6706 | #define B_HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF | 6706 | #define B_HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF |
| 6707 | 6707 | ||
| 6708 | #define B_HI_RA_RAM_SRV_CPY_DBB__A 0x420033 | 6708 | #define B_HI_RA_RAM_SRV_CPY_DBB__A 0x420033 |
| 6709 | #define B_HI_RA_RAM_SRV_CPY_DBB__W 12 | 6709 | #define B_HI_RA_RAM_SRV_CPY_DBB__W 12 |
| 6710 | #define B_HI_RA_RAM_SRV_CPY_DBB__M 0xFFF | 6710 | #define B_HI_RA_RAM_SRV_CPY_DBB__M 0xFFF |
| 6711 | #define B_HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 | 6711 | #define B_HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 |
| 6712 | #define B_HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 | 6712 | #define B_HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 |
| 6713 | #define B_HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F | 6713 | #define B_HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F |
| 6714 | #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 | 6714 | #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 |
| 6715 | #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 | 6715 | #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 |
| 6716 | #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 | 6716 | #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 |
| 6717 | 6717 | ||
| 6718 | #define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 | 6718 | #define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 |
| 6719 | #define B_HI_RA_RAM_SRV_CPY_DAD__W 16 | 6719 | #define B_HI_RA_RAM_SRV_CPY_DAD__W 16 |
| 6720 | #define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF | 6720 | #define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF |
| 6721 | 6721 | ||
| 6722 | #define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 | 6722 | #define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 |
| 6723 | #define B_HI_RA_RAM_SRV_TRM_RES__W 2 | 6723 | #define B_HI_RA_RAM_SRV_TRM_RES__W 2 |
| 6724 | #define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 | 6724 | #define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 |
| 6725 | #define B_HI_RA_RAM_SRV_TRM_RES_OK 0x0 | 6725 | #define B_HI_RA_RAM_SRV_TRM_RES_OK 0x0 |
| 6726 | #define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 | 6726 | #define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 |
| 6727 | #define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 | 6727 | #define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 |
| 6728 | 6728 | ||
| 6729 | #define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 | 6729 | #define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 |
| 6730 | #define B_HI_RA_RAM_SRV_TRM_MST__W 12 | 6730 | #define B_HI_RA_RAM_SRV_TRM_MST__W 12 |
| 6731 | #define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF | 6731 | #define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF |
| 6732 | 6732 | ||
| 6733 | #define B_HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 | 6733 | #define B_HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 |
| 6734 | #define B_HI_RA_RAM_SRV_TRM_SEQ__W 7 | 6734 | #define B_HI_RA_RAM_SRV_TRM_SEQ__W 7 |
| 6735 | #define B_HI_RA_RAM_SRV_TRM_SEQ__M 0x7F | 6735 | #define B_HI_RA_RAM_SRV_TRM_SEQ__M 0x7F |
| 6736 | 6736 | ||
| 6737 | #define B_HI_RA_RAM_SRV_TRM_TRM__A 0x420035 | 6737 | #define B_HI_RA_RAM_SRV_TRM_TRM__A 0x420035 |
| 6738 | #define B_HI_RA_RAM_SRV_TRM_TRM__W 15 | 6738 | #define B_HI_RA_RAM_SRV_TRM_TRM__W 15 |
| 6739 | #define B_HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF | 6739 | #define B_HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF |
| 6740 | #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 | 6740 | #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 |
| 6741 | #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 | 6741 | #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 |
| 6742 | #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF | 6742 | #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF |
| 6743 | 6743 | ||
| 6744 | #define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 | 6744 | #define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 |
| 6745 | #define B_HI_RA_RAM_SRV_TRM_DBB__W 12 | 6745 | #define B_HI_RA_RAM_SRV_TRM_DBB__W 12 |
| 6746 | #define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF | 6746 | #define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF |
| 6747 | #define B_HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 | 6747 | #define B_HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 |
| 6748 | #define B_HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 | 6748 | #define B_HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 |
| 6749 | #define B_HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F | 6749 | #define B_HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F |
| 6750 | #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 | 6750 | #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 |
| 6751 | #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 | 6751 | #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 |
| 6752 | #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 | 6752 | #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 |
| 6753 | 6753 | ||
| 6754 | #define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 | 6754 | #define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 |
| 6755 | #define B_HI_RA_RAM_SRV_TRM_DAD__W 16 | 6755 | #define B_HI_RA_RAM_SRV_TRM_DAD__W 16 |
| 6756 | #define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF | 6756 | #define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF |
| 6757 | 6757 | ||
| 6758 | #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 | 6758 | #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 |
| 6759 | #define B_HI_RA_RAM_USR_BEGIN__W 16 | 6759 | #define B_HI_RA_RAM_USR_BEGIN__W 16 |
| 6760 | #define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF | 6760 | #define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF |
| 6761 | 6761 | ||
| 6762 | #define B_HI_RA_RAM_USR_END__A 0x42007F | 6762 | #define B_HI_RA_RAM_USR_END__A 0x42007F |
| 6763 | #define B_HI_RA_RAM_USR_END__W 16 | 6763 | #define B_HI_RA_RAM_USR_END__W 16 |
| 6764 | #define B_HI_RA_RAM_USR_END__M 0xFFFF | 6764 | #define B_HI_RA_RAM_USR_END__M 0xFFFF |
| 6765 | 6765 | ||
| 6766 | #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 | 6766 | #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 |
| 6767 | #define B_HI_IF_RAM_TRP_BPT0__XSZ 2 | 6767 | #define B_HI_IF_RAM_TRP_BPT0__XSZ 2 |
| 6768 | #define B_HI_IF_RAM_TRP_BPT0__W 12 | 6768 | #define B_HI_IF_RAM_TRP_BPT0__W 12 |
| 6769 | #define B_HI_IF_RAM_TRP_BPT0__M 0xFFF | 6769 | #define B_HI_IF_RAM_TRP_BPT0__M 0xFFF |
| 6770 | 6770 | ||
| 6771 | #define B_HI_IF_RAM_TRP_STKU__AX 0x430002 | 6771 | #define B_HI_IF_RAM_TRP_STKU__AX 0x430002 |
| 6772 | #define B_HI_IF_RAM_TRP_STKU__XSZ 2 | 6772 | #define B_HI_IF_RAM_TRP_STKU__XSZ 2 |
| 6773 | #define B_HI_IF_RAM_TRP_STKU__W 12 | 6773 | #define B_HI_IF_RAM_TRP_STKU__W 12 |
| 6774 | #define B_HI_IF_RAM_TRP_STKU__M 0xFFF | 6774 | #define B_HI_IF_RAM_TRP_STKU__M 0xFFF |
| 6775 | 6775 | ||
| 6776 | #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 | 6776 | #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 |
| 6777 | #define B_HI_IF_RAM_USR_BEGIN__W 12 | 6777 | #define B_HI_IF_RAM_USR_BEGIN__W 12 |
| 6778 | #define B_HI_IF_RAM_USR_BEGIN__M 0xFFF | 6778 | #define B_HI_IF_RAM_USR_BEGIN__M 0xFFF |
| 6779 | 6779 | ||
| 6780 | #define B_HI_IF_RAM_USR_END__A 0x4303FF | 6780 | #define B_HI_IF_RAM_USR_END__A 0x4303FF |
| 6781 | #define B_HI_IF_RAM_USR_END__W 12 | 6781 | #define B_HI_IF_RAM_USR_END__W 12 |
| 6782 | #define B_HI_IF_RAM_USR_END__M 0xFFF | 6782 | #define B_HI_IF_RAM_USR_END__M 0xFFF |
| 6783 | 6783 | ||
| 6784 | #define B_SC_SID 0x11 | 6784 | #define B_SC_SID 0x11 |
| 6785 | 6785 | ||
| 6786 | #define B_SC_COMM_EXEC__A 0x800000 | 6786 | #define B_SC_COMM_EXEC__A 0x800000 |
| 6787 | #define B_SC_COMM_EXEC__W 3 | 6787 | #define B_SC_COMM_EXEC__W 3 |
| 6788 | #define B_SC_COMM_EXEC__M 0x7 | 6788 | #define B_SC_COMM_EXEC__M 0x7 |
| 6789 | #define B_SC_COMM_EXEC_CTL__B 0 | 6789 | #define B_SC_COMM_EXEC_CTL__B 0 |
| 6790 | #define B_SC_COMM_EXEC_CTL__W 3 | 6790 | #define B_SC_COMM_EXEC_CTL__W 3 |
| 6791 | #define B_SC_COMM_EXEC_CTL__M 0x7 | 6791 | #define B_SC_COMM_EXEC_CTL__M 0x7 |
| 6792 | #define B_SC_COMM_EXEC_CTL_STOP 0x0 | 6792 | #define B_SC_COMM_EXEC_CTL_STOP 0x0 |
| 6793 | #define B_SC_COMM_EXEC_CTL_ACTIVE 0x1 | 6793 | #define B_SC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 6794 | #define B_SC_COMM_EXEC_CTL_HOLD 0x2 | 6794 | #define B_SC_COMM_EXEC_CTL_HOLD 0x2 |
| 6795 | #define B_SC_COMM_EXEC_CTL_STEP 0x3 | 6795 | #define B_SC_COMM_EXEC_CTL_STEP 0x3 |
| 6796 | #define B_SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 6796 | #define B_SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 6797 | #define B_SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 6797 | #define B_SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 6798 | 6798 | ||
| 6799 | #define B_SC_COMM_STATE__A 0x800001 | 6799 | #define B_SC_COMM_STATE__A 0x800001 |
| 6800 | #define B_SC_COMM_STATE__W 16 | 6800 | #define B_SC_COMM_STATE__W 16 |
| 6801 | #define B_SC_COMM_STATE__M 0xFFFF | 6801 | #define B_SC_COMM_STATE__M 0xFFFF |
| 6802 | #define B_SC_COMM_MB__A 0x800002 | 6802 | #define B_SC_COMM_MB__A 0x800002 |
| 6803 | #define B_SC_COMM_MB__W 16 | 6803 | #define B_SC_COMM_MB__W 16 |
| 6804 | #define B_SC_COMM_MB__M 0xFFFF | 6804 | #define B_SC_COMM_MB__M 0xFFFF |
| 6805 | #define B_SC_COMM_SERVICE0__A 0x800003 | 6805 | #define B_SC_COMM_SERVICE0__A 0x800003 |
| 6806 | #define B_SC_COMM_SERVICE0__W 16 | 6806 | #define B_SC_COMM_SERVICE0__W 16 |
| 6807 | #define B_SC_COMM_SERVICE0__M 0xFFFF | 6807 | #define B_SC_COMM_SERVICE0__M 0xFFFF |
| 6808 | #define B_SC_COMM_SERVICE1__A 0x800004 | 6808 | #define B_SC_COMM_SERVICE1__A 0x800004 |
| 6809 | #define B_SC_COMM_SERVICE1__W 16 | 6809 | #define B_SC_COMM_SERVICE1__W 16 |
| 6810 | #define B_SC_COMM_SERVICE1__M 0xFFFF | 6810 | #define B_SC_COMM_SERVICE1__M 0xFFFF |
| 6811 | #define B_SC_COMM_INT_STA__A 0x800007 | 6811 | #define B_SC_COMM_INT_STA__A 0x800007 |
| 6812 | #define B_SC_COMM_INT_STA__W 16 | 6812 | #define B_SC_COMM_INT_STA__W 16 |
| 6813 | #define B_SC_COMM_INT_STA__M 0xFFFF | 6813 | #define B_SC_COMM_INT_STA__M 0xFFFF |
| 6814 | #define B_SC_COMM_INT_MSK__A 0x800008 | 6814 | #define B_SC_COMM_INT_MSK__A 0x800008 |
| 6815 | #define B_SC_COMM_INT_MSK__W 16 | 6815 | #define B_SC_COMM_INT_MSK__W 16 |
| 6816 | #define B_SC_COMM_INT_MSK__M 0xFFFF | 6816 | #define B_SC_COMM_INT_MSK__M 0xFFFF |
| 6817 | 6817 | ||
| 6818 | #define B_SC_CT_REG_COMM_EXEC__A 0x810000 | 6818 | #define B_SC_CT_REG_COMM_EXEC__A 0x810000 |
| 6819 | #define B_SC_CT_REG_COMM_EXEC__W 3 | 6819 | #define B_SC_CT_REG_COMM_EXEC__W 3 |
| 6820 | #define B_SC_CT_REG_COMM_EXEC__M 0x7 | 6820 | #define B_SC_CT_REG_COMM_EXEC__M 0x7 |
| 6821 | #define B_SC_CT_REG_COMM_EXEC_CTL__B 0 | 6821 | #define B_SC_CT_REG_COMM_EXEC_CTL__B 0 |
| 6822 | #define B_SC_CT_REG_COMM_EXEC_CTL__W 3 | 6822 | #define B_SC_CT_REG_COMM_EXEC_CTL__W 3 |
| 6823 | #define B_SC_CT_REG_COMM_EXEC_CTL__M 0x7 | 6823 | #define B_SC_CT_REG_COMM_EXEC_CTL__M 0x7 |
| 6824 | #define B_SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 | 6824 | #define B_SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 6825 | #define B_SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 6825 | #define B_SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 6826 | #define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 | 6826 | #define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 6827 | #define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 | 6827 | #define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 6828 | 6828 | ||
| 6829 | #define B_SC_CT_REG_COMM_STATE__A 0x810001 | 6829 | #define B_SC_CT_REG_COMM_STATE__A 0x810001 |
| 6830 | #define B_SC_CT_REG_COMM_STATE__W 10 | 6830 | #define B_SC_CT_REG_COMM_STATE__W 10 |
| 6831 | #define B_SC_CT_REG_COMM_STATE__M 0x3FF | 6831 | #define B_SC_CT_REG_COMM_STATE__M 0x3FF |
| 6832 | #define B_SC_CT_REG_COMM_SERVICE0__A 0x810003 | 6832 | #define B_SC_CT_REG_COMM_SERVICE0__A 0x810003 |
| 6833 | #define B_SC_CT_REG_COMM_SERVICE0__W 16 | 6833 | #define B_SC_CT_REG_COMM_SERVICE0__W 16 |
| 6834 | #define B_SC_CT_REG_COMM_SERVICE0__M 0xFFFF | 6834 | #define B_SC_CT_REG_COMM_SERVICE0__M 0xFFFF |
| 6835 | #define B_SC_CT_REG_COMM_SERVICE1__A 0x810004 | 6835 | #define B_SC_CT_REG_COMM_SERVICE1__A 0x810004 |
| 6836 | #define B_SC_CT_REG_COMM_SERVICE1__W 16 | 6836 | #define B_SC_CT_REG_COMM_SERVICE1__W 16 |
| 6837 | #define B_SC_CT_REG_COMM_SERVICE1__M 0xFFFF | 6837 | #define B_SC_CT_REG_COMM_SERVICE1__M 0xFFFF |
| 6838 | #define B_SC_CT_REG_COMM_SERVICE1_SC__B 1 | 6838 | #define B_SC_CT_REG_COMM_SERVICE1_SC__B 1 |
| 6839 | #define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 | 6839 | #define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 |
| 6840 | #define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 | 6840 | #define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 |
| 6841 | 6841 | ||
| 6842 | #define B_SC_CT_REG_COMM_INT_STA__A 0x810007 | 6842 | #define B_SC_CT_REG_COMM_INT_STA__A 0x810007 |
| 6843 | #define B_SC_CT_REG_COMM_INT_STA__W 1 | 6843 | #define B_SC_CT_REG_COMM_INT_STA__W 1 |
| 6844 | #define B_SC_CT_REG_COMM_INT_STA__M 0x1 | 6844 | #define B_SC_CT_REG_COMM_INT_STA__M 0x1 |
| 6845 | #define B_SC_CT_REG_COMM_INT_STA_REQUEST__B 0 | 6845 | #define B_SC_CT_REG_COMM_INT_STA_REQUEST__B 0 |
| 6846 | #define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 | 6846 | #define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 |
| 6847 | #define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 | 6847 | #define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 |
| 6848 | 6848 | ||
| 6849 | #define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 | 6849 | #define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 |
| 6850 | #define B_SC_CT_REG_COMM_INT_MSK__W 1 | 6850 | #define B_SC_CT_REG_COMM_INT_MSK__W 1 |
| 6851 | #define B_SC_CT_REG_COMM_INT_MSK__M 0x1 | 6851 | #define B_SC_CT_REG_COMM_INT_MSK__M 0x1 |
| 6852 | #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 | 6852 | #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 |
| 6853 | #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 | 6853 | #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 |
| 6854 | #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 | 6854 | #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 |
| 6855 | 6855 | ||
| 6856 | #define B_SC_CT_REG_CTL_STK__AX 0x810010 | 6856 | #define B_SC_CT_REG_CTL_STK__AX 0x810010 |
| 6857 | #define B_SC_CT_REG_CTL_STK__XSZ 4 | 6857 | #define B_SC_CT_REG_CTL_STK__XSZ 4 |
| 6858 | #define B_SC_CT_REG_CTL_STK__W 10 | 6858 | #define B_SC_CT_REG_CTL_STK__W 10 |
| 6859 | #define B_SC_CT_REG_CTL_STK__M 0x3FF | 6859 | #define B_SC_CT_REG_CTL_STK__M 0x3FF |
| 6860 | 6860 | ||
| 6861 | #define B_SC_CT_REG_CTL_BPT_IDX__A 0x81001F | 6861 | #define B_SC_CT_REG_CTL_BPT_IDX__A 0x81001F |
| 6862 | #define B_SC_CT_REG_CTL_BPT_IDX__W 1 | 6862 | #define B_SC_CT_REG_CTL_BPT_IDX__W 1 |
| 6863 | #define B_SC_CT_REG_CTL_BPT_IDX__M 0x1 | 6863 | #define B_SC_CT_REG_CTL_BPT_IDX__M 0x1 |
| 6864 | 6864 | ||
| 6865 | #define B_SC_CT_REG_CTL_BPT__A 0x810020 | 6865 | #define B_SC_CT_REG_CTL_BPT__A 0x810020 |
| 6866 | #define B_SC_CT_REG_CTL_BPT__W 10 | 6866 | #define B_SC_CT_REG_CTL_BPT__W 10 |
| 6867 | #define B_SC_CT_REG_CTL_BPT__M 0x3FF | 6867 | #define B_SC_CT_REG_CTL_BPT__M 0x3FF |
| 6868 | 6868 | ||
| 6869 | #define B_SC_RA_RAM_PARAM0__A 0x820040 | 6869 | #define B_SC_RA_RAM_PARAM0__A 0x820040 |
| 6870 | #define B_SC_RA_RAM_PARAM0__W 16 | 6870 | #define B_SC_RA_RAM_PARAM0__W 16 |
| 6871 | #define B_SC_RA_RAM_PARAM0__M 0xFFFF | 6871 | #define B_SC_RA_RAM_PARAM0__M 0xFFFF |
| 6872 | #define B_SC_RA_RAM_PARAM1__A 0x820041 | 6872 | #define B_SC_RA_RAM_PARAM1__A 0x820041 |
| 6873 | #define B_SC_RA_RAM_PARAM1__W 16 | 6873 | #define B_SC_RA_RAM_PARAM1__W 16 |
| 6874 | #define B_SC_RA_RAM_PARAM1__M 0xFFFF | 6874 | #define B_SC_RA_RAM_PARAM1__M 0xFFFF |
| 6875 | #define B_SC_RA_RAM_CMD_ADDR__A 0x820042 | 6875 | #define B_SC_RA_RAM_CMD_ADDR__A 0x820042 |
| 6876 | #define B_SC_RA_RAM_CMD_ADDR__W 16 | 6876 | #define B_SC_RA_RAM_CMD_ADDR__W 16 |
| 6877 | #define B_SC_RA_RAM_CMD_ADDR__M 0xFFFF | 6877 | #define B_SC_RA_RAM_CMD_ADDR__M 0xFFFF |
| 6878 | #define B_SC_RA_RAM_CMD__A 0x820043 | 6878 | #define B_SC_RA_RAM_CMD__A 0x820043 |
| 6879 | #define B_SC_RA_RAM_CMD__W 16 | 6879 | #define B_SC_RA_RAM_CMD__W 16 |
| 6880 | #define B_SC_RA_RAM_CMD__M 0xFFFF | 6880 | #define B_SC_RA_RAM_CMD__M 0xFFFF |
| 6881 | #define B_SC_RA_RAM_CMD_NULL 0x0 | 6881 | #define B_SC_RA_RAM_CMD_NULL 0x0 |
| 6882 | #define B_SC_RA_RAM_CMD_PROC_START 0x1 | 6882 | #define B_SC_RA_RAM_CMD_PROC_START 0x1 |
| 6883 | #define B_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 | 6883 | #define B_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 |
| 6884 | #define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 | 6884 | #define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 |
| 6885 | #define B_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 | 6885 | #define B_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 |
| 6886 | #define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 | 6886 | #define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 |
| 6887 | #define B_SC_RA_RAM_CMD_USER_IO 0x6 | 6887 | #define B_SC_RA_RAM_CMD_USER_IO 0x6 |
| 6888 | #define B_SC_RA_RAM_CMD_SET_TIMER 0x7 | 6888 | #define B_SC_RA_RAM_CMD_SET_TIMER 0x7 |
| 6889 | #define B_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 | 6889 | #define B_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 |
| 6890 | #define B_SC_RA_RAM_CMD_MAX 0x9 | 6890 | #define B_SC_RA_RAM_CMD_MAX 0x9 |
| 6891 | #define B_SC_RA_RAM_CMDBLOCK__C 0x4 | 6891 | #define B_SC_RA_RAM_CMDBLOCK__C 0x4 |
| 6892 | 6892 | ||
| 6893 | #define B_SC_RA_RAM_PROC_ACTIVATE__A 0x820044 | 6893 | #define B_SC_RA_RAM_PROC_ACTIVATE__A 0x820044 |
| 6894 | #define B_SC_RA_RAM_PROC_ACTIVATE__W 16 | 6894 | #define B_SC_RA_RAM_PROC_ACTIVATE__W 16 |
| 6895 | #define B_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF | 6895 | #define B_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF |
| 6896 | #define B_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF | 6896 | #define B_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF |
| 6897 | #define B_SC_RA_RAM_PROC_TERMINATED__A 0x820045 | 6897 | #define B_SC_RA_RAM_PROC_TERMINATED__A 0x820045 |
| 6898 | #define B_SC_RA_RAM_PROC_TERMINATED__W 16 | 6898 | #define B_SC_RA_RAM_PROC_TERMINATED__W 16 |
| 6899 | #define B_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF | 6899 | #define B_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF |
| 6900 | #define B_SC_RA_RAM_SW_EVENT__A 0x820046 | 6900 | #define B_SC_RA_RAM_SW_EVENT__A 0x820046 |
| 6901 | #define B_SC_RA_RAM_SW_EVENT__W 14 | 6901 | #define B_SC_RA_RAM_SW_EVENT__W 14 |
| 6902 | #define B_SC_RA_RAM_SW_EVENT__M 0x3FFF | 6902 | #define B_SC_RA_RAM_SW_EVENT__M 0x3FFF |
| 6903 | #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 | 6903 | #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 |
| 6904 | #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 | 6904 | #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 |
| 6905 | #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 | 6905 | #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 |
| 6906 | #define B_SC_RA_RAM_SW_EVENT_RUN__B 1 | 6906 | #define B_SC_RA_RAM_SW_EVENT_RUN__B 1 |
| 6907 | #define B_SC_RA_RAM_SW_EVENT_RUN__W 1 | 6907 | #define B_SC_RA_RAM_SW_EVENT_RUN__W 1 |
| 6908 | #define B_SC_RA_RAM_SW_EVENT_RUN__M 0x2 | 6908 | #define B_SC_RA_RAM_SW_EVENT_RUN__M 0x2 |
| 6909 | #define B_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 | 6909 | #define B_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 |
| 6910 | #define B_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 | 6910 | #define B_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 |
| 6911 | #define B_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 | 6911 | #define B_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 |
| 6912 | #define B_SC_RA_RAM_SW_EVENT_FT_START__B 3 | 6912 | #define B_SC_RA_RAM_SW_EVENT_FT_START__B 3 |
| 6913 | #define B_SC_RA_RAM_SW_EVENT_FT_START__W 1 | 6913 | #define B_SC_RA_RAM_SW_EVENT_FT_START__W 1 |
| 6914 | #define B_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 | 6914 | #define B_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 |
| 6915 | #define B_SC_RA_RAM_SW_EVENT_FI_START__B 4 | 6915 | #define B_SC_RA_RAM_SW_EVENT_FI_START__B 4 |
| 6916 | #define B_SC_RA_RAM_SW_EVENT_FI_START__W 1 | 6916 | #define B_SC_RA_RAM_SW_EVENT_FI_START__W 1 |
| 6917 | #define B_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 | 6917 | #define B_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 |
| 6918 | #define B_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 | 6918 | #define B_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 |
| 6919 | #define B_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 | 6919 | #define B_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 |
| 6920 | #define B_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 | 6920 | #define B_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 |
| 6921 | #define B_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 | 6921 | #define B_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 |
| 6922 | #define B_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 | 6922 | #define B_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 |
| 6923 | #define B_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 | 6923 | #define B_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 |
| 6924 | #define B_SC_RA_RAM_SW_EVENT_CE_IR__B 7 | 6924 | #define B_SC_RA_RAM_SW_EVENT_CE_IR__B 7 |
| 6925 | #define B_SC_RA_RAM_SW_EVENT_CE_IR__W 1 | 6925 | #define B_SC_RA_RAM_SW_EVENT_CE_IR__W 1 |
| 6926 | #define B_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 | 6926 | #define B_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 |
| 6927 | #define B_SC_RA_RAM_SW_EVENT_FE_FD__B 8 | 6927 | #define B_SC_RA_RAM_SW_EVENT_FE_FD__B 8 |
| 6928 | #define B_SC_RA_RAM_SW_EVENT_FE_FD__W 1 | 6928 | #define B_SC_RA_RAM_SW_EVENT_FE_FD__W 1 |
| 6929 | #define B_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 | 6929 | #define B_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 |
| 6930 | #define B_SC_RA_RAM_SW_EVENT_FE_CF__B 9 | 6930 | #define B_SC_RA_RAM_SW_EVENT_FE_CF__B 9 |
| 6931 | #define B_SC_RA_RAM_SW_EVENT_FE_CF__W 1 | 6931 | #define B_SC_RA_RAM_SW_EVENT_FE_CF__W 1 |
| 6932 | #define B_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 | 6932 | #define B_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 |
| 6933 | #define B_SC_RA_RAM_SW_EVENT_NF_READY__B 12 | 6933 | #define B_SC_RA_RAM_SW_EVENT_NF_READY__B 12 |
| 6934 | #define B_SC_RA_RAM_SW_EVENT_NF_READY__W 1 | 6934 | #define B_SC_RA_RAM_SW_EVENT_NF_READY__W 1 |
| 6935 | #define B_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 | 6935 | #define B_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 |
| 6936 | 6936 | ||
| 6937 | #define B_SC_RA_RAM_LOCKTRACK__A 0x820047 | 6937 | #define B_SC_RA_RAM_LOCKTRACK__A 0x820047 |
| 6938 | #define B_SC_RA_RAM_LOCKTRACK__W 16 | 6938 | #define B_SC_RA_RAM_LOCKTRACK__W 16 |
| 6939 | #define B_SC_RA_RAM_LOCKTRACK__M 0xFFFF | 6939 | #define B_SC_RA_RAM_LOCKTRACK__M 0xFFFF |
| 6940 | #define B_SC_RA_RAM_LOCKTRACK_NULL 0x0 | 6940 | #define B_SC_RA_RAM_LOCKTRACK_NULL 0x0 |
| 6941 | #define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 | 6941 | #define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 |
| 6942 | #define B_SC_RA_RAM_LOCKTRACK_RESET 0x1 | 6942 | #define B_SC_RA_RAM_LOCKTRACK_RESET 0x1 |
| 6943 | #define B_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 | 6943 | #define B_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 |
| 6944 | #define B_SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 | 6944 | #define B_SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 |
| 6945 | #define B_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 | 6945 | #define B_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 |
| 6946 | #define B_SC_RA_RAM_LOCKTRACK_LC 0x5 | 6946 | #define B_SC_RA_RAM_LOCKTRACK_LC 0x5 |
| 6947 | #define B_SC_RA_RAM_LOCKTRACK_P_ECHO 0x6 | 6947 | #define B_SC_RA_RAM_LOCKTRACK_P_ECHO 0x6 |
| 6948 | #define B_SC_RA_RAM_LOCKTRACK_NE_INIT 0x7 | 6948 | #define B_SC_RA_RAM_LOCKTRACK_NE_INIT 0x7 |
| 6949 | #define B_SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x8 | 6949 | #define B_SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x8 |
| 6950 | #define B_SC_RA_RAM_LOCKTRACK_TRACK 0x9 | 6950 | #define B_SC_RA_RAM_LOCKTRACK_TRACK 0x9 |
| 6951 | #define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA | 6951 | #define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA |
| 6952 | #define B_SC_RA_RAM_LOCKTRACK_MAX 0xB | 6952 | #define B_SC_RA_RAM_LOCKTRACK_MAX 0xB |
| 6953 | 6953 | ||
| 6954 | #define B_SC_RA_RAM_OP_PARAM__A 0x820048 | 6954 | #define B_SC_RA_RAM_OP_PARAM__A 0x820048 |
| 6955 | #define B_SC_RA_RAM_OP_PARAM__W 13 | 6955 | #define B_SC_RA_RAM_OP_PARAM__W 13 |
| 6956 | #define B_SC_RA_RAM_OP_PARAM__M 0x1FFF | 6956 | #define B_SC_RA_RAM_OP_PARAM__M 0x1FFF |
| 6957 | #define B_SC_RA_RAM_OP_PARAM_MODE__B 0 | 6957 | #define B_SC_RA_RAM_OP_PARAM_MODE__B 0 |
| 6958 | #define B_SC_RA_RAM_OP_PARAM_MODE__W 2 | 6958 | #define B_SC_RA_RAM_OP_PARAM_MODE__W 2 |
| 6959 | #define B_SC_RA_RAM_OP_PARAM_MODE__M 0x3 | 6959 | #define B_SC_RA_RAM_OP_PARAM_MODE__M 0x3 |
| 6960 | #define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 | 6960 | #define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 |
| 6961 | #define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 | 6961 | #define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 |
| 6962 | #define B_SC_RA_RAM_OP_PARAM_GUARD__B 2 | 6962 | #define B_SC_RA_RAM_OP_PARAM_GUARD__B 2 |
| 6963 | #define B_SC_RA_RAM_OP_PARAM_GUARD__W 2 | 6963 | #define B_SC_RA_RAM_OP_PARAM_GUARD__W 2 |
| 6964 | #define B_SC_RA_RAM_OP_PARAM_GUARD__M 0xC | 6964 | #define B_SC_RA_RAM_OP_PARAM_GUARD__M 0xC |
| 6965 | #define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 | 6965 | #define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 |
| 6966 | #define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 | 6966 | #define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 |
| 6967 | #define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 | 6967 | #define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 |
| 6968 | #define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC | 6968 | #define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC |
| 6969 | #define B_SC_RA_RAM_OP_PARAM_CONST__B 4 | 6969 | #define B_SC_RA_RAM_OP_PARAM_CONST__B 4 |
| 6970 | #define B_SC_RA_RAM_OP_PARAM_CONST__W 2 | 6970 | #define B_SC_RA_RAM_OP_PARAM_CONST__W 2 |
| 6971 | #define B_SC_RA_RAM_OP_PARAM_CONST__M 0x30 | 6971 | #define B_SC_RA_RAM_OP_PARAM_CONST__M 0x30 |
| 6972 | #define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 | 6972 | #define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 |
| 6973 | #define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 | 6973 | #define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 |
| 6974 | #define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 | 6974 | #define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 |
| 6975 | #define B_SC_RA_RAM_OP_PARAM_HIER__B 6 | 6975 | #define B_SC_RA_RAM_OP_PARAM_HIER__B 6 |
| 6976 | #define B_SC_RA_RAM_OP_PARAM_HIER__W 3 | 6976 | #define B_SC_RA_RAM_OP_PARAM_HIER__W 3 |
| 6977 | #define B_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 | 6977 | #define B_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 |
| 6978 | #define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 | 6978 | #define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 |
| 6979 | #define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 | 6979 | #define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 |
| 6980 | #define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 | 6980 | #define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 |
| 6981 | #define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 | 6981 | #define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 |
| 6982 | #define B_SC_RA_RAM_OP_PARAM_RATE__B 9 | 6982 | #define B_SC_RA_RAM_OP_PARAM_RATE__B 9 |
| 6983 | #define B_SC_RA_RAM_OP_PARAM_RATE__W 3 | 6983 | #define B_SC_RA_RAM_OP_PARAM_RATE__W 3 |
| 6984 | #define B_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 | 6984 | #define B_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 |
| 6985 | #define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 | 6985 | #define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 |
| 6986 | #define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 | 6986 | #define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 |
| 6987 | #define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 | 6987 | #define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 |
| 6988 | #define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 | 6988 | #define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 |
| 6989 | #define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 | 6989 | #define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 |
| 6990 | #define B_SC_RA_RAM_OP_PARAM_PRIO__B 12 | 6990 | #define B_SC_RA_RAM_OP_PARAM_PRIO__B 12 |
| 6991 | #define B_SC_RA_RAM_OP_PARAM_PRIO__W 1 | 6991 | #define B_SC_RA_RAM_OP_PARAM_PRIO__W 1 |
| 6992 | #define B_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 | 6992 | #define B_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 |
| 6993 | #define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 | 6993 | #define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 |
| 6994 | #define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 | 6994 | #define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 |
| 6995 | 6995 | ||
| 6996 | #define B_SC_RA_RAM_OP_AUTO__A 0x820049 | 6996 | #define B_SC_RA_RAM_OP_AUTO__A 0x820049 |
| 6997 | #define B_SC_RA_RAM_OP_AUTO__W 6 | 6997 | #define B_SC_RA_RAM_OP_AUTO__W 6 |
| 6998 | #define B_SC_RA_RAM_OP_AUTO__M 0x3F | 6998 | #define B_SC_RA_RAM_OP_AUTO__M 0x3F |
| 6999 | #define B_SC_RA_RAM_OP_AUTO__PRE 0x1F | 6999 | #define B_SC_RA_RAM_OP_AUTO__PRE 0x1F |
| 7000 | #define B_SC_RA_RAM_OP_AUTO_MODE__B 0 | 7000 | #define B_SC_RA_RAM_OP_AUTO_MODE__B 0 |
| 7001 | #define B_SC_RA_RAM_OP_AUTO_MODE__W 1 | 7001 | #define B_SC_RA_RAM_OP_AUTO_MODE__W 1 |
| 7002 | #define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 | 7002 | #define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 |
| 7003 | #define B_SC_RA_RAM_OP_AUTO_GUARD__B 1 | 7003 | #define B_SC_RA_RAM_OP_AUTO_GUARD__B 1 |
| 7004 | #define B_SC_RA_RAM_OP_AUTO_GUARD__W 1 | 7004 | #define B_SC_RA_RAM_OP_AUTO_GUARD__W 1 |
| 7005 | #define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 | 7005 | #define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 |
| 7006 | #define B_SC_RA_RAM_OP_AUTO_CONST__B 2 | 7006 | #define B_SC_RA_RAM_OP_AUTO_CONST__B 2 |
| 7007 | #define B_SC_RA_RAM_OP_AUTO_CONST__W 1 | 7007 | #define B_SC_RA_RAM_OP_AUTO_CONST__W 1 |
| 7008 | #define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 | 7008 | #define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 |
| 7009 | #define B_SC_RA_RAM_OP_AUTO_HIER__B 3 | 7009 | #define B_SC_RA_RAM_OP_AUTO_HIER__B 3 |
| 7010 | #define B_SC_RA_RAM_OP_AUTO_HIER__W 1 | 7010 | #define B_SC_RA_RAM_OP_AUTO_HIER__W 1 |
| 7011 | #define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 | 7011 | #define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 |
| 7012 | #define B_SC_RA_RAM_OP_AUTO_RATE__B 4 | 7012 | #define B_SC_RA_RAM_OP_AUTO_RATE__B 4 |
| 7013 | #define B_SC_RA_RAM_OP_AUTO_RATE__W 1 | 7013 | #define B_SC_RA_RAM_OP_AUTO_RATE__W 1 |
| 7014 | #define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 | 7014 | #define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 |
| 7015 | #define B_SC_RA_RAM_OP_AUTO_PRIO__B 5 | 7015 | #define B_SC_RA_RAM_OP_AUTO_PRIO__B 5 |
| 7016 | #define B_SC_RA_RAM_OP_AUTO_PRIO__W 1 | 7016 | #define B_SC_RA_RAM_OP_AUTO_PRIO__W 1 |
| 7017 | #define B_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 | 7017 | #define B_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 |
| 7018 | 7018 | ||
| 7019 | #define B_SC_RA_RAM_PILOT_STATUS__A 0x82004A | 7019 | #define B_SC_RA_RAM_PILOT_STATUS__A 0x82004A |
| 7020 | #define B_SC_RA_RAM_PILOT_STATUS__W 16 | 7020 | #define B_SC_RA_RAM_PILOT_STATUS__W 16 |
| 7021 | #define B_SC_RA_RAM_PILOT_STATUS__M 0xFFFF | 7021 | #define B_SC_RA_RAM_PILOT_STATUS__M 0xFFFF |
| 7022 | #define B_SC_RA_RAM_PILOT_STATUS_OK 0x0 | 7022 | #define B_SC_RA_RAM_PILOT_STATUS_OK 0x0 |
| 7023 | #define B_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 | 7023 | #define B_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 |
| 7024 | #define B_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 | 7024 | #define B_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 |
| 7025 | #define B_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 | 7025 | #define B_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 |
| 7026 | 7026 | ||
| 7027 | #define B_SC_RA_RAM_LOCK__A 0x82004B | 7027 | #define B_SC_RA_RAM_LOCK__A 0x82004B |
| 7028 | #define B_SC_RA_RAM_LOCK__W 4 | 7028 | #define B_SC_RA_RAM_LOCK__W 4 |
| 7029 | #define B_SC_RA_RAM_LOCK__M 0xF | 7029 | #define B_SC_RA_RAM_LOCK__M 0xF |
| 7030 | #define B_SC_RA_RAM_LOCK_DEMOD__B 0 | 7030 | #define B_SC_RA_RAM_LOCK_DEMOD__B 0 |
| 7031 | #define B_SC_RA_RAM_LOCK_DEMOD__W 1 | 7031 | #define B_SC_RA_RAM_LOCK_DEMOD__W 1 |
| 7032 | #define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 | 7032 | #define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 |
| 7033 | #define B_SC_RA_RAM_LOCK_FEC__B 1 | 7033 | #define B_SC_RA_RAM_LOCK_FEC__B 1 |
| 7034 | #define B_SC_RA_RAM_LOCK_FEC__W 1 | 7034 | #define B_SC_RA_RAM_LOCK_FEC__W 1 |
| 7035 | #define B_SC_RA_RAM_LOCK_FEC__M 0x2 | 7035 | #define B_SC_RA_RAM_LOCK_FEC__M 0x2 |
| 7036 | #define B_SC_RA_RAM_LOCK_MPEG__B 2 | 7036 | #define B_SC_RA_RAM_LOCK_MPEG__B 2 |
| 7037 | #define B_SC_RA_RAM_LOCK_MPEG__W 1 | 7037 | #define B_SC_RA_RAM_LOCK_MPEG__W 1 |
| 7038 | #define B_SC_RA_RAM_LOCK_MPEG__M 0x4 | 7038 | #define B_SC_RA_RAM_LOCK_MPEG__M 0x4 |
| 7039 | #define B_SC_RA_RAM_LOCK_NODVBT__B 3 | 7039 | #define B_SC_RA_RAM_LOCK_NODVBT__B 3 |
| 7040 | #define B_SC_RA_RAM_LOCK_NODVBT__W 1 | 7040 | #define B_SC_RA_RAM_LOCK_NODVBT__W 1 |
| 7041 | #define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 | 7041 | #define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 |
| 7042 | 7042 | ||
| 7043 | #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C | 7043 | #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C |
| 7044 | #define B_SC_RA_RAM_BE_OPT_ENA__W 5 | 7044 | #define B_SC_RA_RAM_BE_OPT_ENA__W 5 |
| 7045 | #define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F | 7045 | #define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F |
| 7046 | #define B_SC_RA_RAM_BE_OPT_ENA__PRE 0x1E | 7046 | #define B_SC_RA_RAM_BE_OPT_ENA__PRE 0x1E |
| 7047 | #define B_SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 | 7047 | #define B_SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 |
| 7048 | #define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 | 7048 | #define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 |
| 7049 | #define B_SC_RA_RAM_BE_OPT_ENA_CSI_OPT 0x2 | 7049 | #define B_SC_RA_RAM_BE_OPT_ENA_CSI_OPT 0x2 |
| 7050 | #define B_SC_RA_RAM_BE_OPT_ENA_CAL_OPT 0x3 | 7050 | #define B_SC_RA_RAM_BE_OPT_ENA_CAL_OPT 0x3 |
| 7051 | #define B_SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 | 7051 | #define B_SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 |
| 7052 | #define B_SC_RA_RAM_BE_OPT_ENA_MAX 0x5 | 7052 | #define B_SC_RA_RAM_BE_OPT_ENA_MAX 0x5 |
| 7053 | 7053 | ||
| 7054 | #define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D | 7054 | #define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D |
| 7055 | #define B_SC_RA_RAM_BE_OPT_DELAY__W 16 | 7055 | #define B_SC_RA_RAM_BE_OPT_DELAY__W 16 |
| 7056 | #define B_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF | 7056 | #define B_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF |
| 7057 | #define B_SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 | 7057 | #define B_SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 |
| 7058 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E | 7058 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E |
| 7059 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 | 7059 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 |
| 7060 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF | 7060 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF |
| 7061 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 | 7061 | #define B_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 |
| 7062 | #define B_SC_RA_RAM_ECHO_THRES__A 0x82004F | 7062 | #define B_SC_RA_RAM_ECHO_THRES__A 0x82004F |
| 7063 | #define B_SC_RA_RAM_ECHO_THRES__W 16 | 7063 | #define B_SC_RA_RAM_ECHO_THRES__W 16 |
| 7064 | #define B_SC_RA_RAM_ECHO_THRES__M 0xFFFF | 7064 | #define B_SC_RA_RAM_ECHO_THRES__M 0xFFFF |
| 7065 | #define B_SC_RA_RAM_ECHO_THRES__PRE 0x2A | 7065 | #define B_SC_RA_RAM_ECHO_THRES__PRE 0x2A |
| 7066 | #define B_SC_RA_RAM_CONFIG__A 0x820050 | 7066 | #define B_SC_RA_RAM_CONFIG__A 0x820050 |
| 7067 | #define B_SC_RA_RAM_CONFIG__W 16 | 7067 | #define B_SC_RA_RAM_CONFIG__W 16 |
| 7068 | #define B_SC_RA_RAM_CONFIG__M 0xFFFF | 7068 | #define B_SC_RA_RAM_CONFIG__M 0xFFFF |
| 7069 | #define B_SC_RA_RAM_CONFIG__PRE 0x14 | 7069 | #define B_SC_RA_RAM_CONFIG__PRE 0x14 |
| 7070 | #define B_SC_RA_RAM_CONFIG_ID__B 0 | 7070 | #define B_SC_RA_RAM_CONFIG_ID__B 0 |
| 7071 | #define B_SC_RA_RAM_CONFIG_ID__W 1 | 7071 | #define B_SC_RA_RAM_CONFIG_ID__W 1 |
| 7072 | #define B_SC_RA_RAM_CONFIG_ID__M 0x1 | 7072 | #define B_SC_RA_RAM_CONFIG_ID__M 0x1 |
| 7073 | #define B_SC_RA_RAM_CONFIG_ID_PRO 0x0 | 7073 | #define B_SC_RA_RAM_CONFIG_ID_PRO 0x0 |
| 7074 | #define B_SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 | 7074 | #define B_SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 |
| 7075 | #define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 | 7075 | #define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 |
| 7076 | #define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 | 7076 | #define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 |
| 7077 | #define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 | 7077 | #define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 |
| 7078 | #define B_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 | 7078 | #define B_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 |
| 7079 | #define B_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 | 7079 | #define B_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 |
| 7080 | #define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 | 7080 | #define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 |
| 7081 | #define B_SC_RA_RAM_CONFIG_MIXMODE__B 3 | 7081 | #define B_SC_RA_RAM_CONFIG_MIXMODE__B 3 |
| 7082 | #define B_SC_RA_RAM_CONFIG_MIXMODE__W 1 | 7082 | #define B_SC_RA_RAM_CONFIG_MIXMODE__W 1 |
| 7083 | #define B_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 | 7083 | #define B_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 |
| 7084 | #define B_SC_RA_RAM_CONFIG_FREQSCAN__B 4 | 7084 | #define B_SC_RA_RAM_CONFIG_FREQSCAN__B 4 |
| 7085 | #define B_SC_RA_RAM_CONFIG_FREQSCAN__W 1 | 7085 | #define B_SC_RA_RAM_CONFIG_FREQSCAN__W 1 |
| 7086 | #define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 | 7086 | #define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 |
| 7087 | #define B_SC_RA_RAM_CONFIG_SLAVE__B 5 | 7087 | #define B_SC_RA_RAM_CONFIG_SLAVE__B 5 |
| 7088 | #define B_SC_RA_RAM_CONFIG_SLAVE__W 1 | 7088 | #define B_SC_RA_RAM_CONFIG_SLAVE__W 1 |
| 7089 | #define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 | 7089 | #define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 |
| 7090 | #define B_SC_RA_RAM_CONFIG_FAR_OFF__B 6 | 7090 | #define B_SC_RA_RAM_CONFIG_FAR_OFF__B 6 |
| 7091 | #define B_SC_RA_RAM_CONFIG_FAR_OFF__W 1 | 7091 | #define B_SC_RA_RAM_CONFIG_FAR_OFF__W 1 |
| 7092 | #define B_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 | 7092 | #define B_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 |
| 7093 | #define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 | 7093 | #define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 |
| 7094 | #define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 | 7094 | #define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 |
| 7095 | #define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 | 7095 | #define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 |
| 7096 | #define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 | 7096 | #define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 |
| 7097 | #define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 | 7097 | #define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 |
| 7098 | #define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 | 7098 | #define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 |
| 7099 | #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 | 7099 | #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 |
| 7100 | #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 | 7100 | #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 |
| 7101 | #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 | 7101 | #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 |
| 7102 | #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 | 7102 | #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 |
| 7103 | #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 | 7103 | #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 |
| 7104 | #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 | 7104 | #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 |
| 7105 | #define B_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 | 7105 | #define B_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 |
| 7106 | #define B_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 | 7106 | #define B_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 |
| 7107 | #define B_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 | 7107 | #define B_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 |
| 7108 | 7108 | ||
| 7109 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x820054 | 7109 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x820054 |
| 7110 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 | 7110 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 |
| 7111 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF | 7111 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF |
| 7112 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 | 7112 | #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 |
| 7113 | 7113 | ||
| 7114 | #define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 | 7114 | #define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 |
| 7115 | #define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 | 7115 | #define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 |
| 7116 | #define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF | 7116 | #define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF |
| 7117 | #define B_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 | 7117 | #define B_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 |
| 7118 | #define B_SC_RA_RAM_FR_2K_TAP_SH__A 0x820056 | 7118 | #define B_SC_RA_RAM_FR_2K_TAP_SH__A 0x820056 |
| 7119 | #define B_SC_RA_RAM_FR_2K_TAP_SH__W 16 | 7119 | #define B_SC_RA_RAM_FR_2K_TAP_SH__W 16 |
| 7120 | #define B_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF | 7120 | #define B_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF |
| 7121 | #define B_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 | 7121 | #define B_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 |
| 7122 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x820057 | 7122 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x820057 |
| 7123 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 | 7123 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 |
| 7124 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF | 7124 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF |
| 7125 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 | 7125 | #define B_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 |
| 7126 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__A 0x820058 | 7126 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__A 0x820058 |
| 7127 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__W 16 | 7127 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__W 16 |
| 7128 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF | 7128 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF |
| 7129 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 | 7129 | #define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 |
| 7130 | 7130 | ||
| 7131 | #define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 | 7131 | #define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 |
| 7132 | #define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 | 7132 | #define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 |
| 7133 | #define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF | 7133 | #define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF |
| 7134 | #define B_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 | 7134 | #define B_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 |
| 7135 | #define B_SC_RA_RAM_FR_8K_TAP_SH__A 0x82005A | 7135 | #define B_SC_RA_RAM_FR_8K_TAP_SH__A 0x82005A |
| 7136 | #define B_SC_RA_RAM_FR_8K_TAP_SH__W 16 | 7136 | #define B_SC_RA_RAM_FR_8K_TAP_SH__W 16 |
| 7137 | #define B_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF | 7137 | #define B_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF |
| 7138 | #define B_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x4 | 7138 | #define B_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x4 |
| 7139 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x82005B | 7139 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x82005B |
| 7140 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 | 7140 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 |
| 7141 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF | 7141 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF |
| 7142 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 | 7142 | #define B_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 |
| 7143 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__A 0x82005C | 7143 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__A 0x82005C |
| 7144 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__W 16 | 7144 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__W 16 |
| 7145 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF | 7145 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF |
| 7146 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 | 7146 | #define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 |
| 7147 | 7147 | ||
| 7148 | #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D | 7148 | #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D |
| 7149 | #define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 | 7149 | #define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 |
| 7150 | #define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF | 7150 | #define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF |
| 7151 | #define B_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB | 7151 | #define B_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB |
| 7152 | #define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E | 7152 | #define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E |
| 7153 | #define B_SC_RA_RAM_CO_TD_CAL_8K__W 16 | 7153 | #define B_SC_RA_RAM_CO_TD_CAL_8K__W 16 |
| 7154 | #define B_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF | 7154 | #define B_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF |
| 7155 | #define B_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 | 7155 | #define B_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 |
| 7156 | #define B_SC_RA_RAM_MOTION_OFFSET__A 0x82005F | 7156 | #define B_SC_RA_RAM_MOTION_OFFSET__A 0x82005F |
| 7157 | #define B_SC_RA_RAM_MOTION_OFFSET__W 16 | 7157 | #define B_SC_RA_RAM_MOTION_OFFSET__W 16 |
| 7158 | #define B_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF | 7158 | #define B_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF |
| 7159 | #define B_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 | 7159 | #define B_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 |
| 7160 | #define B_SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 | 7160 | #define B_SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 |
| 7161 | #define B_SC_RA_RAM_STATE_PROC_STOP__XSZ 10 | 7161 | #define B_SC_RA_RAM_STATE_PROC_STOP__XSZ 10 |
| 7162 | #define B_SC_RA_RAM_STATE_PROC_STOP__W 16 | 7162 | #define B_SC_RA_RAM_STATE_PROC_STOP__W 16 |
| 7163 | #define B_SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF | 7163 | #define B_SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF |
| 7164 | #define B_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE | 7164 | #define B_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE |
| 7165 | #define B_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 | 7165 | #define B_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 |
| 7166 | #define B_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 | 7166 | #define B_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 |
| 7167 | #define B_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 | 7167 | #define B_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 |
| 7168 | #define B_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 | 7168 | #define B_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 |
| 7169 | #define B_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 | 7169 | #define B_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 |
| 7170 | #define B_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 | 7170 | #define B_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 |
| 7171 | #define B_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 | 7171 | #define B_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 |
| 7172 | #define B_SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 | 7172 | #define B_SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 |
| 7173 | #define B_SC_RA_RAM_STATE_PROC_STOP_10__PRE 0xFFFE | 7173 | #define B_SC_RA_RAM_STATE_PROC_STOP_10__PRE 0xFFFE |
| 7174 | #define B_SC_RA_RAM_STATE_PROC_START__AX 0x820070 | 7174 | #define B_SC_RA_RAM_STATE_PROC_START__AX 0x820070 |
| 7175 | #define B_SC_RA_RAM_STATE_PROC_START__XSZ 10 | 7175 | #define B_SC_RA_RAM_STATE_PROC_START__XSZ 10 |
| 7176 | #define B_SC_RA_RAM_STATE_PROC_START__W 16 | 7176 | #define B_SC_RA_RAM_STATE_PROC_START__W 16 |
| 7177 | #define B_SC_RA_RAM_STATE_PROC_START__M 0xFFFF | 7177 | #define B_SC_RA_RAM_STATE_PROC_START__M 0xFFFF |
| 7178 | #define B_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 | 7178 | #define B_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 |
| 7179 | #define B_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 | 7179 | #define B_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 |
| 7180 | #define B_SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 | 7180 | #define B_SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 |
| 7181 | #define B_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 | 7181 | #define B_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 |
| 7182 | #define B_SC_RA_RAM_STATE_PROC_START_5__PRE 0x100 | 7182 | #define B_SC_RA_RAM_STATE_PROC_START_5__PRE 0x100 |
| 7183 | #define B_SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 | 7183 | #define B_SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 |
| 7184 | #define B_SC_RA_RAM_STATE_PROC_START_7__PRE 0x40 | 7184 | #define B_SC_RA_RAM_STATE_PROC_START_7__PRE 0x40 |
| 7185 | #define B_SC_RA_RAM_STATE_PROC_START_8__PRE 0x10 | 7185 | #define B_SC_RA_RAM_STATE_PROC_START_8__PRE 0x10 |
| 7186 | #define B_SC_RA_RAM_STATE_PROC_START_9__PRE 0x30 | 7186 | #define B_SC_RA_RAM_STATE_PROC_START_9__PRE 0x30 |
| 7187 | #define B_SC_RA_RAM_STATE_PROC_START_10__PRE 0x0 | 7187 | #define B_SC_RA_RAM_STATE_PROC_START_10__PRE 0x0 |
| 7188 | #define B_SC_RA_RAM_IF_SAVE__AX 0x82008E | 7188 | #define B_SC_RA_RAM_IF_SAVE__AX 0x82008E |
| 7189 | #define B_SC_RA_RAM_IF_SAVE__XSZ 2 | 7189 | #define B_SC_RA_RAM_IF_SAVE__XSZ 2 |
| 7190 | #define B_SC_RA_RAM_IF_SAVE__W 16 | 7190 | #define B_SC_RA_RAM_IF_SAVE__W 16 |
| 7191 | #define B_SC_RA_RAM_IF_SAVE__M 0xFFFF | 7191 | #define B_SC_RA_RAM_IF_SAVE__M 0xFFFF |
| 7192 | #define B_SC_RA_RAM_FR_THRES__A 0x82007D | 7192 | #define B_SC_RA_RAM_FR_THRES__A 0x82007D |
| 7193 | #define B_SC_RA_RAM_FR_THRES__W 16 | 7193 | #define B_SC_RA_RAM_FR_THRES__W 16 |
| 7194 | #define B_SC_RA_RAM_FR_THRES__M 0xFFFF | 7194 | #define B_SC_RA_RAM_FR_THRES__M 0xFFFF |
| 7195 | #define B_SC_RA_RAM_FR_THRES__PRE 0x1A2C | 7195 | #define B_SC_RA_RAM_FR_THRES__PRE 0x1A2C |
| 7196 | #define B_SC_RA_RAM_STATUS__A 0x82007E | 7196 | #define B_SC_RA_RAM_STATUS__A 0x82007E |
| 7197 | #define B_SC_RA_RAM_STATUS__W 16 | 7197 | #define B_SC_RA_RAM_STATUS__W 16 |
| 7198 | #define B_SC_RA_RAM_STATUS__M 0xFFFF | 7198 | #define B_SC_RA_RAM_STATUS__M 0xFFFF |
| 7199 | #define B_SC_RA_RAM_NF_BORDER_INIT__A 0x82007F | 7199 | #define B_SC_RA_RAM_NF_BORDER_INIT__A 0x82007F |
| 7200 | #define B_SC_RA_RAM_NF_BORDER_INIT__W 16 | 7200 | #define B_SC_RA_RAM_NF_BORDER_INIT__W 16 |
| 7201 | #define B_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF | 7201 | #define B_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF |
| 7202 | #define B_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 | 7202 | #define B_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 |
| 7203 | #define B_SC_RA_RAM_TIMER__A 0x820080 | 7203 | #define B_SC_RA_RAM_TIMER__A 0x820080 |
| 7204 | #define B_SC_RA_RAM_TIMER__W 16 | 7204 | #define B_SC_RA_RAM_TIMER__W 16 |
| 7205 | #define B_SC_RA_RAM_TIMER__M 0xFFFF | 7205 | #define B_SC_RA_RAM_TIMER__M 0xFFFF |
| 7206 | #define B_SC_RA_RAM_FI_OFFSET__A 0x820081 | 7206 | #define B_SC_RA_RAM_FI_OFFSET__A 0x820081 |
| 7207 | #define B_SC_RA_RAM_FI_OFFSET__W 16 | 7207 | #define B_SC_RA_RAM_FI_OFFSET__W 16 |
| 7208 | #define B_SC_RA_RAM_FI_OFFSET__M 0xFFFF | 7208 | #define B_SC_RA_RAM_FI_OFFSET__M 0xFFFF |
| 7209 | #define B_SC_RA_RAM_FI_OFFSET__PRE 0x382 | 7209 | #define B_SC_RA_RAM_FI_OFFSET__PRE 0x382 |
| 7210 | #define B_SC_RA_RAM_ECHO_GUARD__A 0x820082 | 7210 | #define B_SC_RA_RAM_ECHO_GUARD__A 0x820082 |
| 7211 | #define B_SC_RA_RAM_ECHO_GUARD__W 16 | 7211 | #define B_SC_RA_RAM_ECHO_GUARD__W 16 |
| 7212 | #define B_SC_RA_RAM_ECHO_GUARD__M 0xFFFF | 7212 | #define B_SC_RA_RAM_ECHO_GUARD__M 0xFFFF |
| 7213 | #define B_SC_RA_RAM_ECHO_GUARD__PRE 0x18 | 7213 | #define B_SC_RA_RAM_ECHO_GUARD__PRE 0x18 |
| 7214 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__A 0x8200BA | 7214 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__A 0x8200BA |
| 7215 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__W 16 | 7215 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__W 16 |
| 7216 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__M 0xFFFF | 7216 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__M 0xFFFF |
| 7217 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__PRE 0x3 | 7217 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__PRE 0x3 |
| 7218 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__A 0x8200BB | 7218 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__A 0x8200BB |
| 7219 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__W 16 | 7219 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__W 16 |
| 7220 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF | 7220 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF |
| 7221 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 | 7221 | #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 |
| 7222 | 7222 | ||
| 7223 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 | 7223 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 |
| 7224 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 | 7224 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 |
| 7225 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF | 7225 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF |
| 7226 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 | 7226 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 |
| 7227 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 | 7227 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 |
| 7228 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 | 7228 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 |
| 7229 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF | 7229 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF |
| 7230 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 | 7230 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 |
| 7231 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A | 7231 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A |
| 7232 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 | 7232 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 |
| 7233 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF | 7233 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF |
| 7234 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 | 7234 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 |
| 7235 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B | 7235 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B |
| 7236 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 | 7236 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 |
| 7237 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF | 7237 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF |
| 7238 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 | 7238 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 |
| 7239 | 7239 | ||
| 7240 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C | 7240 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C |
| 7241 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 | 7241 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 |
| 7242 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF | 7242 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF |
| 7243 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC | 7243 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC |
| 7244 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D | 7244 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D |
| 7245 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 | 7245 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 |
| 7246 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF | 7246 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF |
| 7247 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC | 7247 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC |
| 7248 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E | 7248 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E |
| 7249 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 | 7249 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 |
| 7250 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF | 7250 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF |
| 7251 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC | 7251 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC |
| 7252 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F | 7252 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F |
| 7253 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 | 7253 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 |
| 7254 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF | 7254 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF |
| 7255 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC | 7255 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC |
| 7256 | 7256 | ||
| 7257 | #define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 | 7257 | #define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 |
| 7258 | #define B_SC_RA_RAM_IR_FREQ__W 16 | 7258 | #define B_SC_RA_RAM_IR_FREQ__W 16 |
| 7259 | #define B_SC_RA_RAM_IR_FREQ__M 0xFFFF | 7259 | #define B_SC_RA_RAM_IR_FREQ__M 0xFFFF |
| 7260 | #define B_SC_RA_RAM_IR_FREQ__PRE 0x0 | 7260 | #define B_SC_RA_RAM_IR_FREQ__PRE 0x0 |
| 7261 | 7261 | ||
| 7262 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 | 7262 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 |
| 7263 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 | 7263 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 |
| 7264 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF | 7264 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF |
| 7265 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 | 7265 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 |
| 7266 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 | 7266 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 |
| 7267 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 | 7267 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 |
| 7268 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF | 7268 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF |
| 7269 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 | 7269 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 |
| 7270 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 | 7270 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 |
| 7271 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 | 7271 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 |
| 7272 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF | 7272 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF |
| 7273 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 | 7273 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 |
| 7274 | 7274 | ||
| 7275 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 | 7275 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 |
| 7276 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 | 7276 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 |
| 7277 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF | 7277 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF |
| 7278 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 | 7278 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 |
| 7279 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 | 7279 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 |
| 7280 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 | 7280 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 |
| 7281 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF | 7281 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF |
| 7282 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 | 7282 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 |
| 7283 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 | 7283 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 |
| 7284 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 | 7284 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 |
| 7285 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF | 7285 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF |
| 7286 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 | 7286 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 |
| 7287 | 7287 | ||
| 7288 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 | 7288 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 |
| 7289 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 | 7289 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 |
| 7290 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF | 7290 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF |
| 7291 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 | 7291 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 |
| 7292 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 | 7292 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 |
| 7293 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 | 7293 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 |
| 7294 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF | 7294 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF |
| 7295 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 | 7295 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 |
| 7296 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 | 7296 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 |
| 7297 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 | 7297 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 |
| 7298 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF | 7298 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF |
| 7299 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 | 7299 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 |
| 7300 | 7300 | ||
| 7301 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA | 7301 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA |
| 7302 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 | 7302 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 |
| 7303 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF | 7303 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF |
| 7304 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB | 7304 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB |
| 7305 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB | 7305 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB |
| 7306 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 | 7306 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 |
| 7307 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF | 7307 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF |
| 7308 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 | 7308 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 |
| 7309 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC | 7309 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC |
| 7310 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 | 7310 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 |
| 7311 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF | 7311 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF |
| 7312 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 | 7312 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 |
| 7313 | 7313 | ||
| 7314 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD | 7314 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD |
| 7315 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 | 7315 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 |
| 7316 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF | 7316 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF |
| 7317 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 | 7317 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 |
| 7318 | #define B_SC_RA_RAM_ECHO_SHT_LIM__A 0x8200DE | 7318 | #define B_SC_RA_RAM_ECHO_SHT_LIM__A 0x8200DE |
| 7319 | #define B_SC_RA_RAM_ECHO_SHT_LIM__W 16 | 7319 | #define B_SC_RA_RAM_ECHO_SHT_LIM__W 16 |
| 7320 | #define B_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF | 7320 | #define B_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF |
| 7321 | #define B_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 | 7321 | #define B_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 |
| 7322 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x8200DF | 7322 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x8200DF |
| 7323 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 | 7323 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 |
| 7324 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF | 7324 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF |
| 7325 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0xCC0 | 7325 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0xCC0 |
| 7326 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 | 7326 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 |
| 7327 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 | 7327 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 |
| 7328 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF | 7328 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF |
| 7329 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 | 7329 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 |
| 7330 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 | 7330 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 |
| 7331 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 | 7331 | #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 |
| 7332 | 7332 | ||
| 7333 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 | 7333 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 |
| 7334 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 | 7334 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 |
| 7335 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF | 7335 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF |
| 7336 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 | 7336 | #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 |
| 7337 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 | 7337 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 |
| 7338 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 | 7338 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 |
| 7339 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF | 7339 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF |
| 7340 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 | 7340 | #define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 |
| 7341 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 | 7341 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 |
| 7342 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 | 7342 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 |
| 7343 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF | 7343 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF |
| 7344 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 | 7344 | #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 |
| 7345 | 7345 | ||
| 7346 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 | 7346 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 |
| 7347 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 | 7347 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 |
| 7348 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF | 7348 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF |
| 7349 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE | 7349 | #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE |
| 7350 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 | 7350 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 |
| 7351 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 | 7351 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 |
| 7352 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF | 7352 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF |
| 7353 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 | 7353 | #define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 |
| 7354 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 | 7354 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 |
| 7355 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 | 7355 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 |
| 7356 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF | 7356 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF |
| 7357 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 | 7357 | #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 |
| 7358 | 7358 | ||
| 7359 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 | 7359 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 |
| 7360 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 | 7360 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 |
| 7361 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF | 7361 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF |
| 7362 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 | 7362 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 |
| 7363 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 | 7363 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 |
| 7364 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 | 7364 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 |
| 7365 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF | 7365 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF |
| 7366 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C | 7366 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C |
| 7367 | 7367 | ||
| 7368 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA | 7368 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA |
| 7369 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 | 7369 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 |
| 7370 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF | 7370 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF |
| 7371 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 | 7371 | #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 |
| 7372 | #define B_SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB | 7372 | #define B_SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB |
| 7373 | #define B_SC_RA_RAM_TPS_TIMEOUT__W 16 | 7373 | #define B_SC_RA_RAM_TPS_TIMEOUT__W 16 |
| 7374 | #define B_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF | 7374 | #define B_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF |
| 7375 | #define B_SC_RA_RAM_BAND__A 0x8200EC | 7375 | #define B_SC_RA_RAM_BAND__A 0x8200EC |
| 7376 | #define B_SC_RA_RAM_BAND__W 16 | 7376 | #define B_SC_RA_RAM_BAND__W 16 |
| 7377 | #define B_SC_RA_RAM_BAND__M 0xFFFF | 7377 | #define B_SC_RA_RAM_BAND__M 0xFFFF |
| 7378 | #define B_SC_RA_RAM_BAND__PRE 0x0 | 7378 | #define B_SC_RA_RAM_BAND__PRE 0x0 |
| 7379 | #define B_SC_RA_RAM_BAND_INTERVAL__B 0 | 7379 | #define B_SC_RA_RAM_BAND_INTERVAL__B 0 |
| 7380 | #define B_SC_RA_RAM_BAND_INTERVAL__W 4 | 7380 | #define B_SC_RA_RAM_BAND_INTERVAL__W 4 |
| 7381 | #define B_SC_RA_RAM_BAND_INTERVAL__M 0xF | 7381 | #define B_SC_RA_RAM_BAND_INTERVAL__M 0xF |
| 7382 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 | 7382 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 |
| 7383 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 | 7383 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 |
| 7384 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 | 7384 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 |
| 7385 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 | 7385 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 |
| 7386 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 | 7386 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 |
| 7387 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 | 7387 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 |
| 7388 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 | 7388 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 |
| 7389 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 | 7389 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 |
| 7390 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 | 7390 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 |
| 7391 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 | 7391 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 |
| 7392 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 | 7392 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 |
| 7393 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 | 7393 | #define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 |
| 7394 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 | 7394 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 |
| 7395 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 | 7395 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 |
| 7396 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 | 7396 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 |
| 7397 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 | 7397 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 |
| 7398 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 | 7398 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 |
| 7399 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 | 7399 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 |
| 7400 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 | 7400 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 |
| 7401 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 | 7401 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 |
| 7402 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 | 7402 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 |
| 7403 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 | 7403 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 |
| 7404 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 | 7404 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 |
| 7405 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 | 7405 | #define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 |
| 7406 | 7406 | ||
| 7407 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED | 7407 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED |
| 7408 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 | 7408 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 |
| 7409 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF | 7409 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF |
| 7410 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 | 7410 | #define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 |
| 7411 | #define B_SC_RA_RAM_REG__AX 0x8200F0 | 7411 | #define B_SC_RA_RAM_REG__AX 0x8200F0 |
| 7412 | #define B_SC_RA_RAM_REG__XSZ 2 | 7412 | #define B_SC_RA_RAM_REG__XSZ 2 |
| 7413 | #define B_SC_RA_RAM_REG__W 16 | 7413 | #define B_SC_RA_RAM_REG__W 16 |
| 7414 | #define B_SC_RA_RAM_REG__M 0xFFFF | 7414 | #define B_SC_RA_RAM_REG__M 0xFFFF |
| 7415 | #define B_SC_RA_RAM_BREAK__A 0x8200F2 | 7415 | #define B_SC_RA_RAM_BREAK__A 0x8200F2 |
| 7416 | #define B_SC_RA_RAM_BREAK__W 16 | 7416 | #define B_SC_RA_RAM_BREAK__W 16 |
| 7417 | #define B_SC_RA_RAM_BREAK__M 0xFFFF | 7417 | #define B_SC_RA_RAM_BREAK__M 0xFFFF |
| 7418 | #define B_SC_RA_RAM_BOOTCOUNT__A 0x8200F3 | 7418 | #define B_SC_RA_RAM_BOOTCOUNT__A 0x8200F3 |
| 7419 | #define B_SC_RA_RAM_BOOTCOUNT__W 16 | 7419 | #define B_SC_RA_RAM_BOOTCOUNT__W 16 |
| 7420 | #define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF | 7420 | #define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF |
| 7421 | 7421 | ||
| 7422 | #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 | 7422 | #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 |
| 7423 | #define B_SC_RA_RAM_LC_ABS_2K__W 16 | 7423 | #define B_SC_RA_RAM_LC_ABS_2K__W 16 |
| 7424 | #define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF | 7424 | #define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF |
| 7425 | #define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F | 7425 | #define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F |
| 7426 | #define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 | 7426 | #define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 |
| 7427 | #define B_SC_RA_RAM_LC_ABS_8K__W 16 | 7427 | #define B_SC_RA_RAM_LC_ABS_8K__W 16 |
| 7428 | #define B_SC_RA_RAM_LC_ABS_8K__M 0xFFFF | 7428 | #define B_SC_RA_RAM_LC_ABS_8K__M 0xFFFF |
| 7429 | #define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F | 7429 | #define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F |
| 7430 | #define B_SC_RA_RAM_NE_ERR_SELECT__A 0x8200F6 | 7430 | #define B_SC_RA_RAM_NE_ERR_SELECT__A 0x8200F6 |
| 7431 | #define B_SC_RA_RAM_NE_ERR_SELECT__W 16 | 7431 | #define B_SC_RA_RAM_NE_ERR_SELECT__W 16 |
| 7432 | #define B_SC_RA_RAM_NE_ERR_SELECT__M 0xFFFF | 7432 | #define B_SC_RA_RAM_NE_ERR_SELECT__M 0xFFFF |
| 7433 | #define B_SC_RA_RAM_NE_ERR_SELECT__PRE 0x19 | 7433 | #define B_SC_RA_RAM_NE_ERR_SELECT__PRE 0x19 |
| 7434 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x8200F7 | 7434 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x8200F7 |
| 7435 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 | 7435 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 |
| 7436 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF | 7436 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF |
| 7437 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 | 7437 | #define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 |
| 7438 | #define B_SC_RA_RAM_RELOCK__A 0x8200FE | 7438 | #define B_SC_RA_RAM_RELOCK__A 0x8200FE |
| 7439 | #define B_SC_RA_RAM_RELOCK__W 16 | 7439 | #define B_SC_RA_RAM_RELOCK__W 16 |
| 7440 | #define B_SC_RA_RAM_RELOCK__M 0xFFFF | 7440 | #define B_SC_RA_RAM_RELOCK__M 0xFFFF |
| 7441 | #define B_SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF | 7441 | #define B_SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF |
| 7442 | #define B_SC_RA_RAM_STACKUNDERFLOW__W 16 | 7442 | #define B_SC_RA_RAM_STACKUNDERFLOW__W 16 |
| 7443 | #define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF | 7443 | #define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF |
| 7444 | 7444 | ||
| 7445 | #define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 | 7445 | #define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 |
| 7446 | #define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 | 7446 | #define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 |
| 7447 | #define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF | 7447 | #define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF |
| 7448 | #define B_SC_RA_RAM_NF_PREPOST__A 0x820149 | 7448 | #define B_SC_RA_RAM_NF_PREPOST__A 0x820149 |
| 7449 | #define B_SC_RA_RAM_NF_PREPOST__W 16 | 7449 | #define B_SC_RA_RAM_NF_PREPOST__W 16 |
| 7450 | #define B_SC_RA_RAM_NF_PREPOST__M 0xFFFF | 7450 | #define B_SC_RA_RAM_NF_PREPOST__M 0xFFFF |
| 7451 | #define B_SC_RA_RAM_NF_PREBORDER__A 0x82014A | 7451 | #define B_SC_RA_RAM_NF_PREBORDER__A 0x82014A |
| 7452 | #define B_SC_RA_RAM_NF_PREBORDER__W 16 | 7452 | #define B_SC_RA_RAM_NF_PREBORDER__W 16 |
| 7453 | #define B_SC_RA_RAM_NF_PREBORDER__M 0xFFFF | 7453 | #define B_SC_RA_RAM_NF_PREBORDER__M 0xFFFF |
| 7454 | #define B_SC_RA_RAM_NF_START__A 0x82014B | 7454 | #define B_SC_RA_RAM_NF_START__A 0x82014B |
| 7455 | #define B_SC_RA_RAM_NF_START__W 16 | 7455 | #define B_SC_RA_RAM_NF_START__W 16 |
| 7456 | #define B_SC_RA_RAM_NF_START__M 0xFFFF | 7456 | #define B_SC_RA_RAM_NF_START__M 0xFFFF |
| 7457 | #define B_SC_RA_RAM_NF_MINISI__AX 0x82014C | 7457 | #define B_SC_RA_RAM_NF_MINISI__AX 0x82014C |
| 7458 | #define B_SC_RA_RAM_NF_MINISI__XSZ 2 | 7458 | #define B_SC_RA_RAM_NF_MINISI__XSZ 2 |
| 7459 | #define B_SC_RA_RAM_NF_MINISI__W 16 | 7459 | #define B_SC_RA_RAM_NF_MINISI__W 16 |
| 7460 | #define B_SC_RA_RAM_NF_MINISI__M 0xFFFF | 7460 | #define B_SC_RA_RAM_NF_MINISI__M 0xFFFF |
| 7461 | #define B_SC_RA_RAM_NF_MAXECHO__A 0x82014E | 7461 | #define B_SC_RA_RAM_NF_MAXECHO__A 0x82014E |
| 7462 | #define B_SC_RA_RAM_NF_MAXECHO__W 16 | 7462 | #define B_SC_RA_RAM_NF_MAXECHO__W 16 |
| 7463 | #define B_SC_RA_RAM_NF_MAXECHO__M 0xFFFF | 7463 | #define B_SC_RA_RAM_NF_MAXECHO__M 0xFFFF |
| 7464 | #define B_SC_RA_RAM_NF_NRECHOES__A 0x82014F | 7464 | #define B_SC_RA_RAM_NF_NRECHOES__A 0x82014F |
| 7465 | #define B_SC_RA_RAM_NF_NRECHOES__W 16 | 7465 | #define B_SC_RA_RAM_NF_NRECHOES__W 16 |
| 7466 | #define B_SC_RA_RAM_NF_NRECHOES__M 0xFFFF | 7466 | #define B_SC_RA_RAM_NF_NRECHOES__M 0xFFFF |
| 7467 | #define B_SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 | 7467 | #define B_SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 |
| 7468 | #define B_SC_RA_RAM_NF_ECHOTABLE__XSZ 16 | 7468 | #define B_SC_RA_RAM_NF_ECHOTABLE__XSZ 16 |
| 7469 | #define B_SC_RA_RAM_NF_ECHOTABLE__W 16 | 7469 | #define B_SC_RA_RAM_NF_ECHOTABLE__W 16 |
| 7470 | #define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF | 7470 | #define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF |
| 7471 | 7471 | ||
| 7472 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 | 7472 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 |
| 7473 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 | 7473 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 |
| 7474 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF | 7474 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF |
| 7475 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 | 7475 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 |
| 7476 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 | 7476 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 |
| 7477 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 | 7477 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 |
| 7478 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF | 7478 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF |
| 7479 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 | 7479 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 |
| 7480 | 7480 | ||
| 7481 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 | 7481 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 |
| 7482 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 | 7482 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 |
| 7483 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF | 7483 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF |
| 7484 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 | 7484 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 |
| 7485 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 | 7485 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 |
| 7486 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 | 7486 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 |
| 7487 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF | 7487 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF |
| 7488 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 | 7488 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 |
| 7489 | 7489 | ||
| 7490 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 | 7490 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 |
| 7491 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 | 7491 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 |
| 7492 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF | 7492 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF |
| 7493 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D | 7493 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D |
| 7494 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 | 7494 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 |
| 7495 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 | 7495 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 |
| 7496 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF | 7496 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF |
| 7497 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 | 7497 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 |
| 7498 | 7498 | ||
| 7499 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 | 7499 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 |
| 7500 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 | 7500 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 |
| 7501 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF | 7501 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF |
| 7502 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D | 7502 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D |
| 7503 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 | 7503 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 |
| 7504 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 | 7504 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 |
| 7505 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF | 7505 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF |
| 7506 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 | 7506 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 |
| 7507 | 7507 | ||
| 7508 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 | 7508 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 |
| 7509 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 | 7509 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 |
| 7510 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF | 7510 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF |
| 7511 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 | 7511 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 |
| 7512 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 | 7512 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 |
| 7513 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 | 7513 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 |
| 7514 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF | 7514 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF |
| 7515 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 | 7515 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 |
| 7516 | 7516 | ||
| 7517 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA | 7517 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA |
| 7518 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 | 7518 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 |
| 7519 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF | 7519 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF |
| 7520 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 | 7520 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 |
| 7521 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB | 7521 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB |
| 7522 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 | 7522 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 |
| 7523 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF | 7523 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF |
| 7524 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 | 7524 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 |
| 7525 | 7525 | ||
| 7526 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC | 7526 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC |
| 7527 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 | 7527 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 |
| 7528 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF | 7528 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF |
| 7529 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A | 7529 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A |
| 7530 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD | 7530 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD |
| 7531 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 | 7531 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 |
| 7532 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF | 7532 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF |
| 7533 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 | 7533 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 |
| 7534 | 7534 | ||
| 7535 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE | 7535 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE |
| 7536 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 | 7536 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 |
| 7537 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF | 7537 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF |
| 7538 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB | 7538 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB |
| 7539 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF | 7539 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF |
| 7540 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 | 7540 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 |
| 7541 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF | 7541 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF |
| 7542 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 | 7542 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 |
| 7543 | #define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE | 7543 | #define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE |
| 7544 | #define B_SC_RA_RAM_DRIVER_VERSION__XSZ 2 | 7544 | #define B_SC_RA_RAM_DRIVER_VERSION__XSZ 2 |
| 7545 | #define B_SC_RA_RAM_DRIVER_VERSION__W 16 | 7545 | #define B_SC_RA_RAM_DRIVER_VERSION__W 16 |
| 7546 | #define B_SC_RA_RAM_DRIVER_VERSION__M 0xFFFF | 7546 | #define B_SC_RA_RAM_DRIVER_VERSION__M 0xFFFF |
| 7547 | #define B_SC_RA_RAM_EVENT0_MIN 0x7 | 7547 | #define B_SC_RA_RAM_EVENT0_MIN 0x7 |
| 7548 | #define B_SC_RA_RAM_EVENT0_FE_CU 0x7 | 7548 | #define B_SC_RA_RAM_EVENT0_FE_CU 0x7 |
| 7549 | #define B_SC_RA_RAM_EVENT0_CE 0xA | 7549 | #define B_SC_RA_RAM_EVENT0_CE 0xA |
| 7550 | #define B_SC_RA_RAM_EVENT0_EQ 0xE | 7550 | #define B_SC_RA_RAM_EVENT0_EQ 0xE |
| 7551 | #define B_SC_RA_RAM_EVENT0_MAX 0xF | 7551 | #define B_SC_RA_RAM_EVENT0_MAX 0xF |
| 7552 | #define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 | 7552 | #define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 |
| 7553 | #define B_SC_RA_RAM_PROC_MODE_GUARD 0x1 | 7553 | #define B_SC_RA_RAM_PROC_MODE_GUARD 0x1 |
| 7554 | #define B_SC_RA_RAM_PROC_PILOTS 0x2 | 7554 | #define B_SC_RA_RAM_PROC_PILOTS 0x2 |
| 7555 | #define B_SC_RA_RAM_PROC_FESTART_ADJUST 0x3 | 7555 | #define B_SC_RA_RAM_PROC_FESTART_ADJUST 0x3 |
| 7556 | #define B_SC_RA_RAM_PROC_ECHO 0x4 | 7556 | #define B_SC_RA_RAM_PROC_ECHO 0x4 |
| 7557 | #define B_SC_RA_RAM_PROC_BE_OPT 0x5 | 7557 | #define B_SC_RA_RAM_PROC_BE_OPT 0x5 |
| 7558 | #define B_SC_RA_RAM_PROC_LOCK_MON 0x6 | 7558 | #define B_SC_RA_RAM_PROC_LOCK_MON 0x6 |
| 7559 | #define B_SC_RA_RAM_PROC_EQ 0x7 | 7559 | #define B_SC_RA_RAM_PROC_EQ 0x7 |
| 7560 | #define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 | 7560 | #define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 |
| 7561 | #define B_SC_RA_RAM_PROC_MAX 0x9 | 7561 | #define B_SC_RA_RAM_PROC_MAX 0x9 |
| 7562 | 7562 | ||
| 7563 | #define B_SC_IF_RAM_TRP_RST__AX 0x830000 | 7563 | #define B_SC_IF_RAM_TRP_RST__AX 0x830000 |
| 7564 | #define B_SC_IF_RAM_TRP_RST__XSZ 2 | 7564 | #define B_SC_IF_RAM_TRP_RST__XSZ 2 |
| 7565 | #define B_SC_IF_RAM_TRP_RST__W 12 | 7565 | #define B_SC_IF_RAM_TRP_RST__W 12 |
| 7566 | #define B_SC_IF_RAM_TRP_RST__M 0xFFF | 7566 | #define B_SC_IF_RAM_TRP_RST__M 0xFFF |
| 7567 | 7567 | ||
| 7568 | #define B_SC_IF_RAM_TRP_BPT0__AX 0x830002 | 7568 | #define B_SC_IF_RAM_TRP_BPT0__AX 0x830002 |
| 7569 | #define B_SC_IF_RAM_TRP_BPT0__XSZ 2 | 7569 | #define B_SC_IF_RAM_TRP_BPT0__XSZ 2 |
| 7570 | #define B_SC_IF_RAM_TRP_BPT0__W 12 | 7570 | #define B_SC_IF_RAM_TRP_BPT0__W 12 |
| 7571 | #define B_SC_IF_RAM_TRP_BPT0__M 0xFFF | 7571 | #define B_SC_IF_RAM_TRP_BPT0__M 0xFFF |
| 7572 | 7572 | ||
| 7573 | #define B_SC_IF_RAM_TRP_STKU__AX 0x830004 | 7573 | #define B_SC_IF_RAM_TRP_STKU__AX 0x830004 |
| 7574 | #define B_SC_IF_RAM_TRP_STKU__XSZ 2 | 7574 | #define B_SC_IF_RAM_TRP_STKU__XSZ 2 |
| 7575 | #define B_SC_IF_RAM_TRP_STKU__W 12 | 7575 | #define B_SC_IF_RAM_TRP_STKU__W 12 |
| 7576 | #define B_SC_IF_RAM_TRP_STKU__M 0xFFF | 7576 | #define B_SC_IF_RAM_TRP_STKU__M 0xFFF |
| 7577 | 7577 | ||
| 7578 | #define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE | 7578 | #define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE |
| 7579 | #define B_SC_IF_RAM_VERSION_MA_MI__W 12 | 7579 | #define B_SC_IF_RAM_VERSION_MA_MI__W 12 |
| 7580 | #define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF | 7580 | #define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF |
| 7581 | 7581 | ||
| 7582 | #define B_SC_IF_RAM_VERSION_PATCH__A 0x830FFF | 7582 | #define B_SC_IF_RAM_VERSION_PATCH__A 0x830FFF |
| 7583 | #define B_SC_IF_RAM_VERSION_PATCH__W 12 | 7583 | #define B_SC_IF_RAM_VERSION_PATCH__W 12 |
| 7584 | #define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF | 7584 | #define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF |
| 7585 | 7585 | ||
| 7586 | #define B_FE_COMM_EXEC__A 0xC00000 | 7586 | #define B_FE_COMM_EXEC__A 0xC00000 |
| 7587 | #define B_FE_COMM_EXEC__W 3 | 7587 | #define B_FE_COMM_EXEC__W 3 |
| 7588 | #define B_FE_COMM_EXEC__M 0x7 | 7588 | #define B_FE_COMM_EXEC__M 0x7 |
| 7589 | #define B_FE_COMM_EXEC_CTL__B 0 | 7589 | #define B_FE_COMM_EXEC_CTL__B 0 |
| 7590 | #define B_FE_COMM_EXEC_CTL__W 3 | 7590 | #define B_FE_COMM_EXEC_CTL__W 3 |
| 7591 | #define B_FE_COMM_EXEC_CTL__M 0x7 | 7591 | #define B_FE_COMM_EXEC_CTL__M 0x7 |
| 7592 | #define B_FE_COMM_EXEC_CTL_STOP 0x0 | 7592 | #define B_FE_COMM_EXEC_CTL_STOP 0x0 |
| 7593 | #define B_FE_COMM_EXEC_CTL_ACTIVE 0x1 | 7593 | #define B_FE_COMM_EXEC_CTL_ACTIVE 0x1 |
| 7594 | #define B_FE_COMM_EXEC_CTL_HOLD 0x2 | 7594 | #define B_FE_COMM_EXEC_CTL_HOLD 0x2 |
| 7595 | #define B_FE_COMM_EXEC_CTL_STEP 0x3 | 7595 | #define B_FE_COMM_EXEC_CTL_STEP 0x3 |
| 7596 | #define B_FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 7596 | #define B_FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 7597 | #define B_FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 7597 | #define B_FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 7598 | 7598 | ||
| 7599 | #define B_FE_COMM_STATE__A 0xC00001 | 7599 | #define B_FE_COMM_STATE__A 0xC00001 |
| 7600 | #define B_FE_COMM_STATE__W 16 | 7600 | #define B_FE_COMM_STATE__W 16 |
| 7601 | #define B_FE_COMM_STATE__M 0xFFFF | 7601 | #define B_FE_COMM_STATE__M 0xFFFF |
| 7602 | #define B_FE_COMM_MB__A 0xC00002 | 7602 | #define B_FE_COMM_MB__A 0xC00002 |
| 7603 | #define B_FE_COMM_MB__W 16 | 7603 | #define B_FE_COMM_MB__W 16 |
| 7604 | #define B_FE_COMM_MB__M 0xFFFF | 7604 | #define B_FE_COMM_MB__M 0xFFFF |
| 7605 | #define B_FE_COMM_SERVICE0__A 0xC00003 | 7605 | #define B_FE_COMM_SERVICE0__A 0xC00003 |
| 7606 | #define B_FE_COMM_SERVICE0__W 16 | 7606 | #define B_FE_COMM_SERVICE0__W 16 |
| 7607 | #define B_FE_COMM_SERVICE0__M 0xFFFF | 7607 | #define B_FE_COMM_SERVICE0__M 0xFFFF |
| 7608 | #define B_FE_COMM_SERVICE1__A 0xC00004 | 7608 | #define B_FE_COMM_SERVICE1__A 0xC00004 |
| 7609 | #define B_FE_COMM_SERVICE1__W 16 | 7609 | #define B_FE_COMM_SERVICE1__W 16 |
| 7610 | #define B_FE_COMM_SERVICE1__M 0xFFFF | 7610 | #define B_FE_COMM_SERVICE1__M 0xFFFF |
| 7611 | #define B_FE_COMM_INT_STA__A 0xC00007 | 7611 | #define B_FE_COMM_INT_STA__A 0xC00007 |
| 7612 | #define B_FE_COMM_INT_STA__W 16 | 7612 | #define B_FE_COMM_INT_STA__W 16 |
| 7613 | #define B_FE_COMM_INT_STA__M 0xFFFF | 7613 | #define B_FE_COMM_INT_STA__M 0xFFFF |
| 7614 | #define B_FE_COMM_INT_MSK__A 0xC00008 | 7614 | #define B_FE_COMM_INT_MSK__A 0xC00008 |
| 7615 | #define B_FE_COMM_INT_MSK__W 16 | 7615 | #define B_FE_COMM_INT_MSK__W 16 |
| 7616 | #define B_FE_COMM_INT_MSK__M 0xFFFF | 7616 | #define B_FE_COMM_INT_MSK__M 0xFFFF |
| 7617 | 7617 | ||
| 7618 | #define B_FE_AD_SID 0x1 | 7618 | #define B_FE_AD_SID 0x1 |
| 7619 | 7619 | ||
| 7620 | #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 | 7620 | #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 |
| 7621 | #define B_FE_AD_REG_COMM_EXEC__W 3 | 7621 | #define B_FE_AD_REG_COMM_EXEC__W 3 |
| 7622 | #define B_FE_AD_REG_COMM_EXEC__M 0x7 | 7622 | #define B_FE_AD_REG_COMM_EXEC__M 0x7 |
| 7623 | #define B_FE_AD_REG_COMM_EXEC_CTL__B 0 | 7623 | #define B_FE_AD_REG_COMM_EXEC_CTL__B 0 |
| 7624 | #define B_FE_AD_REG_COMM_EXEC_CTL__W 3 | 7624 | #define B_FE_AD_REG_COMM_EXEC_CTL__W 3 |
| 7625 | #define B_FE_AD_REG_COMM_EXEC_CTL__M 0x7 | 7625 | #define B_FE_AD_REG_COMM_EXEC_CTL__M 0x7 |
| 7626 | #define B_FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 | 7626 | #define B_FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 7627 | #define B_FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 7627 | #define B_FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 7628 | #define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 | 7628 | #define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 7629 | #define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 | 7629 | #define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 |
| 7630 | 7630 | ||
| 7631 | #define B_FE_AD_REG_COMM_MB__A 0xC10002 | 7631 | #define B_FE_AD_REG_COMM_MB__A 0xC10002 |
| 7632 | #define B_FE_AD_REG_COMM_MB__W 2 | 7632 | #define B_FE_AD_REG_COMM_MB__W 2 |
| 7633 | #define B_FE_AD_REG_COMM_MB__M 0x3 | 7633 | #define B_FE_AD_REG_COMM_MB__M 0x3 |
| 7634 | #define B_FE_AD_REG_COMM_MB_CTR__B 0 | 7634 | #define B_FE_AD_REG_COMM_MB_CTR__B 0 |
| 7635 | #define B_FE_AD_REG_COMM_MB_CTR__W 1 | 7635 | #define B_FE_AD_REG_COMM_MB_CTR__W 1 |
| 7636 | #define B_FE_AD_REG_COMM_MB_CTR__M 0x1 | 7636 | #define B_FE_AD_REG_COMM_MB_CTR__M 0x1 |
| 7637 | #define B_FE_AD_REG_COMM_MB_CTR_OFF 0x0 | 7637 | #define B_FE_AD_REG_COMM_MB_CTR_OFF 0x0 |
| 7638 | #define B_FE_AD_REG_COMM_MB_CTR_ON 0x1 | 7638 | #define B_FE_AD_REG_COMM_MB_CTR_ON 0x1 |
| 7639 | #define B_FE_AD_REG_COMM_MB_OBS__B 1 | 7639 | #define B_FE_AD_REG_COMM_MB_OBS__B 1 |
| 7640 | #define B_FE_AD_REG_COMM_MB_OBS__W 1 | 7640 | #define B_FE_AD_REG_COMM_MB_OBS__W 1 |
| 7641 | #define B_FE_AD_REG_COMM_MB_OBS__M 0x2 | 7641 | #define B_FE_AD_REG_COMM_MB_OBS__M 0x2 |
| 7642 | #define B_FE_AD_REG_COMM_MB_OBS_OFF 0x0 | 7642 | #define B_FE_AD_REG_COMM_MB_OBS_OFF 0x0 |
| 7643 | #define B_FE_AD_REG_COMM_MB_OBS_ON 0x2 | 7643 | #define B_FE_AD_REG_COMM_MB_OBS_ON 0x2 |
| 7644 | 7644 | ||
| 7645 | #define B_FE_AD_REG_COMM_SERVICE0__A 0xC10003 | 7645 | #define B_FE_AD_REG_COMM_SERVICE0__A 0xC10003 |
| 7646 | #define B_FE_AD_REG_COMM_SERVICE0__W 10 | 7646 | #define B_FE_AD_REG_COMM_SERVICE0__W 10 |
| 7647 | #define B_FE_AD_REG_COMM_SERVICE0__M 0x3FF | 7647 | #define B_FE_AD_REG_COMM_SERVICE0__M 0x3FF |
| 7648 | #define B_FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 | 7648 | #define B_FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 |
| 7649 | #define B_FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 | 7649 | #define B_FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 |
| 7650 | #define B_FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 | 7650 | #define B_FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 |
| 7651 | 7651 | ||
| 7652 | #define B_FE_AD_REG_COMM_SERVICE1__A 0xC10004 | 7652 | #define B_FE_AD_REG_COMM_SERVICE1__A 0xC10004 |
| 7653 | #define B_FE_AD_REG_COMM_SERVICE1__W 11 | 7653 | #define B_FE_AD_REG_COMM_SERVICE1__W 11 |
| 7654 | #define B_FE_AD_REG_COMM_SERVICE1__M 0x7FF | 7654 | #define B_FE_AD_REG_COMM_SERVICE1__M 0x7FF |
| 7655 | 7655 | ||
| 7656 | #define B_FE_AD_REG_COMM_INT_STA__A 0xC10007 | 7656 | #define B_FE_AD_REG_COMM_INT_STA__A 0xC10007 |
| 7657 | #define B_FE_AD_REG_COMM_INT_STA__W 2 | 7657 | #define B_FE_AD_REG_COMM_INT_STA__W 2 |
| 7658 | #define B_FE_AD_REG_COMM_INT_STA__M 0x3 | 7658 | #define B_FE_AD_REG_COMM_INT_STA__M 0x3 |
| 7659 | #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 | 7659 | #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 |
| 7660 | #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 | 7660 | #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 |
| 7661 | #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 | 7661 | #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 |
| 7662 | 7662 | ||
| 7663 | #define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 | 7663 | #define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 |
| 7664 | #define B_FE_AD_REG_COMM_INT_MSK__W 2 | 7664 | #define B_FE_AD_REG_COMM_INT_MSK__W 2 |
| 7665 | #define B_FE_AD_REG_COMM_INT_MSK__M 0x3 | 7665 | #define B_FE_AD_REG_COMM_INT_MSK__M 0x3 |
| 7666 | #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 | 7666 | #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 |
| 7667 | #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 | 7667 | #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 |
| 7668 | #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 | 7668 | #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 |
| 7669 | 7669 | ||
| 7670 | #define B_FE_AD_REG_CUR_SEL__A 0xC10010 | 7670 | #define B_FE_AD_REG_CUR_SEL__A 0xC10010 |
| 7671 | #define B_FE_AD_REG_CUR_SEL__W 2 | 7671 | #define B_FE_AD_REG_CUR_SEL__W 2 |
| 7672 | #define B_FE_AD_REG_CUR_SEL__M 0x3 | 7672 | #define B_FE_AD_REG_CUR_SEL__M 0x3 |
| 7673 | #define B_FE_AD_REG_CUR_SEL_INIT 0x2 | 7673 | #define B_FE_AD_REG_CUR_SEL_INIT 0x2 |
| 7674 | 7674 | ||
| 7675 | #define B_FE_AD_REG_OVERFLOW__A 0xC10011 | 7675 | #define B_FE_AD_REG_OVERFLOW__A 0xC10011 |
| 7676 | #define B_FE_AD_REG_OVERFLOW__W 1 | 7676 | #define B_FE_AD_REG_OVERFLOW__W 1 |
| 7677 | #define B_FE_AD_REG_OVERFLOW__M 0x1 | 7677 | #define B_FE_AD_REG_OVERFLOW__M 0x1 |
| 7678 | #define B_FE_AD_REG_OVERFLOW_INIT 0x0 | 7678 | #define B_FE_AD_REG_OVERFLOW_INIT 0x0 |
| 7679 | 7679 | ||
| 7680 | #define B_FE_AD_REG_FDB_IN__A 0xC10012 | 7680 | #define B_FE_AD_REG_FDB_IN__A 0xC10012 |
| 7681 | #define B_FE_AD_REG_FDB_IN__W 1 | 7681 | #define B_FE_AD_REG_FDB_IN__W 1 |
| 7682 | #define B_FE_AD_REG_FDB_IN__M 0x1 | 7682 | #define B_FE_AD_REG_FDB_IN__M 0x1 |
| 7683 | #define B_FE_AD_REG_FDB_IN_INIT 0x0 | 7683 | #define B_FE_AD_REG_FDB_IN_INIT 0x0 |
| 7684 | 7684 | ||
| 7685 | #define B_FE_AD_REG_PD__A 0xC10013 | 7685 | #define B_FE_AD_REG_PD__A 0xC10013 |
| 7686 | #define B_FE_AD_REG_PD__W 1 | 7686 | #define B_FE_AD_REG_PD__W 1 |
| 7687 | #define B_FE_AD_REG_PD__M 0x1 | 7687 | #define B_FE_AD_REG_PD__M 0x1 |
| 7688 | #define B_FE_AD_REG_PD_INIT 0x1 | 7688 | #define B_FE_AD_REG_PD_INIT 0x1 |
| 7689 | 7689 | ||
| 7690 | #define B_FE_AD_REG_INVEXT__A 0xC10014 | 7690 | #define B_FE_AD_REG_INVEXT__A 0xC10014 |
| 7691 | #define B_FE_AD_REG_INVEXT__W 1 | 7691 | #define B_FE_AD_REG_INVEXT__W 1 |
| 7692 | #define B_FE_AD_REG_INVEXT__M 0x1 | 7692 | #define B_FE_AD_REG_INVEXT__M 0x1 |
| 7693 | #define B_FE_AD_REG_INVEXT_INIT 0x0 | 7693 | #define B_FE_AD_REG_INVEXT_INIT 0x0 |
| 7694 | 7694 | ||
| 7695 | #define B_FE_AD_REG_CLKNEG__A 0xC10015 | 7695 | #define B_FE_AD_REG_CLKNEG__A 0xC10015 |
| 7696 | #define B_FE_AD_REG_CLKNEG__W 1 | 7696 | #define B_FE_AD_REG_CLKNEG__W 1 |
| 7697 | #define B_FE_AD_REG_CLKNEG__M 0x1 | 7697 | #define B_FE_AD_REG_CLKNEG__M 0x1 |
| 7698 | #define B_FE_AD_REG_CLKNEG_INIT 0x0 | 7698 | #define B_FE_AD_REG_CLKNEG_INIT 0x0 |
| 7699 | 7699 | ||
| 7700 | #define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 | 7700 | #define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 |
| 7701 | #define B_FE_AD_REG_MON_IN_MUX__W 2 | 7701 | #define B_FE_AD_REG_MON_IN_MUX__W 2 |
| 7702 | #define B_FE_AD_REG_MON_IN_MUX__M 0x3 | 7702 | #define B_FE_AD_REG_MON_IN_MUX__M 0x3 |
| 7703 | #define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 | 7703 | #define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 |
| 7704 | 7704 | ||
| 7705 | #define B_FE_AD_REG_MON_IN5__A 0xC10017 | 7705 | #define B_FE_AD_REG_MON_IN5__A 0xC10017 |
| 7706 | #define B_FE_AD_REG_MON_IN5__W 10 | 7706 | #define B_FE_AD_REG_MON_IN5__W 10 |
| 7707 | #define B_FE_AD_REG_MON_IN5__M 0x3FF | 7707 | #define B_FE_AD_REG_MON_IN5__M 0x3FF |
| 7708 | #define B_FE_AD_REG_MON_IN5_INIT 0x0 | 7708 | #define B_FE_AD_REG_MON_IN5_INIT 0x0 |
| 7709 | 7709 | ||
| 7710 | #define B_FE_AD_REG_MON_IN4__A 0xC10018 | 7710 | #define B_FE_AD_REG_MON_IN4__A 0xC10018 |
| 7711 | #define B_FE_AD_REG_MON_IN4__W 10 | 7711 | #define B_FE_AD_REG_MON_IN4__W 10 |
| 7712 | #define B_FE_AD_REG_MON_IN4__M 0x3FF | 7712 | #define B_FE_AD_REG_MON_IN4__M 0x3FF |
| 7713 | #define B_FE_AD_REG_MON_IN4_INIT 0x0 | 7713 | #define B_FE_AD_REG_MON_IN4_INIT 0x0 |
| 7714 | 7714 | ||
| 7715 | #define B_FE_AD_REG_MON_IN3__A 0xC10019 | 7715 | #define B_FE_AD_REG_MON_IN3__A 0xC10019 |
| 7716 | #define B_FE_AD_REG_MON_IN3__W 10 | 7716 | #define B_FE_AD_REG_MON_IN3__W 10 |
| 7717 | #define B_FE_AD_REG_MON_IN3__M 0x3FF | 7717 | #define B_FE_AD_REG_MON_IN3__M 0x3FF |
| 7718 | #define B_FE_AD_REG_MON_IN3_INIT 0x0 | 7718 | #define B_FE_AD_REG_MON_IN3_INIT 0x0 |
| 7719 | 7719 | ||
| 7720 | #define B_FE_AD_REG_MON_IN2__A 0xC1001A | 7720 | #define B_FE_AD_REG_MON_IN2__A 0xC1001A |
| 7721 | #define B_FE_AD_REG_MON_IN2__W 10 | 7721 | #define B_FE_AD_REG_MON_IN2__W 10 |
| 7722 | #define B_FE_AD_REG_MON_IN2__M 0x3FF | 7722 | #define B_FE_AD_REG_MON_IN2__M 0x3FF |
| 7723 | #define B_FE_AD_REG_MON_IN2_INIT 0x0 | 7723 | #define B_FE_AD_REG_MON_IN2_INIT 0x0 |
| 7724 | 7724 | ||
| 7725 | #define B_FE_AD_REG_MON_IN1__A 0xC1001B | 7725 | #define B_FE_AD_REG_MON_IN1__A 0xC1001B |
| 7726 | #define B_FE_AD_REG_MON_IN1__W 10 | 7726 | #define B_FE_AD_REG_MON_IN1__W 10 |
| 7727 | #define B_FE_AD_REG_MON_IN1__M 0x3FF | 7727 | #define B_FE_AD_REG_MON_IN1__M 0x3FF |
| 7728 | #define B_FE_AD_REG_MON_IN1_INIT 0x0 | 7728 | #define B_FE_AD_REG_MON_IN1_INIT 0x0 |
| 7729 | 7729 | ||
| 7730 | #define B_FE_AD_REG_MON_IN0__A 0xC1001C | 7730 | #define B_FE_AD_REG_MON_IN0__A 0xC1001C |
| 7731 | #define B_FE_AD_REG_MON_IN0__W 10 | 7731 | #define B_FE_AD_REG_MON_IN0__W 10 |
| 7732 | #define B_FE_AD_REG_MON_IN0__M 0x3FF | 7732 | #define B_FE_AD_REG_MON_IN0__M 0x3FF |
| 7733 | #define B_FE_AD_REG_MON_IN0_INIT 0x0 | 7733 | #define B_FE_AD_REG_MON_IN0_INIT 0x0 |
| 7734 | 7734 | ||
| 7735 | #define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D | 7735 | #define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D |
| 7736 | #define B_FE_AD_REG_MON_IN_VAL__W 1 | 7736 | #define B_FE_AD_REG_MON_IN_VAL__W 1 |
| 7737 | #define B_FE_AD_REG_MON_IN_VAL__M 0x1 | 7737 | #define B_FE_AD_REG_MON_IN_VAL__M 0x1 |
| 7738 | #define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 | 7738 | #define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 |
| 7739 | 7739 | ||
| 7740 | #define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E | 7740 | #define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E |
| 7741 | #define B_FE_AD_REG_CTR_CLK_O__W 1 | 7741 | #define B_FE_AD_REG_CTR_CLK_O__W 1 |
| 7742 | #define B_FE_AD_REG_CTR_CLK_O__M 0x1 | 7742 | #define B_FE_AD_REG_CTR_CLK_O__M 0x1 |
| 7743 | #define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 | 7743 | #define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 |
| 7744 | 7744 | ||
| 7745 | #define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F | 7745 | #define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F |
| 7746 | #define B_FE_AD_REG_CTR_CLK_E_O__W 1 | 7746 | #define B_FE_AD_REG_CTR_CLK_E_O__W 1 |
| 7747 | #define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 | 7747 | #define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 |
| 7748 | #define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 | 7748 | #define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 |
| 7749 | 7749 | ||
| 7750 | #define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 | 7750 | #define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 |
| 7751 | #define B_FE_AD_REG_CTR_VAL_O__W 1 | 7751 | #define B_FE_AD_REG_CTR_VAL_O__W 1 |
| 7752 | #define B_FE_AD_REG_CTR_VAL_O__M 0x1 | 7752 | #define B_FE_AD_REG_CTR_VAL_O__M 0x1 |
| 7753 | #define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 | 7753 | #define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 |
| 7754 | 7754 | ||
| 7755 | #define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 | 7755 | #define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 |
| 7756 | #define B_FE_AD_REG_CTR_VAL_E_O__W 1 | 7756 | #define B_FE_AD_REG_CTR_VAL_E_O__W 1 |
| 7757 | #define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 | 7757 | #define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 |
| 7758 | #define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 | 7758 | #define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 |
| 7759 | 7759 | ||
| 7760 | #define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 | 7760 | #define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 |
| 7761 | #define B_FE_AD_REG_CTR_DATA_O__W 10 | 7761 | #define B_FE_AD_REG_CTR_DATA_O__W 10 |
| 7762 | #define B_FE_AD_REG_CTR_DATA_O__M 0x3FF | 7762 | #define B_FE_AD_REG_CTR_DATA_O__M 0x3FF |
| 7763 | #define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 | 7763 | #define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 |
| 7764 | 7764 | ||
| 7765 | #define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 | 7765 | #define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 |
| 7766 | #define B_FE_AD_REG_CTR_DATA_E_O__W 10 | 7766 | #define B_FE_AD_REG_CTR_DATA_E_O__W 10 |
| 7767 | #define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF | 7767 | #define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF |
| 7768 | #define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF | 7768 | #define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF |
| 7769 | 7769 | ||
| 7770 | #define B_FE_AG_SID 0x2 | 7770 | #define B_FE_AG_SID 0x2 |
| 7771 | 7771 | ||
| 7772 | #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 | 7772 | #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 |
| 7773 | #define B_FE_AG_REG_COMM_EXEC__W 3 | 7773 | #define B_FE_AG_REG_COMM_EXEC__W 3 |
| 7774 | #define B_FE_AG_REG_COMM_EXEC__M 0x7 | 7774 | #define B_FE_AG_REG_COMM_EXEC__M 0x7 |
| 7775 | #define B_FE_AG_REG_COMM_EXEC_CTL__B 0 | 7775 | #define B_FE_AG_REG_COMM_EXEC_CTL__B 0 |
| 7776 | #define B_FE_AG_REG_COMM_EXEC_CTL__W 3 | 7776 | #define B_FE_AG_REG_COMM_EXEC_CTL__W 3 |
| 7777 | #define B_FE_AG_REG_COMM_EXEC_CTL__M 0x7 | 7777 | #define B_FE_AG_REG_COMM_EXEC_CTL__M 0x7 |
| 7778 | #define B_FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 | 7778 | #define B_FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 |
| 7779 | #define B_FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 7779 | #define B_FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 7780 | #define B_FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 | 7780 | #define B_FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 7781 | #define B_FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 | 7781 | #define B_FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 |
| 7782 | 7782 | ||
| 7783 | #define B_FE_AG_REG_COMM_STATE__A 0xC20001 | 7783 | #define B_FE_AG_REG_COMM_STATE__A 0xC20001 |
| 7784 | #define B_FE_AG_REG_COMM_STATE__W 4 | 7784 | #define B_FE_AG_REG_COMM_STATE__W 4 |
| 7785 | #define B_FE_AG_REG_COMM_STATE__M 0xF | 7785 | #define B_FE_AG_REG_COMM_STATE__M 0xF |
| 7786 | 7786 | ||
| 7787 | #define B_FE_AG_REG_COMM_MB__A 0xC20002 | 7787 | #define B_FE_AG_REG_COMM_MB__A 0xC20002 |
| 7788 | #define B_FE_AG_REG_COMM_MB__W 4 | 7788 | #define B_FE_AG_REG_COMM_MB__W 4 |
| 7789 | #define B_FE_AG_REG_COMM_MB__M 0xF | 7789 | #define B_FE_AG_REG_COMM_MB__M 0xF |
| 7790 | #define B_FE_AG_REG_COMM_MB_OBS__B 1 | 7790 | #define B_FE_AG_REG_COMM_MB_OBS__B 1 |
| 7791 | #define B_FE_AG_REG_COMM_MB_OBS__W 1 | 7791 | #define B_FE_AG_REG_COMM_MB_OBS__W 1 |
| 7792 | #define B_FE_AG_REG_COMM_MB_OBS__M 0x2 | 7792 | #define B_FE_AG_REG_COMM_MB_OBS__M 0x2 |
| 7793 | #define B_FE_AG_REG_COMM_MB_OBS_OFF 0x0 | 7793 | #define B_FE_AG_REG_COMM_MB_OBS_OFF 0x0 |
| 7794 | #define B_FE_AG_REG_COMM_MB_OBS_ON 0x2 | 7794 | #define B_FE_AG_REG_COMM_MB_OBS_ON 0x2 |
| 7795 | #define B_FE_AG_REG_COMM_MB_MUX__B 2 | 7795 | #define B_FE_AG_REG_COMM_MB_MUX__B 2 |
| 7796 | #define B_FE_AG_REG_COMM_MB_MUX__W 2 | 7796 | #define B_FE_AG_REG_COMM_MB_MUX__W 2 |
| 7797 | #define B_FE_AG_REG_COMM_MB_MUX__M 0xC | 7797 | #define B_FE_AG_REG_COMM_MB_MUX__M 0xC |
| 7798 | #define B_FE_AG_REG_COMM_MB_MUX_DAT 0x0 | 7798 | #define B_FE_AG_REG_COMM_MB_MUX_DAT 0x0 |
| 7799 | #define B_FE_AG_REG_COMM_MB_MUX_DAT_PD2 0x4 | 7799 | #define B_FE_AG_REG_COMM_MB_MUX_DAT_PD2 0x4 |
| 7800 | #define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 | 7800 | #define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 |
| 7801 | #define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC | 7801 | #define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC |
| 7802 | 7802 | ||
| 7803 | #define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 | 7803 | #define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 |
| 7804 | #define B_FE_AG_REG_COMM_SERVICE0__W 10 | 7804 | #define B_FE_AG_REG_COMM_SERVICE0__W 10 |
| 7805 | #define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF | 7805 | #define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF |
| 7806 | 7806 | ||
| 7807 | #define B_FE_AG_REG_COMM_SERVICE1__A 0xC20004 | 7807 | #define B_FE_AG_REG_COMM_SERVICE1__A 0xC20004 |
| 7808 | #define B_FE_AG_REG_COMM_SERVICE1__W 11 | 7808 | #define B_FE_AG_REG_COMM_SERVICE1__W 11 |
| 7809 | #define B_FE_AG_REG_COMM_SERVICE1__M 0x7FF | 7809 | #define B_FE_AG_REG_COMM_SERVICE1__M 0x7FF |
| 7810 | 7810 | ||
| 7811 | #define B_FE_AG_REG_COMM_INT_STA__A 0xC20007 | 7811 | #define B_FE_AG_REG_COMM_INT_STA__A 0xC20007 |
| 7812 | #define B_FE_AG_REG_COMM_INT_STA__W 8 | 7812 | #define B_FE_AG_REG_COMM_INT_STA__W 8 |
| 7813 | #define B_FE_AG_REG_COMM_INT_STA__M 0xFF | 7813 | #define B_FE_AG_REG_COMM_INT_STA__M 0xFF |
| 7814 | #define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 | 7814 | #define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 |
| 7815 | #define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 | 7815 | #define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 |
| 7816 | #define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 | 7816 | #define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 |
| 7817 | #define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 | 7817 | #define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 |
| 7818 | #define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 | 7818 | #define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 |
| 7819 | #define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 | 7819 | #define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 |
| 7820 | #define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 | 7820 | #define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 |
| 7821 | #define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 | 7821 | #define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 |
| 7822 | #define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 | 7822 | #define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 |
| 7823 | #define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 | 7823 | #define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 |
| 7824 | #define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 | 7824 | #define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 |
| 7825 | #define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 | 7825 | #define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 |
| 7826 | #define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 | 7826 | #define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 |
| 7827 | #define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 | 7827 | #define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 |
| 7828 | #define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 | 7828 | #define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 |
| 7829 | #define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 | 7829 | #define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 |
| 7830 | #define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 | 7830 | #define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 |
| 7831 | #define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 | 7831 | #define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 |
| 7832 | #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 | 7832 | #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 |
| 7833 | #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 | 7833 | #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 |
| 7834 | #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 | 7834 | #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 |
| 7835 | 7835 | ||
| 7836 | #define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 | 7836 | #define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 |
| 7837 | #define B_FE_AG_REG_COMM_INT_MSK__W 8 | 7837 | #define B_FE_AG_REG_COMM_INT_MSK__W 8 |
| 7838 | #define B_FE_AG_REG_COMM_INT_MSK__M 0xFF | 7838 | #define B_FE_AG_REG_COMM_INT_MSK__M 0xFF |
| 7839 | #define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 | 7839 | #define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 |
| 7840 | #define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 | 7840 | #define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 |
| 7841 | #define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 | 7841 | #define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 |
| 7842 | #define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 | 7842 | #define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 |
| 7843 | #define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 | 7843 | #define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 |
| 7844 | #define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 | 7844 | #define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 |
| 7845 | #define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 | 7845 | #define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 |
| 7846 | #define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 | 7846 | #define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 |
| 7847 | #define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 | 7847 | #define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 |
| 7848 | #define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 | 7848 | #define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 |
| 7849 | #define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 | 7849 | #define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 |
| 7850 | #define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 | 7850 | #define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 |
| 7851 | #define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 | 7851 | #define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 |
| 7852 | #define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 | 7852 | #define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 |
| 7853 | #define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 | 7853 | #define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 |
| 7854 | #define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 | 7854 | #define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 |
| 7855 | #define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 | 7855 | #define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 |
| 7856 | #define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 | 7856 | #define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 |
| 7857 | #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 | 7857 | #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 |
| 7858 | #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 | 7858 | #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 |
| 7859 | #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 | 7859 | #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 |
| 7860 | 7860 | ||
| 7861 | #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 | 7861 | #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 |
| 7862 | #define B_FE_AG_REG_AG_MODE_LOP__W 15 | 7862 | #define B_FE_AG_REG_AG_MODE_LOP__W 15 |
| 7863 | #define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF | 7863 | #define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF |
| 7864 | #define B_FE_AG_REG_AG_MODE_LOP_INIT 0x81E | 7864 | #define B_FE_AG_REG_AG_MODE_LOP_INIT 0x81E |
| 7865 | 7865 | ||
| 7866 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 | 7866 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 |
| 7867 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 | 7867 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 |
| 7868 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 | 7868 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 |
| 7869 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 | 7869 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 |
| 7870 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 | 7870 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 |
| 7871 | 7871 | ||
| 7872 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 | 7872 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 |
| 7873 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 | 7873 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 |
| 7874 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 | 7874 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 |
| 7875 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 | 7875 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 |
| 7876 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 | 7876 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 |
| 7877 | 7877 | ||
| 7878 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 | 7878 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 |
| 7879 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 | 7879 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 |
| 7880 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 | 7880 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 |
| 7881 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 | 7881 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 |
| 7882 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 | 7882 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 |
| 7883 | 7883 | ||
| 7884 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 | 7884 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 |
| 7885 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 | 7885 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 |
| 7886 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 | 7886 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 |
| 7887 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 | 7887 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 |
| 7888 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 | 7888 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 |
| 7889 | 7889 | ||
| 7890 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 | 7890 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 |
| 7891 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 | 7891 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 |
| 7892 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 | 7892 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 |
| 7893 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 | 7893 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 |
| 7894 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 | 7894 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 |
| 7895 | 7895 | ||
| 7896 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 | 7896 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 |
| 7897 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 | 7897 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 |
| 7898 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 | 7898 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 |
| 7899 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 | 7899 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 |
| 7900 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 | 7900 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 |
| 7901 | 7901 | ||
| 7902 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 | 7902 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 |
| 7903 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 | 7903 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 |
| 7904 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 | 7904 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 |
| 7905 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 | 7905 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 |
| 7906 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 | 7906 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 |
| 7907 | 7907 | ||
| 7908 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 | 7908 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 |
| 7909 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 | 7909 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 |
| 7910 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 | 7910 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 |
| 7911 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 | 7911 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 |
| 7912 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 | 7912 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 |
| 7913 | 7913 | ||
| 7914 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 | 7914 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 |
| 7915 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 | 7915 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 |
| 7916 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 | 7916 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 |
| 7917 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 | 7917 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 |
| 7918 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 | 7918 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 |
| 7919 | 7919 | ||
| 7920 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 | 7920 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 |
| 7921 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 | 7921 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 |
| 7922 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 | 7922 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 |
| 7923 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 | 7923 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 |
| 7924 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 | 7924 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 |
| 7925 | 7925 | ||
| 7926 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 | 7926 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 |
| 7927 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 | 7927 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 |
| 7928 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 | 7928 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 |
| 7929 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 | 7929 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 |
| 7930 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 | 7930 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 |
| 7931 | 7931 | ||
| 7932 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 | 7932 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 |
| 7933 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 | 7933 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 |
| 7934 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 | 7934 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 |
| 7935 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 | 7935 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 |
| 7936 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 | 7936 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 |
| 7937 | 7937 | ||
| 7938 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 | 7938 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 |
| 7939 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 | 7939 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 |
| 7940 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 | 7940 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 |
| 7941 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 | 7941 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 |
| 7942 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 | 7942 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 |
| 7943 | 7943 | ||
| 7944 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 | 7944 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 |
| 7945 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 | 7945 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 |
| 7946 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 | 7946 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 |
| 7947 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 | 7947 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 |
| 7948 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 | 7948 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 |
| 7949 | 7949 | ||
| 7950 | #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 | 7950 | #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 |
| 7951 | #define B_FE_AG_REG_AG_MODE_HIP__W 5 | 7951 | #define B_FE_AG_REG_AG_MODE_HIP__W 5 |
| 7952 | #define B_FE_AG_REG_AG_MODE_HIP__M 0x1F | 7952 | #define B_FE_AG_REG_AG_MODE_HIP__M 0x1F |
| 7953 | #define B_FE_AG_REG_AG_MODE_HIP_INIT 0x0 | 7953 | #define B_FE_AG_REG_AG_MODE_HIP_INIT 0x0 |
| 7954 | 7954 | ||
| 7955 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 | 7955 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 |
| 7956 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 | 7956 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 |
| 7957 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 | 7957 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 |
| 7958 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 | 7958 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 |
| 7959 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 | 7959 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 |
| 7960 | 7960 | ||
| 7961 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 | 7961 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 |
| 7962 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 | 7962 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 |
| 7963 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 | 7963 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 |
| 7964 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 | 7964 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 |
| 7965 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 | 7965 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 |
| 7966 | 7966 | ||
| 7967 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I__B 2 | 7967 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I__B 2 |
| 7968 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I__W 1 | 7968 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I__W 1 |
| 7969 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I__M 0x4 | 7969 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I__M 0x4 |
| 7970 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH1 0x0 | 7970 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH1 0x0 |
| 7971 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH2 0x4 | 7971 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH2 0x4 |
| 7972 | 7972 | ||
| 7973 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__B 3 | 7973 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__B 3 |
| 7974 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__W 1 | 7974 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__W 1 |
| 7975 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 | 7975 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 |
| 7976 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 | 7976 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 |
| 7977 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 | 7977 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 |
| 7978 | 7978 | ||
| 7979 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K__B 4 | 7979 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K__B 4 |
| 7980 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K__W 1 | 7980 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K__W 1 |
| 7981 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K__M 0x10 | 7981 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K__M 0x10 |
| 7982 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 | 7982 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 |
| 7983 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 | 7983 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 |
| 7984 | 7984 | ||
| 7985 | #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 | 7985 | #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 |
| 7986 | #define B_FE_AG_REG_AG_PGA_MODE__W 3 | 7986 | #define B_FE_AG_REG_AG_PGA_MODE__W 3 |
| 7987 | #define B_FE_AG_REG_AG_PGA_MODE__M 0x7 | 7987 | #define B_FE_AG_REG_AG_PGA_MODE__M 0x7 |
| 7988 | #define B_FE_AG_REG_AG_PGA_MODE_INIT 0x3 | 7988 | #define B_FE_AG_REG_AG_PGA_MODE_INIT 0x3 |
| 7989 | #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 | 7989 | #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 |
| 7990 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 | 7990 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 |
| 7991 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 | 7991 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 |
| 7992 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 | 7992 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 |
| 7993 | #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 | 7993 | #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 |
| 7994 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 | 7994 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 |
| 7995 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 | 7995 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 |
| 7996 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 | 7996 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 |
| 7997 | 7997 | ||
| 7998 | #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 | 7998 | #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 |
| 7999 | #define B_FE_AG_REG_AG_AGC_SIO__W 2 | 7999 | #define B_FE_AG_REG_AG_AGC_SIO__W 2 |
| 8000 | #define B_FE_AG_REG_AG_AGC_SIO__M 0x3 | 8000 | #define B_FE_AG_REG_AG_AGC_SIO__M 0x3 |
| 8001 | #define B_FE_AG_REG_AG_AGC_SIO_INIT 0x3 | 8001 | #define B_FE_AG_REG_AG_AGC_SIO_INIT 0x3 |
| 8002 | 8002 | ||
| 8003 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 | 8003 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 |
| 8004 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 | 8004 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 |
| 8005 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 | 8005 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 |
| 8006 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 | 8006 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 |
| 8007 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 | 8007 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 |
| 8008 | 8008 | ||
| 8009 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 | 8009 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 |
| 8010 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 | 8010 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 |
| 8011 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 | 8011 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 |
| 8012 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 | 8012 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 |
| 8013 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 | 8013 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 |
| 8014 | 8014 | ||
| 8015 | #define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 | 8015 | #define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 |
| 8016 | #define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 | 8016 | #define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 |
| 8017 | #define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 | 8017 | #define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 |
| 8018 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 | 8018 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 |
| 8019 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 | 8019 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 |
| 8020 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 | 8020 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 |
| 8021 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 | 8021 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 |
| 8022 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 | 8022 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 |
| 8023 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 | 8023 | #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 |
| 8024 | 8024 | ||
| 8025 | #define B_FE_AG_REG_AG_PWD__A 0xC20015 | 8025 | #define B_FE_AG_REG_AG_PWD__A 0xC20015 |
| 8026 | #define B_FE_AG_REG_AG_PWD__W 5 | 8026 | #define B_FE_AG_REG_AG_PWD__W 5 |
| 8027 | #define B_FE_AG_REG_AG_PWD__M 0x1F | 8027 | #define B_FE_AG_REG_AG_PWD__M 0x1F |
| 8028 | #define B_FE_AG_REG_AG_PWD_INIT 0x6 | 8028 | #define B_FE_AG_REG_AG_PWD_INIT 0x6 |
| 8029 | 8029 | ||
| 8030 | #define B_FE_AG_REG_AG_PWD_PWD_PD1__B 0 | 8030 | #define B_FE_AG_REG_AG_PWD_PWD_PD1__B 0 |
| 8031 | #define B_FE_AG_REG_AG_PWD_PWD_PD1__W 1 | 8031 | #define B_FE_AG_REG_AG_PWD_PWD_PD1__W 1 |
| 8032 | #define B_FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 | 8032 | #define B_FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 |
| 8033 | #define B_FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 | 8033 | #define B_FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 |
| 8034 | #define B_FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 | 8034 | #define B_FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 |
| 8035 | 8035 | ||
| 8036 | #define B_FE_AG_REG_AG_PWD_PWD_PD2__B 1 | 8036 | #define B_FE_AG_REG_AG_PWD_PWD_PD2__B 1 |
| 8037 | #define B_FE_AG_REG_AG_PWD_PWD_PD2__W 1 | 8037 | #define B_FE_AG_REG_AG_PWD_PWD_PD2__W 1 |
| 8038 | #define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 | 8038 | #define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 |
| 8039 | #define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 | 8039 | #define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 |
| 8040 | #define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 | 8040 | #define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 |
| 8041 | 8041 | ||
| 8042 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 | 8042 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 |
| 8043 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 | 8043 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 |
| 8044 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 | 8044 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 |
| 8045 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 | 8045 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 |
| 8046 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 | 8046 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 |
| 8047 | 8047 | ||
| 8048 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 | 8048 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 |
| 8049 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 | 8049 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 |
| 8050 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 | 8050 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 |
| 8051 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 | 8051 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 |
| 8052 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 | 8052 | #define B_FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 |
| 8053 | 8053 | ||
| 8054 | #define B_FE_AG_REG_AG_PWD_PWD_AAF__B 4 | 8054 | #define B_FE_AG_REG_AG_PWD_PWD_AAF__B 4 |
| 8055 | #define B_FE_AG_REG_AG_PWD_PWD_AAF__W 1 | 8055 | #define B_FE_AG_REG_AG_PWD_PWD_AAF__W 1 |
| 8056 | #define B_FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 | 8056 | #define B_FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 |
| 8057 | #define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 | 8057 | #define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 |
| 8058 | #define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 | 8058 | #define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 |
| 8059 | 8059 | ||
| 8060 | #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 | 8060 | #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 |
| 8061 | #define B_FE_AG_REG_DCE_AUR_CNT__W 5 | 8061 | #define B_FE_AG_REG_DCE_AUR_CNT__W 5 |
| 8062 | #define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F | 8062 | #define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F |
| 8063 | #define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 | 8063 | #define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 |
| 8064 | 8064 | ||
| 8065 | #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 | 8065 | #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 |
| 8066 | #define B_FE_AG_REG_DCE_RUR_CNT__W 5 | 8066 | #define B_FE_AG_REG_DCE_RUR_CNT__W 5 |
| 8067 | #define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F | 8067 | #define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F |
| 8068 | #define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 | 8068 | #define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 |
| 8069 | 8069 | ||
| 8070 | #define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 | 8070 | #define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 |
| 8071 | #define B_FE_AG_REG_DCE_AVE_DAT__W 10 | 8071 | #define B_FE_AG_REG_DCE_AVE_DAT__W 10 |
| 8072 | #define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF | 8072 | #define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF |
| 8073 | 8073 | ||
| 8074 | #define B_FE_AG_REG_DEC_AVE_WRI__A 0xC20019 | 8074 | #define B_FE_AG_REG_DEC_AVE_WRI__A 0xC20019 |
| 8075 | #define B_FE_AG_REG_DEC_AVE_WRI__W 10 | 8075 | #define B_FE_AG_REG_DEC_AVE_WRI__W 10 |
| 8076 | #define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF | 8076 | #define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF |
| 8077 | #define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 | 8077 | #define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 |
| 8078 | 8078 | ||
| 8079 | #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A | 8079 | #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A |
| 8080 | #define B_FE_AG_REG_ACE_AUR_CNT__W 5 | 8080 | #define B_FE_AG_REG_ACE_AUR_CNT__W 5 |
| 8081 | #define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F | 8081 | #define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F |
| 8082 | #define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE | 8082 | #define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE |
| 8083 | 8083 | ||
| 8084 | #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B | 8084 | #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B |
| 8085 | #define B_FE_AG_REG_ACE_RUR_CNT__W 5 | 8085 | #define B_FE_AG_REG_ACE_RUR_CNT__W 5 |
| 8086 | #define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F | 8086 | #define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F |
| 8087 | #define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 | 8087 | #define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 |
| 8088 | 8088 | ||
| 8089 | #define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C | 8089 | #define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C |
| 8090 | #define B_FE_AG_REG_ACE_AVE_DAT__W 10 | 8090 | #define B_FE_AG_REG_ACE_AVE_DAT__W 10 |
| 8091 | #define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF | 8091 | #define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF |
| 8092 | 8092 | ||
| 8093 | #define B_FE_AG_REG_AEC_AVE_INC__A 0xC2001D | 8093 | #define B_FE_AG_REG_AEC_AVE_INC__A 0xC2001D |
| 8094 | #define B_FE_AG_REG_AEC_AVE_INC__W 10 | 8094 | #define B_FE_AG_REG_AEC_AVE_INC__W 10 |
| 8095 | #define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF | 8095 | #define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF |
| 8096 | #define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 | 8096 | #define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 |
| 8097 | 8097 | ||
| 8098 | #define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E | 8098 | #define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E |
| 8099 | #define B_FE_AG_REG_AEC_AVE_DAT__W 10 | 8099 | #define B_FE_AG_REG_AEC_AVE_DAT__W 10 |
| 8100 | #define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF | 8100 | #define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF |
| 8101 | 8101 | ||
| 8102 | #define B_FE_AG_REG_AEC_CLP_LVL__A 0xC2001F | 8102 | #define B_FE_AG_REG_AEC_CLP_LVL__A 0xC2001F |
| 8103 | #define B_FE_AG_REG_AEC_CLP_LVL__W 16 | 8103 | #define B_FE_AG_REG_AEC_CLP_LVL__W 16 |
| 8104 | #define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF | 8104 | #define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF |
| 8105 | #define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 | 8105 | #define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 |
| 8106 | 8106 | ||
| 8107 | #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 | 8107 | #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 |
| 8108 | #define B_FE_AG_REG_CDR_RUR_CNT__W 5 | 8108 | #define B_FE_AG_REG_CDR_RUR_CNT__W 5 |
| 8109 | #define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F | 8109 | #define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F |
| 8110 | #define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 | 8110 | #define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 |
| 8111 | 8111 | ||
| 8112 | #define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 | 8112 | #define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 |
| 8113 | #define B_FE_AG_REG_CDR_CLP_DAT__W 16 | 8113 | #define B_FE_AG_REG_CDR_CLP_DAT__W 16 |
| 8114 | #define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF | 8114 | #define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF |
| 8115 | 8115 | ||
| 8116 | #define B_FE_AG_REG_CDR_CLP_POS__A 0xC20022 | 8116 | #define B_FE_AG_REG_CDR_CLP_POS__A 0xC20022 |
| 8117 | #define B_FE_AG_REG_CDR_CLP_POS__W 10 | 8117 | #define B_FE_AG_REG_CDR_CLP_POS__W 10 |
| 8118 | #define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF | 8118 | #define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF |
| 8119 | #define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A | 8119 | #define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A |
| 8120 | 8120 | ||
| 8121 | #define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 | 8121 | #define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 |
| 8122 | #define B_FE_AG_REG_CDR_CLP_NEG__W 10 | 8122 | #define B_FE_AG_REG_CDR_CLP_NEG__W 10 |
| 8123 | #define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF | 8123 | #define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF |
| 8124 | #define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 | 8124 | #define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 |
| 8125 | 8125 | ||
| 8126 | #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 | 8126 | #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 |
| 8127 | #define B_FE_AG_REG_EGC_RUR_CNT__W 5 | 8127 | #define B_FE_AG_REG_EGC_RUR_CNT__W 5 |
| 8128 | #define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F | 8128 | #define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F |
| 8129 | #define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 | 8129 | #define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 |
| 8130 | 8130 | ||
| 8131 | #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 | 8131 | #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 |
| 8132 | #define B_FE_AG_REG_EGC_SET_LVL__W 9 | 8132 | #define B_FE_AG_REG_EGC_SET_LVL__W 9 |
| 8133 | #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF | 8133 | #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF |
| 8134 | #define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 | 8134 | #define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 |
| 8135 | 8135 | ||
| 8136 | #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 | 8136 | #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 |
| 8137 | #define B_FE_AG_REG_EGC_FLA_RGN__W 9 | 8137 | #define B_FE_AG_REG_EGC_FLA_RGN__W 9 |
| 8138 | #define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF | 8138 | #define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF |
| 8139 | #define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 | 8139 | #define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 |
| 8140 | 8140 | ||
| 8141 | #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 | 8141 | #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 |
| 8142 | #define B_FE_AG_REG_EGC_SLO_RGN__W 9 | 8142 | #define B_FE_AG_REG_EGC_SLO_RGN__W 9 |
| 8143 | #define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF | 8143 | #define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF |
| 8144 | #define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F | 8144 | #define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F |
| 8145 | 8145 | ||
| 8146 | #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 | 8146 | #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 |
| 8147 | #define B_FE_AG_REG_EGC_JMP_PSN__W 4 | 8147 | #define B_FE_AG_REG_EGC_JMP_PSN__W 4 |
| 8148 | #define B_FE_AG_REG_EGC_JMP_PSN__M 0xF | 8148 | #define B_FE_AG_REG_EGC_JMP_PSN__M 0xF |
| 8149 | #define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 | 8149 | #define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 |
| 8150 | 8150 | ||
| 8151 | #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 | 8151 | #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 |
| 8152 | #define B_FE_AG_REG_EGC_FLA_INC__W 16 | 8152 | #define B_FE_AG_REG_EGC_FLA_INC__W 16 |
| 8153 | #define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF | 8153 | #define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF |
| 8154 | #define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 | 8154 | #define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 |
| 8155 | 8155 | ||
| 8156 | #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A | 8156 | #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A |
| 8157 | #define B_FE_AG_REG_EGC_FLA_DEC__W 16 | 8157 | #define B_FE_AG_REG_EGC_FLA_DEC__W 16 |
| 8158 | #define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF | 8158 | #define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF |
| 8159 | #define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 | 8159 | #define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 |
| 8160 | 8160 | ||
| 8161 | #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B | 8161 | #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B |
| 8162 | #define B_FE_AG_REG_EGC_SLO_INC__W 16 | 8162 | #define B_FE_AG_REG_EGC_SLO_INC__W 16 |
| 8163 | #define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF | 8163 | #define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF |
| 8164 | #define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 | 8164 | #define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 |
| 8165 | 8165 | ||
| 8166 | #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C | 8166 | #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C |
| 8167 | #define B_FE_AG_REG_EGC_SLO_DEC__W 16 | 8167 | #define B_FE_AG_REG_EGC_SLO_DEC__W 16 |
| 8168 | #define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF | 8168 | #define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF |
| 8169 | #define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 | 8169 | #define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 |
| 8170 | 8170 | ||
| 8171 | #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D | 8171 | #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D |
| 8172 | #define B_FE_AG_REG_EGC_FAS_INC__W 16 | 8172 | #define B_FE_AG_REG_EGC_FAS_INC__W 16 |
| 8173 | #define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF | 8173 | #define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF |
| 8174 | #define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE | 8174 | #define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE |
| 8175 | 8175 | ||
| 8176 | #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E | 8176 | #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E |
| 8177 | #define B_FE_AG_REG_EGC_FAS_DEC__W 16 | 8177 | #define B_FE_AG_REG_EGC_FAS_DEC__W 16 |
| 8178 | #define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF | 8178 | #define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF |
| 8179 | #define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE | 8179 | #define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE |
| 8180 | 8180 | ||
| 8181 | #define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F | 8181 | #define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F |
| 8182 | #define B_FE_AG_REG_EGC_MAP_DAT__W 16 | 8182 | #define B_FE_AG_REG_EGC_MAP_DAT__W 16 |
| 8183 | #define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF | 8183 | #define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF |
| 8184 | 8184 | ||
| 8185 | #define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 | 8185 | #define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 |
| 8186 | #define B_FE_AG_REG_PM1_AGC_WRI__W 11 | 8186 | #define B_FE_AG_REG_PM1_AGC_WRI__W 11 |
| 8187 | #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF | 8187 | #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF |
| 8188 | #define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 | 8188 | #define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 |
| 8189 | 8189 | ||
| 8190 | #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 | 8190 | #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 |
| 8191 | #define B_FE_AG_REG_GC1_AGC_RIC__W 16 | 8191 | #define B_FE_AG_REG_GC1_AGC_RIC__W 16 |
| 8192 | #define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF | 8192 | #define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF |
| 8193 | #define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 | 8193 | #define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 |
| 8194 | 8194 | ||
| 8195 | #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 | 8195 | #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 |
| 8196 | #define B_FE_AG_REG_GC1_AGC_OFF__W 16 | 8196 | #define B_FE_AG_REG_GC1_AGC_OFF__W 16 |
| 8197 | #define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF | 8197 | #define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF |
| 8198 | #define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 | 8198 | #define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 |
| 8199 | 8199 | ||
| 8200 | #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 | 8200 | #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 |
| 8201 | #define B_FE_AG_REG_GC1_AGC_MAX__W 10 | 8201 | #define B_FE_AG_REG_GC1_AGC_MAX__W 10 |
| 8202 | #define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF | 8202 | #define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF |
| 8203 | #define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF | 8203 | #define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF |
| 8204 | 8204 | ||
| 8205 | #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 | 8205 | #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 |
| 8206 | #define B_FE_AG_REG_GC1_AGC_MIN__W 10 | 8206 | #define B_FE_AG_REG_GC1_AGC_MIN__W 10 |
| 8207 | #define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF | 8207 | #define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF |
| 8208 | #define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 | 8208 | #define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 |
| 8209 | 8209 | ||
| 8210 | #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 | 8210 | #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 |
| 8211 | #define B_FE_AG_REG_GC1_AGC_DAT__W 10 | 8211 | #define B_FE_AG_REG_GC1_AGC_DAT__W 10 |
| 8212 | #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF | 8212 | #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF |
| 8213 | 8213 | ||
| 8214 | #define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 | 8214 | #define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 |
| 8215 | #define B_FE_AG_REG_PM2_AGC_WRI__W 11 | 8215 | #define B_FE_AG_REG_PM2_AGC_WRI__W 11 |
| 8216 | #define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF | 8216 | #define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF |
| 8217 | #define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 | 8217 | #define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 |
| 8218 | 8218 | ||
| 8219 | #define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 | 8219 | #define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 |
| 8220 | #define B_FE_AG_REG_GC2_AGC_RIC__W 16 | 8220 | #define B_FE_AG_REG_GC2_AGC_RIC__W 16 |
| 8221 | #define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF | 8221 | #define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF |
| 8222 | #define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 | 8222 | #define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 |
| 8223 | 8223 | ||
| 8224 | #define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 | 8224 | #define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 |
| 8225 | #define B_FE_AG_REG_GC2_AGC_OFF__W 16 | 8225 | #define B_FE_AG_REG_GC2_AGC_OFF__W 16 |
| 8226 | #define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF | 8226 | #define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF |
| 8227 | #define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 | 8227 | #define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 |
| 8228 | 8228 | ||
| 8229 | #define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 | 8229 | #define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 |
| 8230 | #define B_FE_AG_REG_GC2_AGC_MAX__W 10 | 8230 | #define B_FE_AG_REG_GC2_AGC_MAX__W 10 |
| 8231 | #define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF | 8231 | #define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF |
| 8232 | #define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF | 8232 | #define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF |
| 8233 | 8233 | ||
| 8234 | #define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A | 8234 | #define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A |
| 8235 | #define B_FE_AG_REG_GC2_AGC_MIN__W 10 | 8235 | #define B_FE_AG_REG_GC2_AGC_MIN__W 10 |
| 8236 | #define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF | 8236 | #define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF |
| 8237 | #define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 | 8237 | #define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 |
| 8238 | 8238 | ||
| 8239 | #define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B | 8239 | #define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B |
| 8240 | #define B_FE_AG_REG_GC2_AGC_DAT__W 10 | 8240 | #define B_FE_AG_REG_GC2_AGC_DAT__W 10 |
| 8241 | #define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF | 8241 | #define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF |
| 8242 | 8242 | ||
| 8243 | #define B_FE_AG_REG_IND_WIN__A 0xC2003C | 8243 | #define B_FE_AG_REG_IND_WIN__A 0xC2003C |
| 8244 | #define B_FE_AG_REG_IND_WIN__W 5 | 8244 | #define B_FE_AG_REG_IND_WIN__W 5 |
| 8245 | #define B_FE_AG_REG_IND_WIN__M 0x1F | 8245 | #define B_FE_AG_REG_IND_WIN__M 0x1F |
| 8246 | #define B_FE_AG_REG_IND_WIN_INIT 0x0 | 8246 | #define B_FE_AG_REG_IND_WIN_INIT 0x0 |
| 8247 | 8247 | ||
| 8248 | #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D | 8248 | #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D |
| 8249 | #define B_FE_AG_REG_IND_THD_LOL__W 6 | 8249 | #define B_FE_AG_REG_IND_THD_LOL__W 6 |
| 8250 | #define B_FE_AG_REG_IND_THD_LOL__M 0x3F | 8250 | #define B_FE_AG_REG_IND_THD_LOL__M 0x3F |
| 8251 | #define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 | 8251 | #define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 |
| 8252 | 8252 | ||
| 8253 | #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E | 8253 | #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E |
| 8254 | #define B_FE_AG_REG_IND_THD_HIL__W 6 | 8254 | #define B_FE_AG_REG_IND_THD_HIL__W 6 |
| 8255 | #define B_FE_AG_REG_IND_THD_HIL__M 0x3F | 8255 | #define B_FE_AG_REG_IND_THD_HIL__M 0x3F |
| 8256 | #define B_FE_AG_REG_IND_THD_HIL_INIT 0xF | 8256 | #define B_FE_AG_REG_IND_THD_HIL_INIT 0xF |
| 8257 | 8257 | ||
| 8258 | #define B_FE_AG_REG_IND_DEL__A 0xC2003F | 8258 | #define B_FE_AG_REG_IND_DEL__A 0xC2003F |
| 8259 | #define B_FE_AG_REG_IND_DEL__W 7 | 8259 | #define B_FE_AG_REG_IND_DEL__W 7 |
| 8260 | #define B_FE_AG_REG_IND_DEL__M 0x7F | 8260 | #define B_FE_AG_REG_IND_DEL__M 0x7F |
| 8261 | #define B_FE_AG_REG_IND_DEL_INIT 0x32 | 8261 | #define B_FE_AG_REG_IND_DEL_INIT 0x32 |
| 8262 | 8262 | ||
| 8263 | #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 | 8263 | #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 |
| 8264 | #define B_FE_AG_REG_IND_PD1_WRI__W 6 | 8264 | #define B_FE_AG_REG_IND_PD1_WRI__W 6 |
| 8265 | #define B_FE_AG_REG_IND_PD1_WRI__M 0x3F | 8265 | #define B_FE_AG_REG_IND_PD1_WRI__M 0x3F |
| 8266 | #define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E | 8266 | #define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E |
| 8267 | 8267 | ||
| 8268 | #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 | 8268 | #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 |
| 8269 | #define B_FE_AG_REG_PDA_AUR_CNT__W 5 | 8269 | #define B_FE_AG_REG_PDA_AUR_CNT__W 5 |
| 8270 | #define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F | 8270 | #define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F |
| 8271 | #define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 | 8271 | #define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 |
| 8272 | 8272 | ||
| 8273 | #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 | 8273 | #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 |
| 8274 | #define B_FE_AG_REG_PDA_RUR_CNT__W 5 | 8274 | #define B_FE_AG_REG_PDA_RUR_CNT__W 5 |
| 8275 | #define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F | 8275 | #define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F |
| 8276 | #define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 | 8276 | #define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 |
| 8277 | 8277 | ||
| 8278 | #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 | 8278 | #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 |
| 8279 | #define B_FE_AG_REG_PDA_AVE_DAT__W 6 | 8279 | #define B_FE_AG_REG_PDA_AVE_DAT__W 6 |
| 8280 | #define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F | 8280 | #define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F |
| 8281 | 8281 | ||
| 8282 | #define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 | 8282 | #define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 |
| 8283 | #define B_FE_AG_REG_PDC_RUR_CNT__W 5 | 8283 | #define B_FE_AG_REG_PDC_RUR_CNT__W 5 |
| 8284 | #define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F | 8284 | #define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F |
| 8285 | #define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 | 8285 | #define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 |
| 8286 | 8286 | ||
| 8287 | #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 | 8287 | #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 |
| 8288 | #define B_FE_AG_REG_PDC_SET_LVL__W 6 | 8288 | #define B_FE_AG_REG_PDC_SET_LVL__W 6 |
| 8289 | #define B_FE_AG_REG_PDC_SET_LVL__M 0x3F | 8289 | #define B_FE_AG_REG_PDC_SET_LVL__M 0x3F |
| 8290 | #define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 | 8290 | #define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 |
| 8291 | 8291 | ||
| 8292 | #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 | 8292 | #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 |
| 8293 | #define B_FE_AG_REG_PDC_FLA_RGN__W 6 | 8293 | #define B_FE_AG_REG_PDC_FLA_RGN__W 6 |
| 8294 | #define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F | 8294 | #define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F |
| 8295 | #define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 | 8295 | #define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 |
| 8296 | 8296 | ||
| 8297 | #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 | 8297 | #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 |
| 8298 | #define B_FE_AG_REG_PDC_JMP_PSN__W 3 | 8298 | #define B_FE_AG_REG_PDC_JMP_PSN__W 3 |
| 8299 | #define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 | 8299 | #define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 |
| 8300 | #define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 | 8300 | #define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 |
| 8301 | 8301 | ||
| 8302 | #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 | 8302 | #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 |
| 8303 | #define B_FE_AG_REG_PDC_FLA_STP__W 16 | 8303 | #define B_FE_AG_REG_PDC_FLA_STP__W 16 |
| 8304 | #define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF | 8304 | #define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF |
| 8305 | #define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 | 8305 | #define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 |
| 8306 | 8306 | ||
| 8307 | #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 | 8307 | #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 |
| 8308 | #define B_FE_AG_REG_PDC_SLO_STP__W 16 | 8308 | #define B_FE_AG_REG_PDC_SLO_STP__W 16 |
| 8309 | #define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF | 8309 | #define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF |
| 8310 | #define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 | 8310 | #define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 |
| 8311 | 8311 | ||
| 8312 | #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A | 8312 | #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A |
| 8313 | #define B_FE_AG_REG_PDC_PD2_WRI__W 6 | 8313 | #define B_FE_AG_REG_PDC_PD2_WRI__W 6 |
| 8314 | #define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F | 8314 | #define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F |
| 8315 | #define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F | 8315 | #define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F |
| 8316 | 8316 | ||
| 8317 | #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B | 8317 | #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B |
| 8318 | #define B_FE_AG_REG_PDC_MAP_DAT__W 6 | 8318 | #define B_FE_AG_REG_PDC_MAP_DAT__W 6 |
| 8319 | #define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F | 8319 | #define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F |
| 8320 | 8320 | ||
| 8321 | #define B_FE_AG_REG_PDC_MAX__A 0xC2004C | 8321 | #define B_FE_AG_REG_PDC_MAX__A 0xC2004C |
| 8322 | #define B_FE_AG_REG_PDC_MAX__W 6 | 8322 | #define B_FE_AG_REG_PDC_MAX__W 6 |
| 8323 | #define B_FE_AG_REG_PDC_MAX__M 0x3F | 8323 | #define B_FE_AG_REG_PDC_MAX__M 0x3F |
| 8324 | #define B_FE_AG_REG_PDC_MAX_INIT 0x2 | 8324 | #define B_FE_AG_REG_PDC_MAX_INIT 0x2 |
| 8325 | 8325 | ||
| 8326 | #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D | 8326 | #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D |
| 8327 | #define B_FE_AG_REG_TGA_AUR_CNT__W 5 | 8327 | #define B_FE_AG_REG_TGA_AUR_CNT__W 5 |
| 8328 | #define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F | 8328 | #define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F |
| 8329 | #define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 | 8329 | #define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 |
| 8330 | 8330 | ||
| 8331 | #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E | 8331 | #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E |
| 8332 | #define B_FE_AG_REG_TGA_RUR_CNT__W 5 | 8332 | #define B_FE_AG_REG_TGA_RUR_CNT__W 5 |
| 8333 | #define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F | 8333 | #define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F |
| 8334 | #define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 | 8334 | #define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 |
| 8335 | 8335 | ||
| 8336 | #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F | 8336 | #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F |
| 8337 | #define B_FE_AG_REG_TGA_AVE_DAT__W 6 | 8337 | #define B_FE_AG_REG_TGA_AVE_DAT__W 6 |
| 8338 | #define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F | 8338 | #define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F |
| 8339 | 8339 | ||
| 8340 | #define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 | 8340 | #define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 |
| 8341 | #define B_FE_AG_REG_TGC_RUR_CNT__W 5 | 8341 | #define B_FE_AG_REG_TGC_RUR_CNT__W 5 |
| 8342 | #define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F | 8342 | #define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F |
| 8343 | #define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 | 8343 | #define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 |
| 8344 | 8344 | ||
| 8345 | #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 | 8345 | #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 |
| 8346 | #define B_FE_AG_REG_TGC_SET_LVL__W 6 | 8346 | #define B_FE_AG_REG_TGC_SET_LVL__W 6 |
| 8347 | #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F | 8347 | #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F |
| 8348 | #define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 | 8348 | #define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 |
| 8349 | 8349 | ||
| 8350 | #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 | 8350 | #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 |
| 8351 | #define B_FE_AG_REG_TGC_FLA_RGN__W 6 | 8351 | #define B_FE_AG_REG_TGC_FLA_RGN__W 6 |
| 8352 | #define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F | 8352 | #define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F |
| 8353 | #define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 | 8353 | #define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 |
| 8354 | 8354 | ||
| 8355 | #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 | 8355 | #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 |
| 8356 | #define B_FE_AG_REG_TGC_JMP_PSN__W 4 | 8356 | #define B_FE_AG_REG_TGC_JMP_PSN__W 4 |
| 8357 | #define B_FE_AG_REG_TGC_JMP_PSN__M 0xF | 8357 | #define B_FE_AG_REG_TGC_JMP_PSN__M 0xF |
| 8358 | #define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 | 8358 | #define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 |
| 8359 | 8359 | ||
| 8360 | #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 | 8360 | #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 |
| 8361 | #define B_FE_AG_REG_TGC_FLA_STP__W 16 | 8361 | #define B_FE_AG_REG_TGC_FLA_STP__W 16 |
| 8362 | #define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF | 8362 | #define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF |
| 8363 | #define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 | 8363 | #define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 |
| 8364 | 8364 | ||
| 8365 | #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 | 8365 | #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 |
| 8366 | #define B_FE_AG_REG_TGC_SLO_STP__W 16 | 8366 | #define B_FE_AG_REG_TGC_SLO_STP__W 16 |
| 8367 | #define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF | 8367 | #define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF |
| 8368 | #define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 | 8368 | #define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 |
| 8369 | 8369 | ||
| 8370 | #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 | 8370 | #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 |
| 8371 | #define B_FE_AG_REG_TGC_MAP_DAT__W 10 | 8371 | #define B_FE_AG_REG_TGC_MAP_DAT__W 10 |
| 8372 | #define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF | 8372 | #define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF |
| 8373 | 8373 | ||
| 8374 | #define B_FE_AG_REG_FGM_WRI__A 0xC20061 | 8374 | #define B_FE_AG_REG_FGM_WRI__A 0xC20061 |
| 8375 | #define B_FE_AG_REG_FGM_WRI__W 10 | 8375 | #define B_FE_AG_REG_FGM_WRI__W 10 |
| 8376 | #define B_FE_AG_REG_FGM_WRI__M 0x3FF | 8376 | #define B_FE_AG_REG_FGM_WRI__M 0x3FF |
| 8377 | #define B_FE_AG_REG_FGM_WRI_INIT 0x80 | 8377 | #define B_FE_AG_REG_FGM_WRI_INIT 0x80 |
| 8378 | 8378 | ||
| 8379 | #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 | 8379 | #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 |
| 8380 | #define B_FE_AG_REG_BGC_FGC_WRI__W 4 | 8380 | #define B_FE_AG_REG_BGC_FGC_WRI__W 4 |
| 8381 | #define B_FE_AG_REG_BGC_FGC_WRI__M 0xF | 8381 | #define B_FE_AG_REG_BGC_FGC_WRI__M 0xF |
| 8382 | #define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 | 8382 | #define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 |
| 8383 | 8383 | ||
| 8384 | #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 | 8384 | #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 |
| 8385 | #define B_FE_AG_REG_BGC_CGC_WRI__W 2 | 8385 | #define B_FE_AG_REG_BGC_CGC_WRI__W 2 |
| 8386 | #define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 | 8386 | #define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 |
| 8387 | #define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 | 8387 | #define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 |
| 8388 | 8388 | ||
| 8389 | #define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B | 8389 | #define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B |
| 8390 | #define B_FE_AG_REG_BGC_THD_LVL__W 4 | 8390 | #define B_FE_AG_REG_BGC_THD_LVL__W 4 |
| 8391 | #define B_FE_AG_REG_BGC_THD_LVL__M 0xF | 8391 | #define B_FE_AG_REG_BGC_THD_LVL__M 0xF |
| 8392 | #define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF | 8392 | #define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF |
| 8393 | 8393 | ||
| 8394 | #define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C | 8394 | #define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C |
| 8395 | #define B_FE_AG_REG_BGC_THD_INC__W 4 | 8395 | #define B_FE_AG_REG_BGC_THD_INC__W 4 |
| 8396 | #define B_FE_AG_REG_BGC_THD_INC__M 0xF | 8396 | #define B_FE_AG_REG_BGC_THD_INC__M 0xF |
| 8397 | #define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 | 8397 | #define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 |
| 8398 | 8398 | ||
| 8399 | #define B_FE_AG_REG_BGC_DAT__A 0xC2006D | 8399 | #define B_FE_AG_REG_BGC_DAT__A 0xC2006D |
| 8400 | #define B_FE_AG_REG_BGC_DAT__W 4 | 8400 | #define B_FE_AG_REG_BGC_DAT__W 4 |
| 8401 | #define B_FE_AG_REG_BGC_DAT__M 0xF | 8401 | #define B_FE_AG_REG_BGC_DAT__M 0xF |
| 8402 | 8402 | ||
| 8403 | #define B_FE_AG_REG_IND_PD1_COM__A 0xC2006E | 8403 | #define B_FE_AG_REG_IND_PD1_COM__A 0xC2006E |
| 8404 | #define B_FE_AG_REG_IND_PD1_COM__W 6 | 8404 | #define B_FE_AG_REG_IND_PD1_COM__W 6 |
| 8405 | #define B_FE_AG_REG_IND_PD1_COM__M 0x3F | 8405 | #define B_FE_AG_REG_IND_PD1_COM__M 0x3F |
| 8406 | #define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 | 8406 | #define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 |
| 8407 | 8407 | ||
| 8408 | #define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F | 8408 | #define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F |
| 8409 | #define B_FE_AG_REG_AG_AGC_BUF__W 2 | 8409 | #define B_FE_AG_REG_AG_AGC_BUF__W 2 |
| 8410 | #define B_FE_AG_REG_AG_AGC_BUF__M 0x3 | 8410 | #define B_FE_AG_REG_AG_AGC_BUF__M 0x3 |
| 8411 | #define B_FE_AG_REG_AG_AGC_BUF_INIT 0x3 | 8411 | #define B_FE_AG_REG_AG_AGC_BUF_INIT 0x3 |
| 8412 | 8412 | ||
| 8413 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__B 0 | 8413 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__B 0 |
| 8414 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__W 1 | 8414 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__W 1 |
| 8415 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__M 0x1 | 8415 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__M 0x1 |
| 8416 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_SLOW 0x0 | 8416 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_SLOW 0x0 |
| 8417 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_FAST 0x1 | 8417 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_FAST 0x1 |
| 8418 | 8418 | ||
| 8419 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__B 1 | 8419 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__B 1 |
| 8420 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__W 1 | 8420 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__W 1 |
| 8421 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__M 0x2 | 8421 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__M 0x2 |
| 8422 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 | 8422 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 |
| 8423 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 | 8423 | #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 |
| 8424 | 8424 | ||
| 8425 | #define B_FE_AG_REG_PMX_SPE__A 0xC20070 | 8425 | #define B_FE_AG_REG_PMX_SPE__A 0xC20070 |
| 8426 | #define B_FE_AG_REG_PMX_SPE__W 3 | 8426 | #define B_FE_AG_REG_PMX_SPE__W 3 |
| 8427 | #define B_FE_AG_REG_PMX_SPE__M 0x7 | 8427 | #define B_FE_AG_REG_PMX_SPE__M 0x7 |
| 8428 | #define B_FE_AG_REG_PMX_SPE_INIT 0x1 | 8428 | #define B_FE_AG_REG_PMX_SPE_INIT 0x1 |
| 8429 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_1 0x0 | 8429 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_1 0x0 |
| 8430 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_2 0x1 | 8430 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_2 0x1 |
| 8431 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_3 0x2 | 8431 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_3 0x2 |
| 8432 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_4 0x3 | 8432 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_4 0x3 |
| 8433 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_5 0x4 | 8433 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_5 0x4 |
| 8434 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_6 0x5 | 8434 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_6 0x5 |
| 8435 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 | 8435 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 |
| 8436 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 | 8436 | #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 |
| 8437 | 8437 | ||
| 8438 | #define B_FE_FS_SID 0x3 | 8438 | #define B_FE_FS_SID 0x3 |
| 8439 | 8439 | ||
| 8440 | #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 | 8440 | #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 |
| 8441 | #define B_FE_FS_REG_COMM_EXEC__W 3 | 8441 | #define B_FE_FS_REG_COMM_EXEC__W 3 |
| 8442 | #define B_FE_FS_REG_COMM_EXEC__M 0x7 | 8442 | #define B_FE_FS_REG_COMM_EXEC__M 0x7 |
| 8443 | #define B_FE_FS_REG_COMM_EXEC_CTL__B 0 | 8443 | #define B_FE_FS_REG_COMM_EXEC_CTL__B 0 |
| 8444 | #define B_FE_FS_REG_COMM_EXEC_CTL__W 3 | 8444 | #define B_FE_FS_REG_COMM_EXEC_CTL__W 3 |
| 8445 | #define B_FE_FS_REG_COMM_EXEC_CTL__M 0x7 | 8445 | #define B_FE_FS_REG_COMM_EXEC_CTL__M 0x7 |
| 8446 | #define B_FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 | 8446 | #define B_FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 |
| 8447 | #define B_FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 8447 | #define B_FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8448 | #define B_FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 | 8448 | #define B_FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 8449 | #define B_FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 | 8449 | #define B_FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 |
| 8450 | 8450 | ||
| 8451 | #define B_FE_FS_REG_COMM_STATE__A 0xC30001 | 8451 | #define B_FE_FS_REG_COMM_STATE__A 0xC30001 |
| 8452 | #define B_FE_FS_REG_COMM_STATE__W 4 | 8452 | #define B_FE_FS_REG_COMM_STATE__W 4 |
| 8453 | #define B_FE_FS_REG_COMM_STATE__M 0xF | 8453 | #define B_FE_FS_REG_COMM_STATE__M 0xF |
| 8454 | 8454 | ||
| 8455 | #define B_FE_FS_REG_COMM_MB__A 0xC30002 | 8455 | #define B_FE_FS_REG_COMM_MB__A 0xC30002 |
| 8456 | #define B_FE_FS_REG_COMM_MB__W 3 | 8456 | #define B_FE_FS_REG_COMM_MB__W 3 |
| 8457 | #define B_FE_FS_REG_COMM_MB__M 0x7 | 8457 | #define B_FE_FS_REG_COMM_MB__M 0x7 |
| 8458 | #define B_FE_FS_REG_COMM_MB_CTR__B 0 | 8458 | #define B_FE_FS_REG_COMM_MB_CTR__B 0 |
| 8459 | #define B_FE_FS_REG_COMM_MB_CTR__W 1 | 8459 | #define B_FE_FS_REG_COMM_MB_CTR__W 1 |
| 8460 | #define B_FE_FS_REG_COMM_MB_CTR__M 0x1 | 8460 | #define B_FE_FS_REG_COMM_MB_CTR__M 0x1 |
| 8461 | #define B_FE_FS_REG_COMM_MB_CTR_OFF 0x0 | 8461 | #define B_FE_FS_REG_COMM_MB_CTR_OFF 0x0 |
| 8462 | #define B_FE_FS_REG_COMM_MB_CTR_ON 0x1 | 8462 | #define B_FE_FS_REG_COMM_MB_CTR_ON 0x1 |
| 8463 | #define B_FE_FS_REG_COMM_MB_OBS__B 1 | 8463 | #define B_FE_FS_REG_COMM_MB_OBS__B 1 |
| 8464 | #define B_FE_FS_REG_COMM_MB_OBS__W 1 | 8464 | #define B_FE_FS_REG_COMM_MB_OBS__W 1 |
| 8465 | #define B_FE_FS_REG_COMM_MB_OBS__M 0x2 | 8465 | #define B_FE_FS_REG_COMM_MB_OBS__M 0x2 |
| 8466 | #define B_FE_FS_REG_COMM_MB_OBS_OFF 0x0 | 8466 | #define B_FE_FS_REG_COMM_MB_OBS_OFF 0x0 |
| 8467 | #define B_FE_FS_REG_COMM_MB_OBS_ON 0x2 | 8467 | #define B_FE_FS_REG_COMM_MB_OBS_ON 0x2 |
| 8468 | #define B_FE_FS_REG_COMM_MB_MUX__B 2 | 8468 | #define B_FE_FS_REG_COMM_MB_MUX__B 2 |
| 8469 | #define B_FE_FS_REG_COMM_MB_MUX__W 1 | 8469 | #define B_FE_FS_REG_COMM_MB_MUX__W 1 |
| 8470 | #define B_FE_FS_REG_COMM_MB_MUX__M 0x4 | 8470 | #define B_FE_FS_REG_COMM_MB_MUX__M 0x4 |
| 8471 | #define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 | 8471 | #define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 |
| 8472 | #define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 | 8472 | #define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 |
| 8473 | 8473 | ||
| 8474 | #define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 | 8474 | #define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 |
| 8475 | #define B_FE_FS_REG_COMM_SERVICE0__W 10 | 8475 | #define B_FE_FS_REG_COMM_SERVICE0__W 10 |
| 8476 | #define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF | 8476 | #define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF |
| 8477 | 8477 | ||
| 8478 | #define B_FE_FS_REG_COMM_SERVICE1__A 0xC30004 | 8478 | #define B_FE_FS_REG_COMM_SERVICE1__A 0xC30004 |
| 8479 | #define B_FE_FS_REG_COMM_SERVICE1__W 11 | 8479 | #define B_FE_FS_REG_COMM_SERVICE1__W 11 |
| 8480 | #define B_FE_FS_REG_COMM_SERVICE1__M 0x7FF | 8480 | #define B_FE_FS_REG_COMM_SERVICE1__M 0x7FF |
| 8481 | 8481 | ||
| 8482 | #define B_FE_FS_REG_COMM_ACT__A 0xC30005 | 8482 | #define B_FE_FS_REG_COMM_ACT__A 0xC30005 |
| 8483 | #define B_FE_FS_REG_COMM_ACT__W 2 | 8483 | #define B_FE_FS_REG_COMM_ACT__W 2 |
| 8484 | #define B_FE_FS_REG_COMM_ACT__M 0x3 | 8484 | #define B_FE_FS_REG_COMM_ACT__M 0x3 |
| 8485 | 8485 | ||
| 8486 | #define B_FE_FS_REG_COMM_CNT__A 0xC30006 | 8486 | #define B_FE_FS_REG_COMM_CNT__A 0xC30006 |
| 8487 | #define B_FE_FS_REG_COMM_CNT__W 16 | 8487 | #define B_FE_FS_REG_COMM_CNT__W 16 |
| 8488 | #define B_FE_FS_REG_COMM_CNT__M 0xFFFF | 8488 | #define B_FE_FS_REG_COMM_CNT__M 0xFFFF |
| 8489 | 8489 | ||
| 8490 | #define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 | 8490 | #define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 |
| 8491 | #define B_FE_FS_REG_ADD_INC_LOP__W 16 | 8491 | #define B_FE_FS_REG_ADD_INC_LOP__W 16 |
| 8492 | #define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF | 8492 | #define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF |
| 8493 | #define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 | 8493 | #define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 |
| 8494 | 8494 | ||
| 8495 | #define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 | 8495 | #define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 |
| 8496 | #define B_FE_FS_REG_ADD_INC_HIP__W 12 | 8496 | #define B_FE_FS_REG_ADD_INC_HIP__W 12 |
| 8497 | #define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF | 8497 | #define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF |
| 8498 | #define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 | 8498 | #define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 |
| 8499 | 8499 | ||
| 8500 | #define B_FE_FS_REG_ADD_OFF__A 0xC30012 | 8500 | #define B_FE_FS_REG_ADD_OFF__A 0xC30012 |
| 8501 | #define B_FE_FS_REG_ADD_OFF__W 12 | 8501 | #define B_FE_FS_REG_ADD_OFF__W 12 |
| 8502 | #define B_FE_FS_REG_ADD_OFF__M 0xFFF | 8502 | #define B_FE_FS_REG_ADD_OFF__M 0xFFF |
| 8503 | #define B_FE_FS_REG_ADD_OFF_INIT 0x0 | 8503 | #define B_FE_FS_REG_ADD_OFF_INIT 0x0 |
| 8504 | 8504 | ||
| 8505 | #define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 | 8505 | #define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 |
| 8506 | #define B_FE_FS_REG_ADD_OFF_VAL__W 1 | 8506 | #define B_FE_FS_REG_ADD_OFF_VAL__W 1 |
| 8507 | #define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 | 8507 | #define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 |
| 8508 | #define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 | 8508 | #define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 |
| 8509 | 8509 | ||
| 8510 | #define B_FE_FD_SID 0x4 | 8510 | #define B_FE_FD_SID 0x4 |
| 8511 | 8511 | ||
| 8512 | #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 | 8512 | #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 |
| 8513 | #define B_FE_FD_REG_COMM_EXEC__W 3 | 8513 | #define B_FE_FD_REG_COMM_EXEC__W 3 |
| 8514 | #define B_FE_FD_REG_COMM_EXEC__M 0x7 | 8514 | #define B_FE_FD_REG_COMM_EXEC__M 0x7 |
| 8515 | #define B_FE_FD_REG_COMM_EXEC_CTL__B 0 | 8515 | #define B_FE_FD_REG_COMM_EXEC_CTL__B 0 |
| 8516 | #define B_FE_FD_REG_COMM_EXEC_CTL__W 3 | 8516 | #define B_FE_FD_REG_COMM_EXEC_CTL__W 3 |
| 8517 | #define B_FE_FD_REG_COMM_EXEC_CTL__M 0x7 | 8517 | #define B_FE_FD_REG_COMM_EXEC_CTL__M 0x7 |
| 8518 | #define B_FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 | 8518 | #define B_FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 8519 | #define B_FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 8519 | #define B_FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8520 | #define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 | 8520 | #define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 8521 | #define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 | 8521 | #define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 |
| 8522 | 8522 | ||
| 8523 | #define B_FE_FD_REG_COMM_MB__A 0xC40002 | 8523 | #define B_FE_FD_REG_COMM_MB__A 0xC40002 |
| 8524 | #define B_FE_FD_REG_COMM_MB__W 3 | 8524 | #define B_FE_FD_REG_COMM_MB__W 3 |
| 8525 | #define B_FE_FD_REG_COMM_MB__M 0x7 | 8525 | #define B_FE_FD_REG_COMM_MB__M 0x7 |
| 8526 | #define B_FE_FD_REG_COMM_MB_CTR__B 0 | 8526 | #define B_FE_FD_REG_COMM_MB_CTR__B 0 |
| 8527 | #define B_FE_FD_REG_COMM_MB_CTR__W 1 | 8527 | #define B_FE_FD_REG_COMM_MB_CTR__W 1 |
| 8528 | #define B_FE_FD_REG_COMM_MB_CTR__M 0x1 | 8528 | #define B_FE_FD_REG_COMM_MB_CTR__M 0x1 |
| 8529 | #define B_FE_FD_REG_COMM_MB_CTR_OFF 0x0 | 8529 | #define B_FE_FD_REG_COMM_MB_CTR_OFF 0x0 |
| 8530 | #define B_FE_FD_REG_COMM_MB_CTR_ON 0x1 | 8530 | #define B_FE_FD_REG_COMM_MB_CTR_ON 0x1 |
| 8531 | #define B_FE_FD_REG_COMM_MB_OBS__B 1 | 8531 | #define B_FE_FD_REG_COMM_MB_OBS__B 1 |
| 8532 | #define B_FE_FD_REG_COMM_MB_OBS__W 1 | 8532 | #define B_FE_FD_REG_COMM_MB_OBS__W 1 |
| 8533 | #define B_FE_FD_REG_COMM_MB_OBS__M 0x2 | 8533 | #define B_FE_FD_REG_COMM_MB_OBS__M 0x2 |
| 8534 | #define B_FE_FD_REG_COMM_MB_OBS_OFF 0x0 | 8534 | #define B_FE_FD_REG_COMM_MB_OBS_OFF 0x0 |
| 8535 | #define B_FE_FD_REG_COMM_MB_OBS_ON 0x2 | 8535 | #define B_FE_FD_REG_COMM_MB_OBS_ON 0x2 |
| 8536 | 8536 | ||
| 8537 | #define B_FE_FD_REG_COMM_SERVICE0__A 0xC40003 | 8537 | #define B_FE_FD_REG_COMM_SERVICE0__A 0xC40003 |
| 8538 | #define B_FE_FD_REG_COMM_SERVICE0__W 10 | 8538 | #define B_FE_FD_REG_COMM_SERVICE0__W 10 |
| 8539 | #define B_FE_FD_REG_COMM_SERVICE0__M 0x3FF | 8539 | #define B_FE_FD_REG_COMM_SERVICE0__M 0x3FF |
| 8540 | #define B_FE_FD_REG_COMM_SERVICE1__A 0xC40004 | 8540 | #define B_FE_FD_REG_COMM_SERVICE1__A 0xC40004 |
| 8541 | #define B_FE_FD_REG_COMM_SERVICE1__W 11 | 8541 | #define B_FE_FD_REG_COMM_SERVICE1__W 11 |
| 8542 | #define B_FE_FD_REG_COMM_SERVICE1__M 0x7FF | 8542 | #define B_FE_FD_REG_COMM_SERVICE1__M 0x7FF |
| 8543 | 8543 | ||
| 8544 | #define B_FE_FD_REG_COMM_INT_STA__A 0xC40007 | 8544 | #define B_FE_FD_REG_COMM_INT_STA__A 0xC40007 |
| 8545 | #define B_FE_FD_REG_COMM_INT_STA__W 1 | 8545 | #define B_FE_FD_REG_COMM_INT_STA__W 1 |
| 8546 | #define B_FE_FD_REG_COMM_INT_STA__M 0x1 | 8546 | #define B_FE_FD_REG_COMM_INT_STA__M 0x1 |
| 8547 | #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 | 8547 | #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 |
| 8548 | #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 | 8548 | #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 |
| 8549 | #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 | 8549 | #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 |
| 8550 | 8550 | ||
| 8551 | #define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 | 8551 | #define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 |
| 8552 | #define B_FE_FD_REG_COMM_INT_MSK__W 1 | 8552 | #define B_FE_FD_REG_COMM_INT_MSK__W 1 |
| 8553 | #define B_FE_FD_REG_COMM_INT_MSK__M 0x1 | 8553 | #define B_FE_FD_REG_COMM_INT_MSK__M 0x1 |
| 8554 | #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 | 8554 | #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 |
| 8555 | #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 | 8555 | #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 |
| 8556 | #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 | 8556 | #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 |
| 8557 | 8557 | ||
| 8558 | #define B_FE_FD_REG_SCL__A 0xC40010 | 8558 | #define B_FE_FD_REG_SCL__A 0xC40010 |
| 8559 | #define B_FE_FD_REG_SCL__W 6 | 8559 | #define B_FE_FD_REG_SCL__W 6 |
| 8560 | #define B_FE_FD_REG_SCL__M 0x3F | 8560 | #define B_FE_FD_REG_SCL__M 0x3F |
| 8561 | 8561 | ||
| 8562 | #define B_FE_FD_REG_MAX_LEV__A 0xC40011 | 8562 | #define B_FE_FD_REG_MAX_LEV__A 0xC40011 |
| 8563 | #define B_FE_FD_REG_MAX_LEV__W 3 | 8563 | #define B_FE_FD_REG_MAX_LEV__W 3 |
| 8564 | #define B_FE_FD_REG_MAX_LEV__M 0x7 | 8564 | #define B_FE_FD_REG_MAX_LEV__M 0x7 |
| 8565 | 8565 | ||
| 8566 | #define B_FE_FD_REG_NR__A 0xC40012 | 8566 | #define B_FE_FD_REG_NR__A 0xC40012 |
| 8567 | #define B_FE_FD_REG_NR__W 5 | 8567 | #define B_FE_FD_REG_NR__W 5 |
| 8568 | #define B_FE_FD_REG_NR__M 0x1F | 8568 | #define B_FE_FD_REG_NR__M 0x1F |
| 8569 | 8569 | ||
| 8570 | #define B_FE_FD_REG_MEAS_SEL__A 0xC40013 | 8570 | #define B_FE_FD_REG_MEAS_SEL__A 0xC40013 |
| 8571 | #define B_FE_FD_REG_MEAS_SEL__W 1 | 8571 | #define B_FE_FD_REG_MEAS_SEL__W 1 |
| 8572 | #define B_FE_FD_REG_MEAS_SEL__M 0x1 | 8572 | #define B_FE_FD_REG_MEAS_SEL__M 0x1 |
| 8573 | 8573 | ||
| 8574 | #define B_FE_FD_REG_MEAS_VAL__A 0xC40014 | 8574 | #define B_FE_FD_REG_MEAS_VAL__A 0xC40014 |
| 8575 | #define B_FE_FD_REG_MEAS_VAL__W 1 | 8575 | #define B_FE_FD_REG_MEAS_VAL__W 1 |
| 8576 | #define B_FE_FD_REG_MEAS_VAL__M 0x1 | 8576 | #define B_FE_FD_REG_MEAS_VAL__M 0x1 |
| 8577 | 8577 | ||
| 8578 | #define B_FE_FD_REG_MAX__A 0xC40015 | 8578 | #define B_FE_FD_REG_MAX__A 0xC40015 |
| 8579 | #define B_FE_FD_REG_MAX__W 16 | 8579 | #define B_FE_FD_REG_MAX__W 16 |
| 8580 | #define B_FE_FD_REG_MAX__M 0xFFFF | 8580 | #define B_FE_FD_REG_MAX__M 0xFFFF |
| 8581 | 8581 | ||
| 8582 | #define B_FE_IF_SID 0x5 | 8582 | #define B_FE_IF_SID 0x5 |
| 8583 | 8583 | ||
| 8584 | #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 | 8584 | #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 |
| 8585 | #define B_FE_IF_REG_COMM_EXEC__W 3 | 8585 | #define B_FE_IF_REG_COMM_EXEC__W 3 |
| 8586 | #define B_FE_IF_REG_COMM_EXEC__M 0x7 | 8586 | #define B_FE_IF_REG_COMM_EXEC__M 0x7 |
| 8587 | #define B_FE_IF_REG_COMM_EXEC_CTL__B 0 | 8587 | #define B_FE_IF_REG_COMM_EXEC_CTL__B 0 |
| 8588 | #define B_FE_IF_REG_COMM_EXEC_CTL__W 3 | 8588 | #define B_FE_IF_REG_COMM_EXEC_CTL__W 3 |
| 8589 | #define B_FE_IF_REG_COMM_EXEC_CTL__M 0x7 | 8589 | #define B_FE_IF_REG_COMM_EXEC_CTL__M 0x7 |
| 8590 | #define B_FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 | 8590 | #define B_FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 |
| 8591 | #define B_FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 8591 | #define B_FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8592 | #define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 | 8592 | #define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 8593 | #define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 | 8593 | #define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 |
| 8594 | 8594 | ||
| 8595 | #define B_FE_IF_REG_COMM_MB__A 0xC50002 | 8595 | #define B_FE_IF_REG_COMM_MB__A 0xC50002 |
| 8596 | #define B_FE_IF_REG_COMM_MB__W 3 | 8596 | #define B_FE_IF_REG_COMM_MB__W 3 |
| 8597 | #define B_FE_IF_REG_COMM_MB__M 0x7 | 8597 | #define B_FE_IF_REG_COMM_MB__M 0x7 |
| 8598 | #define B_FE_IF_REG_COMM_MB_CTR__B 0 | 8598 | #define B_FE_IF_REG_COMM_MB_CTR__B 0 |
| 8599 | #define B_FE_IF_REG_COMM_MB_CTR__W 1 | 8599 | #define B_FE_IF_REG_COMM_MB_CTR__W 1 |
| 8600 | #define B_FE_IF_REG_COMM_MB_CTR__M 0x1 | 8600 | #define B_FE_IF_REG_COMM_MB_CTR__M 0x1 |
| 8601 | #define B_FE_IF_REG_COMM_MB_CTR_OFF 0x0 | 8601 | #define B_FE_IF_REG_COMM_MB_CTR_OFF 0x0 |
| 8602 | #define B_FE_IF_REG_COMM_MB_CTR_ON 0x1 | 8602 | #define B_FE_IF_REG_COMM_MB_CTR_ON 0x1 |
| 8603 | #define B_FE_IF_REG_COMM_MB_OBS__B 1 | 8603 | #define B_FE_IF_REG_COMM_MB_OBS__B 1 |
| 8604 | #define B_FE_IF_REG_COMM_MB_OBS__W 1 | 8604 | #define B_FE_IF_REG_COMM_MB_OBS__W 1 |
| 8605 | #define B_FE_IF_REG_COMM_MB_OBS__M 0x2 | 8605 | #define B_FE_IF_REG_COMM_MB_OBS__M 0x2 |
| 8606 | #define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 | 8606 | #define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 |
| 8607 | #define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 | 8607 | #define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 |
| 8608 | 8608 | ||
| 8609 | #define B_FE_IF_REG_INCR0__A 0xC50010 | 8609 | #define B_FE_IF_REG_INCR0__A 0xC50010 |
| 8610 | #define B_FE_IF_REG_INCR0__W 16 | 8610 | #define B_FE_IF_REG_INCR0__W 16 |
| 8611 | #define B_FE_IF_REG_INCR0__M 0xFFFF | 8611 | #define B_FE_IF_REG_INCR0__M 0xFFFF |
| 8612 | #define B_FE_IF_REG_INCR0_INIT 0x0 | 8612 | #define B_FE_IF_REG_INCR0_INIT 0x0 |
| 8613 | 8613 | ||
| 8614 | #define B_FE_IF_REG_INCR1__A 0xC50011 | 8614 | #define B_FE_IF_REG_INCR1__A 0xC50011 |
| 8615 | #define B_FE_IF_REG_INCR1__W 8 | 8615 | #define B_FE_IF_REG_INCR1__W 8 |
| 8616 | #define B_FE_IF_REG_INCR1__M 0xFF | 8616 | #define B_FE_IF_REG_INCR1__M 0xFF |
| 8617 | #define B_FE_IF_REG_INCR1_INIT 0x28 | 8617 | #define B_FE_IF_REG_INCR1_INIT 0x28 |
| 8618 | 8618 | ||
| 8619 | #define B_FE_CF_SID 0x6 | 8619 | #define B_FE_CF_SID 0x6 |
| 8620 | 8620 | ||
| 8621 | #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 | 8621 | #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 |
| 8622 | #define B_FE_CF_REG_COMM_EXEC__W 3 | 8622 | #define B_FE_CF_REG_COMM_EXEC__W 3 |
| 8623 | #define B_FE_CF_REG_COMM_EXEC__M 0x7 | 8623 | #define B_FE_CF_REG_COMM_EXEC__M 0x7 |
| 8624 | #define B_FE_CF_REG_COMM_EXEC_CTL__B 0 | 8624 | #define B_FE_CF_REG_COMM_EXEC_CTL__B 0 |
| 8625 | #define B_FE_CF_REG_COMM_EXEC_CTL__W 3 | 8625 | #define B_FE_CF_REG_COMM_EXEC_CTL__W 3 |
| 8626 | #define B_FE_CF_REG_COMM_EXEC_CTL__M 0x7 | 8626 | #define B_FE_CF_REG_COMM_EXEC_CTL__M 0x7 |
| 8627 | #define B_FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 | 8627 | #define B_FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 |
| 8628 | #define B_FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 8628 | #define B_FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8629 | #define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 | 8629 | #define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 8630 | #define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 | 8630 | #define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 |
| 8631 | 8631 | ||
| 8632 | #define B_FE_CF_REG_COMM_MB__A 0xC60002 | 8632 | #define B_FE_CF_REG_COMM_MB__A 0xC60002 |
| 8633 | #define B_FE_CF_REG_COMM_MB__W 3 | 8633 | #define B_FE_CF_REG_COMM_MB__W 3 |
| 8634 | #define B_FE_CF_REG_COMM_MB__M 0x7 | 8634 | #define B_FE_CF_REG_COMM_MB__M 0x7 |
| 8635 | #define B_FE_CF_REG_COMM_MB_CTR__B 0 | 8635 | #define B_FE_CF_REG_COMM_MB_CTR__B 0 |
| 8636 | #define B_FE_CF_REG_COMM_MB_CTR__W 1 | 8636 | #define B_FE_CF_REG_COMM_MB_CTR__W 1 |
| 8637 | #define B_FE_CF_REG_COMM_MB_CTR__M 0x1 | 8637 | #define B_FE_CF_REG_COMM_MB_CTR__M 0x1 |
| 8638 | #define B_FE_CF_REG_COMM_MB_CTR_OFF 0x0 | 8638 | #define B_FE_CF_REG_COMM_MB_CTR_OFF 0x0 |
| 8639 | #define B_FE_CF_REG_COMM_MB_CTR_ON 0x1 | 8639 | #define B_FE_CF_REG_COMM_MB_CTR_ON 0x1 |
| 8640 | #define B_FE_CF_REG_COMM_MB_OBS__B 1 | 8640 | #define B_FE_CF_REG_COMM_MB_OBS__B 1 |
| 8641 | #define B_FE_CF_REG_COMM_MB_OBS__W 1 | 8641 | #define B_FE_CF_REG_COMM_MB_OBS__W 1 |
| 8642 | #define B_FE_CF_REG_COMM_MB_OBS__M 0x2 | 8642 | #define B_FE_CF_REG_COMM_MB_OBS__M 0x2 |
| 8643 | #define B_FE_CF_REG_COMM_MB_OBS_OFF 0x0 | 8643 | #define B_FE_CF_REG_COMM_MB_OBS_OFF 0x0 |
| 8644 | #define B_FE_CF_REG_COMM_MB_OBS_ON 0x2 | 8644 | #define B_FE_CF_REG_COMM_MB_OBS_ON 0x2 |
| 8645 | 8645 | ||
| 8646 | #define B_FE_CF_REG_COMM_SERVICE0__A 0xC60003 | 8646 | #define B_FE_CF_REG_COMM_SERVICE0__A 0xC60003 |
| 8647 | #define B_FE_CF_REG_COMM_SERVICE0__W 10 | 8647 | #define B_FE_CF_REG_COMM_SERVICE0__W 10 |
| 8648 | #define B_FE_CF_REG_COMM_SERVICE0__M 0x3FF | 8648 | #define B_FE_CF_REG_COMM_SERVICE0__M 0x3FF |
| 8649 | #define B_FE_CF_REG_COMM_SERVICE1__A 0xC60004 | 8649 | #define B_FE_CF_REG_COMM_SERVICE1__A 0xC60004 |
| 8650 | #define B_FE_CF_REG_COMM_SERVICE1__W 11 | 8650 | #define B_FE_CF_REG_COMM_SERVICE1__W 11 |
| 8651 | #define B_FE_CF_REG_COMM_SERVICE1__M 0x7FF | 8651 | #define B_FE_CF_REG_COMM_SERVICE1__M 0x7FF |
| 8652 | 8652 | ||
| 8653 | #define B_FE_CF_REG_COMM_INT_STA__A 0xC60007 | 8653 | #define B_FE_CF_REG_COMM_INT_STA__A 0xC60007 |
| 8654 | #define B_FE_CF_REG_COMM_INT_STA__W 2 | 8654 | #define B_FE_CF_REG_COMM_INT_STA__W 2 |
| 8655 | #define B_FE_CF_REG_COMM_INT_STA__M 0x3 | 8655 | #define B_FE_CF_REG_COMM_INT_STA__M 0x3 |
| 8656 | #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 | 8656 | #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 |
| 8657 | #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 | 8657 | #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 |
| 8658 | #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 | 8658 | #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 |
| 8659 | 8659 | ||
| 8660 | #define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 | 8660 | #define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 |
| 8661 | #define B_FE_CF_REG_COMM_INT_MSK__W 2 | 8661 | #define B_FE_CF_REG_COMM_INT_MSK__W 2 |
| 8662 | #define B_FE_CF_REG_COMM_INT_MSK__M 0x3 | 8662 | #define B_FE_CF_REG_COMM_INT_MSK__M 0x3 |
| 8663 | #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 | 8663 | #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 |
| 8664 | #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 | 8664 | #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 |
| 8665 | #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 | 8665 | #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 |
| 8666 | 8666 | ||
| 8667 | #define B_FE_CF_REG_SCL__A 0xC60010 | 8667 | #define B_FE_CF_REG_SCL__A 0xC60010 |
| 8668 | #define B_FE_CF_REG_SCL__W 9 | 8668 | #define B_FE_CF_REG_SCL__W 9 |
| 8669 | #define B_FE_CF_REG_SCL__M 0x1FF | 8669 | #define B_FE_CF_REG_SCL__M 0x1FF |
| 8670 | 8670 | ||
| 8671 | #define B_FE_CF_REG_MAX_LEV__A 0xC60011 | 8671 | #define B_FE_CF_REG_MAX_LEV__A 0xC60011 |
| 8672 | #define B_FE_CF_REG_MAX_LEV__W 3 | 8672 | #define B_FE_CF_REG_MAX_LEV__W 3 |
| 8673 | #define B_FE_CF_REG_MAX_LEV__M 0x7 | 8673 | #define B_FE_CF_REG_MAX_LEV__M 0x7 |
| 8674 | 8674 | ||
| 8675 | #define B_FE_CF_REG_NR__A 0xC60012 | 8675 | #define B_FE_CF_REG_NR__A 0xC60012 |
| 8676 | #define B_FE_CF_REG_NR__W 5 | 8676 | #define B_FE_CF_REG_NR__W 5 |
| 8677 | #define B_FE_CF_REG_NR__M 0x1F | 8677 | #define B_FE_CF_REG_NR__M 0x1F |
| 8678 | 8678 | ||
| 8679 | #define B_FE_CF_REG_IMP_VAL__A 0xC60013 | 8679 | #define B_FE_CF_REG_IMP_VAL__A 0xC60013 |
| 8680 | #define B_FE_CF_REG_IMP_VAL__W 1 | 8680 | #define B_FE_CF_REG_IMP_VAL__W 1 |
| 8681 | #define B_FE_CF_REG_IMP_VAL__M 0x1 | 8681 | #define B_FE_CF_REG_IMP_VAL__M 0x1 |
| 8682 | 8682 | ||
| 8683 | #define B_FE_CF_REG_MEAS_VAL__A 0xC60014 | 8683 | #define B_FE_CF_REG_MEAS_VAL__A 0xC60014 |
| 8684 | #define B_FE_CF_REG_MEAS_VAL__W 1 | 8684 | #define B_FE_CF_REG_MEAS_VAL__W 1 |
| 8685 | #define B_FE_CF_REG_MEAS_VAL__M 0x1 | 8685 | #define B_FE_CF_REG_MEAS_VAL__M 0x1 |
| 8686 | 8686 | ||
| 8687 | #define B_FE_CF_REG_MAX__A 0xC60015 | 8687 | #define B_FE_CF_REG_MAX__A 0xC60015 |
| 8688 | #define B_FE_CF_REG_MAX__W 16 | 8688 | #define B_FE_CF_REG_MAX__W 16 |
| 8689 | #define B_FE_CF_REG_MAX__M 0xFFFF | 8689 | #define B_FE_CF_REG_MAX__M 0xFFFF |
| 8690 | 8690 | ||
| 8691 | #define B_FE_CU_SID 0x7 | 8691 | #define B_FE_CU_SID 0x7 |
| 8692 | 8692 | ||
| 8693 | #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 | 8693 | #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 |
| 8694 | #define B_FE_CU_REG_COMM_EXEC__W 3 | 8694 | #define B_FE_CU_REG_COMM_EXEC__W 3 |
| 8695 | #define B_FE_CU_REG_COMM_EXEC__M 0x7 | 8695 | #define B_FE_CU_REG_COMM_EXEC__M 0x7 |
| 8696 | #define B_FE_CU_REG_COMM_EXEC_CTL__B 0 | 8696 | #define B_FE_CU_REG_COMM_EXEC_CTL__B 0 |
| 8697 | #define B_FE_CU_REG_COMM_EXEC_CTL__W 3 | 8697 | #define B_FE_CU_REG_COMM_EXEC_CTL__W 3 |
| 8698 | #define B_FE_CU_REG_COMM_EXEC_CTL__M 0x7 | 8698 | #define B_FE_CU_REG_COMM_EXEC_CTL__M 0x7 |
| 8699 | #define B_FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 | 8699 | #define B_FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 |
| 8700 | #define B_FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 8700 | #define B_FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8701 | #define B_FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 | 8701 | #define B_FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 8702 | #define B_FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 | 8702 | #define B_FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 |
| 8703 | 8703 | ||
| 8704 | #define B_FE_CU_REG_COMM_STATE__A 0xC70001 | 8704 | #define B_FE_CU_REG_COMM_STATE__A 0xC70001 |
| 8705 | #define B_FE_CU_REG_COMM_STATE__W 4 | 8705 | #define B_FE_CU_REG_COMM_STATE__W 4 |
| 8706 | #define B_FE_CU_REG_COMM_STATE__M 0xF | 8706 | #define B_FE_CU_REG_COMM_STATE__M 0xF |
| 8707 | 8707 | ||
| 8708 | #define B_FE_CU_REG_COMM_MB__A 0xC70002 | 8708 | #define B_FE_CU_REG_COMM_MB__A 0xC70002 |
| 8709 | #define B_FE_CU_REG_COMM_MB__W 3 | 8709 | #define B_FE_CU_REG_COMM_MB__W 3 |
| 8710 | #define B_FE_CU_REG_COMM_MB__M 0x7 | 8710 | #define B_FE_CU_REG_COMM_MB__M 0x7 |
| 8711 | #define B_FE_CU_REG_COMM_MB_CTR__B 0 | 8711 | #define B_FE_CU_REG_COMM_MB_CTR__B 0 |
| 8712 | #define B_FE_CU_REG_COMM_MB_CTR__W 1 | 8712 | #define B_FE_CU_REG_COMM_MB_CTR__W 1 |
| 8713 | #define B_FE_CU_REG_COMM_MB_CTR__M 0x1 | 8713 | #define B_FE_CU_REG_COMM_MB_CTR__M 0x1 |
| 8714 | #define B_FE_CU_REG_COMM_MB_CTR_OFF 0x0 | 8714 | #define B_FE_CU_REG_COMM_MB_CTR_OFF 0x0 |
| 8715 | #define B_FE_CU_REG_COMM_MB_CTR_ON 0x1 | 8715 | #define B_FE_CU_REG_COMM_MB_CTR_ON 0x1 |
| 8716 | #define B_FE_CU_REG_COMM_MB_OBS__B 1 | 8716 | #define B_FE_CU_REG_COMM_MB_OBS__B 1 |
| 8717 | #define B_FE_CU_REG_COMM_MB_OBS__W 1 | 8717 | #define B_FE_CU_REG_COMM_MB_OBS__W 1 |
| 8718 | #define B_FE_CU_REG_COMM_MB_OBS__M 0x2 | 8718 | #define B_FE_CU_REG_COMM_MB_OBS__M 0x2 |
| 8719 | #define B_FE_CU_REG_COMM_MB_OBS_OFF 0x0 | 8719 | #define B_FE_CU_REG_COMM_MB_OBS_OFF 0x0 |
| 8720 | #define B_FE_CU_REG_COMM_MB_OBS_ON 0x2 | 8720 | #define B_FE_CU_REG_COMM_MB_OBS_ON 0x2 |
| 8721 | #define B_FE_CU_REG_COMM_MB_MUX__B 2 | 8721 | #define B_FE_CU_REG_COMM_MB_MUX__B 2 |
| 8722 | #define B_FE_CU_REG_COMM_MB_MUX__W 1 | 8722 | #define B_FE_CU_REG_COMM_MB_MUX__W 1 |
| 8723 | #define B_FE_CU_REG_COMM_MB_MUX__M 0x4 | 8723 | #define B_FE_CU_REG_COMM_MB_MUX__M 0x4 |
| 8724 | #define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 | 8724 | #define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 |
| 8725 | #define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 | 8725 | #define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 |
| 8726 | 8726 | ||
| 8727 | #define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 | 8727 | #define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 |
| 8728 | #define B_FE_CU_REG_COMM_SERVICE0__W 10 | 8728 | #define B_FE_CU_REG_COMM_SERVICE0__W 10 |
| 8729 | #define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF | 8729 | #define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF |
| 8730 | 8730 | ||
| 8731 | #define B_FE_CU_REG_COMM_SERVICE1__A 0xC70004 | 8731 | #define B_FE_CU_REG_COMM_SERVICE1__A 0xC70004 |
| 8732 | #define B_FE_CU_REG_COMM_SERVICE1__W 11 | 8732 | #define B_FE_CU_REG_COMM_SERVICE1__W 11 |
| 8733 | #define B_FE_CU_REG_COMM_SERVICE1__M 0x7FF | 8733 | #define B_FE_CU_REG_COMM_SERVICE1__M 0x7FF |
| 8734 | 8734 | ||
| 8735 | #define B_FE_CU_REG_COMM_ACT__A 0xC70005 | 8735 | #define B_FE_CU_REG_COMM_ACT__A 0xC70005 |
| 8736 | #define B_FE_CU_REG_COMM_ACT__W 2 | 8736 | #define B_FE_CU_REG_COMM_ACT__W 2 |
| 8737 | #define B_FE_CU_REG_COMM_ACT__M 0x3 | 8737 | #define B_FE_CU_REG_COMM_ACT__M 0x3 |
| 8738 | 8738 | ||
| 8739 | #define B_FE_CU_REG_COMM_CNT__A 0xC70006 | 8739 | #define B_FE_CU_REG_COMM_CNT__A 0xC70006 |
| 8740 | #define B_FE_CU_REG_COMM_CNT__W 16 | 8740 | #define B_FE_CU_REG_COMM_CNT__W 16 |
| 8741 | #define B_FE_CU_REG_COMM_CNT__M 0xFFFF | 8741 | #define B_FE_CU_REG_COMM_CNT__M 0xFFFF |
| 8742 | 8742 | ||
| 8743 | #define B_FE_CU_REG_COMM_INT_STA__A 0xC70007 | 8743 | #define B_FE_CU_REG_COMM_INT_STA__A 0xC70007 |
| 8744 | #define B_FE_CU_REG_COMM_INT_STA__W 4 | 8744 | #define B_FE_CU_REG_COMM_INT_STA__W 4 |
| 8745 | #define B_FE_CU_REG_COMM_INT_STA__M 0xF | 8745 | #define B_FE_CU_REG_COMM_INT_STA__M 0xF |
| 8746 | #define B_FE_CU_REG_COMM_INT_STA_FE_START__B 0 | 8746 | #define B_FE_CU_REG_COMM_INT_STA_FE_START__B 0 |
| 8747 | #define B_FE_CU_REG_COMM_INT_STA_FE_START__W 1 | 8747 | #define B_FE_CU_REG_COMM_INT_STA_FE_START__W 1 |
| 8748 | #define B_FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 | 8748 | #define B_FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 |
| 8749 | #define B_FE_CU_REG_COMM_INT_STA_FT_START__B 1 | 8749 | #define B_FE_CU_REG_COMM_INT_STA_FT_START__B 1 |
| 8750 | #define B_FE_CU_REG_COMM_INT_STA_FT_START__W 1 | 8750 | #define B_FE_CU_REG_COMM_INT_STA_FT_START__W 1 |
| 8751 | #define B_FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 | 8751 | #define B_FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 |
| 8752 | #define B_FE_CU_REG_COMM_INT_STA_SB_START__B 2 | 8752 | #define B_FE_CU_REG_COMM_INT_STA_SB_START__B 2 |
| 8753 | #define B_FE_CU_REG_COMM_INT_STA_SB_START__W 1 | 8753 | #define B_FE_CU_REG_COMM_INT_STA_SB_START__W 1 |
| 8754 | #define B_FE_CU_REG_COMM_INT_STA_SB_START__M 0x4 | 8754 | #define B_FE_CU_REG_COMM_INT_STA_SB_START__M 0x4 |
| 8755 | #define B_FE_CU_REG_COMM_INT_STA_NF_READY__B 3 | 8755 | #define B_FE_CU_REG_COMM_INT_STA_NF_READY__B 3 |
| 8756 | #define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 | 8756 | #define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 |
| 8757 | #define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 | 8757 | #define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 |
| 8758 | 8758 | ||
| 8759 | #define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 | 8759 | #define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 |
| 8760 | #define B_FE_CU_REG_COMM_INT_MSK__W 4 | 8760 | #define B_FE_CU_REG_COMM_INT_MSK__W 4 |
| 8761 | #define B_FE_CU_REG_COMM_INT_MSK__M 0xF | 8761 | #define B_FE_CU_REG_COMM_INT_MSK__M 0xF |
| 8762 | #define B_FE_CU_REG_COMM_INT_MSK_FE_START__B 0 | 8762 | #define B_FE_CU_REG_COMM_INT_MSK_FE_START__B 0 |
| 8763 | #define B_FE_CU_REG_COMM_INT_MSK_FE_START__W 1 | 8763 | #define B_FE_CU_REG_COMM_INT_MSK_FE_START__W 1 |
| 8764 | #define B_FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 | 8764 | #define B_FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 |
| 8765 | #define B_FE_CU_REG_COMM_INT_MSK_FT_START__B 1 | 8765 | #define B_FE_CU_REG_COMM_INT_MSK_FT_START__B 1 |
| 8766 | #define B_FE_CU_REG_COMM_INT_MSK_FT_START__W 1 | 8766 | #define B_FE_CU_REG_COMM_INT_MSK_FT_START__W 1 |
| 8767 | #define B_FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 | 8767 | #define B_FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 |
| 8768 | #define B_FE_CU_REG_COMM_INT_MSK_SB_START__B 2 | 8768 | #define B_FE_CU_REG_COMM_INT_MSK_SB_START__B 2 |
| 8769 | #define B_FE_CU_REG_COMM_INT_MSK_SB_START__W 1 | 8769 | #define B_FE_CU_REG_COMM_INT_MSK_SB_START__W 1 |
| 8770 | #define B_FE_CU_REG_COMM_INT_MSK_SB_START__M 0x4 | 8770 | #define B_FE_CU_REG_COMM_INT_MSK_SB_START__M 0x4 |
| 8771 | #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__B 3 | 8771 | #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__B 3 |
| 8772 | #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 | 8772 | #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 |
| 8773 | #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 | 8773 | #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 |
| 8774 | 8774 | ||
| 8775 | #define B_FE_CU_REG_MODE__A 0xC70010 | 8775 | #define B_FE_CU_REG_MODE__A 0xC70010 |
| 8776 | #define B_FE_CU_REG_MODE__W 5 | 8776 | #define B_FE_CU_REG_MODE__W 5 |
| 8777 | #define B_FE_CU_REG_MODE__M 0x1F | 8777 | #define B_FE_CU_REG_MODE__M 0x1F |
| 8778 | #define B_FE_CU_REG_MODE_INIT 0x0 | 8778 | #define B_FE_CU_REG_MODE_INIT 0x0 |
| 8779 | 8779 | ||
| 8780 | #define B_FE_CU_REG_MODE_FFT__B 0 | 8780 | #define B_FE_CU_REG_MODE_FFT__B 0 |
| 8781 | #define B_FE_CU_REG_MODE_FFT__W 1 | 8781 | #define B_FE_CU_REG_MODE_FFT__W 1 |
| 8782 | #define B_FE_CU_REG_MODE_FFT__M 0x1 | 8782 | #define B_FE_CU_REG_MODE_FFT__M 0x1 |
| 8783 | #define B_FE_CU_REG_MODE_FFT_M8K 0x0 | 8783 | #define B_FE_CU_REG_MODE_FFT_M8K 0x0 |
| 8784 | #define B_FE_CU_REG_MODE_FFT_M2K 0x1 | 8784 | #define B_FE_CU_REG_MODE_FFT_M2K 0x1 |
| 8785 | 8785 | ||
| 8786 | #define B_FE_CU_REG_MODE_COR__B 1 | 8786 | #define B_FE_CU_REG_MODE_COR__B 1 |
| 8787 | #define B_FE_CU_REG_MODE_COR__W 1 | 8787 | #define B_FE_CU_REG_MODE_COR__W 1 |
| 8788 | #define B_FE_CU_REG_MODE_COR__M 0x2 | 8788 | #define B_FE_CU_REG_MODE_COR__M 0x2 |
| 8789 | #define B_FE_CU_REG_MODE_COR_OFF 0x0 | 8789 | #define B_FE_CU_REG_MODE_COR_OFF 0x0 |
| 8790 | #define B_FE_CU_REG_MODE_COR_ON 0x2 | 8790 | #define B_FE_CU_REG_MODE_COR_ON 0x2 |
| 8791 | 8791 | ||
| 8792 | #define B_FE_CU_REG_MODE_IFD__B 2 | 8792 | #define B_FE_CU_REG_MODE_IFD__B 2 |
| 8793 | #define B_FE_CU_REG_MODE_IFD__W 1 | 8793 | #define B_FE_CU_REG_MODE_IFD__W 1 |
| 8794 | #define B_FE_CU_REG_MODE_IFD__M 0x4 | 8794 | #define B_FE_CU_REG_MODE_IFD__M 0x4 |
| 8795 | #define B_FE_CU_REG_MODE_IFD_ENABLE 0x0 | 8795 | #define B_FE_CU_REG_MODE_IFD_ENABLE 0x0 |
| 8796 | #define B_FE_CU_REG_MODE_IFD_DISABLE 0x4 | 8796 | #define B_FE_CU_REG_MODE_IFD_DISABLE 0x4 |
| 8797 | 8797 | ||
| 8798 | #define B_FE_CU_REG_MODE_SEL__B 3 | 8798 | #define B_FE_CU_REG_MODE_SEL__B 3 |
| 8799 | #define B_FE_CU_REG_MODE_SEL__W 1 | 8799 | #define B_FE_CU_REG_MODE_SEL__W 1 |
| 8800 | #define B_FE_CU_REG_MODE_SEL__M 0x8 | 8800 | #define B_FE_CU_REG_MODE_SEL__M 0x8 |
| 8801 | #define B_FE_CU_REG_MODE_SEL_COR 0x0 | 8801 | #define B_FE_CU_REG_MODE_SEL_COR 0x0 |
| 8802 | #define B_FE_CU_REG_MODE_SEL_COR_NFC 0x8 | 8802 | #define B_FE_CU_REG_MODE_SEL_COR_NFC 0x8 |
| 8803 | 8803 | ||
| 8804 | #define B_FE_CU_REG_MODE_FES__B 4 | 8804 | #define B_FE_CU_REG_MODE_FES__B 4 |
| 8805 | #define B_FE_CU_REG_MODE_FES__W 1 | 8805 | #define B_FE_CU_REG_MODE_FES__W 1 |
| 8806 | #define B_FE_CU_REG_MODE_FES__M 0x10 | 8806 | #define B_FE_CU_REG_MODE_FES__M 0x10 |
| 8807 | #define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 | 8807 | #define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 |
| 8808 | #define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 | 8808 | #define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 |
| 8809 | 8809 | ||
| 8810 | #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 | 8810 | #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 |
| 8811 | #define B_FE_CU_REG_FRM_CNT_RST__W 15 | 8811 | #define B_FE_CU_REG_FRM_CNT_RST__W 15 |
| 8812 | #define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF | 8812 | #define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF |
| 8813 | #define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF | 8813 | #define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF |
| 8814 | 8814 | ||
| 8815 | #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 | 8815 | #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 |
| 8816 | #define B_FE_CU_REG_FRM_CNT_STR__W 15 | 8816 | #define B_FE_CU_REG_FRM_CNT_STR__W 15 |
| 8817 | #define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF | 8817 | #define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF |
| 8818 | #define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E | 8818 | #define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E |
| 8819 | 8819 | ||
| 8820 | #define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 | 8820 | #define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 |
| 8821 | #define B_FE_CU_REG_FRM_SMP_CNT__W 15 | 8821 | #define B_FE_CU_REG_FRM_SMP_CNT__W 15 |
| 8822 | #define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF | 8822 | #define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF |
| 8823 | 8823 | ||
| 8824 | #define B_FE_CU_REG_FRM_SMB_CNT__A 0xC70014 | 8824 | #define B_FE_CU_REG_FRM_SMB_CNT__A 0xC70014 |
| 8825 | #define B_FE_CU_REG_FRM_SMB_CNT__W 16 | 8825 | #define B_FE_CU_REG_FRM_SMB_CNT__W 16 |
| 8826 | #define B_FE_CU_REG_FRM_SMB_CNT__M 0xFFFF | 8826 | #define B_FE_CU_REG_FRM_SMB_CNT__M 0xFFFF |
| 8827 | 8827 | ||
| 8828 | #define B_FE_CU_REG_CMP_MAX_DAT__A 0xC70015 | 8828 | #define B_FE_CU_REG_CMP_MAX_DAT__A 0xC70015 |
| 8829 | #define B_FE_CU_REG_CMP_MAX_DAT__W 12 | 8829 | #define B_FE_CU_REG_CMP_MAX_DAT__W 12 |
| 8830 | #define B_FE_CU_REG_CMP_MAX_DAT__M 0xFFF | 8830 | #define B_FE_CU_REG_CMP_MAX_DAT__M 0xFFF |
| 8831 | 8831 | ||
| 8832 | #define B_FE_CU_REG_CMP_MAX_ADR__A 0xC70016 | 8832 | #define B_FE_CU_REG_CMP_MAX_ADR__A 0xC70016 |
| 8833 | #define B_FE_CU_REG_CMP_MAX_ADR__W 10 | 8833 | #define B_FE_CU_REG_CMP_MAX_ADR__W 10 |
| 8834 | #define B_FE_CU_REG_CMP_MAX_ADR__M 0x3FF | 8834 | #define B_FE_CU_REG_CMP_MAX_ADR__M 0x3FF |
| 8835 | 8835 | ||
| 8836 | #define B_FE_CU_REG_BUF_NFC_DEL__A 0xC7001F | 8836 | #define B_FE_CU_REG_BUF_NFC_DEL__A 0xC7001F |
| 8837 | #define B_FE_CU_REG_BUF_NFC_DEL__W 14 | 8837 | #define B_FE_CU_REG_BUF_NFC_DEL__W 14 |
| 8838 | #define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF | 8838 | #define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF |
| 8839 | #define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 | 8839 | #define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 |
| 8840 | 8840 | ||
| 8841 | #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 | 8841 | #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 |
| 8842 | #define B_FE_CU_REG_CTR_NFC_ICR__W 5 | 8842 | #define B_FE_CU_REG_CTR_NFC_ICR__W 5 |
| 8843 | #define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F | 8843 | #define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F |
| 8844 | #define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 | 8844 | #define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 |
| 8845 | 8845 | ||
| 8846 | #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 | 8846 | #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 |
| 8847 | #define B_FE_CU_REG_CTR_NFC_OCR__W 15 | 8847 | #define B_FE_CU_REG_CTR_NFC_OCR__W 15 |
| 8848 | #define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF | 8848 | #define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF |
| 8849 | #define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 | 8849 | #define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 |
| 8850 | 8850 | ||
| 8851 | #define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 | 8851 | #define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 |
| 8852 | #define B_FE_CU_REG_CTR_NFC_CNT__W 15 | 8852 | #define B_FE_CU_REG_CTR_NFC_CNT__W 15 |
| 8853 | #define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF | 8853 | #define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF |
| 8854 | 8854 | ||
| 8855 | #define B_FE_CU_REG_CTR_NFC_STS__A 0xC70023 | 8855 | #define B_FE_CU_REG_CTR_NFC_STS__A 0xC70023 |
| 8856 | #define B_FE_CU_REG_CTR_NFC_STS__W 3 | 8856 | #define B_FE_CU_REG_CTR_NFC_STS__W 3 |
| 8857 | #define B_FE_CU_REG_CTR_NFC_STS__M 0x7 | 8857 | #define B_FE_CU_REG_CTR_NFC_STS__M 0x7 |
| 8858 | #define B_FE_CU_REG_CTR_NFC_STS_RUN 0x0 | 8858 | #define B_FE_CU_REG_CTR_NFC_STS_RUN 0x0 |
| 8859 | #define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_IMA 0x1 | 8859 | #define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_IMA 0x1 |
| 8860 | #define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 | 8860 | #define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 |
| 8861 | #define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 | 8861 | #define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 |
| 8862 | 8862 | ||
| 8863 | #define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 | 8863 | #define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 |
| 8864 | #define B_FE_CU_REG_DIV_NFC_REA__W 14 | 8864 | #define B_FE_CU_REG_DIV_NFC_REA__W 14 |
| 8865 | #define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF | 8865 | #define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF |
| 8866 | 8866 | ||
| 8867 | #define B_FE_CU_REG_DIV_NFC_IMA__A 0xC70025 | 8867 | #define B_FE_CU_REG_DIV_NFC_IMA__A 0xC70025 |
| 8868 | #define B_FE_CU_REG_DIV_NFC_IMA__W 14 | 8868 | #define B_FE_CU_REG_DIV_NFC_IMA__W 14 |
| 8869 | #define B_FE_CU_REG_DIV_NFC_IMA__M 0x3FFF | 8869 | #define B_FE_CU_REG_DIV_NFC_IMA__M 0x3FFF |
| 8870 | 8870 | ||
| 8871 | #define B_FE_CU_REG_FRM_CNT_UPD__A 0xC70026 | 8871 | #define B_FE_CU_REG_FRM_CNT_UPD__A 0xC70026 |
| 8872 | #define B_FE_CU_REG_FRM_CNT_UPD__W 15 | 8872 | #define B_FE_CU_REG_FRM_CNT_UPD__W 15 |
| 8873 | #define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF | 8873 | #define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF |
| 8874 | #define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF | 8874 | #define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF |
| 8875 | 8875 | ||
| 8876 | #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 | 8876 | #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 |
| 8877 | #define B_FE_CU_REG_DIV_NFC_CLP__W 2 | 8877 | #define B_FE_CU_REG_DIV_NFC_CLP__W 2 |
| 8878 | #define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 | 8878 | #define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 |
| 8879 | #define B_FE_CU_REG_DIV_NFC_CLP_INIT 0x1 | 8879 | #define B_FE_CU_REG_DIV_NFC_CLP_INIT 0x1 |
| 8880 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S11 0x0 | 8880 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S11 0x0 |
| 8881 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S12 0x1 | 8881 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S12 0x1 |
| 8882 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 | 8882 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 |
| 8883 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 | 8883 | #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 |
| 8884 | 8884 | ||
| 8885 | #define B_FE_CU_BUF_RAM__A 0xC80000 | 8885 | #define B_FE_CU_BUF_RAM__A 0xC80000 |
| 8886 | 8886 | ||
| 8887 | #define B_FE_CU_CMP_RAM__A 0xC90000 | 8887 | #define B_FE_CU_CMP_RAM__A 0xC90000 |
| 8888 | 8888 | ||
| 8889 | #define B_FT_SID 0x8 | 8889 | #define B_FT_SID 0x8 |
| 8890 | 8890 | ||
| 8891 | #define B_FT_COMM_EXEC__A 0x1000000 | 8891 | #define B_FT_COMM_EXEC__A 0x1000000 |
| 8892 | #define B_FT_COMM_EXEC__W 3 | 8892 | #define B_FT_COMM_EXEC__W 3 |
| 8893 | #define B_FT_COMM_EXEC__M 0x7 | 8893 | #define B_FT_COMM_EXEC__M 0x7 |
| 8894 | #define B_FT_COMM_EXEC_CTL__B 0 | 8894 | #define B_FT_COMM_EXEC_CTL__B 0 |
| 8895 | #define B_FT_COMM_EXEC_CTL__W 3 | 8895 | #define B_FT_COMM_EXEC_CTL__W 3 |
| 8896 | #define B_FT_COMM_EXEC_CTL__M 0x7 | 8896 | #define B_FT_COMM_EXEC_CTL__M 0x7 |
| 8897 | #define B_FT_COMM_EXEC_CTL_STOP 0x0 | 8897 | #define B_FT_COMM_EXEC_CTL_STOP 0x0 |
| 8898 | #define B_FT_COMM_EXEC_CTL_ACTIVE 0x1 | 8898 | #define B_FT_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8899 | #define B_FT_COMM_EXEC_CTL_HOLD 0x2 | 8899 | #define B_FT_COMM_EXEC_CTL_HOLD 0x2 |
| 8900 | #define B_FT_COMM_EXEC_CTL_STEP 0x3 | 8900 | #define B_FT_COMM_EXEC_CTL_STEP 0x3 |
| 8901 | #define B_FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 8901 | #define B_FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 8902 | #define B_FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 8902 | #define B_FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 8903 | 8903 | ||
| 8904 | #define B_FT_COMM_STATE__A 0x1000001 | 8904 | #define B_FT_COMM_STATE__A 0x1000001 |
| 8905 | #define B_FT_COMM_STATE__W 16 | 8905 | #define B_FT_COMM_STATE__W 16 |
| 8906 | #define B_FT_COMM_STATE__M 0xFFFF | 8906 | #define B_FT_COMM_STATE__M 0xFFFF |
| 8907 | #define B_FT_COMM_MB__A 0x1000002 | 8907 | #define B_FT_COMM_MB__A 0x1000002 |
| 8908 | #define B_FT_COMM_MB__W 16 | 8908 | #define B_FT_COMM_MB__W 16 |
| 8909 | #define B_FT_COMM_MB__M 0xFFFF | 8909 | #define B_FT_COMM_MB__M 0xFFFF |
| 8910 | #define B_FT_COMM_SERVICE0__A 0x1000003 | 8910 | #define B_FT_COMM_SERVICE0__A 0x1000003 |
| 8911 | #define B_FT_COMM_SERVICE0__W 16 | 8911 | #define B_FT_COMM_SERVICE0__W 16 |
| 8912 | #define B_FT_COMM_SERVICE0__M 0xFFFF | 8912 | #define B_FT_COMM_SERVICE0__M 0xFFFF |
| 8913 | #define B_FT_COMM_SERVICE1__A 0x1000004 | 8913 | #define B_FT_COMM_SERVICE1__A 0x1000004 |
| 8914 | #define B_FT_COMM_SERVICE1__W 16 | 8914 | #define B_FT_COMM_SERVICE1__W 16 |
| 8915 | #define B_FT_COMM_SERVICE1__M 0xFFFF | 8915 | #define B_FT_COMM_SERVICE1__M 0xFFFF |
| 8916 | #define B_FT_COMM_INT_STA__A 0x1000007 | 8916 | #define B_FT_COMM_INT_STA__A 0x1000007 |
| 8917 | #define B_FT_COMM_INT_STA__W 16 | 8917 | #define B_FT_COMM_INT_STA__W 16 |
| 8918 | #define B_FT_COMM_INT_STA__M 0xFFFF | 8918 | #define B_FT_COMM_INT_STA__M 0xFFFF |
| 8919 | #define B_FT_COMM_INT_MSK__A 0x1000008 | 8919 | #define B_FT_COMM_INT_MSK__A 0x1000008 |
| 8920 | #define B_FT_COMM_INT_MSK__W 16 | 8920 | #define B_FT_COMM_INT_MSK__W 16 |
| 8921 | #define B_FT_COMM_INT_MSK__M 0xFFFF | 8921 | #define B_FT_COMM_INT_MSK__M 0xFFFF |
| 8922 | 8922 | ||
| 8923 | #define B_FT_REG_COMM_EXEC__A 0x1010000 | 8923 | #define B_FT_REG_COMM_EXEC__A 0x1010000 |
| 8924 | #define B_FT_REG_COMM_EXEC__W 3 | 8924 | #define B_FT_REG_COMM_EXEC__W 3 |
| 8925 | #define B_FT_REG_COMM_EXEC__M 0x7 | 8925 | #define B_FT_REG_COMM_EXEC__M 0x7 |
| 8926 | #define B_FT_REG_COMM_EXEC_CTL__B 0 | 8926 | #define B_FT_REG_COMM_EXEC_CTL__B 0 |
| 8927 | #define B_FT_REG_COMM_EXEC_CTL__W 3 | 8927 | #define B_FT_REG_COMM_EXEC_CTL__W 3 |
| 8928 | #define B_FT_REG_COMM_EXEC_CTL__M 0x7 | 8928 | #define B_FT_REG_COMM_EXEC_CTL__M 0x7 |
| 8929 | #define B_FT_REG_COMM_EXEC_CTL_STOP 0x0 | 8929 | #define B_FT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 8930 | #define B_FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 8930 | #define B_FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8931 | #define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 | 8931 | #define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 8932 | #define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 | 8932 | #define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 8933 | 8933 | ||
| 8934 | #define B_FT_REG_COMM_MB__A 0x1010002 | 8934 | #define B_FT_REG_COMM_MB__A 0x1010002 |
| 8935 | #define B_FT_REG_COMM_MB__W 3 | 8935 | #define B_FT_REG_COMM_MB__W 3 |
| 8936 | #define B_FT_REG_COMM_MB__M 0x7 | 8936 | #define B_FT_REG_COMM_MB__M 0x7 |
| 8937 | #define B_FT_REG_COMM_MB_CTR__B 0 | 8937 | #define B_FT_REG_COMM_MB_CTR__B 0 |
| 8938 | #define B_FT_REG_COMM_MB_CTR__W 1 | 8938 | #define B_FT_REG_COMM_MB_CTR__W 1 |
| 8939 | #define B_FT_REG_COMM_MB_CTR__M 0x1 | 8939 | #define B_FT_REG_COMM_MB_CTR__M 0x1 |
| 8940 | #define B_FT_REG_COMM_MB_CTR_OFF 0x0 | 8940 | #define B_FT_REG_COMM_MB_CTR_OFF 0x0 |
| 8941 | #define B_FT_REG_COMM_MB_CTR_ON 0x1 | 8941 | #define B_FT_REG_COMM_MB_CTR_ON 0x1 |
| 8942 | #define B_FT_REG_COMM_MB_OBS__B 1 | 8942 | #define B_FT_REG_COMM_MB_OBS__B 1 |
| 8943 | #define B_FT_REG_COMM_MB_OBS__W 1 | 8943 | #define B_FT_REG_COMM_MB_OBS__W 1 |
| 8944 | #define B_FT_REG_COMM_MB_OBS__M 0x2 | 8944 | #define B_FT_REG_COMM_MB_OBS__M 0x2 |
| 8945 | #define B_FT_REG_COMM_MB_OBS_OFF 0x0 | 8945 | #define B_FT_REG_COMM_MB_OBS_OFF 0x0 |
| 8946 | #define B_FT_REG_COMM_MB_OBS_ON 0x2 | 8946 | #define B_FT_REG_COMM_MB_OBS_ON 0x2 |
| 8947 | 8947 | ||
| 8948 | #define B_FT_REG_MODE_2K__A 0x1010010 | 8948 | #define B_FT_REG_MODE_2K__A 0x1010010 |
| 8949 | #define B_FT_REG_MODE_2K__W 1 | 8949 | #define B_FT_REG_MODE_2K__W 1 |
| 8950 | #define B_FT_REG_MODE_2K__M 0x1 | 8950 | #define B_FT_REG_MODE_2K__M 0x1 |
| 8951 | #define B_FT_REG_MODE_2K_MODE_8K 0x0 | 8951 | #define B_FT_REG_MODE_2K_MODE_8K 0x0 |
| 8952 | #define B_FT_REG_MODE_2K_MODE_2K 0x1 | 8952 | #define B_FT_REG_MODE_2K_MODE_2K 0x1 |
| 8953 | #define B_FT_REG_MODE_2K_INIT 0x0 | 8953 | #define B_FT_REG_MODE_2K_INIT 0x0 |
| 8954 | 8954 | ||
| 8955 | #define B_FT_REG_NORM_OFF__A 0x1010016 | 8955 | #define B_FT_REG_NORM_OFF__A 0x1010016 |
| 8956 | #define B_FT_REG_NORM_OFF__W 4 | 8956 | #define B_FT_REG_NORM_OFF__W 4 |
| 8957 | #define B_FT_REG_NORM_OFF__M 0xF | 8957 | #define B_FT_REG_NORM_OFF__M 0xF |
| 8958 | #define B_FT_REG_NORM_OFF_INIT 0x2 | 8958 | #define B_FT_REG_NORM_OFF_INIT 0x2 |
| 8959 | 8959 | ||
| 8960 | #define B_FT_ST1_RAM__A 0x1020000 | 8960 | #define B_FT_ST1_RAM__A 0x1020000 |
| 8961 | 8961 | ||
| 8962 | #define B_FT_ST2_RAM__A 0x1030000 | 8962 | #define B_FT_ST2_RAM__A 0x1030000 |
| 8963 | 8963 | ||
| 8964 | #define B_FT_ST3_RAM__A 0x1040000 | 8964 | #define B_FT_ST3_RAM__A 0x1040000 |
| 8965 | 8965 | ||
| 8966 | #define B_FT_ST5_RAM__A 0x1050000 | 8966 | #define B_FT_ST5_RAM__A 0x1050000 |
| 8967 | 8967 | ||
| 8968 | #define B_FT_ST6_RAM__A 0x1060000 | 8968 | #define B_FT_ST6_RAM__A 0x1060000 |
| 8969 | 8969 | ||
| 8970 | #define B_FT_ST8_RAM__A 0x1070000 | 8970 | #define B_FT_ST8_RAM__A 0x1070000 |
| 8971 | 8971 | ||
| 8972 | #define B_FT_ST9_RAM__A 0x1080000 | 8972 | #define B_FT_ST9_RAM__A 0x1080000 |
| 8973 | 8973 | ||
| 8974 | #define B_CP_SID 0x9 | 8974 | #define B_CP_SID 0x9 |
| 8975 | 8975 | ||
| 8976 | #define B_CP_COMM_EXEC__A 0x1400000 | 8976 | #define B_CP_COMM_EXEC__A 0x1400000 |
| 8977 | #define B_CP_COMM_EXEC__W 3 | 8977 | #define B_CP_COMM_EXEC__W 3 |
| 8978 | #define B_CP_COMM_EXEC__M 0x7 | 8978 | #define B_CP_COMM_EXEC__M 0x7 |
| 8979 | #define B_CP_COMM_EXEC_CTL__B 0 | 8979 | #define B_CP_COMM_EXEC_CTL__B 0 |
| 8980 | #define B_CP_COMM_EXEC_CTL__W 3 | 8980 | #define B_CP_COMM_EXEC_CTL__W 3 |
| 8981 | #define B_CP_COMM_EXEC_CTL__M 0x7 | 8981 | #define B_CP_COMM_EXEC_CTL__M 0x7 |
| 8982 | #define B_CP_COMM_EXEC_CTL_STOP 0x0 | 8982 | #define B_CP_COMM_EXEC_CTL_STOP 0x0 |
| 8983 | #define B_CP_COMM_EXEC_CTL_ACTIVE 0x1 | 8983 | #define B_CP_COMM_EXEC_CTL_ACTIVE 0x1 |
| 8984 | #define B_CP_COMM_EXEC_CTL_HOLD 0x2 | 8984 | #define B_CP_COMM_EXEC_CTL_HOLD 0x2 |
| 8985 | #define B_CP_COMM_EXEC_CTL_STEP 0x3 | 8985 | #define B_CP_COMM_EXEC_CTL_STEP 0x3 |
| 8986 | #define B_CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 8986 | #define B_CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 8987 | #define B_CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 8987 | #define B_CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 8988 | 8988 | ||
| 8989 | #define B_CP_COMM_STATE__A 0x1400001 | 8989 | #define B_CP_COMM_STATE__A 0x1400001 |
| 8990 | #define B_CP_COMM_STATE__W 16 | 8990 | #define B_CP_COMM_STATE__W 16 |
| 8991 | #define B_CP_COMM_STATE__M 0xFFFF | 8991 | #define B_CP_COMM_STATE__M 0xFFFF |
| 8992 | #define B_CP_COMM_MB__A 0x1400002 | 8992 | #define B_CP_COMM_MB__A 0x1400002 |
| 8993 | #define B_CP_COMM_MB__W 16 | 8993 | #define B_CP_COMM_MB__W 16 |
| 8994 | #define B_CP_COMM_MB__M 0xFFFF | 8994 | #define B_CP_COMM_MB__M 0xFFFF |
| 8995 | #define B_CP_COMM_SERVICE0__A 0x1400003 | 8995 | #define B_CP_COMM_SERVICE0__A 0x1400003 |
| 8996 | #define B_CP_COMM_SERVICE0__W 16 | 8996 | #define B_CP_COMM_SERVICE0__W 16 |
| 8997 | #define B_CP_COMM_SERVICE0__M 0xFFFF | 8997 | #define B_CP_COMM_SERVICE0__M 0xFFFF |
| 8998 | #define B_CP_COMM_SERVICE1__A 0x1400004 | 8998 | #define B_CP_COMM_SERVICE1__A 0x1400004 |
| 8999 | #define B_CP_COMM_SERVICE1__W 16 | 8999 | #define B_CP_COMM_SERVICE1__W 16 |
| 9000 | #define B_CP_COMM_SERVICE1__M 0xFFFF | 9000 | #define B_CP_COMM_SERVICE1__M 0xFFFF |
| 9001 | #define B_CP_COMM_INT_STA__A 0x1400007 | 9001 | #define B_CP_COMM_INT_STA__A 0x1400007 |
| 9002 | #define B_CP_COMM_INT_STA__W 16 | 9002 | #define B_CP_COMM_INT_STA__W 16 |
| 9003 | #define B_CP_COMM_INT_STA__M 0xFFFF | 9003 | #define B_CP_COMM_INT_STA__M 0xFFFF |
| 9004 | #define B_CP_COMM_INT_MSK__A 0x1400008 | 9004 | #define B_CP_COMM_INT_MSK__A 0x1400008 |
| 9005 | #define B_CP_COMM_INT_MSK__W 16 | 9005 | #define B_CP_COMM_INT_MSK__W 16 |
| 9006 | #define B_CP_COMM_INT_MSK__M 0xFFFF | 9006 | #define B_CP_COMM_INT_MSK__M 0xFFFF |
| 9007 | 9007 | ||
| 9008 | #define B_CP_REG_COMM_EXEC__A 0x1410000 | 9008 | #define B_CP_REG_COMM_EXEC__A 0x1410000 |
| 9009 | #define B_CP_REG_COMM_EXEC__W 3 | 9009 | #define B_CP_REG_COMM_EXEC__W 3 |
| 9010 | #define B_CP_REG_COMM_EXEC__M 0x7 | 9010 | #define B_CP_REG_COMM_EXEC__M 0x7 |
| 9011 | #define B_CP_REG_COMM_EXEC_CTL__B 0 | 9011 | #define B_CP_REG_COMM_EXEC_CTL__B 0 |
| 9012 | #define B_CP_REG_COMM_EXEC_CTL__W 3 | 9012 | #define B_CP_REG_COMM_EXEC_CTL__W 3 |
| 9013 | #define B_CP_REG_COMM_EXEC_CTL__M 0x7 | 9013 | #define B_CP_REG_COMM_EXEC_CTL__M 0x7 |
| 9014 | #define B_CP_REG_COMM_EXEC_CTL_STOP 0x0 | 9014 | #define B_CP_REG_COMM_EXEC_CTL_STOP 0x0 |
| 9015 | #define B_CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 9015 | #define B_CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 9016 | #define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 | 9016 | #define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 9017 | #define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 | 9017 | #define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 |
| 9018 | 9018 | ||
| 9019 | #define B_CP_REG_COMM_MB__A 0x1410002 | 9019 | #define B_CP_REG_COMM_MB__A 0x1410002 |
| 9020 | #define B_CP_REG_COMM_MB__W 3 | 9020 | #define B_CP_REG_COMM_MB__W 3 |
| 9021 | #define B_CP_REG_COMM_MB__M 0x7 | 9021 | #define B_CP_REG_COMM_MB__M 0x7 |
| 9022 | #define B_CP_REG_COMM_MB_CTR__B 0 | 9022 | #define B_CP_REG_COMM_MB_CTR__B 0 |
| 9023 | #define B_CP_REG_COMM_MB_CTR__W 1 | 9023 | #define B_CP_REG_COMM_MB_CTR__W 1 |
| 9024 | #define B_CP_REG_COMM_MB_CTR__M 0x1 | 9024 | #define B_CP_REG_COMM_MB_CTR__M 0x1 |
| 9025 | #define B_CP_REG_COMM_MB_CTR_OFF 0x0 | 9025 | #define B_CP_REG_COMM_MB_CTR_OFF 0x0 |
| 9026 | #define B_CP_REG_COMM_MB_CTR_ON 0x1 | 9026 | #define B_CP_REG_COMM_MB_CTR_ON 0x1 |
| 9027 | #define B_CP_REG_COMM_MB_OBS__B 1 | 9027 | #define B_CP_REG_COMM_MB_OBS__B 1 |
| 9028 | #define B_CP_REG_COMM_MB_OBS__W 1 | 9028 | #define B_CP_REG_COMM_MB_OBS__W 1 |
| 9029 | #define B_CP_REG_COMM_MB_OBS__M 0x2 | 9029 | #define B_CP_REG_COMM_MB_OBS__M 0x2 |
| 9030 | #define B_CP_REG_COMM_MB_OBS_OFF 0x0 | 9030 | #define B_CP_REG_COMM_MB_OBS_OFF 0x0 |
| 9031 | #define B_CP_REG_COMM_MB_OBS_ON 0x2 | 9031 | #define B_CP_REG_COMM_MB_OBS_ON 0x2 |
| 9032 | 9032 | ||
| 9033 | #define B_CP_REG_COMM_SERVICE0__A 0x1410003 | 9033 | #define B_CP_REG_COMM_SERVICE0__A 0x1410003 |
| 9034 | #define B_CP_REG_COMM_SERVICE0__W 10 | 9034 | #define B_CP_REG_COMM_SERVICE0__W 10 |
| 9035 | #define B_CP_REG_COMM_SERVICE0__M 0x3FF | 9035 | #define B_CP_REG_COMM_SERVICE0__M 0x3FF |
| 9036 | #define B_CP_REG_COMM_SERVICE0_CP__B 9 | 9036 | #define B_CP_REG_COMM_SERVICE0_CP__B 9 |
| 9037 | #define B_CP_REG_COMM_SERVICE0_CP__W 1 | 9037 | #define B_CP_REG_COMM_SERVICE0_CP__W 1 |
| 9038 | #define B_CP_REG_COMM_SERVICE0_CP__M 0x200 | 9038 | #define B_CP_REG_COMM_SERVICE0_CP__M 0x200 |
| 9039 | 9039 | ||
| 9040 | #define B_CP_REG_COMM_SERVICE1__A 0x1410004 | 9040 | #define B_CP_REG_COMM_SERVICE1__A 0x1410004 |
| 9041 | #define B_CP_REG_COMM_SERVICE1__W 11 | 9041 | #define B_CP_REG_COMM_SERVICE1__W 11 |
| 9042 | #define B_CP_REG_COMM_SERVICE1__M 0x7FF | 9042 | #define B_CP_REG_COMM_SERVICE1__M 0x7FF |
| 9043 | 9043 | ||
| 9044 | #define B_CP_REG_COMM_INT_STA__A 0x1410007 | 9044 | #define B_CP_REG_COMM_INT_STA__A 0x1410007 |
| 9045 | #define B_CP_REG_COMM_INT_STA__W 2 | 9045 | #define B_CP_REG_COMM_INT_STA__W 2 |
| 9046 | #define B_CP_REG_COMM_INT_STA__M 0x3 | 9046 | #define B_CP_REG_COMM_INT_STA__M 0x3 |
| 9047 | #define B_CP_REG_COMM_INT_STA_NEW_MEAS__B 0 | 9047 | #define B_CP_REG_COMM_INT_STA_NEW_MEAS__B 0 |
| 9048 | #define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 | 9048 | #define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 |
| 9049 | #define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 | 9049 | #define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 |
| 9050 | 9050 | ||
| 9051 | #define B_CP_REG_COMM_INT_MSK__A 0x1410008 | 9051 | #define B_CP_REG_COMM_INT_MSK__A 0x1410008 |
| 9052 | #define B_CP_REG_COMM_INT_MSK__W 2 | 9052 | #define B_CP_REG_COMM_INT_MSK__W 2 |
| 9053 | #define B_CP_REG_COMM_INT_MSK__M 0x3 | 9053 | #define B_CP_REG_COMM_INT_MSK__M 0x3 |
| 9054 | #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 | 9054 | #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 |
| 9055 | #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 | 9055 | #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 |
| 9056 | #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 | 9056 | #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 |
| 9057 | 9057 | ||
| 9058 | #define B_CP_REG_MODE_2K__A 0x1410010 | 9058 | #define B_CP_REG_MODE_2K__A 0x1410010 |
| 9059 | #define B_CP_REG_MODE_2K__W 1 | 9059 | #define B_CP_REG_MODE_2K__W 1 |
| 9060 | #define B_CP_REG_MODE_2K__M 0x1 | 9060 | #define B_CP_REG_MODE_2K__M 0x1 |
| 9061 | #define B_CP_REG_MODE_2K_INIT 0x0 | 9061 | #define B_CP_REG_MODE_2K_INIT 0x0 |
| 9062 | 9062 | ||
| 9063 | #define B_CP_REG_INTERVAL__A 0x1410011 | 9063 | #define B_CP_REG_INTERVAL__A 0x1410011 |
| 9064 | #define B_CP_REG_INTERVAL__W 4 | 9064 | #define B_CP_REG_INTERVAL__W 4 |
| 9065 | #define B_CP_REG_INTERVAL__M 0xF | 9065 | #define B_CP_REG_INTERVAL__M 0xF |
| 9066 | #define B_CP_REG_INTERVAL_INIT 0x5 | 9066 | #define B_CP_REG_INTERVAL_INIT 0x5 |
| 9067 | 9067 | ||
| 9068 | #define B_CP_REG_DETECT_ENA__A 0x1410012 | 9068 | #define B_CP_REG_DETECT_ENA__A 0x1410012 |
| 9069 | #define B_CP_REG_DETECT_ENA__W 2 | 9069 | #define B_CP_REG_DETECT_ENA__W 2 |
| 9070 | #define B_CP_REG_DETECT_ENA__M 0x3 | 9070 | #define B_CP_REG_DETECT_ENA__M 0x3 |
| 9071 | 9071 | ||
| 9072 | #define B_CP_REG_DETECT_ENA_SCATTERED__B 0 | 9072 | #define B_CP_REG_DETECT_ENA_SCATTERED__B 0 |
| 9073 | #define B_CP_REG_DETECT_ENA_SCATTERED__W 1 | 9073 | #define B_CP_REG_DETECT_ENA_SCATTERED__W 1 |
| 9074 | #define B_CP_REG_DETECT_ENA_SCATTERED__M 0x1 | 9074 | #define B_CP_REG_DETECT_ENA_SCATTERED__M 0x1 |
| 9075 | 9075 | ||
| 9076 | #define B_CP_REG_DETECT_ENA_CONTINUOUS__B 1 | 9076 | #define B_CP_REG_DETECT_ENA_CONTINUOUS__B 1 |
| 9077 | #define B_CP_REG_DETECT_ENA_CONTINUOUS__W 1 | 9077 | #define B_CP_REG_DETECT_ENA_CONTINUOUS__W 1 |
| 9078 | #define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 | 9078 | #define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 |
| 9079 | #define B_CP_REG_DETECT_ENA_INIT 0x0 | 9079 | #define B_CP_REG_DETECT_ENA_INIT 0x0 |
| 9080 | 9080 | ||
| 9081 | #define B_CP_REG_BR_SMB_NR__A 0x1410021 | 9081 | #define B_CP_REG_BR_SMB_NR__A 0x1410021 |
| 9082 | #define B_CP_REG_BR_SMB_NR__W 4 | 9082 | #define B_CP_REG_BR_SMB_NR__W 4 |
| 9083 | #define B_CP_REG_BR_SMB_NR__M 0xF | 9083 | #define B_CP_REG_BR_SMB_NR__M 0xF |
| 9084 | 9084 | ||
| 9085 | #define B_CP_REG_BR_SMB_NR_SMB__B 0 | 9085 | #define B_CP_REG_BR_SMB_NR_SMB__B 0 |
| 9086 | #define B_CP_REG_BR_SMB_NR_SMB__W 2 | 9086 | #define B_CP_REG_BR_SMB_NR_SMB__W 2 |
| 9087 | #define B_CP_REG_BR_SMB_NR_SMB__M 0x3 | 9087 | #define B_CP_REG_BR_SMB_NR_SMB__M 0x3 |
| 9088 | 9088 | ||
| 9089 | #define B_CP_REG_BR_SMB_NR_VAL__B 2 | 9089 | #define B_CP_REG_BR_SMB_NR_VAL__B 2 |
| 9090 | #define B_CP_REG_BR_SMB_NR_VAL__W 1 | 9090 | #define B_CP_REG_BR_SMB_NR_VAL__W 1 |
| 9091 | #define B_CP_REG_BR_SMB_NR_VAL__M 0x4 | 9091 | #define B_CP_REG_BR_SMB_NR_VAL__M 0x4 |
| 9092 | 9092 | ||
| 9093 | #define B_CP_REG_BR_SMB_NR_OFFSET__B 3 | 9093 | #define B_CP_REG_BR_SMB_NR_OFFSET__B 3 |
| 9094 | #define B_CP_REG_BR_SMB_NR_OFFSET__W 1 | 9094 | #define B_CP_REG_BR_SMB_NR_OFFSET__W 1 |
| 9095 | #define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 | 9095 | #define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 |
| 9096 | #define B_CP_REG_BR_SMB_NR_INIT 0x0 | 9096 | #define B_CP_REG_BR_SMB_NR_INIT 0x0 |
| 9097 | 9097 | ||
| 9098 | #define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 | 9098 | #define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 |
| 9099 | #define B_CP_REG_BR_CP_SMB_NR__W 2 | 9099 | #define B_CP_REG_BR_CP_SMB_NR__W 2 |
| 9100 | #define B_CP_REG_BR_CP_SMB_NR__M 0x3 | 9100 | #define B_CP_REG_BR_CP_SMB_NR__M 0x3 |
| 9101 | #define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 | 9101 | #define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 |
| 9102 | 9102 | ||
| 9103 | #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 | 9103 | #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 |
| 9104 | #define B_CP_REG_BR_SPL_OFFSET__W 3 | 9104 | #define B_CP_REG_BR_SPL_OFFSET__W 3 |
| 9105 | #define B_CP_REG_BR_SPL_OFFSET__M 0x7 | 9105 | #define B_CP_REG_BR_SPL_OFFSET__M 0x7 |
| 9106 | #define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 | 9106 | #define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 |
| 9107 | 9107 | ||
| 9108 | #define B_CP_REG_BR_STR_DEL__A 0x1410024 | 9108 | #define B_CP_REG_BR_STR_DEL__A 0x1410024 |
| 9109 | #define B_CP_REG_BR_STR_DEL__W 10 | 9109 | #define B_CP_REG_BR_STR_DEL__W 10 |
| 9110 | #define B_CP_REG_BR_STR_DEL__M 0x3FF | 9110 | #define B_CP_REG_BR_STR_DEL__M 0x3FF |
| 9111 | #define B_CP_REG_BR_STR_DEL_INIT 0xA | 9111 | #define B_CP_REG_BR_STR_DEL_INIT 0xA |
| 9112 | 9112 | ||
| 9113 | #define B_CP_REG_BR_EXP_ADJ__A 0x1410025 | 9113 | #define B_CP_REG_BR_EXP_ADJ__A 0x1410025 |
| 9114 | #define B_CP_REG_BR_EXP_ADJ__W 5 | 9114 | #define B_CP_REG_BR_EXP_ADJ__W 5 |
| 9115 | #define B_CP_REG_BR_EXP_ADJ__M 0x1F | 9115 | #define B_CP_REG_BR_EXP_ADJ__M 0x1F |
| 9116 | #define B_CP_REG_BR_EXP_ADJ_INIT 0x10 | 9116 | #define B_CP_REG_BR_EXP_ADJ_INIT 0x10 |
| 9117 | 9117 | ||
| 9118 | #define B_CP_REG_RT_ANG_INC0__A 0x1410030 | 9118 | #define B_CP_REG_RT_ANG_INC0__A 0x1410030 |
| 9119 | #define B_CP_REG_RT_ANG_INC0__W 16 | 9119 | #define B_CP_REG_RT_ANG_INC0__W 16 |
| 9120 | #define B_CP_REG_RT_ANG_INC0__M 0xFFFF | 9120 | #define B_CP_REG_RT_ANG_INC0__M 0xFFFF |
| 9121 | #define B_CP_REG_RT_ANG_INC0_INIT 0x0 | 9121 | #define B_CP_REG_RT_ANG_INC0_INIT 0x0 |
| 9122 | 9122 | ||
| 9123 | #define B_CP_REG_RT_ANG_INC1__A 0x1410031 | 9123 | #define B_CP_REG_RT_ANG_INC1__A 0x1410031 |
| 9124 | #define B_CP_REG_RT_ANG_INC1__W 8 | 9124 | #define B_CP_REG_RT_ANG_INC1__W 8 |
| 9125 | #define B_CP_REG_RT_ANG_INC1__M 0xFF | 9125 | #define B_CP_REG_RT_ANG_INC1__M 0xFF |
| 9126 | #define B_CP_REG_RT_ANG_INC1_INIT 0x0 | 9126 | #define B_CP_REG_RT_ANG_INC1_INIT 0x0 |
| 9127 | 9127 | ||
| 9128 | #define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 | 9128 | #define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 |
| 9129 | #define B_CP_REG_RT_SPD_EXP_MARG__W 5 | 9129 | #define B_CP_REG_RT_SPD_EXP_MARG__W 5 |
| 9130 | #define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F | 9130 | #define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F |
| 9131 | #define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 | 9131 | #define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 |
| 9132 | 9132 | ||
| 9133 | #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 | 9133 | #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 |
| 9134 | #define B_CP_REG_RT_DETECT_TRH__W 2 | 9134 | #define B_CP_REG_RT_DETECT_TRH__W 2 |
| 9135 | #define B_CP_REG_RT_DETECT_TRH__M 0x3 | 9135 | #define B_CP_REG_RT_DETECT_TRH__M 0x3 |
| 9136 | #define B_CP_REG_RT_DETECT_TRH_INIT 0x3 | 9136 | #define B_CP_REG_RT_DETECT_TRH_INIT 0x3 |
| 9137 | 9137 | ||
| 9138 | #define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 | 9138 | #define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 |
| 9139 | #define B_CP_REG_RT_SPD_RELIABLE__W 3 | 9139 | #define B_CP_REG_RT_SPD_RELIABLE__W 3 |
| 9140 | #define B_CP_REG_RT_SPD_RELIABLE__M 0x7 | 9140 | #define B_CP_REG_RT_SPD_RELIABLE__M 0x7 |
| 9141 | #define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 | 9141 | #define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 |
| 9142 | 9142 | ||
| 9143 | #define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 | 9143 | #define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 |
| 9144 | #define B_CP_REG_RT_SPD_DIRECTION__W 1 | 9144 | #define B_CP_REG_RT_SPD_DIRECTION__W 1 |
| 9145 | #define B_CP_REG_RT_SPD_DIRECTION__M 0x1 | 9145 | #define B_CP_REG_RT_SPD_DIRECTION__M 0x1 |
| 9146 | #define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 | 9146 | #define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 |
| 9147 | 9147 | ||
| 9148 | #define B_CP_REG_RT_SPD_MOD__A 0x1410036 | 9148 | #define B_CP_REG_RT_SPD_MOD__A 0x1410036 |
| 9149 | #define B_CP_REG_RT_SPD_MOD__W 2 | 9149 | #define B_CP_REG_RT_SPD_MOD__W 2 |
| 9150 | #define B_CP_REG_RT_SPD_MOD__M 0x3 | 9150 | #define B_CP_REG_RT_SPD_MOD__M 0x3 |
| 9151 | #define B_CP_REG_RT_SPD_MOD_INIT 0x0 | 9151 | #define B_CP_REG_RT_SPD_MOD_INIT 0x0 |
| 9152 | 9152 | ||
| 9153 | #define B_CP_REG_RT_SPD_SMB__A 0x1410037 | 9153 | #define B_CP_REG_RT_SPD_SMB__A 0x1410037 |
| 9154 | #define B_CP_REG_RT_SPD_SMB__W 2 | 9154 | #define B_CP_REG_RT_SPD_SMB__W 2 |
| 9155 | #define B_CP_REG_RT_SPD_SMB__M 0x3 | 9155 | #define B_CP_REG_RT_SPD_SMB__M 0x3 |
| 9156 | #define B_CP_REG_RT_SPD_SMB_INIT 0x0 | 9156 | #define B_CP_REG_RT_SPD_SMB_INIT 0x0 |
| 9157 | 9157 | ||
| 9158 | #define B_CP_REG_RT_CPD_MODE__A 0x1410038 | 9158 | #define B_CP_REG_RT_CPD_MODE__A 0x1410038 |
| 9159 | #define B_CP_REG_RT_CPD_MODE__W 3 | 9159 | #define B_CP_REG_RT_CPD_MODE__W 3 |
| 9160 | #define B_CP_REG_RT_CPD_MODE__M 0x7 | 9160 | #define B_CP_REG_RT_CPD_MODE__M 0x7 |
| 9161 | 9161 | ||
| 9162 | #define B_CP_REG_RT_CPD_MODE_MOD3__B 0 | 9162 | #define B_CP_REG_RT_CPD_MODE_MOD3__B 0 |
| 9163 | #define B_CP_REG_RT_CPD_MODE_MOD3__W 2 | 9163 | #define B_CP_REG_RT_CPD_MODE_MOD3__W 2 |
| 9164 | #define B_CP_REG_RT_CPD_MODE_MOD3__M 0x3 | 9164 | #define B_CP_REG_RT_CPD_MODE_MOD3__M 0x3 |
| 9165 | 9165 | ||
| 9166 | #define B_CP_REG_RT_CPD_MODE_ADD__B 2 | 9166 | #define B_CP_REG_RT_CPD_MODE_ADD__B 2 |
| 9167 | #define B_CP_REG_RT_CPD_MODE_ADD__W 1 | 9167 | #define B_CP_REG_RT_CPD_MODE_ADD__W 1 |
| 9168 | #define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 | 9168 | #define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 |
| 9169 | #define B_CP_REG_RT_CPD_MODE_INIT 0x0 | 9169 | #define B_CP_REG_RT_CPD_MODE_INIT 0x0 |
| 9170 | 9170 | ||
| 9171 | #define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 | 9171 | #define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 |
| 9172 | #define B_CP_REG_RT_CPD_RELIABLE__W 3 | 9172 | #define B_CP_REG_RT_CPD_RELIABLE__W 3 |
| 9173 | #define B_CP_REG_RT_CPD_RELIABLE__M 0x7 | 9173 | #define B_CP_REG_RT_CPD_RELIABLE__M 0x7 |
| 9174 | #define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 | 9174 | #define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 |
| 9175 | 9175 | ||
| 9176 | #define B_CP_REG_RT_CPD_BIN__A 0x141003A | 9176 | #define B_CP_REG_RT_CPD_BIN__A 0x141003A |
| 9177 | #define B_CP_REG_RT_CPD_BIN__W 5 | 9177 | #define B_CP_REG_RT_CPD_BIN__W 5 |
| 9178 | #define B_CP_REG_RT_CPD_BIN__M 0x1F | 9178 | #define B_CP_REG_RT_CPD_BIN__M 0x1F |
| 9179 | #define B_CP_REG_RT_CPD_BIN_INIT 0x0 | 9179 | #define B_CP_REG_RT_CPD_BIN_INIT 0x0 |
| 9180 | 9180 | ||
| 9181 | #define B_CP_REG_RT_CPD_MAX__A 0x141003B | 9181 | #define B_CP_REG_RT_CPD_MAX__A 0x141003B |
| 9182 | #define B_CP_REG_RT_CPD_MAX__W 4 | 9182 | #define B_CP_REG_RT_CPD_MAX__W 4 |
| 9183 | #define B_CP_REG_RT_CPD_MAX__M 0xF | 9183 | #define B_CP_REG_RT_CPD_MAX__M 0xF |
| 9184 | #define B_CP_REG_RT_CPD_MAX_INIT 0x0 | 9184 | #define B_CP_REG_RT_CPD_MAX_INIT 0x0 |
| 9185 | 9185 | ||
| 9186 | #define B_CP_REG_RT_SUPR_VAL__A 0x141003C | 9186 | #define B_CP_REG_RT_SUPR_VAL__A 0x141003C |
| 9187 | #define B_CP_REG_RT_SUPR_VAL__W 2 | 9187 | #define B_CP_REG_RT_SUPR_VAL__W 2 |
| 9188 | #define B_CP_REG_RT_SUPR_VAL__M 0x3 | 9188 | #define B_CP_REG_RT_SUPR_VAL__M 0x3 |
| 9189 | 9189 | ||
| 9190 | #define B_CP_REG_RT_SUPR_VAL_CE__B 0 | 9190 | #define B_CP_REG_RT_SUPR_VAL_CE__B 0 |
| 9191 | #define B_CP_REG_RT_SUPR_VAL_CE__W 1 | 9191 | #define B_CP_REG_RT_SUPR_VAL_CE__W 1 |
| 9192 | #define B_CP_REG_RT_SUPR_VAL_CE__M 0x1 | 9192 | #define B_CP_REG_RT_SUPR_VAL_CE__M 0x1 |
| 9193 | 9193 | ||
| 9194 | #define B_CP_REG_RT_SUPR_VAL_DL__B 1 | 9194 | #define B_CP_REG_RT_SUPR_VAL_DL__B 1 |
| 9195 | #define B_CP_REG_RT_SUPR_VAL_DL__W 1 | 9195 | #define B_CP_REG_RT_SUPR_VAL_DL__W 1 |
| 9196 | #define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 | 9196 | #define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 |
| 9197 | #define B_CP_REG_RT_SUPR_VAL_INIT 0x0 | 9197 | #define B_CP_REG_RT_SUPR_VAL_INIT 0x0 |
| 9198 | 9198 | ||
| 9199 | #define B_CP_REG_RT_EXP_AVE__A 0x141003D | 9199 | #define B_CP_REG_RT_EXP_AVE__A 0x141003D |
| 9200 | #define B_CP_REG_RT_EXP_AVE__W 5 | 9200 | #define B_CP_REG_RT_EXP_AVE__W 5 |
| 9201 | #define B_CP_REG_RT_EXP_AVE__M 0x1F | 9201 | #define B_CP_REG_RT_EXP_AVE__M 0x1F |
| 9202 | #define B_CP_REG_RT_EXP_AVE_INIT 0x0 | 9202 | #define B_CP_REG_RT_EXP_AVE_INIT 0x0 |
| 9203 | 9203 | ||
| 9204 | #define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E | 9204 | #define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E |
| 9205 | #define B_CP_REG_RT_CPD_EXP_MARG__W 5 | 9205 | #define B_CP_REG_RT_CPD_EXP_MARG__W 5 |
| 9206 | #define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F | 9206 | #define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F |
| 9207 | #define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 | 9207 | #define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 |
| 9208 | 9208 | ||
| 9209 | #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 | 9209 | #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 |
| 9210 | #define B_CP_REG_AC_NEXP_OFFS__W 8 | 9210 | #define B_CP_REG_AC_NEXP_OFFS__W 8 |
| 9211 | #define B_CP_REG_AC_NEXP_OFFS__M 0xFF | 9211 | #define B_CP_REG_AC_NEXP_OFFS__M 0xFF |
| 9212 | #define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 | 9212 | #define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 |
| 9213 | 9213 | ||
| 9214 | #define B_CP_REG_AC_AVER_POW__A 0x1410041 | 9214 | #define B_CP_REG_AC_AVER_POW__A 0x1410041 |
| 9215 | #define B_CP_REG_AC_AVER_POW__W 8 | 9215 | #define B_CP_REG_AC_AVER_POW__W 8 |
| 9216 | #define B_CP_REG_AC_AVER_POW__M 0xFF | 9216 | #define B_CP_REG_AC_AVER_POW__M 0xFF |
| 9217 | #define B_CP_REG_AC_AVER_POW_INIT 0x5F | 9217 | #define B_CP_REG_AC_AVER_POW_INIT 0x5F |
| 9218 | 9218 | ||
| 9219 | #define B_CP_REG_AC_MAX_POW__A 0x1410042 | 9219 | #define B_CP_REG_AC_MAX_POW__A 0x1410042 |
| 9220 | #define B_CP_REG_AC_MAX_POW__W 8 | 9220 | #define B_CP_REG_AC_MAX_POW__W 8 |
| 9221 | #define B_CP_REG_AC_MAX_POW__M 0xFF | 9221 | #define B_CP_REG_AC_MAX_POW__M 0xFF |
| 9222 | #define B_CP_REG_AC_MAX_POW_INIT 0x7A | 9222 | #define B_CP_REG_AC_MAX_POW_INIT 0x7A |
| 9223 | 9223 | ||
| 9224 | #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 | 9224 | #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 |
| 9225 | #define B_CP_REG_AC_WEIGHT_MAN__W 6 | 9225 | #define B_CP_REG_AC_WEIGHT_MAN__W 6 |
| 9226 | #define B_CP_REG_AC_WEIGHT_MAN__M 0x3F | 9226 | #define B_CP_REG_AC_WEIGHT_MAN__M 0x3F |
| 9227 | #define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 | 9227 | #define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 |
| 9228 | 9228 | ||
| 9229 | #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 | 9229 | #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 |
| 9230 | #define B_CP_REG_AC_WEIGHT_EXP__W 5 | 9230 | #define B_CP_REG_AC_WEIGHT_EXP__W 5 |
| 9231 | #define B_CP_REG_AC_WEIGHT_EXP__M 0x1F | 9231 | #define B_CP_REG_AC_WEIGHT_EXP__M 0x1F |
| 9232 | #define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 | 9232 | #define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 |
| 9233 | 9233 | ||
| 9234 | #define B_CP_REG_AC_GAIN_MAN__A 0x1410045 | 9234 | #define B_CP_REG_AC_GAIN_MAN__A 0x1410045 |
| 9235 | #define B_CP_REG_AC_GAIN_MAN__W 16 | 9235 | #define B_CP_REG_AC_GAIN_MAN__W 16 |
| 9236 | #define B_CP_REG_AC_GAIN_MAN__M 0xFFFF | 9236 | #define B_CP_REG_AC_GAIN_MAN__M 0xFFFF |
| 9237 | #define B_CP_REG_AC_GAIN_MAN_INIT 0x0 | 9237 | #define B_CP_REG_AC_GAIN_MAN_INIT 0x0 |
| 9238 | 9238 | ||
| 9239 | #define B_CP_REG_AC_GAIN_EXP__A 0x1410046 | 9239 | #define B_CP_REG_AC_GAIN_EXP__A 0x1410046 |
| 9240 | #define B_CP_REG_AC_GAIN_EXP__W 5 | 9240 | #define B_CP_REG_AC_GAIN_EXP__W 5 |
| 9241 | #define B_CP_REG_AC_GAIN_EXP__M 0x1F | 9241 | #define B_CP_REG_AC_GAIN_EXP__M 0x1F |
| 9242 | #define B_CP_REG_AC_GAIN_EXP_INIT 0x0 | 9242 | #define B_CP_REG_AC_GAIN_EXP_INIT 0x0 |
| 9243 | 9243 | ||
| 9244 | #define B_CP_REG_AC_AMP_MODE__A 0x1410047 | 9244 | #define B_CP_REG_AC_AMP_MODE__A 0x1410047 |
| 9245 | #define B_CP_REG_AC_AMP_MODE__W 2 | 9245 | #define B_CP_REG_AC_AMP_MODE__W 2 |
| 9246 | #define B_CP_REG_AC_AMP_MODE__M 0x3 | 9246 | #define B_CP_REG_AC_AMP_MODE__M 0x3 |
| 9247 | #define B_CP_REG_AC_AMP_MODE_NEW 0x0 | 9247 | #define B_CP_REG_AC_AMP_MODE_NEW 0x0 |
| 9248 | #define B_CP_REG_AC_AMP_MODE_OLD 0x1 | 9248 | #define B_CP_REG_AC_AMP_MODE_OLD 0x1 |
| 9249 | #define B_CP_REG_AC_AMP_MODE_FIXED 0x2 | 9249 | #define B_CP_REG_AC_AMP_MODE_FIXED 0x2 |
| 9250 | #define B_CP_REG_AC_AMP_MODE_INIT 0x2 | 9250 | #define B_CP_REG_AC_AMP_MODE_INIT 0x2 |
| 9251 | 9251 | ||
| 9252 | #define B_CP_REG_AC_AMP_FIX__A 0x1410048 | 9252 | #define B_CP_REG_AC_AMP_FIX__A 0x1410048 |
| 9253 | #define B_CP_REG_AC_AMP_FIX__W 14 | 9253 | #define B_CP_REG_AC_AMP_FIX__W 14 |
| 9254 | #define B_CP_REG_AC_AMP_FIX__M 0x3FFF | 9254 | #define B_CP_REG_AC_AMP_FIX__M 0x3FFF |
| 9255 | #define B_CP_REG_AC_AMP_FIX_INIT 0x1FF | 9255 | #define B_CP_REG_AC_AMP_FIX_INIT 0x1FF |
| 9256 | 9256 | ||
| 9257 | #define B_CP_REG_AC_AMP_READ__A 0x1410049 | 9257 | #define B_CP_REG_AC_AMP_READ__A 0x1410049 |
| 9258 | #define B_CP_REG_AC_AMP_READ__W 14 | 9258 | #define B_CP_REG_AC_AMP_READ__W 14 |
| 9259 | #define B_CP_REG_AC_AMP_READ__M 0x3FFF | 9259 | #define B_CP_REG_AC_AMP_READ__M 0x3FFF |
| 9260 | #define B_CP_REG_AC_AMP_READ_INIT 0x0 | 9260 | #define B_CP_REG_AC_AMP_READ_INIT 0x0 |
| 9261 | 9261 | ||
| 9262 | #define B_CP_REG_AC_ANG_MODE__A 0x141004A | 9262 | #define B_CP_REG_AC_ANG_MODE__A 0x141004A |
| 9263 | #define B_CP_REG_AC_ANG_MODE__W 2 | 9263 | #define B_CP_REG_AC_ANG_MODE__W 2 |
| 9264 | #define B_CP_REG_AC_ANG_MODE__M 0x3 | 9264 | #define B_CP_REG_AC_ANG_MODE__M 0x3 |
| 9265 | #define B_CP_REG_AC_ANG_MODE_NEW 0x0 | 9265 | #define B_CP_REG_AC_ANG_MODE_NEW 0x0 |
| 9266 | #define B_CP_REG_AC_ANG_MODE_OLD 0x1 | 9266 | #define B_CP_REG_AC_ANG_MODE_OLD 0x1 |
| 9267 | #define B_CP_REG_AC_ANG_MODE_NO_INT 0x2 | 9267 | #define B_CP_REG_AC_ANG_MODE_NO_INT 0x2 |
| 9268 | #define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 | 9268 | #define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 |
| 9269 | #define B_CP_REG_AC_ANG_MODE_INIT 0x3 | 9269 | #define B_CP_REG_AC_ANG_MODE_INIT 0x3 |
| 9270 | 9270 | ||
| 9271 | #define B_CP_REG_AC_ANG_OFFS__A 0x141004B | 9271 | #define B_CP_REG_AC_ANG_OFFS__A 0x141004B |
| 9272 | #define B_CP_REG_AC_ANG_OFFS__W 14 | 9272 | #define B_CP_REG_AC_ANG_OFFS__W 14 |
| 9273 | #define B_CP_REG_AC_ANG_OFFS__M 0x3FFF | 9273 | #define B_CP_REG_AC_ANG_OFFS__M 0x3FFF |
| 9274 | #define B_CP_REG_AC_ANG_OFFS_INIT 0x0 | 9274 | #define B_CP_REG_AC_ANG_OFFS_INIT 0x0 |
| 9275 | 9275 | ||
| 9276 | #define B_CP_REG_AC_ANG_READ__A 0x141004C | 9276 | #define B_CP_REG_AC_ANG_READ__A 0x141004C |
| 9277 | #define B_CP_REG_AC_ANG_READ__W 16 | 9277 | #define B_CP_REG_AC_ANG_READ__W 16 |
| 9278 | #define B_CP_REG_AC_ANG_READ__M 0xFFFF | 9278 | #define B_CP_REG_AC_ANG_READ__M 0xFFFF |
| 9279 | #define B_CP_REG_AC_ANG_READ_INIT 0x0 | 9279 | #define B_CP_REG_AC_ANG_READ_INIT 0x0 |
| 9280 | 9280 | ||
| 9281 | #define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 | 9281 | #define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 |
| 9282 | #define B_CP_REG_AC_ACCU_REAL0__W 8 | 9282 | #define B_CP_REG_AC_ACCU_REAL0__W 8 |
| 9283 | #define B_CP_REG_AC_ACCU_REAL0__M 0xFF | 9283 | #define B_CP_REG_AC_ACCU_REAL0__M 0xFF |
| 9284 | #define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 | 9284 | #define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 |
| 9285 | 9285 | ||
| 9286 | #define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 | 9286 | #define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 |
| 9287 | #define B_CP_REG_AC_ACCU_IMAG0__W 8 | 9287 | #define B_CP_REG_AC_ACCU_IMAG0__W 8 |
| 9288 | #define B_CP_REG_AC_ACCU_IMAG0__M 0xFF | 9288 | #define B_CP_REG_AC_ACCU_IMAG0__M 0xFF |
| 9289 | #define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 | 9289 | #define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 |
| 9290 | 9290 | ||
| 9291 | #define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 | 9291 | #define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 |
| 9292 | #define B_CP_REG_AC_ACCU_REAL1__W 8 | 9292 | #define B_CP_REG_AC_ACCU_REAL1__W 8 |
| 9293 | #define B_CP_REG_AC_ACCU_REAL1__M 0xFF | 9293 | #define B_CP_REG_AC_ACCU_REAL1__M 0xFF |
| 9294 | #define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 | 9294 | #define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 |
| 9295 | 9295 | ||
| 9296 | #define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 | 9296 | #define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 |
| 9297 | #define B_CP_REG_AC_ACCU_IMAG1__W 8 | 9297 | #define B_CP_REG_AC_ACCU_IMAG1__W 8 |
| 9298 | #define B_CP_REG_AC_ACCU_IMAG1__M 0xFF | 9298 | #define B_CP_REG_AC_ACCU_IMAG1__M 0xFF |
| 9299 | #define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 | 9299 | #define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 |
| 9300 | 9300 | ||
| 9301 | #define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 | 9301 | #define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 |
| 9302 | #define B_CP_REG_DL_MB_WR_ADDR__W 15 | 9302 | #define B_CP_REG_DL_MB_WR_ADDR__W 15 |
| 9303 | #define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF | 9303 | #define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF |
| 9304 | #define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 | 9304 | #define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 |
| 9305 | 9305 | ||
| 9306 | #define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 | 9306 | #define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 |
| 9307 | #define B_CP_REG_DL_MB_WR_CTR__W 5 | 9307 | #define B_CP_REG_DL_MB_WR_CTR__W 5 |
| 9308 | #define B_CP_REG_DL_MB_WR_CTR__M 0x1F | 9308 | #define B_CP_REG_DL_MB_WR_CTR__M 0x1F |
| 9309 | 9309 | ||
| 9310 | #define B_CP_REG_DL_MB_WR_CTR_WORD__B 2 | 9310 | #define B_CP_REG_DL_MB_WR_CTR_WORD__B 2 |
| 9311 | #define B_CP_REG_DL_MB_WR_CTR_WORD__W 3 | 9311 | #define B_CP_REG_DL_MB_WR_CTR_WORD__W 3 |
| 9312 | #define B_CP_REG_DL_MB_WR_CTR_WORD__M 0x1C | 9312 | #define B_CP_REG_DL_MB_WR_CTR_WORD__M 0x1C |
| 9313 | 9313 | ||
| 9314 | #define B_CP_REG_DL_MB_WR_CTR_OBS__B 1 | 9314 | #define B_CP_REG_DL_MB_WR_CTR_OBS__B 1 |
| 9315 | #define B_CP_REG_DL_MB_WR_CTR_OBS__W 1 | 9315 | #define B_CP_REG_DL_MB_WR_CTR_OBS__W 1 |
| 9316 | #define B_CP_REG_DL_MB_WR_CTR_OBS__M 0x2 | 9316 | #define B_CP_REG_DL_MB_WR_CTR_OBS__M 0x2 |
| 9317 | 9317 | ||
| 9318 | #define B_CP_REG_DL_MB_WR_CTR_CTR__B 0 | 9318 | #define B_CP_REG_DL_MB_WR_CTR_CTR__B 0 |
| 9319 | #define B_CP_REG_DL_MB_WR_CTR_CTR__W 1 | 9319 | #define B_CP_REG_DL_MB_WR_CTR_CTR__W 1 |
| 9320 | #define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 | 9320 | #define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 |
| 9321 | #define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 | 9321 | #define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 |
| 9322 | 9322 | ||
| 9323 | #define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 | 9323 | #define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 |
| 9324 | #define B_CP_REG_DL_MB_RD_ADDR__W 15 | 9324 | #define B_CP_REG_DL_MB_RD_ADDR__W 15 |
| 9325 | #define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF | 9325 | #define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF |
| 9326 | #define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 | 9326 | #define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 |
| 9327 | 9327 | ||
| 9328 | #define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 | 9328 | #define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 |
| 9329 | #define B_CP_REG_DL_MB_RD_CTR__W 11 | 9329 | #define B_CP_REG_DL_MB_RD_CTR__W 11 |
| 9330 | #define B_CP_REG_DL_MB_RD_CTR__M 0x7FF | 9330 | #define B_CP_REG_DL_MB_RD_CTR__M 0x7FF |
| 9331 | 9331 | ||
| 9332 | #define B_CP_REG_DL_MB_RD_CTR_TEST__B 10 | 9332 | #define B_CP_REG_DL_MB_RD_CTR_TEST__B 10 |
| 9333 | #define B_CP_REG_DL_MB_RD_CTR_TEST__W 1 | 9333 | #define B_CP_REG_DL_MB_RD_CTR_TEST__W 1 |
| 9334 | #define B_CP_REG_DL_MB_RD_CTR_TEST__M 0x400 | 9334 | #define B_CP_REG_DL_MB_RD_CTR_TEST__M 0x400 |
| 9335 | 9335 | ||
| 9336 | #define B_CP_REG_DL_MB_RD_CTR_OFFSET__B 8 | 9336 | #define B_CP_REG_DL_MB_RD_CTR_OFFSET__B 8 |
| 9337 | #define B_CP_REG_DL_MB_RD_CTR_OFFSET__W 2 | 9337 | #define B_CP_REG_DL_MB_RD_CTR_OFFSET__W 2 |
| 9338 | #define B_CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 | 9338 | #define B_CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 |
| 9339 | 9339 | ||
| 9340 | #define B_CP_REG_DL_MB_RD_CTR_VALID__B 5 | 9340 | #define B_CP_REG_DL_MB_RD_CTR_VALID__B 5 |
| 9341 | #define B_CP_REG_DL_MB_RD_CTR_VALID__W 3 | 9341 | #define B_CP_REG_DL_MB_RD_CTR_VALID__W 3 |
| 9342 | #define B_CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 | 9342 | #define B_CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 |
| 9343 | 9343 | ||
| 9344 | #define B_CP_REG_DL_MB_RD_CTR_WORD__B 2 | 9344 | #define B_CP_REG_DL_MB_RD_CTR_WORD__B 2 |
| 9345 | #define B_CP_REG_DL_MB_RD_CTR_WORD__W 3 | 9345 | #define B_CP_REG_DL_MB_RD_CTR_WORD__W 3 |
| 9346 | #define B_CP_REG_DL_MB_RD_CTR_WORD__M 0x1C | 9346 | #define B_CP_REG_DL_MB_RD_CTR_WORD__M 0x1C |
| 9347 | 9347 | ||
| 9348 | #define B_CP_REG_DL_MB_RD_CTR_OBS__B 1 | 9348 | #define B_CP_REG_DL_MB_RD_CTR_OBS__B 1 |
| 9349 | #define B_CP_REG_DL_MB_RD_CTR_OBS__W 1 | 9349 | #define B_CP_REG_DL_MB_RD_CTR_OBS__W 1 |
| 9350 | #define B_CP_REG_DL_MB_RD_CTR_OBS__M 0x2 | 9350 | #define B_CP_REG_DL_MB_RD_CTR_OBS__M 0x2 |
| 9351 | 9351 | ||
| 9352 | #define B_CP_REG_DL_MB_RD_CTR_CTR__B 0 | 9352 | #define B_CP_REG_DL_MB_RD_CTR_CTR__B 0 |
| 9353 | #define B_CP_REG_DL_MB_RD_CTR_CTR__W 1 | 9353 | #define B_CP_REG_DL_MB_RD_CTR_CTR__W 1 |
| 9354 | #define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 | 9354 | #define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 |
| 9355 | #define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 | 9355 | #define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 |
| 9356 | 9356 | ||
| 9357 | #define B_CP_BR_BUF_RAM__A 0x1420000 | 9357 | #define B_CP_BR_BUF_RAM__A 0x1420000 |
| 9358 | 9358 | ||
| 9359 | #define B_CP_BR_CPL_RAM__A 0x1430000 | 9359 | #define B_CP_BR_CPL_RAM__A 0x1430000 |
| 9360 | 9360 | ||
| 9361 | #define B_CP_PB_DL0_RAM__A 0x1440000 | 9361 | #define B_CP_PB_DL0_RAM__A 0x1440000 |
| 9362 | 9362 | ||
| 9363 | #define B_CP_PB_DL1_RAM__A 0x1450000 | 9363 | #define B_CP_PB_DL1_RAM__A 0x1450000 |
| 9364 | 9364 | ||
| 9365 | #define B_CP_PB_DL2_RAM__A 0x1460000 | 9365 | #define B_CP_PB_DL2_RAM__A 0x1460000 |
| 9366 | 9366 | ||
| 9367 | #define B_CE_SID 0xA | 9367 | #define B_CE_SID 0xA |
| 9368 | 9368 | ||
| 9369 | #define B_CE_COMM_EXEC__A 0x1800000 | 9369 | #define B_CE_COMM_EXEC__A 0x1800000 |
| 9370 | #define B_CE_COMM_EXEC__W 3 | 9370 | #define B_CE_COMM_EXEC__W 3 |
| 9371 | #define B_CE_COMM_EXEC__M 0x7 | 9371 | #define B_CE_COMM_EXEC__M 0x7 |
| 9372 | #define B_CE_COMM_EXEC_CTL__B 0 | 9372 | #define B_CE_COMM_EXEC_CTL__B 0 |
| 9373 | #define B_CE_COMM_EXEC_CTL__W 3 | 9373 | #define B_CE_COMM_EXEC_CTL__W 3 |
| 9374 | #define B_CE_COMM_EXEC_CTL__M 0x7 | 9374 | #define B_CE_COMM_EXEC_CTL__M 0x7 |
| 9375 | #define B_CE_COMM_EXEC_CTL_STOP 0x0 | 9375 | #define B_CE_COMM_EXEC_CTL_STOP 0x0 |
| 9376 | #define B_CE_COMM_EXEC_CTL_ACTIVE 0x1 | 9376 | #define B_CE_COMM_EXEC_CTL_ACTIVE 0x1 |
| 9377 | #define B_CE_COMM_EXEC_CTL_HOLD 0x2 | 9377 | #define B_CE_COMM_EXEC_CTL_HOLD 0x2 |
| 9378 | #define B_CE_COMM_EXEC_CTL_STEP 0x3 | 9378 | #define B_CE_COMM_EXEC_CTL_STEP 0x3 |
| 9379 | #define B_CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 9379 | #define B_CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 9380 | #define B_CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 9380 | #define B_CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 9381 | 9381 | ||
| 9382 | #define B_CE_COMM_STATE__A 0x1800001 | 9382 | #define B_CE_COMM_STATE__A 0x1800001 |
| 9383 | #define B_CE_COMM_STATE__W 16 | 9383 | #define B_CE_COMM_STATE__W 16 |
| 9384 | #define B_CE_COMM_STATE__M 0xFFFF | 9384 | #define B_CE_COMM_STATE__M 0xFFFF |
| 9385 | #define B_CE_COMM_MB__A 0x1800002 | 9385 | #define B_CE_COMM_MB__A 0x1800002 |
| 9386 | #define B_CE_COMM_MB__W 16 | 9386 | #define B_CE_COMM_MB__W 16 |
| 9387 | #define B_CE_COMM_MB__M 0xFFFF | 9387 | #define B_CE_COMM_MB__M 0xFFFF |
| 9388 | #define B_CE_COMM_SERVICE0__A 0x1800003 | 9388 | #define B_CE_COMM_SERVICE0__A 0x1800003 |
| 9389 | #define B_CE_COMM_SERVICE0__W 16 | 9389 | #define B_CE_COMM_SERVICE0__W 16 |
| 9390 | #define B_CE_COMM_SERVICE0__M 0xFFFF | 9390 | #define B_CE_COMM_SERVICE0__M 0xFFFF |
| 9391 | #define B_CE_COMM_SERVICE1__A 0x1800004 | 9391 | #define B_CE_COMM_SERVICE1__A 0x1800004 |
| 9392 | #define B_CE_COMM_SERVICE1__W 16 | 9392 | #define B_CE_COMM_SERVICE1__W 16 |
| 9393 | #define B_CE_COMM_SERVICE1__M 0xFFFF | 9393 | #define B_CE_COMM_SERVICE1__M 0xFFFF |
| 9394 | #define B_CE_COMM_INT_STA__A 0x1800007 | 9394 | #define B_CE_COMM_INT_STA__A 0x1800007 |
| 9395 | #define B_CE_COMM_INT_STA__W 16 | 9395 | #define B_CE_COMM_INT_STA__W 16 |
| 9396 | #define B_CE_COMM_INT_STA__M 0xFFFF | 9396 | #define B_CE_COMM_INT_STA__M 0xFFFF |
| 9397 | #define B_CE_COMM_INT_MSK__A 0x1800008 | 9397 | #define B_CE_COMM_INT_MSK__A 0x1800008 |
| 9398 | #define B_CE_COMM_INT_MSK__W 16 | 9398 | #define B_CE_COMM_INT_MSK__W 16 |
| 9399 | #define B_CE_COMM_INT_MSK__M 0xFFFF | 9399 | #define B_CE_COMM_INT_MSK__M 0xFFFF |
| 9400 | 9400 | ||
| 9401 | #define B_CE_REG_COMM_EXEC__A 0x1810000 | 9401 | #define B_CE_REG_COMM_EXEC__A 0x1810000 |
| 9402 | #define B_CE_REG_COMM_EXEC__W 3 | 9402 | #define B_CE_REG_COMM_EXEC__W 3 |
| 9403 | #define B_CE_REG_COMM_EXEC__M 0x7 | 9403 | #define B_CE_REG_COMM_EXEC__M 0x7 |
| 9404 | #define B_CE_REG_COMM_EXEC_CTL__B 0 | 9404 | #define B_CE_REG_COMM_EXEC_CTL__B 0 |
| 9405 | #define B_CE_REG_COMM_EXEC_CTL__W 3 | 9405 | #define B_CE_REG_COMM_EXEC_CTL__W 3 |
| 9406 | #define B_CE_REG_COMM_EXEC_CTL__M 0x7 | 9406 | #define B_CE_REG_COMM_EXEC_CTL__M 0x7 |
| 9407 | #define B_CE_REG_COMM_EXEC_CTL_STOP 0x0 | 9407 | #define B_CE_REG_COMM_EXEC_CTL_STOP 0x0 |
| 9408 | #define B_CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 9408 | #define B_CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 9409 | #define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 | 9409 | #define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 9410 | #define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 | 9410 | #define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 |
| 9411 | 9411 | ||
| 9412 | #define B_CE_REG_COMM_MB__A 0x1810002 | 9412 | #define B_CE_REG_COMM_MB__A 0x1810002 |
| 9413 | #define B_CE_REG_COMM_MB__W 4 | 9413 | #define B_CE_REG_COMM_MB__W 4 |
| 9414 | #define B_CE_REG_COMM_MB__M 0xF | 9414 | #define B_CE_REG_COMM_MB__M 0xF |
| 9415 | #define B_CE_REG_COMM_MB_CTR__B 0 | 9415 | #define B_CE_REG_COMM_MB_CTR__B 0 |
| 9416 | #define B_CE_REG_COMM_MB_CTR__W 1 | 9416 | #define B_CE_REG_COMM_MB_CTR__W 1 |
| 9417 | #define B_CE_REG_COMM_MB_CTR__M 0x1 | 9417 | #define B_CE_REG_COMM_MB_CTR__M 0x1 |
| 9418 | #define B_CE_REG_COMM_MB_CTR_OFF 0x0 | 9418 | #define B_CE_REG_COMM_MB_CTR_OFF 0x0 |
| 9419 | #define B_CE_REG_COMM_MB_CTR_ON 0x1 | 9419 | #define B_CE_REG_COMM_MB_CTR_ON 0x1 |
| 9420 | #define B_CE_REG_COMM_MB_OBS__B 1 | 9420 | #define B_CE_REG_COMM_MB_OBS__B 1 |
| 9421 | #define B_CE_REG_COMM_MB_OBS__W 1 | 9421 | #define B_CE_REG_COMM_MB_OBS__W 1 |
| 9422 | #define B_CE_REG_COMM_MB_OBS__M 0x2 | 9422 | #define B_CE_REG_COMM_MB_OBS__M 0x2 |
| 9423 | #define B_CE_REG_COMM_MB_OBS_OFF 0x0 | 9423 | #define B_CE_REG_COMM_MB_OBS_OFF 0x0 |
| 9424 | #define B_CE_REG_COMM_MB_OBS_ON 0x2 | 9424 | #define B_CE_REG_COMM_MB_OBS_ON 0x2 |
| 9425 | #define B_CE_REG_COMM_MB_OBS_SEL__B 2 | 9425 | #define B_CE_REG_COMM_MB_OBS_SEL__B 2 |
| 9426 | #define B_CE_REG_COMM_MB_OBS_SEL__W 2 | 9426 | #define B_CE_REG_COMM_MB_OBS_SEL__W 2 |
| 9427 | #define B_CE_REG_COMM_MB_OBS_SEL__M 0xC | 9427 | #define B_CE_REG_COMM_MB_OBS_SEL__M 0xC |
| 9428 | #define B_CE_REG_COMM_MB_OBS_SEL_FI 0x0 | 9428 | #define B_CE_REG_COMM_MB_OBS_SEL_FI 0x0 |
| 9429 | #define B_CE_REG_COMM_MB_OBS_SEL_TP 0x4 | 9429 | #define B_CE_REG_COMM_MB_OBS_SEL_TP 0x4 |
| 9430 | #define B_CE_REG_COMM_MB_OBS_SEL_TI 0x8 | 9430 | #define B_CE_REG_COMM_MB_OBS_SEL_TI 0x8 |
| 9431 | #define B_CE_REG_COMM_MB_OBS_SEL_FR 0x8 | 9431 | #define B_CE_REG_COMM_MB_OBS_SEL_FR 0x8 |
| 9432 | 9432 | ||
| 9433 | #define B_CE_REG_COMM_SERVICE0__A 0x1810003 | 9433 | #define B_CE_REG_COMM_SERVICE0__A 0x1810003 |
| 9434 | #define B_CE_REG_COMM_SERVICE0__W 10 | 9434 | #define B_CE_REG_COMM_SERVICE0__W 10 |
| 9435 | #define B_CE_REG_COMM_SERVICE0__M 0x3FF | 9435 | #define B_CE_REG_COMM_SERVICE0__M 0x3FF |
| 9436 | #define B_CE_REG_COMM_SERVICE0_FT__B 8 | 9436 | #define B_CE_REG_COMM_SERVICE0_FT__B 8 |
| 9437 | #define B_CE_REG_COMM_SERVICE0_FT__W 1 | 9437 | #define B_CE_REG_COMM_SERVICE0_FT__W 1 |
| 9438 | #define B_CE_REG_COMM_SERVICE0_FT__M 0x100 | 9438 | #define B_CE_REG_COMM_SERVICE0_FT__M 0x100 |
| 9439 | 9439 | ||
| 9440 | #define B_CE_REG_COMM_SERVICE1__A 0x1810004 | 9440 | #define B_CE_REG_COMM_SERVICE1__A 0x1810004 |
| 9441 | #define B_CE_REG_COMM_SERVICE1__W 11 | 9441 | #define B_CE_REG_COMM_SERVICE1__W 11 |
| 9442 | #define B_CE_REG_COMM_SERVICE1__M 0x7FF | 9442 | #define B_CE_REG_COMM_SERVICE1__M 0x7FF |
| 9443 | 9443 | ||
| 9444 | #define B_CE_REG_COMM_INT_STA__A 0x1810007 | 9444 | #define B_CE_REG_COMM_INT_STA__A 0x1810007 |
| 9445 | #define B_CE_REG_COMM_INT_STA__W 3 | 9445 | #define B_CE_REG_COMM_INT_STA__W 3 |
| 9446 | #define B_CE_REG_COMM_INT_STA__M 0x7 | 9446 | #define B_CE_REG_COMM_INT_STA__M 0x7 |
| 9447 | #define B_CE_REG_COMM_INT_STA_CE_PE__B 0 | 9447 | #define B_CE_REG_COMM_INT_STA_CE_PE__B 0 |
| 9448 | #define B_CE_REG_COMM_INT_STA_CE_PE__W 1 | 9448 | #define B_CE_REG_COMM_INT_STA_CE_PE__W 1 |
| 9449 | #define B_CE_REG_COMM_INT_STA_CE_PE__M 0x1 | 9449 | #define B_CE_REG_COMM_INT_STA_CE_PE__M 0x1 |
| 9450 | #define B_CE_REG_COMM_INT_STA_CE_IR__B 1 | 9450 | #define B_CE_REG_COMM_INT_STA_CE_IR__B 1 |
| 9451 | #define B_CE_REG_COMM_INT_STA_CE_IR__W 1 | 9451 | #define B_CE_REG_COMM_INT_STA_CE_IR__W 1 |
| 9452 | #define B_CE_REG_COMM_INT_STA_CE_IR__M 0x2 | 9452 | #define B_CE_REG_COMM_INT_STA_CE_IR__M 0x2 |
| 9453 | #define B_CE_REG_COMM_INT_STA_CE_FI__B 2 | 9453 | #define B_CE_REG_COMM_INT_STA_CE_FI__B 2 |
| 9454 | #define B_CE_REG_COMM_INT_STA_CE_FI__W 1 | 9454 | #define B_CE_REG_COMM_INT_STA_CE_FI__W 1 |
| 9455 | #define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 | 9455 | #define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 |
| 9456 | 9456 | ||
| 9457 | #define B_CE_REG_COMM_INT_MSK__A 0x1810008 | 9457 | #define B_CE_REG_COMM_INT_MSK__A 0x1810008 |
| 9458 | #define B_CE_REG_COMM_INT_MSK__W 3 | 9458 | #define B_CE_REG_COMM_INT_MSK__W 3 |
| 9459 | #define B_CE_REG_COMM_INT_MSK__M 0x7 | 9459 | #define B_CE_REG_COMM_INT_MSK__M 0x7 |
| 9460 | #define B_CE_REG_COMM_INT_MSK_CE_PE__B 0 | 9460 | #define B_CE_REG_COMM_INT_MSK_CE_PE__B 0 |
| 9461 | #define B_CE_REG_COMM_INT_MSK_CE_PE__W 1 | 9461 | #define B_CE_REG_COMM_INT_MSK_CE_PE__W 1 |
| 9462 | #define B_CE_REG_COMM_INT_MSK_CE_PE__M 0x1 | 9462 | #define B_CE_REG_COMM_INT_MSK_CE_PE__M 0x1 |
| 9463 | #define B_CE_REG_COMM_INT_MSK_CE_IR__B 1 | 9463 | #define B_CE_REG_COMM_INT_MSK_CE_IR__B 1 |
| 9464 | #define B_CE_REG_COMM_INT_MSK_CE_IR__W 1 | 9464 | #define B_CE_REG_COMM_INT_MSK_CE_IR__W 1 |
| 9465 | #define B_CE_REG_COMM_INT_MSK_CE_IR__M 0x2 | 9465 | #define B_CE_REG_COMM_INT_MSK_CE_IR__M 0x2 |
| 9466 | #define B_CE_REG_COMM_INT_MSK_CE_FI__B 2 | 9466 | #define B_CE_REG_COMM_INT_MSK_CE_FI__B 2 |
| 9467 | #define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 | 9467 | #define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 |
| 9468 | #define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 | 9468 | #define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 |
| 9469 | 9469 | ||
| 9470 | #define B_CE_REG_2K__A 0x1810010 | 9470 | #define B_CE_REG_2K__A 0x1810010 |
| 9471 | #define B_CE_REG_2K__W 1 | 9471 | #define B_CE_REG_2K__W 1 |
| 9472 | #define B_CE_REG_2K__M 0x1 | 9472 | #define B_CE_REG_2K__M 0x1 |
| 9473 | #define B_CE_REG_2K_INIT 0x0 | 9473 | #define B_CE_REG_2K_INIT 0x0 |
| 9474 | 9474 | ||
| 9475 | #define B_CE_REG_TAPSET__A 0x1810011 | 9475 | #define B_CE_REG_TAPSET__A 0x1810011 |
| 9476 | #define B_CE_REG_TAPSET__W 4 | 9476 | #define B_CE_REG_TAPSET__W 4 |
| 9477 | #define B_CE_REG_TAPSET__M 0xF | 9477 | #define B_CE_REG_TAPSET__M 0xF |
| 9478 | 9478 | ||
| 9479 | #define B_CE_REG_TAPSET_MOTION_INIT 0x0 | 9479 | #define B_CE_REG_TAPSET_MOTION_INIT 0x0 |
| 9480 | 9480 | ||
| 9481 | #define B_CE_REG_TAPSET_MOTION_NO 0x0 | 9481 | #define B_CE_REG_TAPSET_MOTION_NO 0x0 |
| 9482 | 9482 | ||
| 9483 | #define B_CE_REG_TAPSET_MOTION_LOW 0x1 | 9483 | #define B_CE_REG_TAPSET_MOTION_LOW 0x1 |
| 9484 | 9484 | ||
| 9485 | #define B_CE_REG_TAPSET_MOTION_HIGH 0x2 | 9485 | #define B_CE_REG_TAPSET_MOTION_HIGH 0x2 |
| 9486 | 9486 | ||
| 9487 | #define B_CE_REG_TAPSET_MOTION_HIGH2 0x4 | 9487 | #define B_CE_REG_TAPSET_MOTION_HIGH2 0x4 |
| 9488 | 9488 | ||
| 9489 | #define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 | 9489 | #define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 |
| 9490 | 9490 | ||
| 9491 | #define B_CE_REG_AVG_POW__A 0x1810012 | 9491 | #define B_CE_REG_AVG_POW__A 0x1810012 |
| 9492 | #define B_CE_REG_AVG_POW__W 8 | 9492 | #define B_CE_REG_AVG_POW__W 8 |
| 9493 | #define B_CE_REG_AVG_POW__M 0xFF | 9493 | #define B_CE_REG_AVG_POW__M 0xFF |
| 9494 | #define B_CE_REG_AVG_POW_INIT 0x0 | 9494 | #define B_CE_REG_AVG_POW_INIT 0x0 |
| 9495 | 9495 | ||
| 9496 | #define B_CE_REG_MAX_POW__A 0x1810013 | 9496 | #define B_CE_REG_MAX_POW__A 0x1810013 |
| 9497 | #define B_CE_REG_MAX_POW__W 8 | 9497 | #define B_CE_REG_MAX_POW__W 8 |
| 9498 | #define B_CE_REG_MAX_POW__M 0xFF | 9498 | #define B_CE_REG_MAX_POW__M 0xFF |
| 9499 | #define B_CE_REG_MAX_POW_INIT 0x0 | 9499 | #define B_CE_REG_MAX_POW_INIT 0x0 |
| 9500 | 9500 | ||
| 9501 | #define B_CE_REG_ATT__A 0x1810014 | 9501 | #define B_CE_REG_ATT__A 0x1810014 |
| 9502 | #define B_CE_REG_ATT__W 8 | 9502 | #define B_CE_REG_ATT__W 8 |
| 9503 | #define B_CE_REG_ATT__M 0xFF | 9503 | #define B_CE_REG_ATT__M 0xFF |
| 9504 | #define B_CE_REG_ATT_INIT 0x0 | 9504 | #define B_CE_REG_ATT_INIT 0x0 |
| 9505 | 9505 | ||
| 9506 | #define B_CE_REG_NRED__A 0x1810015 | 9506 | #define B_CE_REG_NRED__A 0x1810015 |
| 9507 | #define B_CE_REG_NRED__W 6 | 9507 | #define B_CE_REG_NRED__W 6 |
| 9508 | #define B_CE_REG_NRED__M 0x3F | 9508 | #define B_CE_REG_NRED__M 0x3F |
| 9509 | #define B_CE_REG_NRED_INIT 0x0 | 9509 | #define B_CE_REG_NRED_INIT 0x0 |
| 9510 | 9510 | ||
| 9511 | #define B_CE_REG_PU_SIGN__A 0x1810020 | 9511 | #define B_CE_REG_PU_SIGN__A 0x1810020 |
| 9512 | #define B_CE_REG_PU_SIGN__W 1 | 9512 | #define B_CE_REG_PU_SIGN__W 1 |
| 9513 | #define B_CE_REG_PU_SIGN__M 0x1 | 9513 | #define B_CE_REG_PU_SIGN__M 0x1 |
| 9514 | #define B_CE_REG_PU_SIGN_INIT 0x0 | 9514 | #define B_CE_REG_PU_SIGN_INIT 0x0 |
| 9515 | 9515 | ||
| 9516 | #define B_CE_REG_PU_MIX__A 0x1810021 | 9516 | #define B_CE_REG_PU_MIX__A 0x1810021 |
| 9517 | #define B_CE_REG_PU_MIX__W 1 | 9517 | #define B_CE_REG_PU_MIX__W 1 |
| 9518 | #define B_CE_REG_PU_MIX__M 0x1 | 9518 | #define B_CE_REG_PU_MIX__M 0x1 |
| 9519 | #define B_CE_REG_PU_MIX_INIT 0x0 | 9519 | #define B_CE_REG_PU_MIX_INIT 0x0 |
| 9520 | 9520 | ||
| 9521 | #define B_CE_REG_PB_PILOT_REQ__A 0x1810030 | 9521 | #define B_CE_REG_PB_PILOT_REQ__A 0x1810030 |
| 9522 | #define B_CE_REG_PB_PILOT_REQ__W 15 | 9522 | #define B_CE_REG_PB_PILOT_REQ__W 15 |
| 9523 | #define B_CE_REG_PB_PILOT_REQ__M 0x7FFF | 9523 | #define B_CE_REG_PB_PILOT_REQ__M 0x7FFF |
| 9524 | #define B_CE_REG_PB_PILOT_REQ_INIT 0x0 | 9524 | #define B_CE_REG_PB_PILOT_REQ_INIT 0x0 |
| 9525 | #define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 | 9525 | #define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 |
| 9526 | #define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 | 9526 | #define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 |
| 9527 | #define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 | 9527 | #define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 |
| 9528 | #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 | 9528 | #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 |
| 9529 | #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 | 9529 | #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 |
| 9530 | #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF | 9530 | #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF |
| 9531 | 9531 | ||
| 9532 | #define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 | 9532 | #define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 |
| 9533 | #define B_CE_REG_PB_PILOT_REQ_VALID__W 1 | 9533 | #define B_CE_REG_PB_PILOT_REQ_VALID__W 1 |
| 9534 | #define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 | 9534 | #define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 |
| 9535 | #define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 | 9535 | #define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 |
| 9536 | 9536 | ||
| 9537 | #define B_CE_REG_PB_FREEZE__A 0x1810032 | 9537 | #define B_CE_REG_PB_FREEZE__A 0x1810032 |
| 9538 | #define B_CE_REG_PB_FREEZE__W 1 | 9538 | #define B_CE_REG_PB_FREEZE__W 1 |
| 9539 | #define B_CE_REG_PB_FREEZE__M 0x1 | 9539 | #define B_CE_REG_PB_FREEZE__M 0x1 |
| 9540 | #define B_CE_REG_PB_FREEZE_INIT 0x0 | 9540 | #define B_CE_REG_PB_FREEZE_INIT 0x0 |
| 9541 | 9541 | ||
| 9542 | #define B_CE_REG_PB_PILOT_EXP__A 0x1810038 | 9542 | #define B_CE_REG_PB_PILOT_EXP__A 0x1810038 |
| 9543 | #define B_CE_REG_PB_PILOT_EXP__W 4 | 9543 | #define B_CE_REG_PB_PILOT_EXP__W 4 |
| 9544 | #define B_CE_REG_PB_PILOT_EXP__M 0xF | 9544 | #define B_CE_REG_PB_PILOT_EXP__M 0xF |
| 9545 | #define B_CE_REG_PB_PILOT_EXP_INIT 0x0 | 9545 | #define B_CE_REG_PB_PILOT_EXP_INIT 0x0 |
| 9546 | 9546 | ||
| 9547 | #define B_CE_REG_PB_PILOT_REAL__A 0x1810039 | 9547 | #define B_CE_REG_PB_PILOT_REAL__A 0x1810039 |
| 9548 | #define B_CE_REG_PB_PILOT_REAL__W 10 | 9548 | #define B_CE_REG_PB_PILOT_REAL__W 10 |
| 9549 | #define B_CE_REG_PB_PILOT_REAL__M 0x3FF | 9549 | #define B_CE_REG_PB_PILOT_REAL__M 0x3FF |
| 9550 | #define B_CE_REG_PB_PILOT_REAL_INIT 0x0 | 9550 | #define B_CE_REG_PB_PILOT_REAL_INIT 0x0 |
| 9551 | 9551 | ||
| 9552 | #define B_CE_REG_PB_PILOT_IMAG__A 0x181003A | 9552 | #define B_CE_REG_PB_PILOT_IMAG__A 0x181003A |
| 9553 | #define B_CE_REG_PB_PILOT_IMAG__W 10 | 9553 | #define B_CE_REG_PB_PILOT_IMAG__W 10 |
| 9554 | #define B_CE_REG_PB_PILOT_IMAG__M 0x3FF | 9554 | #define B_CE_REG_PB_PILOT_IMAG__M 0x3FF |
| 9555 | #define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 | 9555 | #define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 |
| 9556 | 9556 | ||
| 9557 | #define B_CE_REG_PB_SMBNR__A 0x181003B | 9557 | #define B_CE_REG_PB_SMBNR__A 0x181003B |
| 9558 | #define B_CE_REG_PB_SMBNR__W 5 | 9558 | #define B_CE_REG_PB_SMBNR__W 5 |
| 9559 | #define B_CE_REG_PB_SMBNR__M 0x1F | 9559 | #define B_CE_REG_PB_SMBNR__M 0x1F |
| 9560 | #define B_CE_REG_PB_SMBNR_INIT 0x0 | 9560 | #define B_CE_REG_PB_SMBNR_INIT 0x0 |
| 9561 | 9561 | ||
| 9562 | #define B_CE_REG_NE_PILOT_REQ__A 0x1810040 | 9562 | #define B_CE_REG_NE_PILOT_REQ__A 0x1810040 |
| 9563 | #define B_CE_REG_NE_PILOT_REQ__W 12 | 9563 | #define B_CE_REG_NE_PILOT_REQ__W 12 |
| 9564 | #define B_CE_REG_NE_PILOT_REQ__M 0xFFF | 9564 | #define B_CE_REG_NE_PILOT_REQ__M 0xFFF |
| 9565 | #define B_CE_REG_NE_PILOT_REQ_INIT 0x0 | 9565 | #define B_CE_REG_NE_PILOT_REQ_INIT 0x0 |
| 9566 | 9566 | ||
| 9567 | #define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 | 9567 | #define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 |
| 9568 | #define B_CE_REG_NE_PILOT_REQ_VALID__W 2 | 9568 | #define B_CE_REG_NE_PILOT_REQ_VALID__W 2 |
| 9569 | #define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 | 9569 | #define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 |
| 9570 | #define B_CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 | 9570 | #define B_CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 |
| 9571 | #define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 | 9571 | #define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 |
| 9572 | #define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 | 9572 | #define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 |
| 9573 | #define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 | 9573 | #define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 |
| 9574 | #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 | 9574 | #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 |
| 9575 | #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 | 9575 | #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 |
| 9576 | #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 | 9576 | #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 |
| 9577 | 9577 | ||
| 9578 | #define B_CE_REG_NE_PILOT_DATA__A 0x1810042 | 9578 | #define B_CE_REG_NE_PILOT_DATA__A 0x1810042 |
| 9579 | #define B_CE_REG_NE_PILOT_DATA__W 10 | 9579 | #define B_CE_REG_NE_PILOT_DATA__W 10 |
| 9580 | #define B_CE_REG_NE_PILOT_DATA__M 0x3FF | 9580 | #define B_CE_REG_NE_PILOT_DATA__M 0x3FF |
| 9581 | #define B_CE_REG_NE_PILOT_DATA_INIT 0x0 | 9581 | #define B_CE_REG_NE_PILOT_DATA_INIT 0x0 |
| 9582 | 9582 | ||
| 9583 | #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 | 9583 | #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 |
| 9584 | #define B_CE_REG_NE_ERR_SELECT__W 5 | 9584 | #define B_CE_REG_NE_ERR_SELECT__W 5 |
| 9585 | #define B_CE_REG_NE_ERR_SELECT__M 0x1F | 9585 | #define B_CE_REG_NE_ERR_SELECT__M 0x1F |
| 9586 | #define B_CE_REG_NE_ERR_SELECT_INIT 0x7 | 9586 | #define B_CE_REG_NE_ERR_SELECT_INIT 0x7 |
| 9587 | 9587 | ||
| 9588 | #define B_CE_REG_NE_ERR_SELECT_MAX_UPD__B 4 | 9588 | #define B_CE_REG_NE_ERR_SELECT_MAX_UPD__B 4 |
| 9589 | #define B_CE_REG_NE_ERR_SELECT_MAX_UPD__W 1 | 9589 | #define B_CE_REG_NE_ERR_SELECT_MAX_UPD__W 1 |
| 9590 | #define B_CE_REG_NE_ERR_SELECT_MAX_UPD__M 0x10 | 9590 | #define B_CE_REG_NE_ERR_SELECT_MAX_UPD__M 0x10 |
| 9591 | 9591 | ||
| 9592 | #define B_CE_REG_NE_ERR_SELECT_MED_MATCH__B 3 | 9592 | #define B_CE_REG_NE_ERR_SELECT_MED_MATCH__B 3 |
| 9593 | #define B_CE_REG_NE_ERR_SELECT_MED_MATCH__W 1 | 9593 | #define B_CE_REG_NE_ERR_SELECT_MED_MATCH__W 1 |
| 9594 | #define B_CE_REG_NE_ERR_SELECT_MED_MATCH__M 0x8 | 9594 | #define B_CE_REG_NE_ERR_SELECT_MED_MATCH__M 0x8 |
| 9595 | 9595 | ||
| 9596 | #define B_CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 | 9596 | #define B_CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 |
| 9597 | #define B_CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 | 9597 | #define B_CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 |
| 9598 | #define B_CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 | 9598 | #define B_CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 |
| 9599 | 9599 | ||
| 9600 | #define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 | 9600 | #define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 |
| 9601 | #define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 | 9601 | #define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 |
| 9602 | #define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 | 9602 | #define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 |
| 9603 | 9603 | ||
| 9604 | #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 | 9604 | #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 |
| 9605 | #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 | 9605 | #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 |
| 9606 | #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 | 9606 | #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 |
| 9607 | 9607 | ||
| 9608 | #define B_CE_REG_NE_TD_CAL__A 0x1810044 | 9608 | #define B_CE_REG_NE_TD_CAL__A 0x1810044 |
| 9609 | #define B_CE_REG_NE_TD_CAL__W 9 | 9609 | #define B_CE_REG_NE_TD_CAL__W 9 |
| 9610 | #define B_CE_REG_NE_TD_CAL__M 0x1FF | 9610 | #define B_CE_REG_NE_TD_CAL__M 0x1FF |
| 9611 | #define B_CE_REG_NE_TD_CAL_INIT 0x1E8 | 9611 | #define B_CE_REG_NE_TD_CAL_INIT 0x1E8 |
| 9612 | 9612 | ||
| 9613 | #define B_CE_REG_NE_FD_CAL__A 0x1810045 | 9613 | #define B_CE_REG_NE_FD_CAL__A 0x1810045 |
| 9614 | #define B_CE_REG_NE_FD_CAL__W 9 | 9614 | #define B_CE_REG_NE_FD_CAL__W 9 |
| 9615 | #define B_CE_REG_NE_FD_CAL__M 0x1FF | 9615 | #define B_CE_REG_NE_FD_CAL__M 0x1FF |
| 9616 | #define B_CE_REG_NE_FD_CAL_INIT 0x1D9 | 9616 | #define B_CE_REG_NE_FD_CAL_INIT 0x1D9 |
| 9617 | 9617 | ||
| 9618 | #define B_CE_REG_NE_MIXAVG__A 0x1810046 | 9618 | #define B_CE_REG_NE_MIXAVG__A 0x1810046 |
| 9619 | #define B_CE_REG_NE_MIXAVG__W 3 | 9619 | #define B_CE_REG_NE_MIXAVG__W 3 |
| 9620 | #define B_CE_REG_NE_MIXAVG__M 0x7 | 9620 | #define B_CE_REG_NE_MIXAVG__M 0x7 |
| 9621 | #define B_CE_REG_NE_MIXAVG_INIT 0x6 | 9621 | #define B_CE_REG_NE_MIXAVG_INIT 0x6 |
| 9622 | 9622 | ||
| 9623 | #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 | 9623 | #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 |
| 9624 | #define B_CE_REG_NE_NUPD_OFS__W 4 | 9624 | #define B_CE_REG_NE_NUPD_OFS__W 4 |
| 9625 | #define B_CE_REG_NE_NUPD_OFS__M 0xF | 9625 | #define B_CE_REG_NE_NUPD_OFS__M 0xF |
| 9626 | #define B_CE_REG_NE_NUPD_OFS_INIT 0x4 | 9626 | #define B_CE_REG_NE_NUPD_OFS_INIT 0x4 |
| 9627 | 9627 | ||
| 9628 | #define B_CE_REG_NE_TD_POW__A 0x1810048 | 9628 | #define B_CE_REG_NE_TD_POW__A 0x1810048 |
| 9629 | #define B_CE_REG_NE_TD_POW__W 15 | 9629 | #define B_CE_REG_NE_TD_POW__W 15 |
| 9630 | #define B_CE_REG_NE_TD_POW__M 0x7FFF | 9630 | #define B_CE_REG_NE_TD_POW__M 0x7FFF |
| 9631 | #define B_CE_REG_NE_TD_POW_INIT 0x0 | 9631 | #define B_CE_REG_NE_TD_POW_INIT 0x0 |
| 9632 | 9632 | ||
| 9633 | #define B_CE_REG_NE_TD_POW_EXPONENT__B 10 | 9633 | #define B_CE_REG_NE_TD_POW_EXPONENT__B 10 |
| 9634 | #define B_CE_REG_NE_TD_POW_EXPONENT__W 5 | 9634 | #define B_CE_REG_NE_TD_POW_EXPONENT__W 5 |
| 9635 | #define B_CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 | 9635 | #define B_CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 |
| 9636 | 9636 | ||
| 9637 | #define B_CE_REG_NE_TD_POW_MANTISSA__B 0 | 9637 | #define B_CE_REG_NE_TD_POW_MANTISSA__B 0 |
| 9638 | #define B_CE_REG_NE_TD_POW_MANTISSA__W 10 | 9638 | #define B_CE_REG_NE_TD_POW_MANTISSA__W 10 |
| 9639 | #define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF | 9639 | #define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF |
| 9640 | 9640 | ||
| 9641 | #define B_CE_REG_NE_FD_POW__A 0x1810049 | 9641 | #define B_CE_REG_NE_FD_POW__A 0x1810049 |
| 9642 | #define B_CE_REG_NE_FD_POW__W 15 | 9642 | #define B_CE_REG_NE_FD_POW__W 15 |
| 9643 | #define B_CE_REG_NE_FD_POW__M 0x7FFF | 9643 | #define B_CE_REG_NE_FD_POW__M 0x7FFF |
| 9644 | #define B_CE_REG_NE_FD_POW_INIT 0x0 | 9644 | #define B_CE_REG_NE_FD_POW_INIT 0x0 |
| 9645 | 9645 | ||
| 9646 | #define B_CE_REG_NE_FD_POW_EXPONENT__B 10 | 9646 | #define B_CE_REG_NE_FD_POW_EXPONENT__B 10 |
| 9647 | #define B_CE_REG_NE_FD_POW_EXPONENT__W 5 | 9647 | #define B_CE_REG_NE_FD_POW_EXPONENT__W 5 |
| 9648 | #define B_CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 | 9648 | #define B_CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 |
| 9649 | 9649 | ||
| 9650 | #define B_CE_REG_NE_FD_POW_MANTISSA__B 0 | 9650 | #define B_CE_REG_NE_FD_POW_MANTISSA__B 0 |
| 9651 | #define B_CE_REG_NE_FD_POW_MANTISSA__W 10 | 9651 | #define B_CE_REG_NE_FD_POW_MANTISSA__W 10 |
| 9652 | #define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF | 9652 | #define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF |
| 9653 | 9653 | ||
| 9654 | #define B_CE_REG_NE_NEXP_AVG__A 0x181004A | 9654 | #define B_CE_REG_NE_NEXP_AVG__A 0x181004A |
| 9655 | #define B_CE_REG_NE_NEXP_AVG__W 8 | 9655 | #define B_CE_REG_NE_NEXP_AVG__W 8 |
| 9656 | #define B_CE_REG_NE_NEXP_AVG__M 0xFF | 9656 | #define B_CE_REG_NE_NEXP_AVG__M 0xFF |
| 9657 | #define B_CE_REG_NE_NEXP_AVG_INIT 0x0 | 9657 | #define B_CE_REG_NE_NEXP_AVG_INIT 0x0 |
| 9658 | 9658 | ||
| 9659 | #define B_CE_REG_NE_OFFSET__A 0x181004B | 9659 | #define B_CE_REG_NE_OFFSET__A 0x181004B |
| 9660 | #define B_CE_REG_NE_OFFSET__W 9 | 9660 | #define B_CE_REG_NE_OFFSET__W 9 |
| 9661 | #define B_CE_REG_NE_OFFSET__M 0x1FF | 9661 | #define B_CE_REG_NE_OFFSET__M 0x1FF |
| 9662 | #define B_CE_REG_NE_OFFSET_INIT 0x0 | 9662 | #define B_CE_REG_NE_OFFSET_INIT 0x0 |
| 9663 | 9663 | ||
| 9664 | #define B_CE_REG_NE_NUPD_TRH__A 0x181004C | 9664 | #define B_CE_REG_NE_NUPD_TRH__A 0x181004C |
| 9665 | #define B_CE_REG_NE_NUPD_TRH__W 5 | 9665 | #define B_CE_REG_NE_NUPD_TRH__W 5 |
| 9666 | #define B_CE_REG_NE_NUPD_TRH__M 0x1F | 9666 | #define B_CE_REG_NE_NUPD_TRH__M 0x1F |
| 9667 | #define B_CE_REG_NE_NUPD_TRH_INIT 0x14 | 9667 | #define B_CE_REG_NE_NUPD_TRH_INIT 0x14 |
| 9668 | 9668 | ||
| 9669 | #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 | 9669 | #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 |
| 9670 | #define B_CE_REG_PE_NEXP_OFFS__W 8 | 9670 | #define B_CE_REG_PE_NEXP_OFFS__W 8 |
| 9671 | #define B_CE_REG_PE_NEXP_OFFS__M 0xFF | 9671 | #define B_CE_REG_PE_NEXP_OFFS__M 0xFF |
| 9672 | #define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 | 9672 | #define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 |
| 9673 | 9673 | ||
| 9674 | #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 | 9674 | #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 |
| 9675 | #define B_CE_REG_PE_TIMESHIFT__W 14 | 9675 | #define B_CE_REG_PE_TIMESHIFT__W 14 |
| 9676 | #define B_CE_REG_PE_TIMESHIFT__M 0x3FFF | 9676 | #define B_CE_REG_PE_TIMESHIFT__M 0x3FFF |
| 9677 | #define B_CE_REG_PE_TIMESHIFT_INIT 0x0 | 9677 | #define B_CE_REG_PE_TIMESHIFT_INIT 0x0 |
| 9678 | 9678 | ||
| 9679 | #define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 | 9679 | #define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 |
| 9680 | #define B_CE_REG_PE_DIF_REAL_L__W 16 | 9680 | #define B_CE_REG_PE_DIF_REAL_L__W 16 |
| 9681 | #define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF | 9681 | #define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF |
| 9682 | #define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 | 9682 | #define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 |
| 9683 | 9683 | ||
| 9684 | #define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 | 9684 | #define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 |
| 9685 | #define B_CE_REG_PE_DIF_IMAG_L__W 16 | 9685 | #define B_CE_REG_PE_DIF_IMAG_L__W 16 |
| 9686 | #define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF | 9686 | #define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF |
| 9687 | #define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 | 9687 | #define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 |
| 9688 | 9688 | ||
| 9689 | #define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 | 9689 | #define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 |
| 9690 | #define B_CE_REG_PE_DIF_REAL_R__W 16 | 9690 | #define B_CE_REG_PE_DIF_REAL_R__W 16 |
| 9691 | #define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF | 9691 | #define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF |
| 9692 | #define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 | 9692 | #define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 |
| 9693 | 9693 | ||
| 9694 | #define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 | 9694 | #define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 |
| 9695 | #define B_CE_REG_PE_DIF_IMAG_R__W 16 | 9695 | #define B_CE_REG_PE_DIF_IMAG_R__W 16 |
| 9696 | #define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF | 9696 | #define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF |
| 9697 | #define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 | 9697 | #define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 |
| 9698 | 9698 | ||
| 9699 | #define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 | 9699 | #define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 |
| 9700 | #define B_CE_REG_PE_ABS_REAL_L__W 16 | 9700 | #define B_CE_REG_PE_ABS_REAL_L__W 16 |
| 9701 | #define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF | 9701 | #define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF |
| 9702 | #define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 | 9702 | #define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 |
| 9703 | 9703 | ||
| 9704 | #define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 | 9704 | #define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 |
| 9705 | #define B_CE_REG_PE_ABS_IMAG_L__W 16 | 9705 | #define B_CE_REG_PE_ABS_IMAG_L__W 16 |
| 9706 | #define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF | 9706 | #define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF |
| 9707 | #define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 | 9707 | #define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 |
| 9708 | 9708 | ||
| 9709 | #define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 | 9709 | #define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 |
| 9710 | #define B_CE_REG_PE_ABS_REAL_R__W 16 | 9710 | #define B_CE_REG_PE_ABS_REAL_R__W 16 |
| 9711 | #define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF | 9711 | #define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF |
| 9712 | #define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 | 9712 | #define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 |
| 9713 | 9713 | ||
| 9714 | #define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 | 9714 | #define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 |
| 9715 | #define B_CE_REG_PE_ABS_IMAG_R__W 16 | 9715 | #define B_CE_REG_PE_ABS_IMAG_R__W 16 |
| 9716 | #define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF | 9716 | #define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF |
| 9717 | #define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 | 9717 | #define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 |
| 9718 | 9718 | ||
| 9719 | #define B_CE_REG_PE_ABS_EXP_L__A 0x181005A | 9719 | #define B_CE_REG_PE_ABS_EXP_L__A 0x181005A |
| 9720 | #define B_CE_REG_PE_ABS_EXP_L__W 5 | 9720 | #define B_CE_REG_PE_ABS_EXP_L__W 5 |
| 9721 | #define B_CE_REG_PE_ABS_EXP_L__M 0x1F | 9721 | #define B_CE_REG_PE_ABS_EXP_L__M 0x1F |
| 9722 | #define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 | 9722 | #define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 |
| 9723 | 9723 | ||
| 9724 | #define B_CE_REG_PE_ABS_EXP_R__A 0x181005B | 9724 | #define B_CE_REG_PE_ABS_EXP_R__A 0x181005B |
| 9725 | #define B_CE_REG_PE_ABS_EXP_R__W 5 | 9725 | #define B_CE_REG_PE_ABS_EXP_R__W 5 |
| 9726 | #define B_CE_REG_PE_ABS_EXP_R__M 0x1F | 9726 | #define B_CE_REG_PE_ABS_EXP_R__M 0x1F |
| 9727 | #define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 | 9727 | #define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 |
| 9728 | 9728 | ||
| 9729 | #define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 | 9729 | #define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 |
| 9730 | #define B_CE_REG_TP_UPDATE_MODE__W 1 | 9730 | #define B_CE_REG_TP_UPDATE_MODE__W 1 |
| 9731 | #define B_CE_REG_TP_UPDATE_MODE__M 0x1 | 9731 | #define B_CE_REG_TP_UPDATE_MODE__M 0x1 |
| 9732 | #define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 | 9732 | #define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 |
| 9733 | 9733 | ||
| 9734 | #define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 | 9734 | #define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 |
| 9735 | #define B_CE_REG_TP_LMS_TAP_ON__W 1 | 9735 | #define B_CE_REG_TP_LMS_TAP_ON__W 1 |
| 9736 | #define B_CE_REG_TP_LMS_TAP_ON__M 0x1 | 9736 | #define B_CE_REG_TP_LMS_TAP_ON__M 0x1 |
| 9737 | 9737 | ||
| 9738 | #define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 | 9738 | #define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 |
| 9739 | #define B_CE_REG_TP_A0_TAP_NEW__W 10 | 9739 | #define B_CE_REG_TP_A0_TAP_NEW__W 10 |
| 9740 | #define B_CE_REG_TP_A0_TAP_NEW__M 0x3FF | 9740 | #define B_CE_REG_TP_A0_TAP_NEW__M 0x3FF |
| 9741 | 9741 | ||
| 9742 | #define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 | 9742 | #define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 |
| 9743 | #define B_CE_REG_TP_A0_TAP_NEW_VALID__W 1 | 9743 | #define B_CE_REG_TP_A0_TAP_NEW_VALID__W 1 |
| 9744 | #define B_CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 | 9744 | #define B_CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 |
| 9745 | 9745 | ||
| 9746 | #define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 | 9746 | #define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 |
| 9747 | #define B_CE_REG_TP_A0_MU_LMS_STEP__W 5 | 9747 | #define B_CE_REG_TP_A0_MU_LMS_STEP__W 5 |
| 9748 | #define B_CE_REG_TP_A0_MU_LMS_STEP__M 0x1F | 9748 | #define B_CE_REG_TP_A0_MU_LMS_STEP__M 0x1F |
| 9749 | 9749 | ||
| 9750 | #define B_CE_REG_TP_A0_TAP_CURR__A 0x1810067 | 9750 | #define B_CE_REG_TP_A0_TAP_CURR__A 0x1810067 |
| 9751 | #define B_CE_REG_TP_A0_TAP_CURR__W 10 | 9751 | #define B_CE_REG_TP_A0_TAP_CURR__W 10 |
| 9752 | #define B_CE_REG_TP_A0_TAP_CURR__M 0x3FF | 9752 | #define B_CE_REG_TP_A0_TAP_CURR__M 0x3FF |
| 9753 | 9753 | ||
| 9754 | #define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 | 9754 | #define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 |
| 9755 | #define B_CE_REG_TP_A1_TAP_NEW__W 10 | 9755 | #define B_CE_REG_TP_A1_TAP_NEW__W 10 |
| 9756 | #define B_CE_REG_TP_A1_TAP_NEW__M 0x3FF | 9756 | #define B_CE_REG_TP_A1_TAP_NEW__M 0x3FF |
| 9757 | 9757 | ||
| 9758 | #define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 | 9758 | #define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 |
| 9759 | #define B_CE_REG_TP_A1_TAP_NEW_VALID__W 1 | 9759 | #define B_CE_REG_TP_A1_TAP_NEW_VALID__W 1 |
| 9760 | #define B_CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 | 9760 | #define B_CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 |
| 9761 | 9761 | ||
| 9762 | #define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A | 9762 | #define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A |
| 9763 | #define B_CE_REG_TP_A1_MU_LMS_STEP__W 5 | 9763 | #define B_CE_REG_TP_A1_MU_LMS_STEP__W 5 |
| 9764 | #define B_CE_REG_TP_A1_MU_LMS_STEP__M 0x1F | 9764 | #define B_CE_REG_TP_A1_MU_LMS_STEP__M 0x1F |
| 9765 | 9765 | ||
| 9766 | #define B_CE_REG_TP_A1_TAP_CURR__A 0x181006B | 9766 | #define B_CE_REG_TP_A1_TAP_CURR__A 0x181006B |
| 9767 | #define B_CE_REG_TP_A1_TAP_CURR__W 10 | 9767 | #define B_CE_REG_TP_A1_TAP_CURR__W 10 |
| 9768 | #define B_CE_REG_TP_A1_TAP_CURR__M 0x3FF | 9768 | #define B_CE_REG_TP_A1_TAP_CURR__M 0x3FF |
| 9769 | 9769 | ||
| 9770 | #define B_CE_REG_TP_DOPP_ENERGY__A 0x181006C | 9770 | #define B_CE_REG_TP_DOPP_ENERGY__A 0x181006C |
| 9771 | #define B_CE_REG_TP_DOPP_ENERGY__W 15 | 9771 | #define B_CE_REG_TP_DOPP_ENERGY__W 15 |
| 9772 | #define B_CE_REG_TP_DOPP_ENERGY__M 0x7FFF | 9772 | #define B_CE_REG_TP_DOPP_ENERGY__M 0x7FFF |
| 9773 | #define B_CE_REG_TP_DOPP_ENERGY_INIT 0x0 | 9773 | #define B_CE_REG_TP_DOPP_ENERGY_INIT 0x0 |
| 9774 | 9774 | ||
| 9775 | #define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 | 9775 | #define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 |
| 9776 | #define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 | 9776 | #define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 |
| 9777 | #define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 | 9777 | #define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 |
| 9778 | 9778 | ||
| 9779 | #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 | 9779 | #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 |
| 9780 | #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 | 9780 | #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 |
| 9781 | #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF | 9781 | #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF |
| 9782 | 9782 | ||
| 9783 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D | 9783 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D |
| 9784 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 | 9784 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 |
| 9785 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF | 9785 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF |
| 9786 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 | 9786 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 |
| 9787 | 9787 | ||
| 9788 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 | 9788 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 |
| 9789 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 | 9789 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 |
| 9790 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 | 9790 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 |
| 9791 | 9791 | ||
| 9792 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 | 9792 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 |
| 9793 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 | 9793 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 |
| 9794 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF | 9794 | #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF |
| 9795 | 9795 | ||
| 9796 | #define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E | 9796 | #define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E |
| 9797 | #define B_CE_REG_TP_A0_TAP_ENERGY__W 15 | 9797 | #define B_CE_REG_TP_A0_TAP_ENERGY__W 15 |
| 9798 | #define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF | 9798 | #define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF |
| 9799 | #define B_CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 | 9799 | #define B_CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 |
| 9800 | 9800 | ||
| 9801 | #define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 | 9801 | #define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 |
| 9802 | #define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 | 9802 | #define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 |
| 9803 | #define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 | 9803 | #define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 |
| 9804 | 9804 | ||
| 9805 | #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 | 9805 | #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 |
| 9806 | #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 | 9806 | #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 |
| 9807 | #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF | 9807 | #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF |
| 9808 | 9808 | ||
| 9809 | #define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F | 9809 | #define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F |
| 9810 | #define B_CE_REG_TP_A1_TAP_ENERGY__W 15 | 9810 | #define B_CE_REG_TP_A1_TAP_ENERGY__W 15 |
| 9811 | #define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF | 9811 | #define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF |
| 9812 | #define B_CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 | 9812 | #define B_CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 |
| 9813 | 9813 | ||
| 9814 | #define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 | 9814 | #define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 |
| 9815 | #define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 | 9815 | #define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 |
| 9816 | #define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 | 9816 | #define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 |
| 9817 | 9817 | ||
| 9818 | #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 | 9818 | #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 |
| 9819 | #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 | 9819 | #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 |
| 9820 | #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF | 9820 | #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF |
| 9821 | 9821 | ||
| 9822 | #define B_CE_REG_TI_SYM_CNT__A 0x1810072 | 9822 | #define B_CE_REG_TI_SYM_CNT__A 0x1810072 |
| 9823 | #define B_CE_REG_TI_SYM_CNT__W 6 | 9823 | #define B_CE_REG_TI_SYM_CNT__W 6 |
| 9824 | #define B_CE_REG_TI_SYM_CNT__M 0x3F | 9824 | #define B_CE_REG_TI_SYM_CNT__M 0x3F |
| 9825 | #define B_CE_REG_TI_SYM_CNT_INIT 0x0 | 9825 | #define B_CE_REG_TI_SYM_CNT_INIT 0x0 |
| 9826 | 9826 | ||
| 9827 | #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 | 9827 | #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 |
| 9828 | #define B_CE_REG_TI_PHN_ENABLE__W 1 | 9828 | #define B_CE_REG_TI_PHN_ENABLE__W 1 |
| 9829 | #define B_CE_REG_TI_PHN_ENABLE__M 0x1 | 9829 | #define B_CE_REG_TI_PHN_ENABLE__M 0x1 |
| 9830 | #define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 | 9830 | #define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 |
| 9831 | 9831 | ||
| 9832 | #define B_CE_REG_TI_SHIFT__A 0x1810074 | 9832 | #define B_CE_REG_TI_SHIFT__A 0x1810074 |
| 9833 | #define B_CE_REG_TI_SHIFT__W 2 | 9833 | #define B_CE_REG_TI_SHIFT__W 2 |
| 9834 | #define B_CE_REG_TI_SHIFT__M 0x3 | 9834 | #define B_CE_REG_TI_SHIFT__M 0x3 |
| 9835 | #define B_CE_REG_TI_SHIFT_INIT 0x0 | 9835 | #define B_CE_REG_TI_SHIFT_INIT 0x0 |
| 9836 | 9836 | ||
| 9837 | #define B_CE_REG_TI_SLOW__A 0x1810075 | 9837 | #define B_CE_REG_TI_SLOW__A 0x1810075 |
| 9838 | #define B_CE_REG_TI_SLOW__W 1 | 9838 | #define B_CE_REG_TI_SLOW__W 1 |
| 9839 | #define B_CE_REG_TI_SLOW__M 0x1 | 9839 | #define B_CE_REG_TI_SLOW__M 0x1 |
| 9840 | #define B_CE_REG_TI_SLOW_INIT 0x0 | 9840 | #define B_CE_REG_TI_SLOW_INIT 0x0 |
| 9841 | 9841 | ||
| 9842 | #define B_CE_REG_TI_MGAIN__A 0x1810076 | 9842 | #define B_CE_REG_TI_MGAIN__A 0x1810076 |
| 9843 | #define B_CE_REG_TI_MGAIN__W 8 | 9843 | #define B_CE_REG_TI_MGAIN__W 8 |
| 9844 | #define B_CE_REG_TI_MGAIN__M 0xFF | 9844 | #define B_CE_REG_TI_MGAIN__M 0xFF |
| 9845 | #define B_CE_REG_TI_MGAIN_INIT 0x0 | 9845 | #define B_CE_REG_TI_MGAIN_INIT 0x0 |
| 9846 | 9846 | ||
| 9847 | #define B_CE_REG_TI_ACCU1__A 0x1810077 | 9847 | #define B_CE_REG_TI_ACCU1__A 0x1810077 |
| 9848 | #define B_CE_REG_TI_ACCU1__W 8 | 9848 | #define B_CE_REG_TI_ACCU1__W 8 |
| 9849 | #define B_CE_REG_TI_ACCU1__M 0xFF | 9849 | #define B_CE_REG_TI_ACCU1__M 0xFF |
| 9850 | #define B_CE_REG_TI_ACCU1_INIT 0x0 | 9850 | #define B_CE_REG_TI_ACCU1_INIT 0x0 |
| 9851 | 9851 | ||
| 9852 | #define B_CE_REG_NI_PER_LEFT__A 0x18100B0 | 9852 | #define B_CE_REG_NI_PER_LEFT__A 0x18100B0 |
| 9853 | #define B_CE_REG_NI_PER_LEFT__W 5 | 9853 | #define B_CE_REG_NI_PER_LEFT__W 5 |
| 9854 | #define B_CE_REG_NI_PER_LEFT__M 0x1F | 9854 | #define B_CE_REG_NI_PER_LEFT__M 0x1F |
| 9855 | #define B_CE_REG_NI_PER_LEFT_INIT 0xE | 9855 | #define B_CE_REG_NI_PER_LEFT_INIT 0xE |
| 9856 | 9856 | ||
| 9857 | #define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 | 9857 | #define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 |
| 9858 | #define B_CE_REG_NI_PER_RIGHT__W 5 | 9858 | #define B_CE_REG_NI_PER_RIGHT__W 5 |
| 9859 | #define B_CE_REG_NI_PER_RIGHT__M 0x1F | 9859 | #define B_CE_REG_NI_PER_RIGHT__M 0x1F |
| 9860 | #define B_CE_REG_NI_PER_RIGHT_INIT 0x7 | 9860 | #define B_CE_REG_NI_PER_RIGHT_INIT 0x7 |
| 9861 | 9861 | ||
| 9862 | #define B_CE_REG_NI_POS_LR__A 0x18100B2 | 9862 | #define B_CE_REG_NI_POS_LR__A 0x18100B2 |
| 9863 | #define B_CE_REG_NI_POS_LR__W 9 | 9863 | #define B_CE_REG_NI_POS_LR__W 9 |
| 9864 | #define B_CE_REG_NI_POS_LR__M 0x1FF | 9864 | #define B_CE_REG_NI_POS_LR__M 0x1FF |
| 9865 | #define B_CE_REG_NI_POS_LR_INIT 0xA0 | 9865 | #define B_CE_REG_NI_POS_LR_INIT 0xA0 |
| 9866 | 9866 | ||
| 9867 | #define B_CE_REG_FI_SHT_INCR__A 0x1810090 | 9867 | #define B_CE_REG_FI_SHT_INCR__A 0x1810090 |
| 9868 | #define B_CE_REG_FI_SHT_INCR__W 7 | 9868 | #define B_CE_REG_FI_SHT_INCR__W 7 |
| 9869 | #define B_CE_REG_FI_SHT_INCR__M 0x7F | 9869 | #define B_CE_REG_FI_SHT_INCR__M 0x7F |
| 9870 | #define B_CE_REG_FI_SHT_INCR_INIT 0x9 | 9870 | #define B_CE_REG_FI_SHT_INCR_INIT 0x9 |
| 9871 | 9871 | ||
| 9872 | #define B_CE_REG_FI_EXP_NORM__A 0x1810091 | 9872 | #define B_CE_REG_FI_EXP_NORM__A 0x1810091 |
| 9873 | #define B_CE_REG_FI_EXP_NORM__W 4 | 9873 | #define B_CE_REG_FI_EXP_NORM__W 4 |
| 9874 | #define B_CE_REG_FI_EXP_NORM__M 0xF | 9874 | #define B_CE_REG_FI_EXP_NORM__M 0xF |
| 9875 | #define B_CE_REG_FI_EXP_NORM_INIT 0x4 | 9875 | #define B_CE_REG_FI_EXP_NORM_INIT 0x4 |
| 9876 | 9876 | ||
| 9877 | #define B_CE_REG_FI_SUPR_VAL__A 0x1810092 | 9877 | #define B_CE_REG_FI_SUPR_VAL__A 0x1810092 |
| 9878 | #define B_CE_REG_FI_SUPR_VAL__W 1 | 9878 | #define B_CE_REG_FI_SUPR_VAL__W 1 |
| 9879 | #define B_CE_REG_FI_SUPR_VAL__M 0x1 | 9879 | #define B_CE_REG_FI_SUPR_VAL__M 0x1 |
| 9880 | #define B_CE_REG_FI_SUPR_VAL_INIT 0x1 | 9880 | #define B_CE_REG_FI_SUPR_VAL_INIT 0x1 |
| 9881 | 9881 | ||
| 9882 | #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 | 9882 | #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 |
| 9883 | #define B_CE_REG_IR_INPUTSEL__W 1 | 9883 | #define B_CE_REG_IR_INPUTSEL__W 1 |
| 9884 | #define B_CE_REG_IR_INPUTSEL__M 0x1 | 9884 | #define B_CE_REG_IR_INPUTSEL__M 0x1 |
| 9885 | #define B_CE_REG_IR_INPUTSEL_INIT 0x0 | 9885 | #define B_CE_REG_IR_INPUTSEL_INIT 0x0 |
| 9886 | 9886 | ||
| 9887 | #define B_CE_REG_IR_STARTPOS__A 0x18100A1 | 9887 | #define B_CE_REG_IR_STARTPOS__A 0x18100A1 |
| 9888 | #define B_CE_REG_IR_STARTPOS__W 8 | 9888 | #define B_CE_REG_IR_STARTPOS__W 8 |
| 9889 | #define B_CE_REG_IR_STARTPOS__M 0xFF | 9889 | #define B_CE_REG_IR_STARTPOS__M 0xFF |
| 9890 | #define B_CE_REG_IR_STARTPOS_INIT 0x0 | 9890 | #define B_CE_REG_IR_STARTPOS_INIT 0x0 |
| 9891 | 9891 | ||
| 9892 | #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 | 9892 | #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 |
| 9893 | #define B_CE_REG_IR_NEXP_THRES__W 8 | 9893 | #define B_CE_REG_IR_NEXP_THRES__W 8 |
| 9894 | #define B_CE_REG_IR_NEXP_THRES__M 0xFF | 9894 | #define B_CE_REG_IR_NEXP_THRES__M 0xFF |
| 9895 | #define B_CE_REG_IR_NEXP_THRES_INIT 0x0 | 9895 | #define B_CE_REG_IR_NEXP_THRES_INIT 0x0 |
| 9896 | 9896 | ||
| 9897 | #define B_CE_REG_IR_LENGTH__A 0x18100A3 | 9897 | #define B_CE_REG_IR_LENGTH__A 0x18100A3 |
| 9898 | #define B_CE_REG_IR_LENGTH__W 4 | 9898 | #define B_CE_REG_IR_LENGTH__W 4 |
| 9899 | #define B_CE_REG_IR_LENGTH__M 0xF | 9899 | #define B_CE_REG_IR_LENGTH__M 0xF |
| 9900 | #define B_CE_REG_IR_LENGTH_INIT 0x0 | 9900 | #define B_CE_REG_IR_LENGTH_INIT 0x0 |
| 9901 | 9901 | ||
| 9902 | #define B_CE_REG_IR_FREQ__A 0x18100A4 | 9902 | #define B_CE_REG_IR_FREQ__A 0x18100A4 |
| 9903 | #define B_CE_REG_IR_FREQ__W 11 | 9903 | #define B_CE_REG_IR_FREQ__W 11 |
| 9904 | #define B_CE_REG_IR_FREQ__M 0x7FF | 9904 | #define B_CE_REG_IR_FREQ__M 0x7FF |
| 9905 | #define B_CE_REG_IR_FREQ_INIT 0x0 | 9905 | #define B_CE_REG_IR_FREQ_INIT 0x0 |
| 9906 | 9906 | ||
| 9907 | #define B_CE_REG_IR_FREQINC__A 0x18100A5 | 9907 | #define B_CE_REG_IR_FREQINC__A 0x18100A5 |
| 9908 | #define B_CE_REG_IR_FREQINC__W 11 | 9908 | #define B_CE_REG_IR_FREQINC__W 11 |
| 9909 | #define B_CE_REG_IR_FREQINC__M 0x7FF | 9909 | #define B_CE_REG_IR_FREQINC__M 0x7FF |
| 9910 | #define B_CE_REG_IR_FREQINC_INIT 0x0 | 9910 | #define B_CE_REG_IR_FREQINC_INIT 0x0 |
| 9911 | 9911 | ||
| 9912 | #define B_CE_REG_IR_KAISINC__A 0x18100A6 | 9912 | #define B_CE_REG_IR_KAISINC__A 0x18100A6 |
| 9913 | #define B_CE_REG_IR_KAISINC__W 15 | 9913 | #define B_CE_REG_IR_KAISINC__W 15 |
| 9914 | #define B_CE_REG_IR_KAISINC__M 0x7FFF | 9914 | #define B_CE_REG_IR_KAISINC__M 0x7FFF |
| 9915 | #define B_CE_REG_IR_KAISINC_INIT 0x0 | 9915 | #define B_CE_REG_IR_KAISINC_INIT 0x0 |
| 9916 | 9916 | ||
| 9917 | #define B_CE_REG_IR_CTL__A 0x18100A7 | 9917 | #define B_CE_REG_IR_CTL__A 0x18100A7 |
| 9918 | #define B_CE_REG_IR_CTL__W 3 | 9918 | #define B_CE_REG_IR_CTL__W 3 |
| 9919 | #define B_CE_REG_IR_CTL__M 0x7 | 9919 | #define B_CE_REG_IR_CTL__M 0x7 |
| 9920 | #define B_CE_REG_IR_CTL_INIT 0x0 | 9920 | #define B_CE_REG_IR_CTL_INIT 0x0 |
| 9921 | 9921 | ||
| 9922 | #define B_CE_REG_IR_REAL__A 0x18100A8 | 9922 | #define B_CE_REG_IR_REAL__A 0x18100A8 |
| 9923 | #define B_CE_REG_IR_REAL__W 16 | 9923 | #define B_CE_REG_IR_REAL__W 16 |
| 9924 | #define B_CE_REG_IR_REAL__M 0xFFFF | 9924 | #define B_CE_REG_IR_REAL__M 0xFFFF |
| 9925 | #define B_CE_REG_IR_REAL_INIT 0x0 | 9925 | #define B_CE_REG_IR_REAL_INIT 0x0 |
| 9926 | 9926 | ||
| 9927 | #define B_CE_REG_IR_IMAG__A 0x18100A9 | 9927 | #define B_CE_REG_IR_IMAG__A 0x18100A9 |
| 9928 | #define B_CE_REG_IR_IMAG__W 16 | 9928 | #define B_CE_REG_IR_IMAG__W 16 |
| 9929 | #define B_CE_REG_IR_IMAG__M 0xFFFF | 9929 | #define B_CE_REG_IR_IMAG__M 0xFFFF |
| 9930 | #define B_CE_REG_IR_IMAG_INIT 0x0 | 9930 | #define B_CE_REG_IR_IMAG_INIT 0x0 |
| 9931 | 9931 | ||
| 9932 | #define B_CE_REG_IR_INDEX__A 0x18100AA | 9932 | #define B_CE_REG_IR_INDEX__A 0x18100AA |
| 9933 | #define B_CE_REG_IR_INDEX__W 12 | 9933 | #define B_CE_REG_IR_INDEX__W 12 |
| 9934 | #define B_CE_REG_IR_INDEX__M 0xFFF | 9934 | #define B_CE_REG_IR_INDEX__M 0xFFF |
| 9935 | #define B_CE_REG_IR_INDEX_INIT 0x0 | 9935 | #define B_CE_REG_IR_INDEX_INIT 0x0 |
| 9936 | 9936 | ||
| 9937 | #define B_CE_REG_FR_COMM_EXEC__A 0x1820000 | 9937 | #define B_CE_REG_FR_COMM_EXEC__A 0x1820000 |
| 9938 | #define B_CE_REG_FR_COMM_EXEC__W 1 | 9938 | #define B_CE_REG_FR_COMM_EXEC__W 1 |
| 9939 | #define B_CE_REG_FR_COMM_EXEC__M 0x1 | 9939 | #define B_CE_REG_FR_COMM_EXEC__M 0x1 |
| 9940 | 9940 | ||
| 9941 | #define B_CE_REG_FR_TREAL00__A 0x1820010 | 9941 | #define B_CE_REG_FR_TREAL00__A 0x1820010 |
| 9942 | #define B_CE_REG_FR_TREAL00__W 11 | 9942 | #define B_CE_REG_FR_TREAL00__W 11 |
| 9943 | #define B_CE_REG_FR_TREAL00__M 0x7FF | 9943 | #define B_CE_REG_FR_TREAL00__M 0x7FF |
| 9944 | #define B_CE_REG_FR_TREAL00_INIT 0x52 | 9944 | #define B_CE_REG_FR_TREAL00_INIT 0x52 |
| 9945 | 9945 | ||
| 9946 | #define B_CE_REG_FR_TIMAG00__A 0x1820011 | 9946 | #define B_CE_REG_FR_TIMAG00__A 0x1820011 |
| 9947 | #define B_CE_REG_FR_TIMAG00__W 11 | 9947 | #define B_CE_REG_FR_TIMAG00__W 11 |
| 9948 | #define B_CE_REG_FR_TIMAG00__M 0x7FF | 9948 | #define B_CE_REG_FR_TIMAG00__M 0x7FF |
| 9949 | #define B_CE_REG_FR_TIMAG00_INIT 0x0 | 9949 | #define B_CE_REG_FR_TIMAG00_INIT 0x0 |
| 9950 | 9950 | ||
| 9951 | #define B_CE_REG_FR_TREAL01__A 0x1820012 | 9951 | #define B_CE_REG_FR_TREAL01__A 0x1820012 |
| 9952 | #define B_CE_REG_FR_TREAL01__W 11 | 9952 | #define B_CE_REG_FR_TREAL01__W 11 |
| 9953 | #define B_CE_REG_FR_TREAL01__M 0x7FF | 9953 | #define B_CE_REG_FR_TREAL01__M 0x7FF |
| 9954 | #define B_CE_REG_FR_TREAL01_INIT 0x52 | 9954 | #define B_CE_REG_FR_TREAL01_INIT 0x52 |
| 9955 | 9955 | ||
| 9956 | #define B_CE_REG_FR_TIMAG01__A 0x1820013 | 9956 | #define B_CE_REG_FR_TIMAG01__A 0x1820013 |
| 9957 | #define B_CE_REG_FR_TIMAG01__W 11 | 9957 | #define B_CE_REG_FR_TIMAG01__W 11 |
| 9958 | #define B_CE_REG_FR_TIMAG01__M 0x7FF | 9958 | #define B_CE_REG_FR_TIMAG01__M 0x7FF |
| 9959 | #define B_CE_REG_FR_TIMAG01_INIT 0x0 | 9959 | #define B_CE_REG_FR_TIMAG01_INIT 0x0 |
| 9960 | 9960 | ||
| 9961 | #define B_CE_REG_FR_TREAL02__A 0x1820014 | 9961 | #define B_CE_REG_FR_TREAL02__A 0x1820014 |
| 9962 | #define B_CE_REG_FR_TREAL02__W 11 | 9962 | #define B_CE_REG_FR_TREAL02__W 11 |
| 9963 | #define B_CE_REG_FR_TREAL02__M 0x7FF | 9963 | #define B_CE_REG_FR_TREAL02__M 0x7FF |
| 9964 | #define B_CE_REG_FR_TREAL02_INIT 0x52 | 9964 | #define B_CE_REG_FR_TREAL02_INIT 0x52 |
| 9965 | 9965 | ||
| 9966 | #define B_CE_REG_FR_TIMAG02__A 0x1820015 | 9966 | #define B_CE_REG_FR_TIMAG02__A 0x1820015 |
| 9967 | #define B_CE_REG_FR_TIMAG02__W 11 | 9967 | #define B_CE_REG_FR_TIMAG02__W 11 |
| 9968 | #define B_CE_REG_FR_TIMAG02__M 0x7FF | 9968 | #define B_CE_REG_FR_TIMAG02__M 0x7FF |
| 9969 | #define B_CE_REG_FR_TIMAG02_INIT 0x0 | 9969 | #define B_CE_REG_FR_TIMAG02_INIT 0x0 |
| 9970 | 9970 | ||
| 9971 | #define B_CE_REG_FR_TREAL03__A 0x1820016 | 9971 | #define B_CE_REG_FR_TREAL03__A 0x1820016 |
| 9972 | #define B_CE_REG_FR_TREAL03__W 11 | 9972 | #define B_CE_REG_FR_TREAL03__W 11 |
| 9973 | #define B_CE_REG_FR_TREAL03__M 0x7FF | 9973 | #define B_CE_REG_FR_TREAL03__M 0x7FF |
| 9974 | #define B_CE_REG_FR_TREAL03_INIT 0x52 | 9974 | #define B_CE_REG_FR_TREAL03_INIT 0x52 |
| 9975 | 9975 | ||
| 9976 | #define B_CE_REG_FR_TIMAG03__A 0x1820017 | 9976 | #define B_CE_REG_FR_TIMAG03__A 0x1820017 |
| 9977 | #define B_CE_REG_FR_TIMAG03__W 11 | 9977 | #define B_CE_REG_FR_TIMAG03__W 11 |
| 9978 | #define B_CE_REG_FR_TIMAG03__M 0x7FF | 9978 | #define B_CE_REG_FR_TIMAG03__M 0x7FF |
| 9979 | #define B_CE_REG_FR_TIMAG03_INIT 0x0 | 9979 | #define B_CE_REG_FR_TIMAG03_INIT 0x0 |
| 9980 | 9980 | ||
| 9981 | #define B_CE_REG_FR_TREAL04__A 0x1820018 | 9981 | #define B_CE_REG_FR_TREAL04__A 0x1820018 |
| 9982 | #define B_CE_REG_FR_TREAL04__W 11 | 9982 | #define B_CE_REG_FR_TREAL04__W 11 |
| 9983 | #define B_CE_REG_FR_TREAL04__M 0x7FF | 9983 | #define B_CE_REG_FR_TREAL04__M 0x7FF |
| 9984 | #define B_CE_REG_FR_TREAL04_INIT 0x52 | 9984 | #define B_CE_REG_FR_TREAL04_INIT 0x52 |
| 9985 | 9985 | ||
| 9986 | #define B_CE_REG_FR_TIMAG04__A 0x1820019 | 9986 | #define B_CE_REG_FR_TIMAG04__A 0x1820019 |
| 9987 | #define B_CE_REG_FR_TIMAG04__W 11 | 9987 | #define B_CE_REG_FR_TIMAG04__W 11 |
| 9988 | #define B_CE_REG_FR_TIMAG04__M 0x7FF | 9988 | #define B_CE_REG_FR_TIMAG04__M 0x7FF |
| 9989 | #define B_CE_REG_FR_TIMAG04_INIT 0x0 | 9989 | #define B_CE_REG_FR_TIMAG04_INIT 0x0 |
| 9990 | 9990 | ||
| 9991 | #define B_CE_REG_FR_TREAL05__A 0x182001A | 9991 | #define B_CE_REG_FR_TREAL05__A 0x182001A |
| 9992 | #define B_CE_REG_FR_TREAL05__W 11 | 9992 | #define B_CE_REG_FR_TREAL05__W 11 |
| 9993 | #define B_CE_REG_FR_TREAL05__M 0x7FF | 9993 | #define B_CE_REG_FR_TREAL05__M 0x7FF |
| 9994 | #define B_CE_REG_FR_TREAL05_INIT 0x52 | 9994 | #define B_CE_REG_FR_TREAL05_INIT 0x52 |
| 9995 | 9995 | ||
| 9996 | #define B_CE_REG_FR_TIMAG05__A 0x182001B | 9996 | #define B_CE_REG_FR_TIMAG05__A 0x182001B |
| 9997 | #define B_CE_REG_FR_TIMAG05__W 11 | 9997 | #define B_CE_REG_FR_TIMAG05__W 11 |
| 9998 | #define B_CE_REG_FR_TIMAG05__M 0x7FF | 9998 | #define B_CE_REG_FR_TIMAG05__M 0x7FF |
| 9999 | #define B_CE_REG_FR_TIMAG05_INIT 0x0 | 9999 | #define B_CE_REG_FR_TIMAG05_INIT 0x0 |
| 10000 | 10000 | ||
| 10001 | #define B_CE_REG_FR_TREAL06__A 0x182001C | 10001 | #define B_CE_REG_FR_TREAL06__A 0x182001C |
| 10002 | #define B_CE_REG_FR_TREAL06__W 11 | 10002 | #define B_CE_REG_FR_TREAL06__W 11 |
| 10003 | #define B_CE_REG_FR_TREAL06__M 0x7FF | 10003 | #define B_CE_REG_FR_TREAL06__M 0x7FF |
| 10004 | #define B_CE_REG_FR_TREAL06_INIT 0x52 | 10004 | #define B_CE_REG_FR_TREAL06_INIT 0x52 |
| 10005 | 10005 | ||
| 10006 | #define B_CE_REG_FR_TIMAG06__A 0x182001D | 10006 | #define B_CE_REG_FR_TIMAG06__A 0x182001D |
| 10007 | #define B_CE_REG_FR_TIMAG06__W 11 | 10007 | #define B_CE_REG_FR_TIMAG06__W 11 |
| 10008 | #define B_CE_REG_FR_TIMAG06__M 0x7FF | 10008 | #define B_CE_REG_FR_TIMAG06__M 0x7FF |
| 10009 | #define B_CE_REG_FR_TIMAG06_INIT 0x0 | 10009 | #define B_CE_REG_FR_TIMAG06_INIT 0x0 |
| 10010 | 10010 | ||
| 10011 | #define B_CE_REG_FR_TREAL07__A 0x182001E | 10011 | #define B_CE_REG_FR_TREAL07__A 0x182001E |
| 10012 | #define B_CE_REG_FR_TREAL07__W 11 | 10012 | #define B_CE_REG_FR_TREAL07__W 11 |
| 10013 | #define B_CE_REG_FR_TREAL07__M 0x7FF | 10013 | #define B_CE_REG_FR_TREAL07__M 0x7FF |
| 10014 | #define B_CE_REG_FR_TREAL07_INIT 0x52 | 10014 | #define B_CE_REG_FR_TREAL07_INIT 0x52 |
| 10015 | 10015 | ||
| 10016 | #define B_CE_REG_FR_TIMAG07__A 0x182001F | 10016 | #define B_CE_REG_FR_TIMAG07__A 0x182001F |
| 10017 | #define B_CE_REG_FR_TIMAG07__W 11 | 10017 | #define B_CE_REG_FR_TIMAG07__W 11 |
| 10018 | #define B_CE_REG_FR_TIMAG07__M 0x7FF | 10018 | #define B_CE_REG_FR_TIMAG07__M 0x7FF |
| 10019 | #define B_CE_REG_FR_TIMAG07_INIT 0x0 | 10019 | #define B_CE_REG_FR_TIMAG07_INIT 0x0 |
| 10020 | 10020 | ||
| 10021 | #define B_CE_REG_FR_TREAL08__A 0x1820020 | 10021 | #define B_CE_REG_FR_TREAL08__A 0x1820020 |
| 10022 | #define B_CE_REG_FR_TREAL08__W 11 | 10022 | #define B_CE_REG_FR_TREAL08__W 11 |
| 10023 | #define B_CE_REG_FR_TREAL08__M 0x7FF | 10023 | #define B_CE_REG_FR_TREAL08__M 0x7FF |
| 10024 | #define B_CE_REG_FR_TREAL08_INIT 0x52 | 10024 | #define B_CE_REG_FR_TREAL08_INIT 0x52 |
| 10025 | 10025 | ||
| 10026 | #define B_CE_REG_FR_TIMAG08__A 0x1820021 | 10026 | #define B_CE_REG_FR_TIMAG08__A 0x1820021 |
| 10027 | #define B_CE_REG_FR_TIMAG08__W 11 | 10027 | #define B_CE_REG_FR_TIMAG08__W 11 |
| 10028 | #define B_CE_REG_FR_TIMAG08__M 0x7FF | 10028 | #define B_CE_REG_FR_TIMAG08__M 0x7FF |
| 10029 | #define B_CE_REG_FR_TIMAG08_INIT 0x0 | 10029 | #define B_CE_REG_FR_TIMAG08_INIT 0x0 |
| 10030 | 10030 | ||
| 10031 | #define B_CE_REG_FR_TREAL09__A 0x1820022 | 10031 | #define B_CE_REG_FR_TREAL09__A 0x1820022 |
| 10032 | #define B_CE_REG_FR_TREAL09__W 11 | 10032 | #define B_CE_REG_FR_TREAL09__W 11 |
| 10033 | #define B_CE_REG_FR_TREAL09__M 0x7FF | 10033 | #define B_CE_REG_FR_TREAL09__M 0x7FF |
| 10034 | #define B_CE_REG_FR_TREAL09_INIT 0x52 | 10034 | #define B_CE_REG_FR_TREAL09_INIT 0x52 |
| 10035 | 10035 | ||
| 10036 | #define B_CE_REG_FR_TIMAG09__A 0x1820023 | 10036 | #define B_CE_REG_FR_TIMAG09__A 0x1820023 |
| 10037 | #define B_CE_REG_FR_TIMAG09__W 11 | 10037 | #define B_CE_REG_FR_TIMAG09__W 11 |
| 10038 | #define B_CE_REG_FR_TIMAG09__M 0x7FF | 10038 | #define B_CE_REG_FR_TIMAG09__M 0x7FF |
| 10039 | #define B_CE_REG_FR_TIMAG09_INIT 0x0 | 10039 | #define B_CE_REG_FR_TIMAG09_INIT 0x0 |
| 10040 | 10040 | ||
| 10041 | #define B_CE_REG_FR_TREAL10__A 0x1820024 | 10041 | #define B_CE_REG_FR_TREAL10__A 0x1820024 |
| 10042 | #define B_CE_REG_FR_TREAL10__W 11 | 10042 | #define B_CE_REG_FR_TREAL10__W 11 |
| 10043 | #define B_CE_REG_FR_TREAL10__M 0x7FF | 10043 | #define B_CE_REG_FR_TREAL10__M 0x7FF |
| 10044 | #define B_CE_REG_FR_TREAL10_INIT 0x52 | 10044 | #define B_CE_REG_FR_TREAL10_INIT 0x52 |
| 10045 | 10045 | ||
| 10046 | #define B_CE_REG_FR_TIMAG10__A 0x1820025 | 10046 | #define B_CE_REG_FR_TIMAG10__A 0x1820025 |
| 10047 | #define B_CE_REG_FR_TIMAG10__W 11 | 10047 | #define B_CE_REG_FR_TIMAG10__W 11 |
| 10048 | #define B_CE_REG_FR_TIMAG10__M 0x7FF | 10048 | #define B_CE_REG_FR_TIMAG10__M 0x7FF |
| 10049 | #define B_CE_REG_FR_TIMAG10_INIT 0x0 | 10049 | #define B_CE_REG_FR_TIMAG10_INIT 0x0 |
| 10050 | 10050 | ||
| 10051 | #define B_CE_REG_FR_TREAL11__A 0x1820026 | 10051 | #define B_CE_REG_FR_TREAL11__A 0x1820026 |
| 10052 | #define B_CE_REG_FR_TREAL11__W 11 | 10052 | #define B_CE_REG_FR_TREAL11__W 11 |
| 10053 | #define B_CE_REG_FR_TREAL11__M 0x7FF | 10053 | #define B_CE_REG_FR_TREAL11__M 0x7FF |
| 10054 | #define B_CE_REG_FR_TREAL11_INIT 0x52 | 10054 | #define B_CE_REG_FR_TREAL11_INIT 0x52 |
| 10055 | 10055 | ||
| 10056 | #define B_CE_REG_FR_TIMAG11__A 0x1820027 | 10056 | #define B_CE_REG_FR_TIMAG11__A 0x1820027 |
| 10057 | #define B_CE_REG_FR_TIMAG11__W 11 | 10057 | #define B_CE_REG_FR_TIMAG11__W 11 |
| 10058 | #define B_CE_REG_FR_TIMAG11__M 0x7FF | 10058 | #define B_CE_REG_FR_TIMAG11__M 0x7FF |
| 10059 | #define B_CE_REG_FR_TIMAG11_INIT 0x0 | 10059 | #define B_CE_REG_FR_TIMAG11_INIT 0x0 |
| 10060 | 10060 | ||
| 10061 | #define B_CE_REG_FR_MID_TAP__A 0x1820028 | 10061 | #define B_CE_REG_FR_MID_TAP__A 0x1820028 |
| 10062 | #define B_CE_REG_FR_MID_TAP__W 11 | 10062 | #define B_CE_REG_FR_MID_TAP__W 11 |
| 10063 | #define B_CE_REG_FR_MID_TAP__M 0x7FF | 10063 | #define B_CE_REG_FR_MID_TAP__M 0x7FF |
| 10064 | #define B_CE_REG_FR_MID_TAP_INIT 0x51 | 10064 | #define B_CE_REG_FR_MID_TAP_INIT 0x51 |
| 10065 | 10065 | ||
| 10066 | #define B_CE_REG_FR_SQS_G00__A 0x1820029 | 10066 | #define B_CE_REG_FR_SQS_G00__A 0x1820029 |
| 10067 | #define B_CE_REG_FR_SQS_G00__W 8 | 10067 | #define B_CE_REG_FR_SQS_G00__W 8 |
| 10068 | #define B_CE_REG_FR_SQS_G00__M 0xFF | 10068 | #define B_CE_REG_FR_SQS_G00__M 0xFF |
| 10069 | #define B_CE_REG_FR_SQS_G00_INIT 0xB | 10069 | #define B_CE_REG_FR_SQS_G00_INIT 0xB |
| 10070 | 10070 | ||
| 10071 | #define B_CE_REG_FR_SQS_G01__A 0x182002A | 10071 | #define B_CE_REG_FR_SQS_G01__A 0x182002A |
| 10072 | #define B_CE_REG_FR_SQS_G01__W 8 | 10072 | #define B_CE_REG_FR_SQS_G01__W 8 |
| 10073 | #define B_CE_REG_FR_SQS_G01__M 0xFF | 10073 | #define B_CE_REG_FR_SQS_G01__M 0xFF |
| 10074 | #define B_CE_REG_FR_SQS_G01_INIT 0xB | 10074 | #define B_CE_REG_FR_SQS_G01_INIT 0xB |
| 10075 | 10075 | ||
| 10076 | #define B_CE_REG_FR_SQS_G02__A 0x182002B | 10076 | #define B_CE_REG_FR_SQS_G02__A 0x182002B |
| 10077 | #define B_CE_REG_FR_SQS_G02__W 8 | 10077 | #define B_CE_REG_FR_SQS_G02__W 8 |
| 10078 | #define B_CE_REG_FR_SQS_G02__M 0xFF | 10078 | #define B_CE_REG_FR_SQS_G02__M 0xFF |
| 10079 | #define B_CE_REG_FR_SQS_G02_INIT 0xB | 10079 | #define B_CE_REG_FR_SQS_G02_INIT 0xB |
| 10080 | 10080 | ||
| 10081 | #define B_CE_REG_FR_SQS_G03__A 0x182002C | 10081 | #define B_CE_REG_FR_SQS_G03__A 0x182002C |
| 10082 | #define B_CE_REG_FR_SQS_G03__W 8 | 10082 | #define B_CE_REG_FR_SQS_G03__W 8 |
| 10083 | #define B_CE_REG_FR_SQS_G03__M 0xFF | 10083 | #define B_CE_REG_FR_SQS_G03__M 0xFF |
| 10084 | #define B_CE_REG_FR_SQS_G03_INIT 0xB | 10084 | #define B_CE_REG_FR_SQS_G03_INIT 0xB |
| 10085 | 10085 | ||
| 10086 | #define B_CE_REG_FR_SQS_G04__A 0x182002D | 10086 | #define B_CE_REG_FR_SQS_G04__A 0x182002D |
| 10087 | #define B_CE_REG_FR_SQS_G04__W 8 | 10087 | #define B_CE_REG_FR_SQS_G04__W 8 |
| 10088 | #define B_CE_REG_FR_SQS_G04__M 0xFF | 10088 | #define B_CE_REG_FR_SQS_G04__M 0xFF |
| 10089 | #define B_CE_REG_FR_SQS_G04_INIT 0xB | 10089 | #define B_CE_REG_FR_SQS_G04_INIT 0xB |
| 10090 | 10090 | ||
| 10091 | #define B_CE_REG_FR_SQS_G05__A 0x182002E | 10091 | #define B_CE_REG_FR_SQS_G05__A 0x182002E |
| 10092 | #define B_CE_REG_FR_SQS_G05__W 8 | 10092 | #define B_CE_REG_FR_SQS_G05__W 8 |
| 10093 | #define B_CE_REG_FR_SQS_G05__M 0xFF | 10093 | #define B_CE_REG_FR_SQS_G05__M 0xFF |
| 10094 | #define B_CE_REG_FR_SQS_G05_INIT 0xB | 10094 | #define B_CE_REG_FR_SQS_G05_INIT 0xB |
| 10095 | 10095 | ||
| 10096 | #define B_CE_REG_FR_SQS_G06__A 0x182002F | 10096 | #define B_CE_REG_FR_SQS_G06__A 0x182002F |
| 10097 | #define B_CE_REG_FR_SQS_G06__W 8 | 10097 | #define B_CE_REG_FR_SQS_G06__W 8 |
| 10098 | #define B_CE_REG_FR_SQS_G06__M 0xFF | 10098 | #define B_CE_REG_FR_SQS_G06__M 0xFF |
| 10099 | #define B_CE_REG_FR_SQS_G06_INIT 0xB | 10099 | #define B_CE_REG_FR_SQS_G06_INIT 0xB |
| 10100 | 10100 | ||
| 10101 | #define B_CE_REG_FR_SQS_G07__A 0x1820030 | 10101 | #define B_CE_REG_FR_SQS_G07__A 0x1820030 |
| 10102 | #define B_CE_REG_FR_SQS_G07__W 8 | 10102 | #define B_CE_REG_FR_SQS_G07__W 8 |
| 10103 | #define B_CE_REG_FR_SQS_G07__M 0xFF | 10103 | #define B_CE_REG_FR_SQS_G07__M 0xFF |
| 10104 | #define B_CE_REG_FR_SQS_G07_INIT 0xB | 10104 | #define B_CE_REG_FR_SQS_G07_INIT 0xB |
| 10105 | 10105 | ||
| 10106 | #define B_CE_REG_FR_SQS_G08__A 0x1820031 | 10106 | #define B_CE_REG_FR_SQS_G08__A 0x1820031 |
| 10107 | #define B_CE_REG_FR_SQS_G08__W 8 | 10107 | #define B_CE_REG_FR_SQS_G08__W 8 |
| 10108 | #define B_CE_REG_FR_SQS_G08__M 0xFF | 10108 | #define B_CE_REG_FR_SQS_G08__M 0xFF |
| 10109 | #define B_CE_REG_FR_SQS_G08_INIT 0xB | 10109 | #define B_CE_REG_FR_SQS_G08_INIT 0xB |
| 10110 | 10110 | ||
| 10111 | #define B_CE_REG_FR_SQS_G09__A 0x1820032 | 10111 | #define B_CE_REG_FR_SQS_G09__A 0x1820032 |
| 10112 | #define B_CE_REG_FR_SQS_G09__W 8 | 10112 | #define B_CE_REG_FR_SQS_G09__W 8 |
| 10113 | #define B_CE_REG_FR_SQS_G09__M 0xFF | 10113 | #define B_CE_REG_FR_SQS_G09__M 0xFF |
| 10114 | #define B_CE_REG_FR_SQS_G09_INIT 0xB | 10114 | #define B_CE_REG_FR_SQS_G09_INIT 0xB |
| 10115 | 10115 | ||
| 10116 | #define B_CE_REG_FR_SQS_G10__A 0x1820033 | 10116 | #define B_CE_REG_FR_SQS_G10__A 0x1820033 |
| 10117 | #define B_CE_REG_FR_SQS_G10__W 8 | 10117 | #define B_CE_REG_FR_SQS_G10__W 8 |
| 10118 | #define B_CE_REG_FR_SQS_G10__M 0xFF | 10118 | #define B_CE_REG_FR_SQS_G10__M 0xFF |
| 10119 | #define B_CE_REG_FR_SQS_G10_INIT 0xB | 10119 | #define B_CE_REG_FR_SQS_G10_INIT 0xB |
| 10120 | 10120 | ||
| 10121 | #define B_CE_REG_FR_SQS_G11__A 0x1820034 | 10121 | #define B_CE_REG_FR_SQS_G11__A 0x1820034 |
| 10122 | #define B_CE_REG_FR_SQS_G11__W 8 | 10122 | #define B_CE_REG_FR_SQS_G11__W 8 |
| 10123 | #define B_CE_REG_FR_SQS_G11__M 0xFF | 10123 | #define B_CE_REG_FR_SQS_G11__M 0xFF |
| 10124 | #define B_CE_REG_FR_SQS_G11_INIT 0xB | 10124 | #define B_CE_REG_FR_SQS_G11_INIT 0xB |
| 10125 | 10125 | ||
| 10126 | #define B_CE_REG_FR_SQS_G12__A 0x1820035 | 10126 | #define B_CE_REG_FR_SQS_G12__A 0x1820035 |
| 10127 | #define B_CE_REG_FR_SQS_G12__W 8 | 10127 | #define B_CE_REG_FR_SQS_G12__W 8 |
| 10128 | #define B_CE_REG_FR_SQS_G12__M 0xFF | 10128 | #define B_CE_REG_FR_SQS_G12__M 0xFF |
| 10129 | #define B_CE_REG_FR_SQS_G12_INIT 0x5 | 10129 | #define B_CE_REG_FR_SQS_G12_INIT 0x5 |
| 10130 | 10130 | ||
| 10131 | #define B_CE_REG_FR_RIO_G00__A 0x1820036 | 10131 | #define B_CE_REG_FR_RIO_G00__A 0x1820036 |
| 10132 | #define B_CE_REG_FR_RIO_G00__W 9 | 10132 | #define B_CE_REG_FR_RIO_G00__W 9 |
| 10133 | #define B_CE_REG_FR_RIO_G00__M 0x1FF | 10133 | #define B_CE_REG_FR_RIO_G00__M 0x1FF |
| 10134 | #define B_CE_REG_FR_RIO_G00_INIT 0x1FF | 10134 | #define B_CE_REG_FR_RIO_G00_INIT 0x1FF |
| 10135 | 10135 | ||
| 10136 | #define B_CE_REG_FR_RIO_G01__A 0x1820037 | 10136 | #define B_CE_REG_FR_RIO_G01__A 0x1820037 |
| 10137 | #define B_CE_REG_FR_RIO_G01__W 9 | 10137 | #define B_CE_REG_FR_RIO_G01__W 9 |
| 10138 | #define B_CE_REG_FR_RIO_G01__M 0x1FF | 10138 | #define B_CE_REG_FR_RIO_G01__M 0x1FF |
| 10139 | #define B_CE_REG_FR_RIO_G01_INIT 0x190 | 10139 | #define B_CE_REG_FR_RIO_G01_INIT 0x190 |
| 10140 | 10140 | ||
| 10141 | #define B_CE_REG_FR_RIO_G02__A 0x1820038 | 10141 | #define B_CE_REG_FR_RIO_G02__A 0x1820038 |
| 10142 | #define B_CE_REG_FR_RIO_G02__W 9 | 10142 | #define B_CE_REG_FR_RIO_G02__W 9 |
| 10143 | #define B_CE_REG_FR_RIO_G02__M 0x1FF | 10143 | #define B_CE_REG_FR_RIO_G02__M 0x1FF |
| 10144 | #define B_CE_REG_FR_RIO_G02_INIT 0x10B | 10144 | #define B_CE_REG_FR_RIO_G02_INIT 0x10B |
| 10145 | 10145 | ||
| 10146 | #define B_CE_REG_FR_RIO_G03__A 0x1820039 | 10146 | #define B_CE_REG_FR_RIO_G03__A 0x1820039 |
| 10147 | #define B_CE_REG_FR_RIO_G03__W 9 | 10147 | #define B_CE_REG_FR_RIO_G03__W 9 |
| 10148 | #define B_CE_REG_FR_RIO_G03__M 0x1FF | 10148 | #define B_CE_REG_FR_RIO_G03__M 0x1FF |
| 10149 | #define B_CE_REG_FR_RIO_G03_INIT 0xC8 | 10149 | #define B_CE_REG_FR_RIO_G03_INIT 0xC8 |
| 10150 | 10150 | ||
| 10151 | #define B_CE_REG_FR_RIO_G04__A 0x182003A | 10151 | #define B_CE_REG_FR_RIO_G04__A 0x182003A |
| 10152 | #define B_CE_REG_FR_RIO_G04__W 9 | 10152 | #define B_CE_REG_FR_RIO_G04__W 9 |
| 10153 | #define B_CE_REG_FR_RIO_G04__M 0x1FF | 10153 | #define B_CE_REG_FR_RIO_G04__M 0x1FF |
| 10154 | #define B_CE_REG_FR_RIO_G04_INIT 0xA0 | 10154 | #define B_CE_REG_FR_RIO_G04_INIT 0xA0 |
| 10155 | 10155 | ||
| 10156 | #define B_CE_REG_FR_RIO_G05__A 0x182003B | 10156 | #define B_CE_REG_FR_RIO_G05__A 0x182003B |
| 10157 | #define B_CE_REG_FR_RIO_G05__W 9 | 10157 | #define B_CE_REG_FR_RIO_G05__W 9 |
| 10158 | #define B_CE_REG_FR_RIO_G05__M 0x1FF | 10158 | #define B_CE_REG_FR_RIO_G05__M 0x1FF |
| 10159 | #define B_CE_REG_FR_RIO_G05_INIT 0x85 | 10159 | #define B_CE_REG_FR_RIO_G05_INIT 0x85 |
| 10160 | 10160 | ||
| 10161 | #define B_CE_REG_FR_RIO_G06__A 0x182003C | 10161 | #define B_CE_REG_FR_RIO_G06__A 0x182003C |
| 10162 | #define B_CE_REG_FR_RIO_G06__W 9 | 10162 | #define B_CE_REG_FR_RIO_G06__W 9 |
| 10163 | #define B_CE_REG_FR_RIO_G06__M 0x1FF | 10163 | #define B_CE_REG_FR_RIO_G06__M 0x1FF |
| 10164 | #define B_CE_REG_FR_RIO_G06_INIT 0x72 | 10164 | #define B_CE_REG_FR_RIO_G06_INIT 0x72 |
| 10165 | 10165 | ||
| 10166 | #define B_CE_REG_FR_RIO_G07__A 0x182003D | 10166 | #define B_CE_REG_FR_RIO_G07__A 0x182003D |
| 10167 | #define B_CE_REG_FR_RIO_G07__W 9 | 10167 | #define B_CE_REG_FR_RIO_G07__W 9 |
| 10168 | #define B_CE_REG_FR_RIO_G07__M 0x1FF | 10168 | #define B_CE_REG_FR_RIO_G07__M 0x1FF |
| 10169 | #define B_CE_REG_FR_RIO_G07_INIT 0x64 | 10169 | #define B_CE_REG_FR_RIO_G07_INIT 0x64 |
| 10170 | 10170 | ||
| 10171 | #define B_CE_REG_FR_RIO_G08__A 0x182003E | 10171 | #define B_CE_REG_FR_RIO_G08__A 0x182003E |
| 10172 | #define B_CE_REG_FR_RIO_G08__W 9 | 10172 | #define B_CE_REG_FR_RIO_G08__W 9 |
| 10173 | #define B_CE_REG_FR_RIO_G08__M 0x1FF | 10173 | #define B_CE_REG_FR_RIO_G08__M 0x1FF |
| 10174 | #define B_CE_REG_FR_RIO_G08_INIT 0x59 | 10174 | #define B_CE_REG_FR_RIO_G08_INIT 0x59 |
| 10175 | 10175 | ||
| 10176 | #define B_CE_REG_FR_RIO_G09__A 0x182003F | 10176 | #define B_CE_REG_FR_RIO_G09__A 0x182003F |
| 10177 | #define B_CE_REG_FR_RIO_G09__W 9 | 10177 | #define B_CE_REG_FR_RIO_G09__W 9 |
| 10178 | #define B_CE_REG_FR_RIO_G09__M 0x1FF | 10178 | #define B_CE_REG_FR_RIO_G09__M 0x1FF |
| 10179 | #define B_CE_REG_FR_RIO_G09_INIT 0x50 | 10179 | #define B_CE_REG_FR_RIO_G09_INIT 0x50 |
| 10180 | 10180 | ||
| 10181 | #define B_CE_REG_FR_RIO_G10__A 0x1820040 | 10181 | #define B_CE_REG_FR_RIO_G10__A 0x1820040 |
| 10182 | #define B_CE_REG_FR_RIO_G10__W 9 | 10182 | #define B_CE_REG_FR_RIO_G10__W 9 |
| 10183 | #define B_CE_REG_FR_RIO_G10__M 0x1FF | 10183 | #define B_CE_REG_FR_RIO_G10__M 0x1FF |
| 10184 | #define B_CE_REG_FR_RIO_G10_INIT 0x49 | 10184 | #define B_CE_REG_FR_RIO_G10_INIT 0x49 |
| 10185 | 10185 | ||
| 10186 | #define B_CE_REG_FR_MODE__A 0x1820041 | 10186 | #define B_CE_REG_FR_MODE__A 0x1820041 |
| 10187 | #define B_CE_REG_FR_MODE__W 9 | 10187 | #define B_CE_REG_FR_MODE__W 9 |
| 10188 | #define B_CE_REG_FR_MODE__M 0x1FF | 10188 | #define B_CE_REG_FR_MODE__M 0x1FF |
| 10189 | 10189 | ||
| 10190 | #define B_CE_REG_FR_MODE_UPDATE_ENABLE__B 0 | 10190 | #define B_CE_REG_FR_MODE_UPDATE_ENABLE__B 0 |
| 10191 | #define B_CE_REG_FR_MODE_UPDATE_ENABLE__W 1 | 10191 | #define B_CE_REG_FR_MODE_UPDATE_ENABLE__W 1 |
| 10192 | #define B_CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 | 10192 | #define B_CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 |
| 10193 | 10193 | ||
| 10194 | #define B_CE_REG_FR_MODE_ERROR_SHIFT__B 1 | 10194 | #define B_CE_REG_FR_MODE_ERROR_SHIFT__B 1 |
| 10195 | #define B_CE_REG_FR_MODE_ERROR_SHIFT__W 1 | 10195 | #define B_CE_REG_FR_MODE_ERROR_SHIFT__W 1 |
| 10196 | #define B_CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 | 10196 | #define B_CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 |
| 10197 | 10197 | ||
| 10198 | #define B_CE_REG_FR_MODE_NEXP_UPDATE__B 2 | 10198 | #define B_CE_REG_FR_MODE_NEXP_UPDATE__B 2 |
| 10199 | #define B_CE_REG_FR_MODE_NEXP_UPDATE__W 1 | 10199 | #define B_CE_REG_FR_MODE_NEXP_UPDATE__W 1 |
| 10200 | #define B_CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 | 10200 | #define B_CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 |
| 10201 | 10201 | ||
| 10202 | #define B_CE_REG_FR_MODE_MANUAL_SHIFT__B 3 | 10202 | #define B_CE_REG_FR_MODE_MANUAL_SHIFT__B 3 |
| 10203 | #define B_CE_REG_FR_MODE_MANUAL_SHIFT__W 1 | 10203 | #define B_CE_REG_FR_MODE_MANUAL_SHIFT__W 1 |
| 10204 | #define B_CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 | 10204 | #define B_CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 |
| 10205 | 10205 | ||
| 10206 | #define B_CE_REG_FR_MODE_SQUASH_MODE__B 4 | 10206 | #define B_CE_REG_FR_MODE_SQUASH_MODE__B 4 |
| 10207 | #define B_CE_REG_FR_MODE_SQUASH_MODE__W 1 | 10207 | #define B_CE_REG_FR_MODE_SQUASH_MODE__W 1 |
| 10208 | #define B_CE_REG_FR_MODE_SQUASH_MODE__M 0x10 | 10208 | #define B_CE_REG_FR_MODE_SQUASH_MODE__M 0x10 |
| 10209 | 10209 | ||
| 10210 | #define B_CE_REG_FR_MODE_UPDATE_MODE__B 5 | 10210 | #define B_CE_REG_FR_MODE_UPDATE_MODE__B 5 |
| 10211 | #define B_CE_REG_FR_MODE_UPDATE_MODE__W 1 | 10211 | #define B_CE_REG_FR_MODE_UPDATE_MODE__W 1 |
| 10212 | #define B_CE_REG_FR_MODE_UPDATE_MODE__M 0x20 | 10212 | #define B_CE_REG_FR_MODE_UPDATE_MODE__M 0x20 |
| 10213 | 10213 | ||
| 10214 | #define B_CE_REG_FR_MODE_MID_MODE__B 6 | 10214 | #define B_CE_REG_FR_MODE_MID_MODE__B 6 |
| 10215 | #define B_CE_REG_FR_MODE_MID_MODE__W 1 | 10215 | #define B_CE_REG_FR_MODE_MID_MODE__W 1 |
| 10216 | #define B_CE_REG_FR_MODE_MID_MODE__M 0x40 | 10216 | #define B_CE_REG_FR_MODE_MID_MODE__M 0x40 |
| 10217 | 10217 | ||
| 10218 | #define B_CE_REG_FR_MODE_NOISE_MODE__B 7 | 10218 | #define B_CE_REG_FR_MODE_NOISE_MODE__B 7 |
| 10219 | #define B_CE_REG_FR_MODE_NOISE_MODE__W 1 | 10219 | #define B_CE_REG_FR_MODE_NOISE_MODE__W 1 |
| 10220 | #define B_CE_REG_FR_MODE_NOISE_MODE__M 0x80 | 10220 | #define B_CE_REG_FR_MODE_NOISE_MODE__M 0x80 |
| 10221 | 10221 | ||
| 10222 | #define B_CE_REG_FR_MODE_NOTCH_MODE__B 8 | 10222 | #define B_CE_REG_FR_MODE_NOTCH_MODE__B 8 |
| 10223 | #define B_CE_REG_FR_MODE_NOTCH_MODE__W 1 | 10223 | #define B_CE_REG_FR_MODE_NOTCH_MODE__W 1 |
| 10224 | #define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 | 10224 | #define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 |
| 10225 | #define B_CE_REG_FR_MODE_INIT 0xDE | 10225 | #define B_CE_REG_FR_MODE_INIT 0xDE |
| 10226 | 10226 | ||
| 10227 | #define B_CE_REG_FR_SQS_TRH__A 0x1820042 | 10227 | #define B_CE_REG_FR_SQS_TRH__A 0x1820042 |
| 10228 | #define B_CE_REG_FR_SQS_TRH__W 8 | 10228 | #define B_CE_REG_FR_SQS_TRH__W 8 |
| 10229 | #define B_CE_REG_FR_SQS_TRH__M 0xFF | 10229 | #define B_CE_REG_FR_SQS_TRH__M 0xFF |
| 10230 | #define B_CE_REG_FR_SQS_TRH_INIT 0x80 | 10230 | #define B_CE_REG_FR_SQS_TRH_INIT 0x80 |
| 10231 | 10231 | ||
| 10232 | #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 | 10232 | #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 |
| 10233 | #define B_CE_REG_FR_RIO_GAIN__W 3 | 10233 | #define B_CE_REG_FR_RIO_GAIN__W 3 |
| 10234 | #define B_CE_REG_FR_RIO_GAIN__M 0x7 | 10234 | #define B_CE_REG_FR_RIO_GAIN__M 0x7 |
| 10235 | #define B_CE_REG_FR_RIO_GAIN_INIT 0x2 | 10235 | #define B_CE_REG_FR_RIO_GAIN_INIT 0x2 |
| 10236 | 10236 | ||
| 10237 | #define B_CE_REG_FR_BYPASS__A 0x1820044 | 10237 | #define B_CE_REG_FR_BYPASS__A 0x1820044 |
| 10238 | #define B_CE_REG_FR_BYPASS__W 10 | 10238 | #define B_CE_REG_FR_BYPASS__W 10 |
| 10239 | #define B_CE_REG_FR_BYPASS__M 0x3FF | 10239 | #define B_CE_REG_FR_BYPASS__M 0x3FF |
| 10240 | 10240 | ||
| 10241 | #define B_CE_REG_FR_BYPASS_RUN_IN__B 0 | 10241 | #define B_CE_REG_FR_BYPASS_RUN_IN__B 0 |
| 10242 | #define B_CE_REG_FR_BYPASS_RUN_IN__W 4 | 10242 | #define B_CE_REG_FR_BYPASS_RUN_IN__W 4 |
| 10243 | #define B_CE_REG_FR_BYPASS_RUN_IN__M 0xF | 10243 | #define B_CE_REG_FR_BYPASS_RUN_IN__M 0xF |
| 10244 | 10244 | ||
| 10245 | #define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 | 10245 | #define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 |
| 10246 | #define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 | 10246 | #define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 |
| 10247 | #define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 | 10247 | #define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 |
| 10248 | 10248 | ||
| 10249 | #define B_CE_REG_FR_BYPASS_TOTAL__B 9 | 10249 | #define B_CE_REG_FR_BYPASS_TOTAL__B 9 |
| 10250 | #define B_CE_REG_FR_BYPASS_TOTAL__W 1 | 10250 | #define B_CE_REG_FR_BYPASS_TOTAL__W 1 |
| 10251 | #define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 | 10251 | #define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 |
| 10252 | #define B_CE_REG_FR_BYPASS_INIT 0x13B | 10252 | #define B_CE_REG_FR_BYPASS_INIT 0x13B |
| 10253 | 10253 | ||
| 10254 | #define B_CE_REG_FR_PM_SET__A 0x1820045 | 10254 | #define B_CE_REG_FR_PM_SET__A 0x1820045 |
| 10255 | #define B_CE_REG_FR_PM_SET__W 4 | 10255 | #define B_CE_REG_FR_PM_SET__W 4 |
| 10256 | #define B_CE_REG_FR_PM_SET__M 0xF | 10256 | #define B_CE_REG_FR_PM_SET__M 0xF |
| 10257 | #define B_CE_REG_FR_PM_SET_INIT 0x4 | 10257 | #define B_CE_REG_FR_PM_SET_INIT 0x4 |
| 10258 | 10258 | ||
| 10259 | #define B_CE_REG_FR_ERR_SH__A 0x1820046 | 10259 | #define B_CE_REG_FR_ERR_SH__A 0x1820046 |
| 10260 | #define B_CE_REG_FR_ERR_SH__W 4 | 10260 | #define B_CE_REG_FR_ERR_SH__W 4 |
| 10261 | #define B_CE_REG_FR_ERR_SH__M 0xF | 10261 | #define B_CE_REG_FR_ERR_SH__M 0xF |
| 10262 | #define B_CE_REG_FR_ERR_SH_INIT 0x4 | 10262 | #define B_CE_REG_FR_ERR_SH_INIT 0x4 |
| 10263 | 10263 | ||
| 10264 | #define B_CE_REG_FR_MAN_SH__A 0x1820047 | 10264 | #define B_CE_REG_FR_MAN_SH__A 0x1820047 |
| 10265 | #define B_CE_REG_FR_MAN_SH__W 4 | 10265 | #define B_CE_REG_FR_MAN_SH__W 4 |
| 10266 | #define B_CE_REG_FR_MAN_SH__M 0xF | 10266 | #define B_CE_REG_FR_MAN_SH__M 0xF |
| 10267 | #define B_CE_REG_FR_MAN_SH_INIT 0x7 | 10267 | #define B_CE_REG_FR_MAN_SH_INIT 0x7 |
| 10268 | 10268 | ||
| 10269 | #define B_CE_REG_FR_TAP_SH__A 0x1820048 | 10269 | #define B_CE_REG_FR_TAP_SH__A 0x1820048 |
| 10270 | #define B_CE_REG_FR_TAP_SH__W 3 | 10270 | #define B_CE_REG_FR_TAP_SH__W 3 |
| 10271 | #define B_CE_REG_FR_TAP_SH__M 0x7 | 10271 | #define B_CE_REG_FR_TAP_SH__M 0x7 |
| 10272 | #define B_CE_REG_FR_TAP_SH_INIT 0x3 | 10272 | #define B_CE_REG_FR_TAP_SH_INIT 0x3 |
| 10273 | 10273 | ||
| 10274 | #define B_CE_REG_FR_CLIP__A 0x1820049 | 10274 | #define B_CE_REG_FR_CLIP__A 0x1820049 |
| 10275 | #define B_CE_REG_FR_CLIP__W 9 | 10275 | #define B_CE_REG_FR_CLIP__W 9 |
| 10276 | #define B_CE_REG_FR_CLIP__M 0x1FF | 10276 | #define B_CE_REG_FR_CLIP__M 0x1FF |
| 10277 | #define B_CE_REG_FR_CLIP_INIT 0x49 | 10277 | #define B_CE_REG_FR_CLIP_INIT 0x49 |
| 10278 | 10278 | ||
| 10279 | #define B_CE_REG_FR_LEAK_UPD__A 0x182004A | 10279 | #define B_CE_REG_FR_LEAK_UPD__A 0x182004A |
| 10280 | #define B_CE_REG_FR_LEAK_UPD__W 3 | 10280 | #define B_CE_REG_FR_LEAK_UPD__W 3 |
| 10281 | #define B_CE_REG_FR_LEAK_UPD__M 0x7 | 10281 | #define B_CE_REG_FR_LEAK_UPD__M 0x7 |
| 10282 | #define B_CE_REG_FR_LEAK_UPD_INIT 0x1 | 10282 | #define B_CE_REG_FR_LEAK_UPD_INIT 0x1 |
| 10283 | 10283 | ||
| 10284 | #define B_CE_REG_FR_LEAK_SH__A 0x182004B | 10284 | #define B_CE_REG_FR_LEAK_SH__A 0x182004B |
| 10285 | #define B_CE_REG_FR_LEAK_SH__W 3 | 10285 | #define B_CE_REG_FR_LEAK_SH__W 3 |
| 10286 | #define B_CE_REG_FR_LEAK_SH__M 0x7 | 10286 | #define B_CE_REG_FR_LEAK_SH__M 0x7 |
| 10287 | #define B_CE_REG_FR_LEAK_SH_INIT 0x1 | 10287 | #define B_CE_REG_FR_LEAK_SH_INIT 0x1 |
| 10288 | 10288 | ||
| 10289 | #define B_CE_PB_RAM__A 0x1830000 | 10289 | #define B_CE_PB_RAM__A 0x1830000 |
| 10290 | 10290 | ||
| 10291 | #define B_CE_NE_RAM__A 0x1840000 | 10291 | #define B_CE_NE_RAM__A 0x1840000 |
| 10292 | 10292 | ||
| 10293 | #define B_EQ_SID 0xE | 10293 | #define B_EQ_SID 0xE |
| 10294 | 10294 | ||
| 10295 | #define B_EQ_COMM_EXEC__A 0x1C00000 | 10295 | #define B_EQ_COMM_EXEC__A 0x1C00000 |
| 10296 | #define B_EQ_COMM_EXEC__W 3 | 10296 | #define B_EQ_COMM_EXEC__W 3 |
| 10297 | #define B_EQ_COMM_EXEC__M 0x7 | 10297 | #define B_EQ_COMM_EXEC__M 0x7 |
| 10298 | #define B_EQ_COMM_EXEC_CTL__B 0 | 10298 | #define B_EQ_COMM_EXEC_CTL__B 0 |
| 10299 | #define B_EQ_COMM_EXEC_CTL__W 3 | 10299 | #define B_EQ_COMM_EXEC_CTL__W 3 |
| 10300 | #define B_EQ_COMM_EXEC_CTL__M 0x7 | 10300 | #define B_EQ_COMM_EXEC_CTL__M 0x7 |
| 10301 | #define B_EQ_COMM_EXEC_CTL_STOP 0x0 | 10301 | #define B_EQ_COMM_EXEC_CTL_STOP 0x0 |
| 10302 | #define B_EQ_COMM_EXEC_CTL_ACTIVE 0x1 | 10302 | #define B_EQ_COMM_EXEC_CTL_ACTIVE 0x1 |
| 10303 | #define B_EQ_COMM_EXEC_CTL_HOLD 0x2 | 10303 | #define B_EQ_COMM_EXEC_CTL_HOLD 0x2 |
| 10304 | #define B_EQ_COMM_EXEC_CTL_STEP 0x3 | 10304 | #define B_EQ_COMM_EXEC_CTL_STEP 0x3 |
| 10305 | #define B_EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 10305 | #define B_EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 10306 | #define B_EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 10306 | #define B_EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 10307 | 10307 | ||
| 10308 | #define B_EQ_COMM_STATE__A 0x1C00001 | 10308 | #define B_EQ_COMM_STATE__A 0x1C00001 |
| 10309 | #define B_EQ_COMM_STATE__W 16 | 10309 | #define B_EQ_COMM_STATE__W 16 |
| 10310 | #define B_EQ_COMM_STATE__M 0xFFFF | 10310 | #define B_EQ_COMM_STATE__M 0xFFFF |
| 10311 | #define B_EQ_COMM_MB__A 0x1C00002 | 10311 | #define B_EQ_COMM_MB__A 0x1C00002 |
| 10312 | #define B_EQ_COMM_MB__W 16 | 10312 | #define B_EQ_COMM_MB__W 16 |
| 10313 | #define B_EQ_COMM_MB__M 0xFFFF | 10313 | #define B_EQ_COMM_MB__M 0xFFFF |
| 10314 | #define B_EQ_COMM_SERVICE0__A 0x1C00003 | 10314 | #define B_EQ_COMM_SERVICE0__A 0x1C00003 |
| 10315 | #define B_EQ_COMM_SERVICE0__W 16 | 10315 | #define B_EQ_COMM_SERVICE0__W 16 |
| 10316 | #define B_EQ_COMM_SERVICE0__M 0xFFFF | 10316 | #define B_EQ_COMM_SERVICE0__M 0xFFFF |
| 10317 | #define B_EQ_COMM_SERVICE1__A 0x1C00004 | 10317 | #define B_EQ_COMM_SERVICE1__A 0x1C00004 |
| 10318 | #define B_EQ_COMM_SERVICE1__W 16 | 10318 | #define B_EQ_COMM_SERVICE1__W 16 |
| 10319 | #define B_EQ_COMM_SERVICE1__M 0xFFFF | 10319 | #define B_EQ_COMM_SERVICE1__M 0xFFFF |
| 10320 | #define B_EQ_COMM_INT_STA__A 0x1C00007 | 10320 | #define B_EQ_COMM_INT_STA__A 0x1C00007 |
| 10321 | #define B_EQ_COMM_INT_STA__W 16 | 10321 | #define B_EQ_COMM_INT_STA__W 16 |
| 10322 | #define B_EQ_COMM_INT_STA__M 0xFFFF | 10322 | #define B_EQ_COMM_INT_STA__M 0xFFFF |
| 10323 | #define B_EQ_COMM_INT_MSK__A 0x1C00008 | 10323 | #define B_EQ_COMM_INT_MSK__A 0x1C00008 |
| 10324 | #define B_EQ_COMM_INT_MSK__W 16 | 10324 | #define B_EQ_COMM_INT_MSK__W 16 |
| 10325 | #define B_EQ_COMM_INT_MSK__M 0xFFFF | 10325 | #define B_EQ_COMM_INT_MSK__M 0xFFFF |
| 10326 | 10326 | ||
| 10327 | #define B_EQ_REG_COMM_EXEC__A 0x1C10000 | 10327 | #define B_EQ_REG_COMM_EXEC__A 0x1C10000 |
| 10328 | #define B_EQ_REG_COMM_EXEC__W 3 | 10328 | #define B_EQ_REG_COMM_EXEC__W 3 |
| 10329 | #define B_EQ_REG_COMM_EXEC__M 0x7 | 10329 | #define B_EQ_REG_COMM_EXEC__M 0x7 |
| 10330 | #define B_EQ_REG_COMM_EXEC_CTL__B 0 | 10330 | #define B_EQ_REG_COMM_EXEC_CTL__B 0 |
| 10331 | #define B_EQ_REG_COMM_EXEC_CTL__W 3 | 10331 | #define B_EQ_REG_COMM_EXEC_CTL__W 3 |
| 10332 | #define B_EQ_REG_COMM_EXEC_CTL__M 0x7 | 10332 | #define B_EQ_REG_COMM_EXEC_CTL__M 0x7 |
| 10333 | #define B_EQ_REG_COMM_EXEC_CTL_STOP 0x0 | 10333 | #define B_EQ_REG_COMM_EXEC_CTL_STOP 0x0 |
| 10334 | #define B_EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 10334 | #define B_EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 10335 | #define B_EQ_REG_COMM_EXEC_CTL_HOLD 0x2 | 10335 | #define B_EQ_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 10336 | #define B_EQ_REG_COMM_EXEC_CTL_STEP 0x3 | 10336 | #define B_EQ_REG_COMM_EXEC_CTL_STEP 0x3 |
| 10337 | 10337 | ||
| 10338 | #define B_EQ_REG_COMM_STATE__A 0x1C10001 | 10338 | #define B_EQ_REG_COMM_STATE__A 0x1C10001 |
| 10339 | #define B_EQ_REG_COMM_STATE__W 4 | 10339 | #define B_EQ_REG_COMM_STATE__W 4 |
| 10340 | #define B_EQ_REG_COMM_STATE__M 0xF | 10340 | #define B_EQ_REG_COMM_STATE__M 0xF |
| 10341 | 10341 | ||
| 10342 | #define B_EQ_REG_COMM_MB__A 0x1C10002 | 10342 | #define B_EQ_REG_COMM_MB__A 0x1C10002 |
| 10343 | #define B_EQ_REG_COMM_MB__W 6 | 10343 | #define B_EQ_REG_COMM_MB__W 6 |
| 10344 | #define B_EQ_REG_COMM_MB__M 0x3F | 10344 | #define B_EQ_REG_COMM_MB__M 0x3F |
| 10345 | #define B_EQ_REG_COMM_MB_CTR__B 0 | 10345 | #define B_EQ_REG_COMM_MB_CTR__B 0 |
| 10346 | #define B_EQ_REG_COMM_MB_CTR__W 1 | 10346 | #define B_EQ_REG_COMM_MB_CTR__W 1 |
| 10347 | #define B_EQ_REG_COMM_MB_CTR__M 0x1 | 10347 | #define B_EQ_REG_COMM_MB_CTR__M 0x1 |
| 10348 | #define B_EQ_REG_COMM_MB_CTR_OFF 0x0 | 10348 | #define B_EQ_REG_COMM_MB_CTR_OFF 0x0 |
| 10349 | #define B_EQ_REG_COMM_MB_CTR_ON 0x1 | 10349 | #define B_EQ_REG_COMM_MB_CTR_ON 0x1 |
| 10350 | #define B_EQ_REG_COMM_MB_OBS__B 1 | 10350 | #define B_EQ_REG_COMM_MB_OBS__B 1 |
| 10351 | #define B_EQ_REG_COMM_MB_OBS__W 1 | 10351 | #define B_EQ_REG_COMM_MB_OBS__W 1 |
| 10352 | #define B_EQ_REG_COMM_MB_OBS__M 0x2 | 10352 | #define B_EQ_REG_COMM_MB_OBS__M 0x2 |
| 10353 | #define B_EQ_REG_COMM_MB_OBS_OFF 0x0 | 10353 | #define B_EQ_REG_COMM_MB_OBS_OFF 0x0 |
| 10354 | #define B_EQ_REG_COMM_MB_OBS_ON 0x2 | 10354 | #define B_EQ_REG_COMM_MB_OBS_ON 0x2 |
| 10355 | #define B_EQ_REG_COMM_MB_CTR_MUX__B 2 | 10355 | #define B_EQ_REG_COMM_MB_CTR_MUX__B 2 |
| 10356 | #define B_EQ_REG_COMM_MB_CTR_MUX__W 2 | 10356 | #define B_EQ_REG_COMM_MB_CTR_MUX__W 2 |
| 10357 | #define B_EQ_REG_COMM_MB_CTR_MUX__M 0xC | 10357 | #define B_EQ_REG_COMM_MB_CTR_MUX__M 0xC |
| 10358 | #define B_EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 | 10358 | #define B_EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 |
| 10359 | #define B_EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 | 10359 | #define B_EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 |
| 10360 | #define B_EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 | 10360 | #define B_EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 |
| 10361 | #define B_EQ_REG_COMM_MB_OBS_MUX__B 4 | 10361 | #define B_EQ_REG_COMM_MB_OBS_MUX__B 4 |
| 10362 | #define B_EQ_REG_COMM_MB_OBS_MUX__W 2 | 10362 | #define B_EQ_REG_COMM_MB_OBS_MUX__W 2 |
| 10363 | #define B_EQ_REG_COMM_MB_OBS_MUX__M 0x30 | 10363 | #define B_EQ_REG_COMM_MB_OBS_MUX__M 0x30 |
| 10364 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 | 10364 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 |
| 10365 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 | 10365 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 |
| 10366 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 | 10366 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 |
| 10367 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 | 10367 | #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 |
| 10368 | 10368 | ||
| 10369 | #define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 | 10369 | #define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 |
| 10370 | #define B_EQ_REG_COMM_SERVICE0__W 10 | 10370 | #define B_EQ_REG_COMM_SERVICE0__W 10 |
| 10371 | #define B_EQ_REG_COMM_SERVICE0__M 0x3FF | 10371 | #define B_EQ_REG_COMM_SERVICE0__M 0x3FF |
| 10372 | 10372 | ||
| 10373 | #define B_EQ_REG_COMM_SERVICE1__A 0x1C10004 | 10373 | #define B_EQ_REG_COMM_SERVICE1__A 0x1C10004 |
| 10374 | #define B_EQ_REG_COMM_SERVICE1__W 11 | 10374 | #define B_EQ_REG_COMM_SERVICE1__W 11 |
| 10375 | #define B_EQ_REG_COMM_SERVICE1__M 0x7FF | 10375 | #define B_EQ_REG_COMM_SERVICE1__M 0x7FF |
| 10376 | 10376 | ||
| 10377 | #define B_EQ_REG_COMM_INT_STA__A 0x1C10007 | 10377 | #define B_EQ_REG_COMM_INT_STA__A 0x1C10007 |
| 10378 | #define B_EQ_REG_COMM_INT_STA__W 2 | 10378 | #define B_EQ_REG_COMM_INT_STA__W 2 |
| 10379 | #define B_EQ_REG_COMM_INT_STA__M 0x3 | 10379 | #define B_EQ_REG_COMM_INT_STA__M 0x3 |
| 10380 | #define B_EQ_REG_COMM_INT_STA_TPS_RDY__B 0 | 10380 | #define B_EQ_REG_COMM_INT_STA_TPS_RDY__B 0 |
| 10381 | #define B_EQ_REG_COMM_INT_STA_TPS_RDY__W 1 | 10381 | #define B_EQ_REG_COMM_INT_STA_TPS_RDY__W 1 |
| 10382 | #define B_EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 | 10382 | #define B_EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 |
| 10383 | #define B_EQ_REG_COMM_INT_STA_ERR_RDY__B 1 | 10383 | #define B_EQ_REG_COMM_INT_STA_ERR_RDY__B 1 |
| 10384 | #define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 | 10384 | #define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 |
| 10385 | #define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 | 10385 | #define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 |
| 10386 | 10386 | ||
| 10387 | #define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 | 10387 | #define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 |
| 10388 | #define B_EQ_REG_COMM_INT_MSK__W 2 | 10388 | #define B_EQ_REG_COMM_INT_MSK__W 2 |
| 10389 | #define B_EQ_REG_COMM_INT_MSK__M 0x3 | 10389 | #define B_EQ_REG_COMM_INT_MSK__M 0x3 |
| 10390 | #define B_EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 | 10390 | #define B_EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 |
| 10391 | #define B_EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 | 10391 | #define B_EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 |
| 10392 | #define B_EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 | 10392 | #define B_EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 |
| 10393 | #define B_EQ_REG_COMM_INT_MSK_MER_RDY__B 1 | 10393 | #define B_EQ_REG_COMM_INT_MSK_MER_RDY__B 1 |
| 10394 | #define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 | 10394 | #define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 |
| 10395 | #define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 | 10395 | #define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 |
| 10396 | 10396 | ||
| 10397 | #define B_EQ_REG_IS_MODE__A 0x1C10014 | 10397 | #define B_EQ_REG_IS_MODE__A 0x1C10014 |
| 10398 | #define B_EQ_REG_IS_MODE__W 4 | 10398 | #define B_EQ_REG_IS_MODE__W 4 |
| 10399 | #define B_EQ_REG_IS_MODE__M 0xF | 10399 | #define B_EQ_REG_IS_MODE__M 0xF |
| 10400 | #define B_EQ_REG_IS_MODE_INIT 0x0 | 10400 | #define B_EQ_REG_IS_MODE_INIT 0x0 |
| 10401 | 10401 | ||
| 10402 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 | 10402 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 |
| 10403 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 | 10403 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 |
| 10404 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 | 10404 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 |
| 10405 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 | 10405 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 |
| 10406 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 | 10406 | #define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 |
| 10407 | 10407 | ||
| 10408 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 | 10408 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 |
| 10409 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 | 10409 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 |
| 10410 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 | 10410 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 |
| 10411 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 | 10411 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 |
| 10412 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 | 10412 | #define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 |
| 10413 | 10413 | ||
| 10414 | #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 | 10414 | #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 |
| 10415 | #define B_EQ_REG_IS_GAIN_MAN__W 10 | 10415 | #define B_EQ_REG_IS_GAIN_MAN__W 10 |
| 10416 | #define B_EQ_REG_IS_GAIN_MAN__M 0x3FF | 10416 | #define B_EQ_REG_IS_GAIN_MAN__M 0x3FF |
| 10417 | #define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 | 10417 | #define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 |
| 10418 | 10418 | ||
| 10419 | #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 | 10419 | #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 |
| 10420 | #define B_EQ_REG_IS_GAIN_EXP__W 5 | 10420 | #define B_EQ_REG_IS_GAIN_EXP__W 5 |
| 10421 | #define B_EQ_REG_IS_GAIN_EXP__M 0x1F | 10421 | #define B_EQ_REG_IS_GAIN_EXP__M 0x1F |
| 10422 | #define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 | 10422 | #define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 |
| 10423 | 10423 | ||
| 10424 | #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 | 10424 | #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 |
| 10425 | #define B_EQ_REG_IS_CLIP_EXP__W 5 | 10425 | #define B_EQ_REG_IS_CLIP_EXP__W 5 |
| 10426 | #define B_EQ_REG_IS_CLIP_EXP__M 0x1F | 10426 | #define B_EQ_REG_IS_CLIP_EXP__M 0x1F |
| 10427 | #define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 | 10427 | #define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 |
| 10428 | 10428 | ||
| 10429 | #define B_EQ_REG_DV_MODE__A 0x1C1001E | 10429 | #define B_EQ_REG_DV_MODE__A 0x1C1001E |
| 10430 | #define B_EQ_REG_DV_MODE__W 4 | 10430 | #define B_EQ_REG_DV_MODE__W 4 |
| 10431 | #define B_EQ_REG_DV_MODE__M 0xF | 10431 | #define B_EQ_REG_DV_MODE__M 0xF |
| 10432 | #define B_EQ_REG_DV_MODE_INIT 0xF | 10432 | #define B_EQ_REG_DV_MODE_INIT 0xF |
| 10433 | 10433 | ||
| 10434 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 | 10434 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 |
| 10435 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 | 10435 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 |
| 10436 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 | 10436 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 |
| 10437 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 | 10437 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 |
| 10438 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 | 10438 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 |
| 10439 | 10439 | ||
| 10440 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 | 10440 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 |
| 10441 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 | 10441 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 |
| 10442 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 | 10442 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 |
| 10443 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 | 10443 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 |
| 10444 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 | 10444 | #define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 |
| 10445 | 10445 | ||
| 10446 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA__B 2 | 10446 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA__B 2 |
| 10447 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA__W 1 | 10447 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA__W 1 |
| 10448 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 | 10448 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 |
| 10449 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 | 10449 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 |
| 10450 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 | 10450 | #define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 |
| 10451 | 10451 | ||
| 10452 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 | 10452 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 |
| 10453 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 | 10453 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 |
| 10454 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 | 10454 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 |
| 10455 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 | 10455 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 |
| 10456 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 | 10456 | #define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 |
| 10457 | 10457 | ||
| 10458 | #define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F | 10458 | #define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F |
| 10459 | #define B_EQ_REG_DV_POS_CLIP_DAT__W 16 | 10459 | #define B_EQ_REG_DV_POS_CLIP_DAT__W 16 |
| 10460 | #define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF | 10460 | #define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF |
| 10461 | 10461 | ||
| 10462 | #define B_EQ_REG_SN_MODE__A 0x1C10028 | 10462 | #define B_EQ_REG_SN_MODE__A 0x1C10028 |
| 10463 | #define B_EQ_REG_SN_MODE__W 8 | 10463 | #define B_EQ_REG_SN_MODE__W 8 |
| 10464 | #define B_EQ_REG_SN_MODE__M 0xFF | 10464 | #define B_EQ_REG_SN_MODE__M 0xFF |
| 10465 | #define B_EQ_REG_SN_MODE_INIT 0x18 | 10465 | #define B_EQ_REG_SN_MODE_INIT 0x18 |
| 10466 | 10466 | ||
| 10467 | #define B_EQ_REG_SN_MODE_MODE_0__B 0 | 10467 | #define B_EQ_REG_SN_MODE_MODE_0__B 0 |
| 10468 | #define B_EQ_REG_SN_MODE_MODE_0__W 1 | 10468 | #define B_EQ_REG_SN_MODE_MODE_0__W 1 |
| 10469 | #define B_EQ_REG_SN_MODE_MODE_0__M 0x1 | 10469 | #define B_EQ_REG_SN_MODE_MODE_0__M 0x1 |
| 10470 | #define B_EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 | 10470 | #define B_EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 |
| 10471 | #define B_EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 | 10471 | #define B_EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 |
| 10472 | 10472 | ||
| 10473 | #define B_EQ_REG_SN_MODE_MODE_1__B 1 | 10473 | #define B_EQ_REG_SN_MODE_MODE_1__B 1 |
| 10474 | #define B_EQ_REG_SN_MODE_MODE_1__W 1 | 10474 | #define B_EQ_REG_SN_MODE_MODE_1__W 1 |
| 10475 | #define B_EQ_REG_SN_MODE_MODE_1__M 0x2 | 10475 | #define B_EQ_REG_SN_MODE_MODE_1__M 0x2 |
| 10476 | #define B_EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 | 10476 | #define B_EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 |
| 10477 | #define B_EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 | 10477 | #define B_EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 |
| 10478 | 10478 | ||
| 10479 | #define B_EQ_REG_SN_MODE_MODE_2__B 2 | 10479 | #define B_EQ_REG_SN_MODE_MODE_2__B 2 |
| 10480 | #define B_EQ_REG_SN_MODE_MODE_2__W 1 | 10480 | #define B_EQ_REG_SN_MODE_MODE_2__W 1 |
| 10481 | #define B_EQ_REG_SN_MODE_MODE_2__M 0x4 | 10481 | #define B_EQ_REG_SN_MODE_MODE_2__M 0x4 |
| 10482 | #define B_EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 | 10482 | #define B_EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 |
| 10483 | #define B_EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 | 10483 | #define B_EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 |
| 10484 | 10484 | ||
| 10485 | #define B_EQ_REG_SN_MODE_MODE_3__B 3 | 10485 | #define B_EQ_REG_SN_MODE_MODE_3__B 3 |
| 10486 | #define B_EQ_REG_SN_MODE_MODE_3__W 1 | 10486 | #define B_EQ_REG_SN_MODE_MODE_3__W 1 |
| 10487 | #define B_EQ_REG_SN_MODE_MODE_3__M 0x8 | 10487 | #define B_EQ_REG_SN_MODE_MODE_3__M 0x8 |
| 10488 | #define B_EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 | 10488 | #define B_EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 |
| 10489 | #define B_EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 | 10489 | #define B_EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 |
| 10490 | 10490 | ||
| 10491 | #define B_EQ_REG_SN_MODE_MODE_4__B 4 | 10491 | #define B_EQ_REG_SN_MODE_MODE_4__B 4 |
| 10492 | #define B_EQ_REG_SN_MODE_MODE_4__W 1 | 10492 | #define B_EQ_REG_SN_MODE_MODE_4__W 1 |
| 10493 | #define B_EQ_REG_SN_MODE_MODE_4__M 0x10 | 10493 | #define B_EQ_REG_SN_MODE_MODE_4__M 0x10 |
| 10494 | #define B_EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 | 10494 | #define B_EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 |
| 10495 | #define B_EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 | 10495 | #define B_EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 |
| 10496 | 10496 | ||
| 10497 | #define B_EQ_REG_SN_MODE_MODE_5__B 5 | 10497 | #define B_EQ_REG_SN_MODE_MODE_5__B 5 |
| 10498 | #define B_EQ_REG_SN_MODE_MODE_5__W 1 | 10498 | #define B_EQ_REG_SN_MODE_MODE_5__W 1 |
| 10499 | #define B_EQ_REG_SN_MODE_MODE_5__M 0x20 | 10499 | #define B_EQ_REG_SN_MODE_MODE_5__M 0x20 |
| 10500 | #define B_EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 | 10500 | #define B_EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 |
| 10501 | #define B_EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 | 10501 | #define B_EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 |
| 10502 | 10502 | ||
| 10503 | #define B_EQ_REG_SN_MODE_MODE_6__B 6 | 10503 | #define B_EQ_REG_SN_MODE_MODE_6__B 6 |
| 10504 | #define B_EQ_REG_SN_MODE_MODE_6__W 1 | 10504 | #define B_EQ_REG_SN_MODE_MODE_6__W 1 |
| 10505 | #define B_EQ_REG_SN_MODE_MODE_6__M 0x40 | 10505 | #define B_EQ_REG_SN_MODE_MODE_6__M 0x40 |
| 10506 | #define B_EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 | 10506 | #define B_EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 |
| 10507 | #define B_EQ_REG_SN_MODE_MODE_6_STATIC 0x40 | 10507 | #define B_EQ_REG_SN_MODE_MODE_6_STATIC 0x40 |
| 10508 | 10508 | ||
| 10509 | #define B_EQ_REG_SN_MODE_MODE_7__B 7 | 10509 | #define B_EQ_REG_SN_MODE_MODE_7__B 7 |
| 10510 | #define B_EQ_REG_SN_MODE_MODE_7__W 1 | 10510 | #define B_EQ_REG_SN_MODE_MODE_7__W 1 |
| 10511 | #define B_EQ_REG_SN_MODE_MODE_7__M 0x80 | 10511 | #define B_EQ_REG_SN_MODE_MODE_7__M 0x80 |
| 10512 | #define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 | 10512 | #define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 |
| 10513 | #define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 | 10513 | #define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 |
| 10514 | 10514 | ||
| 10515 | #define B_EQ_REG_SN_PFIX__A 0x1C10029 | 10515 | #define B_EQ_REG_SN_PFIX__A 0x1C10029 |
| 10516 | #define B_EQ_REG_SN_PFIX__W 8 | 10516 | #define B_EQ_REG_SN_PFIX__W 8 |
| 10517 | #define B_EQ_REG_SN_PFIX__M 0xFF | 10517 | #define B_EQ_REG_SN_PFIX__M 0xFF |
| 10518 | #define B_EQ_REG_SN_PFIX_INIT 0x0 | 10518 | #define B_EQ_REG_SN_PFIX_INIT 0x0 |
| 10519 | 10519 | ||
| 10520 | #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A | 10520 | #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A |
| 10521 | #define B_EQ_REG_SN_CEGAIN__W 8 | 10521 | #define B_EQ_REG_SN_CEGAIN__W 8 |
| 10522 | #define B_EQ_REG_SN_CEGAIN__M 0xFF | 10522 | #define B_EQ_REG_SN_CEGAIN__M 0xFF |
| 10523 | #define B_EQ_REG_SN_CEGAIN_INIT 0x30 | 10523 | #define B_EQ_REG_SN_CEGAIN_INIT 0x30 |
| 10524 | 10524 | ||
| 10525 | #define B_EQ_REG_SN_OFFSET__A 0x1C1002B | 10525 | #define B_EQ_REG_SN_OFFSET__A 0x1C1002B |
| 10526 | #define B_EQ_REG_SN_OFFSET__W 6 | 10526 | #define B_EQ_REG_SN_OFFSET__W 6 |
| 10527 | #define B_EQ_REG_SN_OFFSET__M 0x3F | 10527 | #define B_EQ_REG_SN_OFFSET__M 0x3F |
| 10528 | #define B_EQ_REG_SN_OFFSET_INIT 0x39 | 10528 | #define B_EQ_REG_SN_OFFSET_INIT 0x39 |
| 10529 | 10529 | ||
| 10530 | #define B_EQ_REG_SN_NULLIFY__A 0x1C1002C | 10530 | #define B_EQ_REG_SN_NULLIFY__A 0x1C1002C |
| 10531 | #define B_EQ_REG_SN_NULLIFY__W 6 | 10531 | #define B_EQ_REG_SN_NULLIFY__W 6 |
| 10532 | #define B_EQ_REG_SN_NULLIFY__M 0x3F | 10532 | #define B_EQ_REG_SN_NULLIFY__M 0x3F |
| 10533 | #define B_EQ_REG_SN_NULLIFY_INIT 0x0 | 10533 | #define B_EQ_REG_SN_NULLIFY_INIT 0x0 |
| 10534 | 10534 | ||
| 10535 | #define B_EQ_REG_SN_SQUASH__A 0x1C1002D | 10535 | #define B_EQ_REG_SN_SQUASH__A 0x1C1002D |
| 10536 | #define B_EQ_REG_SN_SQUASH__W 10 | 10536 | #define B_EQ_REG_SN_SQUASH__W 10 |
| 10537 | #define B_EQ_REG_SN_SQUASH__M 0x3FF | 10537 | #define B_EQ_REG_SN_SQUASH__M 0x3FF |
| 10538 | #define B_EQ_REG_SN_SQUASH_INIT 0x7 | 10538 | #define B_EQ_REG_SN_SQUASH_INIT 0x7 |
| 10539 | 10539 | ||
| 10540 | #define B_EQ_REG_SN_SQUASH_MAN__B 0 | 10540 | #define B_EQ_REG_SN_SQUASH_MAN__B 0 |
| 10541 | #define B_EQ_REG_SN_SQUASH_MAN__W 6 | 10541 | #define B_EQ_REG_SN_SQUASH_MAN__W 6 |
| 10542 | #define B_EQ_REG_SN_SQUASH_MAN__M 0x3F | 10542 | #define B_EQ_REG_SN_SQUASH_MAN__M 0x3F |
| 10543 | 10543 | ||
| 10544 | #define B_EQ_REG_SN_SQUASH_EXP__B 6 | 10544 | #define B_EQ_REG_SN_SQUASH_EXP__B 6 |
| 10545 | #define B_EQ_REG_SN_SQUASH_EXP__W 4 | 10545 | #define B_EQ_REG_SN_SQUASH_EXP__W 4 |
| 10546 | #define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 | 10546 | #define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 |
| 10547 | 10547 | ||
| 10548 | #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 | 10548 | #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 |
| 10549 | #define B_EQ_REG_RC_SEL_CAR__W 8 | 10549 | #define B_EQ_REG_RC_SEL_CAR__W 8 |
| 10550 | #define B_EQ_REG_RC_SEL_CAR__M 0xFF | 10550 | #define B_EQ_REG_RC_SEL_CAR__M 0xFF |
| 10551 | #define B_EQ_REG_RC_SEL_CAR_INIT 0x2 | 10551 | #define B_EQ_REG_RC_SEL_CAR_INIT 0x2 |
| 10552 | #define B_EQ_REG_RC_SEL_CAR_DIV__B 0 | 10552 | #define B_EQ_REG_RC_SEL_CAR_DIV__B 0 |
| 10553 | #define B_EQ_REG_RC_SEL_CAR_DIV__W 1 | 10553 | #define B_EQ_REG_RC_SEL_CAR_DIV__W 1 |
| 10554 | #define B_EQ_REG_RC_SEL_CAR_DIV__M 0x1 | 10554 | #define B_EQ_REG_RC_SEL_CAR_DIV__M 0x1 |
| 10555 | #define B_EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 | 10555 | #define B_EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 |
| 10556 | #define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 | 10556 | #define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 |
| 10557 | 10557 | ||
| 10558 | #define B_EQ_REG_RC_SEL_CAR_PASS__B 1 | 10558 | #define B_EQ_REG_RC_SEL_CAR_PASS__B 1 |
| 10559 | #define B_EQ_REG_RC_SEL_CAR_PASS__W 2 | 10559 | #define B_EQ_REG_RC_SEL_CAR_PASS__W 2 |
| 10560 | #define B_EQ_REG_RC_SEL_CAR_PASS__M 0x6 | 10560 | #define B_EQ_REG_RC_SEL_CAR_PASS__M 0x6 |
| 10561 | #define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 | 10561 | #define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 |
| 10562 | #define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 | 10562 | #define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 |
| 10563 | #define B_EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 | 10563 | #define B_EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 |
| 10564 | #define B_EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 | 10564 | #define B_EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 |
| 10565 | 10565 | ||
| 10566 | #define B_EQ_REG_RC_SEL_CAR_LOCAL__B 3 | 10566 | #define B_EQ_REG_RC_SEL_CAR_LOCAL__B 3 |
| 10567 | #define B_EQ_REG_RC_SEL_CAR_LOCAL__W 2 | 10567 | #define B_EQ_REG_RC_SEL_CAR_LOCAL__W 2 |
| 10568 | #define B_EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 | 10568 | #define B_EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 |
| 10569 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 | 10569 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 |
| 10570 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 | 10570 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 |
| 10571 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 | 10571 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 |
| 10572 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 | 10572 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 |
| 10573 | 10573 | ||
| 10574 | #define B_EQ_REG_RC_SEL_CAR_MEAS__B 5 | 10574 | #define B_EQ_REG_RC_SEL_CAR_MEAS__B 5 |
| 10575 | #define B_EQ_REG_RC_SEL_CAR_MEAS__W 2 | 10575 | #define B_EQ_REG_RC_SEL_CAR_MEAS__W 2 |
| 10576 | #define B_EQ_REG_RC_SEL_CAR_MEAS__M 0x60 | 10576 | #define B_EQ_REG_RC_SEL_CAR_MEAS__M 0x60 |
| 10577 | #define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 | 10577 | #define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 |
| 10578 | #define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 | 10578 | #define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 |
| 10579 | #define B_EQ_REG_RC_SEL_CAR_MEAS_C_DRI 0x40 | 10579 | #define B_EQ_REG_RC_SEL_CAR_MEAS_C_DRI 0x40 |
| 10580 | #define B_EQ_REG_RC_SEL_CAR_MEAS_D_CC 0x60 | 10580 | #define B_EQ_REG_RC_SEL_CAR_MEAS_D_CC 0x60 |
| 10581 | 10581 | ||
| 10582 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE__B 7 | 10582 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE__B 7 |
| 10583 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE__W 1 | 10583 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE__W 1 |
| 10584 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 | 10584 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 |
| 10585 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 | 10585 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 |
| 10586 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 | 10586 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 |
| 10587 | 10587 | ||
| 10588 | #define B_EQ_REG_RC_STS__A 0x1C10033 | 10588 | #define B_EQ_REG_RC_STS__A 0x1C10033 |
| 10589 | #define B_EQ_REG_RC_STS__W 14 | 10589 | #define B_EQ_REG_RC_STS__W 14 |
| 10590 | #define B_EQ_REG_RC_STS__M 0x3FFF | 10590 | #define B_EQ_REG_RC_STS__M 0x3FFF |
| 10591 | 10591 | ||
| 10592 | #define B_EQ_REG_RC_STS_DIFF__B 0 | 10592 | #define B_EQ_REG_RC_STS_DIFF__B 0 |
| 10593 | #define B_EQ_REG_RC_STS_DIFF__W 9 | 10593 | #define B_EQ_REG_RC_STS_DIFF__W 9 |
| 10594 | #define B_EQ_REG_RC_STS_DIFF__M 0x1FF | 10594 | #define B_EQ_REG_RC_STS_DIFF__M 0x1FF |
| 10595 | 10595 | ||
| 10596 | #define B_EQ_REG_RC_STS_FIRST__B 9 | 10596 | #define B_EQ_REG_RC_STS_FIRST__B 9 |
| 10597 | #define B_EQ_REG_RC_STS_FIRST__W 1 | 10597 | #define B_EQ_REG_RC_STS_FIRST__W 1 |
| 10598 | #define B_EQ_REG_RC_STS_FIRST__M 0x200 | 10598 | #define B_EQ_REG_RC_STS_FIRST__M 0x200 |
| 10599 | #define B_EQ_REG_RC_STS_FIRST_A_CE 0x0 | 10599 | #define B_EQ_REG_RC_STS_FIRST_A_CE 0x0 |
| 10600 | #define B_EQ_REG_RC_STS_FIRST_B_DRI 0x200 | 10600 | #define B_EQ_REG_RC_STS_FIRST_B_DRI 0x200 |
| 10601 | 10601 | ||
| 10602 | #define B_EQ_REG_RC_STS_SELEC__B 10 | 10602 | #define B_EQ_REG_RC_STS_SELEC__B 10 |
| 10603 | #define B_EQ_REG_RC_STS_SELEC__W 1 | 10603 | #define B_EQ_REG_RC_STS_SELEC__W 1 |
| 10604 | #define B_EQ_REG_RC_STS_SELEC__M 0x400 | 10604 | #define B_EQ_REG_RC_STS_SELEC__M 0x400 |
| 10605 | #define B_EQ_REG_RC_STS_SELEC_A_CE 0x0 | 10605 | #define B_EQ_REG_RC_STS_SELEC_A_CE 0x0 |
| 10606 | #define B_EQ_REG_RC_STS_SELEC_B_DRI 0x400 | 10606 | #define B_EQ_REG_RC_STS_SELEC_B_DRI 0x400 |
| 10607 | 10607 | ||
| 10608 | #define B_EQ_REG_RC_STS_OVERFLOW__B 11 | 10608 | #define B_EQ_REG_RC_STS_OVERFLOW__B 11 |
| 10609 | #define B_EQ_REG_RC_STS_OVERFLOW__W 1 | 10609 | #define B_EQ_REG_RC_STS_OVERFLOW__W 1 |
| 10610 | #define B_EQ_REG_RC_STS_OVERFLOW__M 0x800 | 10610 | #define B_EQ_REG_RC_STS_OVERFLOW__M 0x800 |
| 10611 | #define B_EQ_REG_RC_STS_OVERFLOW_NO 0x0 | 10611 | #define B_EQ_REG_RC_STS_OVERFLOW_NO 0x0 |
| 10612 | #define B_EQ_REG_RC_STS_OVERFLOW_YES 0x800 | 10612 | #define B_EQ_REG_RC_STS_OVERFLOW_YES 0x800 |
| 10613 | 10613 | ||
| 10614 | #define B_EQ_REG_RC_STS_LOC_PRS__B 12 | 10614 | #define B_EQ_REG_RC_STS_LOC_PRS__B 12 |
| 10615 | #define B_EQ_REG_RC_STS_LOC_PRS__W 1 | 10615 | #define B_EQ_REG_RC_STS_LOC_PRS__W 1 |
| 10616 | #define B_EQ_REG_RC_STS_LOC_PRS__M 0x1000 | 10616 | #define B_EQ_REG_RC_STS_LOC_PRS__M 0x1000 |
| 10617 | #define B_EQ_REG_RC_STS_LOC_PRS_NO 0x0 | 10617 | #define B_EQ_REG_RC_STS_LOC_PRS_NO 0x0 |
| 10618 | #define B_EQ_REG_RC_STS_LOC_PRS_YES 0x1000 | 10618 | #define B_EQ_REG_RC_STS_LOC_PRS_YES 0x1000 |
| 10619 | 10619 | ||
| 10620 | #define B_EQ_REG_RC_STS_DRI_PRS__B 13 | 10620 | #define B_EQ_REG_RC_STS_DRI_PRS__B 13 |
| 10621 | #define B_EQ_REG_RC_STS_DRI_PRS__W 1 | 10621 | #define B_EQ_REG_RC_STS_DRI_PRS__W 1 |
| 10622 | #define B_EQ_REG_RC_STS_DRI_PRS__M 0x2000 | 10622 | #define B_EQ_REG_RC_STS_DRI_PRS__M 0x2000 |
| 10623 | #define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 | 10623 | #define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 |
| 10624 | #define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 | 10624 | #define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 |
| 10625 | 10625 | ||
| 10626 | #define B_EQ_REG_OT_CONST__A 0x1C10046 | 10626 | #define B_EQ_REG_OT_CONST__A 0x1C10046 |
| 10627 | #define B_EQ_REG_OT_CONST__W 2 | 10627 | #define B_EQ_REG_OT_CONST__W 2 |
| 10628 | #define B_EQ_REG_OT_CONST__M 0x3 | 10628 | #define B_EQ_REG_OT_CONST__M 0x3 |
| 10629 | #define B_EQ_REG_OT_CONST_INIT 0x2 | 10629 | #define B_EQ_REG_OT_CONST_INIT 0x2 |
| 10630 | 10630 | ||
| 10631 | #define B_EQ_REG_OT_ALPHA__A 0x1C10047 | 10631 | #define B_EQ_REG_OT_ALPHA__A 0x1C10047 |
| 10632 | #define B_EQ_REG_OT_ALPHA__W 2 | 10632 | #define B_EQ_REG_OT_ALPHA__W 2 |
| 10633 | #define B_EQ_REG_OT_ALPHA__M 0x3 | 10633 | #define B_EQ_REG_OT_ALPHA__M 0x3 |
| 10634 | #define B_EQ_REG_OT_ALPHA_INIT 0x0 | 10634 | #define B_EQ_REG_OT_ALPHA_INIT 0x0 |
| 10635 | 10635 | ||
| 10636 | #define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 | 10636 | #define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 |
| 10637 | #define B_EQ_REG_OT_QNT_THRES0__W 5 | 10637 | #define B_EQ_REG_OT_QNT_THRES0__W 5 |
| 10638 | #define B_EQ_REG_OT_QNT_THRES0__M 0x1F | 10638 | #define B_EQ_REG_OT_QNT_THRES0__M 0x1F |
| 10639 | #define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E | 10639 | #define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E |
| 10640 | 10640 | ||
| 10641 | #define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 | 10641 | #define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 |
| 10642 | #define B_EQ_REG_OT_QNT_THRES1__W 5 | 10642 | #define B_EQ_REG_OT_QNT_THRES1__W 5 |
| 10643 | #define B_EQ_REG_OT_QNT_THRES1__M 0x1F | 10643 | #define B_EQ_REG_OT_QNT_THRES1__M 0x1F |
| 10644 | #define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F | 10644 | #define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F |
| 10645 | 10645 | ||
| 10646 | #define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A | 10646 | #define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A |
| 10647 | #define B_EQ_REG_OT_CSI_STEP__W 4 | 10647 | #define B_EQ_REG_OT_CSI_STEP__W 4 |
| 10648 | #define B_EQ_REG_OT_CSI_STEP__M 0xF | 10648 | #define B_EQ_REG_OT_CSI_STEP__M 0xF |
| 10649 | #define B_EQ_REG_OT_CSI_STEP_INIT 0x5 | 10649 | #define B_EQ_REG_OT_CSI_STEP_INIT 0x5 |
| 10650 | 10650 | ||
| 10651 | #define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B | 10651 | #define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B |
| 10652 | #define B_EQ_REG_OT_CSI_OFFSET__W 7 | 10652 | #define B_EQ_REG_OT_CSI_OFFSET__W 7 |
| 10653 | #define B_EQ_REG_OT_CSI_OFFSET__M 0x7F | 10653 | #define B_EQ_REG_OT_CSI_OFFSET__M 0x7F |
| 10654 | #define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 | 10654 | #define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 |
| 10655 | 10655 | ||
| 10656 | #define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C | 10656 | #define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C |
| 10657 | #define B_EQ_REG_OT_CSI_GAIN__W 8 | 10657 | #define B_EQ_REG_OT_CSI_GAIN__W 8 |
| 10658 | #define B_EQ_REG_OT_CSI_GAIN__M 0xFF | 10658 | #define B_EQ_REG_OT_CSI_GAIN__M 0xFF |
| 10659 | #define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B | 10659 | #define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B |
| 10660 | 10660 | ||
| 10661 | #define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D | 10661 | #define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D |
| 10662 | #define B_EQ_REG_OT_CSI_MEAN__W 7 | 10662 | #define B_EQ_REG_OT_CSI_MEAN__W 7 |
| 10663 | #define B_EQ_REG_OT_CSI_MEAN__M 0x7F | 10663 | #define B_EQ_REG_OT_CSI_MEAN__M 0x7F |
| 10664 | 10664 | ||
| 10665 | #define B_EQ_REG_OT_CSI_VARIANCE__A 0x1C1004E | 10665 | #define B_EQ_REG_OT_CSI_VARIANCE__A 0x1C1004E |
| 10666 | #define B_EQ_REG_OT_CSI_VARIANCE__W 7 | 10666 | #define B_EQ_REG_OT_CSI_VARIANCE__W 7 |
| 10667 | #define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F | 10667 | #define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F |
| 10668 | 10668 | ||
| 10669 | #define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 | 10669 | #define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 |
| 10670 | #define B_EQ_REG_TD_TPS_INIT__W 1 | 10670 | #define B_EQ_REG_TD_TPS_INIT__W 1 |
| 10671 | #define B_EQ_REG_TD_TPS_INIT__M 0x1 | 10671 | #define B_EQ_REG_TD_TPS_INIT__M 0x1 |
| 10672 | #define B_EQ_REG_TD_TPS_INIT_INIT 0x0 | 10672 | #define B_EQ_REG_TD_TPS_INIT_INIT 0x0 |
| 10673 | #define B_EQ_REG_TD_TPS_INIT_POS 0x0 | 10673 | #define B_EQ_REG_TD_TPS_INIT_POS 0x0 |
| 10674 | #define B_EQ_REG_TD_TPS_INIT_NEG 0x1 | 10674 | #define B_EQ_REG_TD_TPS_INIT_NEG 0x1 |
| 10675 | 10675 | ||
| 10676 | #define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 | 10676 | #define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 |
| 10677 | #define B_EQ_REG_TD_TPS_SYNC__W 16 | 10677 | #define B_EQ_REG_TD_TPS_SYNC__W 16 |
| 10678 | #define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF | 10678 | #define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF |
| 10679 | #define B_EQ_REG_TD_TPS_SYNC_INIT 0x0 | 10679 | #define B_EQ_REG_TD_TPS_SYNC_INIT 0x0 |
| 10680 | #define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE | 10680 | #define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE |
| 10681 | #define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 | 10681 | #define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 |
| 10682 | 10682 | ||
| 10683 | #define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 | 10683 | #define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 |
| 10684 | #define B_EQ_REG_TD_TPS_LEN__W 6 | 10684 | #define B_EQ_REG_TD_TPS_LEN__W 6 |
| 10685 | #define B_EQ_REG_TD_TPS_LEN__M 0x3F | 10685 | #define B_EQ_REG_TD_TPS_LEN__M 0x3F |
| 10686 | #define B_EQ_REG_TD_TPS_LEN_INIT 0x0 | 10686 | #define B_EQ_REG_TD_TPS_LEN_INIT 0x0 |
| 10687 | #define B_EQ_REG_TD_TPS_LEN_DEF 0x17 | 10687 | #define B_EQ_REG_TD_TPS_LEN_DEF 0x17 |
| 10688 | #define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F | 10688 | #define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F |
| 10689 | 10689 | ||
| 10690 | #define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 | 10690 | #define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 |
| 10691 | #define B_EQ_REG_TD_TPS_FRM_NMB__W 2 | 10691 | #define B_EQ_REG_TD_TPS_FRM_NMB__W 2 |
| 10692 | #define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 | 10692 | #define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 |
| 10693 | #define B_EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 | 10693 | #define B_EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 |
| 10694 | #define B_EQ_REG_TD_TPS_FRM_NMB_1 0x0 | 10694 | #define B_EQ_REG_TD_TPS_FRM_NMB_1 0x0 |
| 10695 | #define B_EQ_REG_TD_TPS_FRM_NMB_2 0x1 | 10695 | #define B_EQ_REG_TD_TPS_FRM_NMB_2 0x1 |
| 10696 | #define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 | 10696 | #define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 |
| 10697 | #define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 | 10697 | #define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 |
| 10698 | 10698 | ||
| 10699 | #define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 | 10699 | #define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 |
| 10700 | #define B_EQ_REG_TD_TPS_CONST__W 2 | 10700 | #define B_EQ_REG_TD_TPS_CONST__W 2 |
| 10701 | #define B_EQ_REG_TD_TPS_CONST__M 0x3 | 10701 | #define B_EQ_REG_TD_TPS_CONST__M 0x3 |
| 10702 | #define B_EQ_REG_TD_TPS_CONST_INIT 0x0 | 10702 | #define B_EQ_REG_TD_TPS_CONST_INIT 0x0 |
| 10703 | #define B_EQ_REG_TD_TPS_CONST_QPSK 0x0 | 10703 | #define B_EQ_REG_TD_TPS_CONST_QPSK 0x0 |
| 10704 | #define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 | 10704 | #define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 |
| 10705 | #define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 | 10705 | #define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 |
| 10706 | 10706 | ||
| 10707 | #define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 | 10707 | #define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 |
| 10708 | #define B_EQ_REG_TD_TPS_HINFO__W 3 | 10708 | #define B_EQ_REG_TD_TPS_HINFO__W 3 |
| 10709 | #define B_EQ_REG_TD_TPS_HINFO__M 0x7 | 10709 | #define B_EQ_REG_TD_TPS_HINFO__M 0x7 |
| 10710 | #define B_EQ_REG_TD_TPS_HINFO_INIT 0x0 | 10710 | #define B_EQ_REG_TD_TPS_HINFO_INIT 0x0 |
| 10711 | #define B_EQ_REG_TD_TPS_HINFO_NH 0x0 | 10711 | #define B_EQ_REG_TD_TPS_HINFO_NH 0x0 |
| 10712 | #define B_EQ_REG_TD_TPS_HINFO_H1 0x1 | 10712 | #define B_EQ_REG_TD_TPS_HINFO_H1 0x1 |
| 10713 | #define B_EQ_REG_TD_TPS_HINFO_H2 0x2 | 10713 | #define B_EQ_REG_TD_TPS_HINFO_H2 0x2 |
| 10714 | #define B_EQ_REG_TD_TPS_HINFO_H4 0x3 | 10714 | #define B_EQ_REG_TD_TPS_HINFO_H4 0x3 |
| 10715 | 10715 | ||
| 10716 | #define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 | 10716 | #define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 |
| 10717 | #define B_EQ_REG_TD_TPS_CODE_HP__W 3 | 10717 | #define B_EQ_REG_TD_TPS_CODE_HP__W 3 |
| 10718 | #define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 | 10718 | #define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 |
| 10719 | #define B_EQ_REG_TD_TPS_CODE_HP_INIT 0x0 | 10719 | #define B_EQ_REG_TD_TPS_CODE_HP_INIT 0x0 |
| 10720 | #define B_EQ_REG_TD_TPS_CODE_HP_1_2 0x0 | 10720 | #define B_EQ_REG_TD_TPS_CODE_HP_1_2 0x0 |
| 10721 | #define B_EQ_REG_TD_TPS_CODE_HP_2_3 0x1 | 10721 | #define B_EQ_REG_TD_TPS_CODE_HP_2_3 0x1 |
| 10722 | #define B_EQ_REG_TD_TPS_CODE_HP_3_4 0x2 | 10722 | #define B_EQ_REG_TD_TPS_CODE_HP_3_4 0x2 |
| 10723 | #define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 | 10723 | #define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 |
| 10724 | #define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 | 10724 | #define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 |
| 10725 | 10725 | ||
| 10726 | #define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 | 10726 | #define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 |
| 10727 | #define B_EQ_REG_TD_TPS_CODE_LP__W 3 | 10727 | #define B_EQ_REG_TD_TPS_CODE_LP__W 3 |
| 10728 | #define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 | 10728 | #define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 |
| 10729 | #define B_EQ_REG_TD_TPS_CODE_LP_INIT 0x0 | 10729 | #define B_EQ_REG_TD_TPS_CODE_LP_INIT 0x0 |
| 10730 | #define B_EQ_REG_TD_TPS_CODE_LP_1_2 0x0 | 10730 | #define B_EQ_REG_TD_TPS_CODE_LP_1_2 0x0 |
| 10731 | #define B_EQ_REG_TD_TPS_CODE_LP_2_3 0x1 | 10731 | #define B_EQ_REG_TD_TPS_CODE_LP_2_3 0x1 |
| 10732 | #define B_EQ_REG_TD_TPS_CODE_LP_3_4 0x2 | 10732 | #define B_EQ_REG_TD_TPS_CODE_LP_3_4 0x2 |
| 10733 | #define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 | 10733 | #define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 |
| 10734 | #define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 | 10734 | #define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 |
| 10735 | 10735 | ||
| 10736 | #define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 | 10736 | #define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 |
| 10737 | #define B_EQ_REG_TD_TPS_GUARD__W 2 | 10737 | #define B_EQ_REG_TD_TPS_GUARD__W 2 |
| 10738 | #define B_EQ_REG_TD_TPS_GUARD__M 0x3 | 10738 | #define B_EQ_REG_TD_TPS_GUARD__M 0x3 |
| 10739 | #define B_EQ_REG_TD_TPS_GUARD_INIT 0x0 | 10739 | #define B_EQ_REG_TD_TPS_GUARD_INIT 0x0 |
| 10740 | #define B_EQ_REG_TD_TPS_GUARD_32 0x0 | 10740 | #define B_EQ_REG_TD_TPS_GUARD_32 0x0 |
| 10741 | #define B_EQ_REG_TD_TPS_GUARD_16 0x1 | 10741 | #define B_EQ_REG_TD_TPS_GUARD_16 0x1 |
| 10742 | #define B_EQ_REG_TD_TPS_GUARD_08 0x2 | 10742 | #define B_EQ_REG_TD_TPS_GUARD_08 0x2 |
| 10743 | #define B_EQ_REG_TD_TPS_GUARD_04 0x3 | 10743 | #define B_EQ_REG_TD_TPS_GUARD_04 0x3 |
| 10744 | 10744 | ||
| 10745 | #define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 | 10745 | #define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 |
| 10746 | #define B_EQ_REG_TD_TPS_TR_MODE__W 2 | 10746 | #define B_EQ_REG_TD_TPS_TR_MODE__W 2 |
| 10747 | #define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 | 10747 | #define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 |
| 10748 | #define B_EQ_REG_TD_TPS_TR_MODE_INIT 0x0 | 10748 | #define B_EQ_REG_TD_TPS_TR_MODE_INIT 0x0 |
| 10749 | #define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 | 10749 | #define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 |
| 10750 | #define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 | 10750 | #define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 |
| 10751 | 10751 | ||
| 10752 | #define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A | 10752 | #define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A |
| 10753 | #define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 | 10753 | #define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 |
| 10754 | #define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF | 10754 | #define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF |
| 10755 | #define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 | 10755 | #define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 |
| 10756 | 10756 | ||
| 10757 | #define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B | 10757 | #define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B |
| 10758 | #define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 | 10758 | #define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 |
| 10759 | #define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF | 10759 | #define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF |
| 10760 | #define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 | 10760 | #define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 |
| 10761 | 10761 | ||
| 10762 | #define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C | 10762 | #define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C |
| 10763 | #define B_EQ_REG_TD_TPS_RSV__W 6 | 10763 | #define B_EQ_REG_TD_TPS_RSV__W 6 |
| 10764 | #define B_EQ_REG_TD_TPS_RSV__M 0x3F | 10764 | #define B_EQ_REG_TD_TPS_RSV__M 0x3F |
| 10765 | #define B_EQ_REG_TD_TPS_RSV_INIT 0x0 | 10765 | #define B_EQ_REG_TD_TPS_RSV_INIT 0x0 |
| 10766 | 10766 | ||
| 10767 | #define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D | 10767 | #define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D |
| 10768 | #define B_EQ_REG_TD_TPS_BCH__W 14 | 10768 | #define B_EQ_REG_TD_TPS_BCH__W 14 |
| 10769 | #define B_EQ_REG_TD_TPS_BCH__M 0x3FFF | 10769 | #define B_EQ_REG_TD_TPS_BCH__M 0x3FFF |
| 10770 | #define B_EQ_REG_TD_TPS_BCH_INIT 0x0 | 10770 | #define B_EQ_REG_TD_TPS_BCH_INIT 0x0 |
| 10771 | 10771 | ||
| 10772 | #define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E | 10772 | #define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E |
| 10773 | #define B_EQ_REG_TD_SQR_ERR_I__W 16 | 10773 | #define B_EQ_REG_TD_SQR_ERR_I__W 16 |
| 10774 | #define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF | 10774 | #define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF |
| 10775 | #define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 | 10775 | #define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 |
| 10776 | 10776 | ||
| 10777 | #define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F | 10777 | #define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F |
| 10778 | #define B_EQ_REG_TD_SQR_ERR_Q__W 16 | 10778 | #define B_EQ_REG_TD_SQR_ERR_Q__W 16 |
| 10779 | #define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF | 10779 | #define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF |
| 10780 | #define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 | 10780 | #define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 |
| 10781 | 10781 | ||
| 10782 | #define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 | 10782 | #define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 |
| 10783 | #define B_EQ_REG_TD_SQR_ERR_EXP__W 4 | 10783 | #define B_EQ_REG_TD_SQR_ERR_EXP__W 4 |
| 10784 | #define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF | 10784 | #define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF |
| 10785 | #define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 | 10785 | #define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 |
| 10786 | 10786 | ||
| 10787 | #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 | 10787 | #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 |
| 10788 | #define B_EQ_REG_TD_REQ_SMB_CNT__W 16 | 10788 | #define B_EQ_REG_TD_REQ_SMB_CNT__W 16 |
| 10789 | #define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF | 10789 | #define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF |
| 10790 | #define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 | 10790 | #define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 |
| 10791 | 10791 | ||
| 10792 | #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 | 10792 | #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 |
| 10793 | #define B_EQ_REG_TD_TPS_PWR_OFS__W 16 | 10793 | #define B_EQ_REG_TD_TPS_PWR_OFS__W 16 |
| 10794 | #define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF | 10794 | #define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF |
| 10795 | #define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F | 10795 | #define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F |
| 10796 | 10796 | ||
| 10797 | #define B_EC_COMM_EXEC__A 0x2000000 | 10797 | #define B_EC_COMM_EXEC__A 0x2000000 |
| 10798 | #define B_EC_COMM_EXEC__W 3 | 10798 | #define B_EC_COMM_EXEC__W 3 |
| 10799 | #define B_EC_COMM_EXEC__M 0x7 | 10799 | #define B_EC_COMM_EXEC__M 0x7 |
| 10800 | #define B_EC_COMM_EXEC_CTL__B 0 | 10800 | #define B_EC_COMM_EXEC_CTL__B 0 |
| 10801 | #define B_EC_COMM_EXEC_CTL__W 3 | 10801 | #define B_EC_COMM_EXEC_CTL__W 3 |
| 10802 | #define B_EC_COMM_EXEC_CTL__M 0x7 | 10802 | #define B_EC_COMM_EXEC_CTL__M 0x7 |
| 10803 | #define B_EC_COMM_EXEC_CTL_STOP 0x0 | 10803 | #define B_EC_COMM_EXEC_CTL_STOP 0x0 |
| 10804 | #define B_EC_COMM_EXEC_CTL_ACTIVE 0x1 | 10804 | #define B_EC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 10805 | #define B_EC_COMM_EXEC_CTL_HOLD 0x2 | 10805 | #define B_EC_COMM_EXEC_CTL_HOLD 0x2 |
| 10806 | #define B_EC_COMM_EXEC_CTL_STEP 0x3 | 10806 | #define B_EC_COMM_EXEC_CTL_STEP 0x3 |
| 10807 | #define B_EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 10807 | #define B_EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 10808 | #define B_EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 10808 | #define B_EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 10809 | 10809 | ||
| 10810 | #define B_EC_COMM_STATE__A 0x2000001 | 10810 | #define B_EC_COMM_STATE__A 0x2000001 |
| 10811 | #define B_EC_COMM_STATE__W 16 | 10811 | #define B_EC_COMM_STATE__W 16 |
| 10812 | #define B_EC_COMM_STATE__M 0xFFFF | 10812 | #define B_EC_COMM_STATE__M 0xFFFF |
| 10813 | #define B_EC_COMM_MB__A 0x2000002 | 10813 | #define B_EC_COMM_MB__A 0x2000002 |
| 10814 | #define B_EC_COMM_MB__W 16 | 10814 | #define B_EC_COMM_MB__W 16 |
| 10815 | #define B_EC_COMM_MB__M 0xFFFF | 10815 | #define B_EC_COMM_MB__M 0xFFFF |
| 10816 | #define B_EC_COMM_SERVICE0__A 0x2000003 | 10816 | #define B_EC_COMM_SERVICE0__A 0x2000003 |
| 10817 | #define B_EC_COMM_SERVICE0__W 16 | 10817 | #define B_EC_COMM_SERVICE0__W 16 |
| 10818 | #define B_EC_COMM_SERVICE0__M 0xFFFF | 10818 | #define B_EC_COMM_SERVICE0__M 0xFFFF |
| 10819 | #define B_EC_COMM_SERVICE1__A 0x2000004 | 10819 | #define B_EC_COMM_SERVICE1__A 0x2000004 |
| 10820 | #define B_EC_COMM_SERVICE1__W 16 | 10820 | #define B_EC_COMM_SERVICE1__W 16 |
| 10821 | #define B_EC_COMM_SERVICE1__M 0xFFFF | 10821 | #define B_EC_COMM_SERVICE1__M 0xFFFF |
| 10822 | #define B_EC_COMM_INT_STA__A 0x2000007 | 10822 | #define B_EC_COMM_INT_STA__A 0x2000007 |
| 10823 | #define B_EC_COMM_INT_STA__W 16 | 10823 | #define B_EC_COMM_INT_STA__W 16 |
| 10824 | #define B_EC_COMM_INT_STA__M 0xFFFF | 10824 | #define B_EC_COMM_INT_STA__M 0xFFFF |
| 10825 | #define B_EC_COMM_INT_MSK__A 0x2000008 | 10825 | #define B_EC_COMM_INT_MSK__A 0x2000008 |
| 10826 | #define B_EC_COMM_INT_MSK__W 16 | 10826 | #define B_EC_COMM_INT_MSK__W 16 |
| 10827 | #define B_EC_COMM_INT_MSK__M 0xFFFF | 10827 | #define B_EC_COMM_INT_MSK__M 0xFFFF |
| 10828 | 10828 | ||
| 10829 | #define B_EC_SB_SID 0x16 | 10829 | #define B_EC_SB_SID 0x16 |
| 10830 | 10830 | ||
| 10831 | #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 | 10831 | #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 |
| 10832 | #define B_EC_SB_REG_COMM_EXEC__W 3 | 10832 | #define B_EC_SB_REG_COMM_EXEC__W 3 |
| 10833 | #define B_EC_SB_REG_COMM_EXEC__M 0x7 | 10833 | #define B_EC_SB_REG_COMM_EXEC__M 0x7 |
| 10834 | #define B_EC_SB_REG_COMM_EXEC_CTL__B 0 | 10834 | #define B_EC_SB_REG_COMM_EXEC_CTL__B 0 |
| 10835 | #define B_EC_SB_REG_COMM_EXEC_CTL__W 3 | 10835 | #define B_EC_SB_REG_COMM_EXEC_CTL__W 3 |
| 10836 | #define B_EC_SB_REG_COMM_EXEC_CTL__M 0x7 | 10836 | #define B_EC_SB_REG_COMM_EXEC_CTL__M 0x7 |
| 10837 | #define B_EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 | 10837 | #define B_EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 |
| 10838 | #define B_EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 10838 | #define B_EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 10839 | #define B_EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 | 10839 | #define B_EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 10840 | 10840 | ||
| 10841 | #define B_EC_SB_REG_COMM_STATE__A 0x2010001 | 10841 | #define B_EC_SB_REG_COMM_STATE__A 0x2010001 |
| 10842 | #define B_EC_SB_REG_COMM_STATE__W 4 | 10842 | #define B_EC_SB_REG_COMM_STATE__W 4 |
| 10843 | #define B_EC_SB_REG_COMM_STATE__M 0xF | 10843 | #define B_EC_SB_REG_COMM_STATE__M 0xF |
| 10844 | #define B_EC_SB_REG_COMM_MB__A 0x2010002 | 10844 | #define B_EC_SB_REG_COMM_MB__A 0x2010002 |
| 10845 | #define B_EC_SB_REG_COMM_MB__W 2 | 10845 | #define B_EC_SB_REG_COMM_MB__W 2 |
| 10846 | #define B_EC_SB_REG_COMM_MB__M 0x3 | 10846 | #define B_EC_SB_REG_COMM_MB__M 0x3 |
| 10847 | #define B_EC_SB_REG_COMM_MB_CTR__B 0 | 10847 | #define B_EC_SB_REG_COMM_MB_CTR__B 0 |
| 10848 | #define B_EC_SB_REG_COMM_MB_CTR__W 1 | 10848 | #define B_EC_SB_REG_COMM_MB_CTR__W 1 |
| 10849 | #define B_EC_SB_REG_COMM_MB_CTR__M 0x1 | 10849 | #define B_EC_SB_REG_COMM_MB_CTR__M 0x1 |
| 10850 | #define B_EC_SB_REG_COMM_MB_CTR_OFF 0x0 | 10850 | #define B_EC_SB_REG_COMM_MB_CTR_OFF 0x0 |
| 10851 | #define B_EC_SB_REG_COMM_MB_CTR_ON 0x1 | 10851 | #define B_EC_SB_REG_COMM_MB_CTR_ON 0x1 |
| 10852 | #define B_EC_SB_REG_COMM_MB_OBS__B 1 | 10852 | #define B_EC_SB_REG_COMM_MB_OBS__B 1 |
| 10853 | #define B_EC_SB_REG_COMM_MB_OBS__W 1 | 10853 | #define B_EC_SB_REG_COMM_MB_OBS__W 1 |
| 10854 | #define B_EC_SB_REG_COMM_MB_OBS__M 0x2 | 10854 | #define B_EC_SB_REG_COMM_MB_OBS__M 0x2 |
| 10855 | #define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 | 10855 | #define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 |
| 10856 | #define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 | 10856 | #define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 |
| 10857 | 10857 | ||
| 10858 | #define B_EC_SB_REG_TR_MODE__A 0x2010010 | 10858 | #define B_EC_SB_REG_TR_MODE__A 0x2010010 |
| 10859 | #define B_EC_SB_REG_TR_MODE__W 1 | 10859 | #define B_EC_SB_REG_TR_MODE__W 1 |
| 10860 | #define B_EC_SB_REG_TR_MODE__M 0x1 | 10860 | #define B_EC_SB_REG_TR_MODE__M 0x1 |
| 10861 | #define B_EC_SB_REG_TR_MODE_INIT 0x0 | 10861 | #define B_EC_SB_REG_TR_MODE_INIT 0x0 |
| 10862 | #define B_EC_SB_REG_TR_MODE_8K 0x0 | 10862 | #define B_EC_SB_REG_TR_MODE_8K 0x0 |
| 10863 | #define B_EC_SB_REG_TR_MODE_2K 0x1 | 10863 | #define B_EC_SB_REG_TR_MODE_2K 0x1 |
| 10864 | 10864 | ||
| 10865 | #define B_EC_SB_REG_CONST__A 0x2010011 | 10865 | #define B_EC_SB_REG_CONST__A 0x2010011 |
| 10866 | #define B_EC_SB_REG_CONST__W 2 | 10866 | #define B_EC_SB_REG_CONST__W 2 |
| 10867 | #define B_EC_SB_REG_CONST__M 0x3 | 10867 | #define B_EC_SB_REG_CONST__M 0x3 |
| 10868 | #define B_EC_SB_REG_CONST_INIT 0x2 | 10868 | #define B_EC_SB_REG_CONST_INIT 0x2 |
| 10869 | #define B_EC_SB_REG_CONST_QPSK 0x0 | 10869 | #define B_EC_SB_REG_CONST_QPSK 0x0 |
| 10870 | #define B_EC_SB_REG_CONST_16QAM 0x1 | 10870 | #define B_EC_SB_REG_CONST_16QAM 0x1 |
| 10871 | #define B_EC_SB_REG_CONST_64QAM 0x2 | 10871 | #define B_EC_SB_REG_CONST_64QAM 0x2 |
| 10872 | 10872 | ||
| 10873 | #define B_EC_SB_REG_ALPHA__A 0x2010012 | 10873 | #define B_EC_SB_REG_ALPHA__A 0x2010012 |
| 10874 | #define B_EC_SB_REG_ALPHA__W 3 | 10874 | #define B_EC_SB_REG_ALPHA__W 3 |
| 10875 | #define B_EC_SB_REG_ALPHA__M 0x7 | 10875 | #define B_EC_SB_REG_ALPHA__M 0x7 |
| 10876 | 10876 | ||
| 10877 | #define B_EC_SB_REG_ALPHA_INIT 0x0 | 10877 | #define B_EC_SB_REG_ALPHA_INIT 0x0 |
| 10878 | 10878 | ||
| 10879 | #define B_EC_SB_REG_ALPHA_NH 0x0 | 10879 | #define B_EC_SB_REG_ALPHA_NH 0x0 |
| 10880 | 10880 | ||
| 10881 | #define B_EC_SB_REG_ALPHA_H1 0x1 | 10881 | #define B_EC_SB_REG_ALPHA_H1 0x1 |
| 10882 | 10882 | ||
| 10883 | #define B_EC_SB_REG_ALPHA_H2 0x2 | 10883 | #define B_EC_SB_REG_ALPHA_H2 0x2 |
| 10884 | 10884 | ||
| 10885 | #define B_EC_SB_REG_ALPHA_H4 0x3 | 10885 | #define B_EC_SB_REG_ALPHA_H4 0x3 |
| 10886 | 10886 | ||
| 10887 | #define B_EC_SB_REG_PRIOR__A 0x2010013 | 10887 | #define B_EC_SB_REG_PRIOR__A 0x2010013 |
| 10888 | #define B_EC_SB_REG_PRIOR__W 1 | 10888 | #define B_EC_SB_REG_PRIOR__W 1 |
| 10889 | #define B_EC_SB_REG_PRIOR__M 0x1 | 10889 | #define B_EC_SB_REG_PRIOR__M 0x1 |
| 10890 | #define B_EC_SB_REG_PRIOR_INIT 0x0 | 10890 | #define B_EC_SB_REG_PRIOR_INIT 0x0 |
| 10891 | #define B_EC_SB_REG_PRIOR_HI 0x0 | 10891 | #define B_EC_SB_REG_PRIOR_HI 0x0 |
| 10892 | #define B_EC_SB_REG_PRIOR_LO 0x1 | 10892 | #define B_EC_SB_REG_PRIOR_LO 0x1 |
| 10893 | 10893 | ||
| 10894 | #define B_EC_SB_REG_CSI_HI__A 0x2010014 | 10894 | #define B_EC_SB_REG_CSI_HI__A 0x2010014 |
| 10895 | #define B_EC_SB_REG_CSI_HI__W 5 | 10895 | #define B_EC_SB_REG_CSI_HI__W 5 |
| 10896 | #define B_EC_SB_REG_CSI_HI__M 0x1F | 10896 | #define B_EC_SB_REG_CSI_HI__M 0x1F |
| 10897 | #define B_EC_SB_REG_CSI_HI_INIT 0x1F | 10897 | #define B_EC_SB_REG_CSI_HI_INIT 0x1F |
| 10898 | #define B_EC_SB_REG_CSI_HI_MAX 0x1F | 10898 | #define B_EC_SB_REG_CSI_HI_MAX 0x1F |
| 10899 | #define B_EC_SB_REG_CSI_HI_MIN 0x0 | 10899 | #define B_EC_SB_REG_CSI_HI_MIN 0x0 |
| 10900 | #define B_EC_SB_REG_CSI_HI_TAG 0x0 | 10900 | #define B_EC_SB_REG_CSI_HI_TAG 0x0 |
| 10901 | 10901 | ||
| 10902 | #define B_EC_SB_REG_CSI_LO__A 0x2010015 | 10902 | #define B_EC_SB_REG_CSI_LO__A 0x2010015 |
| 10903 | #define B_EC_SB_REG_CSI_LO__W 5 | 10903 | #define B_EC_SB_REG_CSI_LO__W 5 |
| 10904 | #define B_EC_SB_REG_CSI_LO__M 0x1F | 10904 | #define B_EC_SB_REG_CSI_LO__M 0x1F |
| 10905 | #define B_EC_SB_REG_CSI_LO_INIT 0x1E | 10905 | #define B_EC_SB_REG_CSI_LO_INIT 0x1E |
| 10906 | #define B_EC_SB_REG_CSI_LO_MAX 0x1F | 10906 | #define B_EC_SB_REG_CSI_LO_MAX 0x1F |
| 10907 | #define B_EC_SB_REG_CSI_LO_MIN 0x0 | 10907 | #define B_EC_SB_REG_CSI_LO_MIN 0x0 |
| 10908 | #define B_EC_SB_REG_CSI_LO_TAG 0x0 | 10908 | #define B_EC_SB_REG_CSI_LO_TAG 0x0 |
| 10909 | 10909 | ||
| 10910 | #define B_EC_SB_REG_SMB_TGL__A 0x2010016 | 10910 | #define B_EC_SB_REG_SMB_TGL__A 0x2010016 |
| 10911 | #define B_EC_SB_REG_SMB_TGL__W 1 | 10911 | #define B_EC_SB_REG_SMB_TGL__W 1 |
| 10912 | #define B_EC_SB_REG_SMB_TGL__M 0x1 | 10912 | #define B_EC_SB_REG_SMB_TGL__M 0x1 |
| 10913 | #define B_EC_SB_REG_SMB_TGL_OFF 0x0 | 10913 | #define B_EC_SB_REG_SMB_TGL_OFF 0x0 |
| 10914 | #define B_EC_SB_REG_SMB_TGL_ON 0x1 | 10914 | #define B_EC_SB_REG_SMB_TGL_ON 0x1 |
| 10915 | #define B_EC_SB_REG_SMB_TGL_INIT 0x1 | 10915 | #define B_EC_SB_REG_SMB_TGL_INIT 0x1 |
| 10916 | 10916 | ||
| 10917 | #define B_EC_SB_REG_SNR_HI__A 0x2010017 | 10917 | #define B_EC_SB_REG_SNR_HI__A 0x2010017 |
| 10918 | #define B_EC_SB_REG_SNR_HI__W 8 | 10918 | #define B_EC_SB_REG_SNR_HI__W 8 |
| 10919 | #define B_EC_SB_REG_SNR_HI__M 0xFF | 10919 | #define B_EC_SB_REG_SNR_HI__M 0xFF |
| 10920 | #define B_EC_SB_REG_SNR_HI_INIT 0x6E | 10920 | #define B_EC_SB_REG_SNR_HI_INIT 0x6E |
| 10921 | #define B_EC_SB_REG_SNR_HI_MAX 0xFF | 10921 | #define B_EC_SB_REG_SNR_HI_MAX 0xFF |
| 10922 | #define B_EC_SB_REG_SNR_HI_MIN 0x0 | 10922 | #define B_EC_SB_REG_SNR_HI_MIN 0x0 |
| 10923 | #define B_EC_SB_REG_SNR_HI_TAG 0x0 | 10923 | #define B_EC_SB_REG_SNR_HI_TAG 0x0 |
| 10924 | 10924 | ||
| 10925 | #define B_EC_SB_REG_SNR_MID__A 0x2010018 | 10925 | #define B_EC_SB_REG_SNR_MID__A 0x2010018 |
| 10926 | #define B_EC_SB_REG_SNR_MID__W 8 | 10926 | #define B_EC_SB_REG_SNR_MID__W 8 |
| 10927 | #define B_EC_SB_REG_SNR_MID__M 0xFF | 10927 | #define B_EC_SB_REG_SNR_MID__M 0xFF |
| 10928 | #define B_EC_SB_REG_SNR_MID_INIT 0x6C | 10928 | #define B_EC_SB_REG_SNR_MID_INIT 0x6C |
| 10929 | #define B_EC_SB_REG_SNR_MID_MAX 0xFF | 10929 | #define B_EC_SB_REG_SNR_MID_MAX 0xFF |
| 10930 | #define B_EC_SB_REG_SNR_MID_MIN 0x0 | 10930 | #define B_EC_SB_REG_SNR_MID_MIN 0x0 |
| 10931 | #define B_EC_SB_REG_SNR_MID_TAG 0x0 | 10931 | #define B_EC_SB_REG_SNR_MID_TAG 0x0 |
| 10932 | 10932 | ||
| 10933 | #define B_EC_SB_REG_SNR_LO__A 0x2010019 | 10933 | #define B_EC_SB_REG_SNR_LO__A 0x2010019 |
| 10934 | #define B_EC_SB_REG_SNR_LO__W 8 | 10934 | #define B_EC_SB_REG_SNR_LO__W 8 |
| 10935 | #define B_EC_SB_REG_SNR_LO__M 0xFF | 10935 | #define B_EC_SB_REG_SNR_LO__M 0xFF |
| 10936 | #define B_EC_SB_REG_SNR_LO_INIT 0x68 | 10936 | #define B_EC_SB_REG_SNR_LO_INIT 0x68 |
| 10937 | #define B_EC_SB_REG_SNR_LO_MAX 0xFF | 10937 | #define B_EC_SB_REG_SNR_LO_MAX 0xFF |
| 10938 | #define B_EC_SB_REG_SNR_LO_MIN 0x0 | 10938 | #define B_EC_SB_REG_SNR_LO_MIN 0x0 |
| 10939 | #define B_EC_SB_REG_SNR_LO_TAG 0x0 | 10939 | #define B_EC_SB_REG_SNR_LO_TAG 0x0 |
| 10940 | 10940 | ||
| 10941 | #define B_EC_SB_REG_SCALE_MSB__A 0x201001A | 10941 | #define B_EC_SB_REG_SCALE_MSB__A 0x201001A |
| 10942 | #define B_EC_SB_REG_SCALE_MSB__W 6 | 10942 | #define B_EC_SB_REG_SCALE_MSB__W 6 |
| 10943 | #define B_EC_SB_REG_SCALE_MSB__M 0x3F | 10943 | #define B_EC_SB_REG_SCALE_MSB__M 0x3F |
| 10944 | #define B_EC_SB_REG_SCALE_MSB_INIT 0x30 | 10944 | #define B_EC_SB_REG_SCALE_MSB_INIT 0x30 |
| 10945 | #define B_EC_SB_REG_SCALE_MSB_MAX 0x3F | 10945 | #define B_EC_SB_REG_SCALE_MSB_MAX 0x3F |
| 10946 | 10946 | ||
| 10947 | #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B | 10947 | #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B |
| 10948 | #define B_EC_SB_REG_SCALE_BIT2__W 6 | 10948 | #define B_EC_SB_REG_SCALE_BIT2__W 6 |
| 10949 | #define B_EC_SB_REG_SCALE_BIT2__M 0x3F | 10949 | #define B_EC_SB_REG_SCALE_BIT2__M 0x3F |
| 10950 | #define B_EC_SB_REG_SCALE_BIT2_INIT 0xC | 10950 | #define B_EC_SB_REG_SCALE_BIT2_INIT 0xC |
| 10951 | #define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F | 10951 | #define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F |
| 10952 | 10952 | ||
| 10953 | #define B_EC_SB_REG_SCALE_LSB__A 0x201001C | 10953 | #define B_EC_SB_REG_SCALE_LSB__A 0x201001C |
| 10954 | #define B_EC_SB_REG_SCALE_LSB__W 6 | 10954 | #define B_EC_SB_REG_SCALE_LSB__W 6 |
| 10955 | #define B_EC_SB_REG_SCALE_LSB__M 0x3F | 10955 | #define B_EC_SB_REG_SCALE_LSB__M 0x3F |
| 10956 | #define B_EC_SB_REG_SCALE_LSB_INIT 0x3 | 10956 | #define B_EC_SB_REG_SCALE_LSB_INIT 0x3 |
| 10957 | #define B_EC_SB_REG_SCALE_LSB_MAX 0x3F | 10957 | #define B_EC_SB_REG_SCALE_LSB_MAX 0x3F |
| 10958 | 10958 | ||
| 10959 | #define B_EC_SB_REG_CSI_OFS0__A 0x201001D | 10959 | #define B_EC_SB_REG_CSI_OFS0__A 0x201001D |
| 10960 | #define B_EC_SB_REG_CSI_OFS0__W 4 | 10960 | #define B_EC_SB_REG_CSI_OFS0__W 4 |
| 10961 | #define B_EC_SB_REG_CSI_OFS0__M 0xF | 10961 | #define B_EC_SB_REG_CSI_OFS0__M 0xF |
| 10962 | #define B_EC_SB_REG_CSI_OFS0_INIT 0x4 | 10962 | #define B_EC_SB_REG_CSI_OFS0_INIT 0x4 |
| 10963 | 10963 | ||
| 10964 | #define B_EC_SB_REG_CSI_OFS1__A 0x201001E | 10964 | #define B_EC_SB_REG_CSI_OFS1__A 0x201001E |
| 10965 | #define B_EC_SB_REG_CSI_OFS1__W 4 | 10965 | #define B_EC_SB_REG_CSI_OFS1__W 4 |
| 10966 | #define B_EC_SB_REG_CSI_OFS1__M 0xF | 10966 | #define B_EC_SB_REG_CSI_OFS1__M 0xF |
| 10967 | #define B_EC_SB_REG_CSI_OFS1_INIT 0x1 | 10967 | #define B_EC_SB_REG_CSI_OFS1_INIT 0x1 |
| 10968 | 10968 | ||
| 10969 | #define B_EC_SB_REG_CSI_OFS2__A 0x201001F | 10969 | #define B_EC_SB_REG_CSI_OFS2__A 0x201001F |
| 10970 | #define B_EC_SB_REG_CSI_OFS2__W 4 | 10970 | #define B_EC_SB_REG_CSI_OFS2__W 4 |
| 10971 | #define B_EC_SB_REG_CSI_OFS2__M 0xF | 10971 | #define B_EC_SB_REG_CSI_OFS2__M 0xF |
| 10972 | #define B_EC_SB_REG_CSI_OFS2_INIT 0x2 | 10972 | #define B_EC_SB_REG_CSI_OFS2_INIT 0x2 |
| 10973 | 10973 | ||
| 10974 | #define B_EC_SB_REG_MAX0__A 0x2010020 | 10974 | #define B_EC_SB_REG_MAX0__A 0x2010020 |
| 10975 | #define B_EC_SB_REG_MAX0__W 6 | 10975 | #define B_EC_SB_REG_MAX0__W 6 |
| 10976 | #define B_EC_SB_REG_MAX0__M 0x3F | 10976 | #define B_EC_SB_REG_MAX0__M 0x3F |
| 10977 | #define B_EC_SB_REG_MAX0_INIT 0x3F | 10977 | #define B_EC_SB_REG_MAX0_INIT 0x3F |
| 10978 | 10978 | ||
| 10979 | #define B_EC_SB_REG_MAX1__A 0x2010021 | 10979 | #define B_EC_SB_REG_MAX1__A 0x2010021 |
| 10980 | #define B_EC_SB_REG_MAX1__W 6 | 10980 | #define B_EC_SB_REG_MAX1__W 6 |
| 10981 | #define B_EC_SB_REG_MAX1__M 0x3F | 10981 | #define B_EC_SB_REG_MAX1__M 0x3F |
| 10982 | #define B_EC_SB_REG_MAX1_INIT 0x3F | 10982 | #define B_EC_SB_REG_MAX1_INIT 0x3F |
| 10983 | 10983 | ||
| 10984 | #define B_EC_SB_REG_MAX2__A 0x2010022 | 10984 | #define B_EC_SB_REG_MAX2__A 0x2010022 |
| 10985 | #define B_EC_SB_REG_MAX2__W 6 | 10985 | #define B_EC_SB_REG_MAX2__W 6 |
| 10986 | #define B_EC_SB_REG_MAX2__M 0x3F | 10986 | #define B_EC_SB_REG_MAX2__M 0x3F |
| 10987 | #define B_EC_SB_REG_MAX2_INIT 0x3F | 10987 | #define B_EC_SB_REG_MAX2_INIT 0x3F |
| 10988 | 10988 | ||
| 10989 | #define B_EC_SB_REG_CSI_DIS__A 0x2010023 | 10989 | #define B_EC_SB_REG_CSI_DIS__A 0x2010023 |
| 10990 | #define B_EC_SB_REG_CSI_DIS__W 1 | 10990 | #define B_EC_SB_REG_CSI_DIS__W 1 |
| 10991 | #define B_EC_SB_REG_CSI_DIS__M 0x1 | 10991 | #define B_EC_SB_REG_CSI_DIS__M 0x1 |
| 10992 | #define B_EC_SB_REG_CSI_DIS_INIT 0x0 | 10992 | #define B_EC_SB_REG_CSI_DIS_INIT 0x0 |
| 10993 | 10993 | ||
| 10994 | #define B_EC_SB_SD_RAM__A 0x2020000 | 10994 | #define B_EC_SB_SD_RAM__A 0x2020000 |
| 10995 | 10995 | ||
| 10996 | #define B_EC_SB_BD0_RAM__A 0x2030000 | 10996 | #define B_EC_SB_BD0_RAM__A 0x2030000 |
| 10997 | 10997 | ||
| 10998 | #define B_EC_SB_BD1_RAM__A 0x2040000 | 10998 | #define B_EC_SB_BD1_RAM__A 0x2040000 |
| 10999 | 10999 | ||
| 11000 | #define B_EC_VD_SID 0x17 | 11000 | #define B_EC_VD_SID 0x17 |
| 11001 | 11001 | ||
| 11002 | #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 | 11002 | #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 |
| 11003 | #define B_EC_VD_REG_COMM_EXEC__W 3 | 11003 | #define B_EC_VD_REG_COMM_EXEC__W 3 |
| 11004 | #define B_EC_VD_REG_COMM_EXEC__M 0x7 | 11004 | #define B_EC_VD_REG_COMM_EXEC__M 0x7 |
| 11005 | #define B_EC_VD_REG_COMM_EXEC_CTL__B 0 | 11005 | #define B_EC_VD_REG_COMM_EXEC_CTL__B 0 |
| 11006 | #define B_EC_VD_REG_COMM_EXEC_CTL__W 3 | 11006 | #define B_EC_VD_REG_COMM_EXEC_CTL__W 3 |
| 11007 | #define B_EC_VD_REG_COMM_EXEC_CTL__M 0x7 | 11007 | #define B_EC_VD_REG_COMM_EXEC_CTL__M 0x7 |
| 11008 | #define B_EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 | 11008 | #define B_EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 11009 | #define B_EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 11009 | #define B_EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 11010 | #define B_EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 | 11010 | #define B_EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 11011 | 11011 | ||
| 11012 | #define B_EC_VD_REG_COMM_STATE__A 0x2090001 | 11012 | #define B_EC_VD_REG_COMM_STATE__A 0x2090001 |
| 11013 | #define B_EC_VD_REG_COMM_STATE__W 4 | 11013 | #define B_EC_VD_REG_COMM_STATE__W 4 |
| 11014 | #define B_EC_VD_REG_COMM_STATE__M 0xF | 11014 | #define B_EC_VD_REG_COMM_STATE__M 0xF |
| 11015 | #define B_EC_VD_REG_COMM_MB__A 0x2090002 | 11015 | #define B_EC_VD_REG_COMM_MB__A 0x2090002 |
| 11016 | #define B_EC_VD_REG_COMM_MB__W 2 | 11016 | #define B_EC_VD_REG_COMM_MB__W 2 |
| 11017 | #define B_EC_VD_REG_COMM_MB__M 0x3 | 11017 | #define B_EC_VD_REG_COMM_MB__M 0x3 |
| 11018 | #define B_EC_VD_REG_COMM_MB_CTR__B 0 | 11018 | #define B_EC_VD_REG_COMM_MB_CTR__B 0 |
| 11019 | #define B_EC_VD_REG_COMM_MB_CTR__W 1 | 11019 | #define B_EC_VD_REG_COMM_MB_CTR__W 1 |
| 11020 | #define B_EC_VD_REG_COMM_MB_CTR__M 0x1 | 11020 | #define B_EC_VD_REG_COMM_MB_CTR__M 0x1 |
| 11021 | #define B_EC_VD_REG_COMM_MB_CTR_OFF 0x0 | 11021 | #define B_EC_VD_REG_COMM_MB_CTR_OFF 0x0 |
| 11022 | #define B_EC_VD_REG_COMM_MB_CTR_ON 0x1 | 11022 | #define B_EC_VD_REG_COMM_MB_CTR_ON 0x1 |
| 11023 | #define B_EC_VD_REG_COMM_MB_OBS__B 1 | 11023 | #define B_EC_VD_REG_COMM_MB_OBS__B 1 |
| 11024 | #define B_EC_VD_REG_COMM_MB_OBS__W 1 | 11024 | #define B_EC_VD_REG_COMM_MB_OBS__W 1 |
| 11025 | #define B_EC_VD_REG_COMM_MB_OBS__M 0x2 | 11025 | #define B_EC_VD_REG_COMM_MB_OBS__M 0x2 |
| 11026 | #define B_EC_VD_REG_COMM_MB_OBS_OFF 0x0 | 11026 | #define B_EC_VD_REG_COMM_MB_OBS_OFF 0x0 |
| 11027 | #define B_EC_VD_REG_COMM_MB_OBS_ON 0x2 | 11027 | #define B_EC_VD_REG_COMM_MB_OBS_ON 0x2 |
| 11028 | 11028 | ||
| 11029 | #define B_EC_VD_REG_COMM_SERVICE0__A 0x2090003 | 11029 | #define B_EC_VD_REG_COMM_SERVICE0__A 0x2090003 |
| 11030 | #define B_EC_VD_REG_COMM_SERVICE0__W 16 | 11030 | #define B_EC_VD_REG_COMM_SERVICE0__W 16 |
| 11031 | #define B_EC_VD_REG_COMM_SERVICE0__M 0xFFFF | 11031 | #define B_EC_VD_REG_COMM_SERVICE0__M 0xFFFF |
| 11032 | #define B_EC_VD_REG_COMM_SERVICE1__A 0x2090004 | 11032 | #define B_EC_VD_REG_COMM_SERVICE1__A 0x2090004 |
| 11033 | #define B_EC_VD_REG_COMM_SERVICE1__W 16 | 11033 | #define B_EC_VD_REG_COMM_SERVICE1__W 16 |
| 11034 | #define B_EC_VD_REG_COMM_SERVICE1__M 0xFFFF | 11034 | #define B_EC_VD_REG_COMM_SERVICE1__M 0xFFFF |
| 11035 | #define B_EC_VD_REG_COMM_INT_STA__A 0x2090007 | 11035 | #define B_EC_VD_REG_COMM_INT_STA__A 0x2090007 |
| 11036 | #define B_EC_VD_REG_COMM_INT_STA__W 1 | 11036 | #define B_EC_VD_REG_COMM_INT_STA__W 1 |
| 11037 | #define B_EC_VD_REG_COMM_INT_STA__M 0x1 | 11037 | #define B_EC_VD_REG_COMM_INT_STA__M 0x1 |
| 11038 | #define B_EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 | 11038 | #define B_EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 |
| 11039 | #define B_EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 | 11039 | #define B_EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 |
| 11040 | #define B_EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 | 11040 | #define B_EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 |
| 11041 | 11041 | ||
| 11042 | #define B_EC_VD_REG_COMM_INT_MSK__A 0x2090008 | 11042 | #define B_EC_VD_REG_COMM_INT_MSK__A 0x2090008 |
| 11043 | #define B_EC_VD_REG_COMM_INT_MSK__W 1 | 11043 | #define B_EC_VD_REG_COMM_INT_MSK__W 1 |
| 11044 | #define B_EC_VD_REG_COMM_INT_MSK__M 0x1 | 11044 | #define B_EC_VD_REG_COMM_INT_MSK__M 0x1 |
| 11045 | #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 | 11045 | #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 |
| 11046 | #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 | 11046 | #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 |
| 11047 | #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 | 11047 | #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 |
| 11048 | 11048 | ||
| 11049 | #define B_EC_VD_REG_FORCE__A 0x2090010 | 11049 | #define B_EC_VD_REG_FORCE__A 0x2090010 |
| 11050 | #define B_EC_VD_REG_FORCE__W 2 | 11050 | #define B_EC_VD_REG_FORCE__W 2 |
| 11051 | #define B_EC_VD_REG_FORCE__M 0x3 | 11051 | #define B_EC_VD_REG_FORCE__M 0x3 |
| 11052 | #define B_EC_VD_REG_FORCE_INIT 0x2 | 11052 | #define B_EC_VD_REG_FORCE_INIT 0x2 |
| 11053 | #define B_EC_VD_REG_FORCE_FREE 0x0 | 11053 | #define B_EC_VD_REG_FORCE_FREE 0x0 |
| 11054 | #define B_EC_VD_REG_FORCE_PROP 0x1 | 11054 | #define B_EC_VD_REG_FORCE_PROP 0x1 |
| 11055 | #define B_EC_VD_REG_FORCE_FORCED 0x2 | 11055 | #define B_EC_VD_REG_FORCE_FORCED 0x2 |
| 11056 | #define B_EC_VD_REG_FORCE_FIXED 0x3 | 11056 | #define B_EC_VD_REG_FORCE_FIXED 0x3 |
| 11057 | 11057 | ||
| 11058 | #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 | 11058 | #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 |
| 11059 | #define B_EC_VD_REG_SET_CODERATE__W 3 | 11059 | #define B_EC_VD_REG_SET_CODERATE__W 3 |
| 11060 | #define B_EC_VD_REG_SET_CODERATE__M 0x7 | 11060 | #define B_EC_VD_REG_SET_CODERATE__M 0x7 |
| 11061 | #define B_EC_VD_REG_SET_CODERATE_INIT 0x1 | 11061 | #define B_EC_VD_REG_SET_CODERATE_INIT 0x1 |
| 11062 | #define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 | 11062 | #define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 |
| 11063 | #define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 | 11063 | #define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 |
| 11064 | #define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 | 11064 | #define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 |
| 11065 | #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 | 11065 | #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 |
| 11066 | #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 | 11066 | #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 |
| 11067 | 11067 | ||
| 11068 | #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 | 11068 | #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 |
| 11069 | #define B_EC_VD_REG_REQ_SMB_CNT__W 16 | 11069 | #define B_EC_VD_REG_REQ_SMB_CNT__W 16 |
| 11070 | #define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF | 11070 | #define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF |
| 11071 | #define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 | 11071 | #define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 |
| 11072 | 11072 | ||
| 11073 | #define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 | 11073 | #define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 |
| 11074 | #define B_EC_VD_REG_REQ_BIT_CNT__W 16 | 11074 | #define B_EC_VD_REG_REQ_BIT_CNT__W 16 |
| 11075 | #define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF | 11075 | #define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF |
| 11076 | #define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF | 11076 | #define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF |
| 11077 | 11077 | ||
| 11078 | #define B_EC_VD_REG_RLK_ENA__A 0x2090014 | 11078 | #define B_EC_VD_REG_RLK_ENA__A 0x2090014 |
| 11079 | #define B_EC_VD_REG_RLK_ENA__W 1 | 11079 | #define B_EC_VD_REG_RLK_ENA__W 1 |
| 11080 | #define B_EC_VD_REG_RLK_ENA__M 0x1 | 11080 | #define B_EC_VD_REG_RLK_ENA__M 0x1 |
| 11081 | #define B_EC_VD_REG_RLK_ENA_INIT 0x1 | 11081 | #define B_EC_VD_REG_RLK_ENA_INIT 0x1 |
| 11082 | #define B_EC_VD_REG_RLK_ENA_OFF 0x0 | 11082 | #define B_EC_VD_REG_RLK_ENA_OFF 0x0 |
| 11083 | #define B_EC_VD_REG_RLK_ENA_ON 0x1 | 11083 | #define B_EC_VD_REG_RLK_ENA_ON 0x1 |
| 11084 | 11084 | ||
| 11085 | #define B_EC_VD_REG_VAL__A 0x2090015 | 11085 | #define B_EC_VD_REG_VAL__A 0x2090015 |
| 11086 | #define B_EC_VD_REG_VAL__W 2 | 11086 | #define B_EC_VD_REG_VAL__W 2 |
| 11087 | #define B_EC_VD_REG_VAL__M 0x3 | 11087 | #define B_EC_VD_REG_VAL__M 0x3 |
| 11088 | #define B_EC_VD_REG_VAL_INIT 0x0 | 11088 | #define B_EC_VD_REG_VAL_INIT 0x0 |
| 11089 | #define B_EC_VD_REG_VAL_CODE 0x1 | 11089 | #define B_EC_VD_REG_VAL_CODE 0x1 |
| 11090 | #define B_EC_VD_REG_VAL_CNT 0x2 | 11090 | #define B_EC_VD_REG_VAL_CNT 0x2 |
| 11091 | 11091 | ||
| 11092 | #define B_EC_VD_REG_GET_CODERATE__A 0x2090016 | 11092 | #define B_EC_VD_REG_GET_CODERATE__A 0x2090016 |
| 11093 | #define B_EC_VD_REG_GET_CODERATE__W 3 | 11093 | #define B_EC_VD_REG_GET_CODERATE__W 3 |
| 11094 | #define B_EC_VD_REG_GET_CODERATE__M 0x7 | 11094 | #define B_EC_VD_REG_GET_CODERATE__M 0x7 |
| 11095 | #define B_EC_VD_REG_GET_CODERATE_INIT 0x0 | 11095 | #define B_EC_VD_REG_GET_CODERATE_INIT 0x0 |
| 11096 | #define B_EC_VD_REG_GET_CODERATE_C1_2 0x0 | 11096 | #define B_EC_VD_REG_GET_CODERATE_C1_2 0x0 |
| 11097 | #define B_EC_VD_REG_GET_CODERATE_C2_3 0x1 | 11097 | #define B_EC_VD_REG_GET_CODERATE_C2_3 0x1 |
| 11098 | #define B_EC_VD_REG_GET_CODERATE_C3_4 0x2 | 11098 | #define B_EC_VD_REG_GET_CODERATE_C3_4 0x2 |
| 11099 | #define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 | 11099 | #define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 |
| 11100 | #define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 | 11100 | #define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 |
| 11101 | 11101 | ||
| 11102 | #define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 | 11102 | #define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 |
| 11103 | #define B_EC_VD_REG_ERR_BIT_CNT__W 16 | 11103 | #define B_EC_VD_REG_ERR_BIT_CNT__W 16 |
| 11104 | #define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF | 11104 | #define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF |
| 11105 | #define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF | 11105 | #define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF |
| 11106 | 11106 | ||
| 11107 | #define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 | 11107 | #define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 |
| 11108 | #define B_EC_VD_REG_IN_BIT_CNT__W 16 | 11108 | #define B_EC_VD_REG_IN_BIT_CNT__W 16 |
| 11109 | #define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF | 11109 | #define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF |
| 11110 | #define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 | 11110 | #define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 |
| 11111 | 11111 | ||
| 11112 | #define B_EC_VD_REG_STS__A 0x2090019 | 11112 | #define B_EC_VD_REG_STS__A 0x2090019 |
| 11113 | #define B_EC_VD_REG_STS__W 1 | 11113 | #define B_EC_VD_REG_STS__W 1 |
| 11114 | #define B_EC_VD_REG_STS__M 0x1 | 11114 | #define B_EC_VD_REG_STS__M 0x1 |
| 11115 | #define B_EC_VD_REG_STS_INIT 0x0 | 11115 | #define B_EC_VD_REG_STS_INIT 0x0 |
| 11116 | #define B_EC_VD_REG_STS_NO_LOCK 0x0 | 11116 | #define B_EC_VD_REG_STS_NO_LOCK 0x0 |
| 11117 | #define B_EC_VD_REG_STS_IN_LOCK 0x1 | 11117 | #define B_EC_VD_REG_STS_IN_LOCK 0x1 |
| 11118 | 11118 | ||
| 11119 | #define B_EC_VD_REG_RLK_CNT__A 0x209001A | 11119 | #define B_EC_VD_REG_RLK_CNT__A 0x209001A |
| 11120 | #define B_EC_VD_REG_RLK_CNT__W 16 | 11120 | #define B_EC_VD_REG_RLK_CNT__W 16 |
| 11121 | #define B_EC_VD_REG_RLK_CNT__M 0xFFFF | 11121 | #define B_EC_VD_REG_RLK_CNT__M 0xFFFF |
| 11122 | #define B_EC_VD_REG_RLK_CNT_INIT 0x0 | 11122 | #define B_EC_VD_REG_RLK_CNT_INIT 0x0 |
| 11123 | 11123 | ||
| 11124 | #define B_EC_VD_TB0_RAM__A 0x20A0000 | 11124 | #define B_EC_VD_TB0_RAM__A 0x20A0000 |
| 11125 | 11125 | ||
| 11126 | #define B_EC_VD_TB1_RAM__A 0x20B0000 | 11126 | #define B_EC_VD_TB1_RAM__A 0x20B0000 |
| 11127 | 11127 | ||
| 11128 | #define B_EC_VD_TB2_RAM__A 0x20C0000 | 11128 | #define B_EC_VD_TB2_RAM__A 0x20C0000 |
| 11129 | 11129 | ||
| 11130 | #define B_EC_VD_TB3_RAM__A 0x20D0000 | 11130 | #define B_EC_VD_TB3_RAM__A 0x20D0000 |
| 11131 | 11131 | ||
| 11132 | #define B_EC_VD_RE_RAM__A 0x2100000 | 11132 | #define B_EC_VD_RE_RAM__A 0x2100000 |
| 11133 | 11133 | ||
| 11134 | #define B_EC_OD_SID 0x18 | 11134 | #define B_EC_OD_SID 0x18 |
| 11135 | 11135 | ||
| 11136 | #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 | 11136 | #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 |
| 11137 | #define B_EC_OD_REG_COMM_EXEC__W 3 | 11137 | #define B_EC_OD_REG_COMM_EXEC__W 3 |
| 11138 | #define B_EC_OD_REG_COMM_EXEC__M 0x7 | 11138 | #define B_EC_OD_REG_COMM_EXEC__M 0x7 |
| 11139 | #define B_EC_OD_REG_COMM_EXEC_CTL__B 0 | 11139 | #define B_EC_OD_REG_COMM_EXEC_CTL__B 0 |
| 11140 | #define B_EC_OD_REG_COMM_EXEC_CTL__W 3 | 11140 | #define B_EC_OD_REG_COMM_EXEC_CTL__W 3 |
| 11141 | #define B_EC_OD_REG_COMM_EXEC_CTL__M 0x7 | 11141 | #define B_EC_OD_REG_COMM_EXEC_CTL__M 0x7 |
| 11142 | #define B_EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 | 11142 | #define B_EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 |
| 11143 | #define B_EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 11143 | #define B_EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 11144 | #define B_EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 | 11144 | #define B_EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 11145 | #define B_EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 | 11145 | #define B_EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 |
| 11146 | 11146 | ||
| 11147 | #define B_EC_OD_REG_COMM_STATE__A 0x2110001 | 11147 | #define B_EC_OD_REG_COMM_STATE__A 0x2110001 |
| 11148 | #define B_EC_OD_REG_COMM_STATE__W 1 | 11148 | #define B_EC_OD_REG_COMM_STATE__W 1 |
| 11149 | #define B_EC_OD_REG_COMM_STATE__M 0x1 | 11149 | #define B_EC_OD_REG_COMM_STATE__M 0x1 |
| 11150 | #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__B 0 | 11150 | #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__B 0 |
| 11151 | #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 | 11151 | #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 |
| 11152 | #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 | 11152 | #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 |
| 11153 | 11153 | ||
| 11154 | #define B_EC_OD_REG_COMM_MB__A 0x2110002 | 11154 | #define B_EC_OD_REG_COMM_MB__A 0x2110002 |
| 11155 | #define B_EC_OD_REG_COMM_MB__W 3 | 11155 | #define B_EC_OD_REG_COMM_MB__W 3 |
| 11156 | #define B_EC_OD_REG_COMM_MB__M 0x7 | 11156 | #define B_EC_OD_REG_COMM_MB__M 0x7 |
| 11157 | #define B_EC_OD_REG_COMM_MB_CTR__B 0 | 11157 | #define B_EC_OD_REG_COMM_MB_CTR__B 0 |
| 11158 | #define B_EC_OD_REG_COMM_MB_CTR__W 1 | 11158 | #define B_EC_OD_REG_COMM_MB_CTR__W 1 |
| 11159 | #define B_EC_OD_REG_COMM_MB_CTR__M 0x1 | 11159 | #define B_EC_OD_REG_COMM_MB_CTR__M 0x1 |
| 11160 | #define B_EC_OD_REG_COMM_MB_CTR_OFF 0x0 | 11160 | #define B_EC_OD_REG_COMM_MB_CTR_OFF 0x0 |
| 11161 | #define B_EC_OD_REG_COMM_MB_CTR_ON 0x1 | 11161 | #define B_EC_OD_REG_COMM_MB_CTR_ON 0x1 |
| 11162 | #define B_EC_OD_REG_COMM_MB_OBS__B 1 | 11162 | #define B_EC_OD_REG_COMM_MB_OBS__B 1 |
| 11163 | #define B_EC_OD_REG_COMM_MB_OBS__W 1 | 11163 | #define B_EC_OD_REG_COMM_MB_OBS__W 1 |
| 11164 | #define B_EC_OD_REG_COMM_MB_OBS__M 0x2 | 11164 | #define B_EC_OD_REG_COMM_MB_OBS__M 0x2 |
| 11165 | #define B_EC_OD_REG_COMM_MB_OBS_OFF 0x0 | 11165 | #define B_EC_OD_REG_COMM_MB_OBS_OFF 0x0 |
| 11166 | #define B_EC_OD_REG_COMM_MB_OBS_ON 0x2 | 11166 | #define B_EC_OD_REG_COMM_MB_OBS_ON 0x2 |
| 11167 | 11167 | ||
| 11168 | #define B_EC_OD_REG_COMM_SERVICE0__A 0x2110003 | 11168 | #define B_EC_OD_REG_COMM_SERVICE0__A 0x2110003 |
| 11169 | #define B_EC_OD_REG_COMM_SERVICE0__W 10 | 11169 | #define B_EC_OD_REG_COMM_SERVICE0__W 10 |
| 11170 | #define B_EC_OD_REG_COMM_SERVICE0__M 0x3FF | 11170 | #define B_EC_OD_REG_COMM_SERVICE0__M 0x3FF |
| 11171 | #define B_EC_OD_REG_COMM_SERVICE1__A 0x2110004 | 11171 | #define B_EC_OD_REG_COMM_SERVICE1__A 0x2110004 |
| 11172 | #define B_EC_OD_REG_COMM_SERVICE1__W 11 | 11172 | #define B_EC_OD_REG_COMM_SERVICE1__W 11 |
| 11173 | #define B_EC_OD_REG_COMM_SERVICE1__M 0x7FF | 11173 | #define B_EC_OD_REG_COMM_SERVICE1__M 0x7FF |
| 11174 | 11174 | ||
| 11175 | #define B_EC_OD_REG_COMM_ACTIVATE__A 0x2110005 | 11175 | #define B_EC_OD_REG_COMM_ACTIVATE__A 0x2110005 |
| 11176 | #define B_EC_OD_REG_COMM_ACTIVATE__W 2 | 11176 | #define B_EC_OD_REG_COMM_ACTIVATE__W 2 |
| 11177 | #define B_EC_OD_REG_COMM_ACTIVATE__M 0x3 | 11177 | #define B_EC_OD_REG_COMM_ACTIVATE__M 0x3 |
| 11178 | 11178 | ||
| 11179 | #define B_EC_OD_REG_COMM_COUNT__A 0x2110006 | 11179 | #define B_EC_OD_REG_COMM_COUNT__A 0x2110006 |
| 11180 | #define B_EC_OD_REG_COMM_COUNT__W 16 | 11180 | #define B_EC_OD_REG_COMM_COUNT__W 16 |
| 11181 | #define B_EC_OD_REG_COMM_COUNT__M 0xFFFF | 11181 | #define B_EC_OD_REG_COMM_COUNT__M 0xFFFF |
| 11182 | 11182 | ||
| 11183 | #define B_EC_OD_REG_COMM_INT_STA__A 0x2110007 | 11183 | #define B_EC_OD_REG_COMM_INT_STA__A 0x2110007 |
| 11184 | #define B_EC_OD_REG_COMM_INT_STA__W 2 | 11184 | #define B_EC_OD_REG_COMM_INT_STA__W 2 |
| 11185 | #define B_EC_OD_REG_COMM_INT_STA__M 0x3 | 11185 | #define B_EC_OD_REG_COMM_INT_STA__M 0x3 |
| 11186 | #define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 | 11186 | #define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 |
| 11187 | #define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 | 11187 | #define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 |
| 11188 | #define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 | 11188 | #define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 |
| 11189 | #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 | 11189 | #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 |
| 11190 | #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 | 11190 | #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 |
| 11191 | #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 | 11191 | #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 |
| 11192 | 11192 | ||
| 11193 | #define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 | 11193 | #define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 |
| 11194 | #define B_EC_OD_REG_COMM_INT_MSK__W 2 | 11194 | #define B_EC_OD_REG_COMM_INT_MSK__W 2 |
| 11195 | #define B_EC_OD_REG_COMM_INT_MSK__M 0x3 | 11195 | #define B_EC_OD_REG_COMM_INT_MSK__M 0x3 |
| 11196 | #define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 | 11196 | #define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 |
| 11197 | #define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 | 11197 | #define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 |
| 11198 | #define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 | 11198 | #define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 |
| 11199 | #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 | 11199 | #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 |
| 11200 | #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 | 11200 | #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 |
| 11201 | #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 | 11201 | #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 |
| 11202 | 11202 | ||
| 11203 | #define B_EC_OD_REG_SYNC__A 0x2110664 | 11203 | #define B_EC_OD_REG_SYNC__A 0x2110664 |
| 11204 | #define B_EC_OD_REG_SYNC__W 12 | 11204 | #define B_EC_OD_REG_SYNC__W 12 |
| 11205 | #define B_EC_OD_REG_SYNC__M 0xFFF | 11205 | #define B_EC_OD_REG_SYNC__M 0xFFF |
| 11206 | #define B_EC_OD_REG_SYNC_NR_SYNC__B 0 | 11206 | #define B_EC_OD_REG_SYNC_NR_SYNC__B 0 |
| 11207 | #define B_EC_OD_REG_SYNC_NR_SYNC__W 5 | 11207 | #define B_EC_OD_REG_SYNC_NR_SYNC__W 5 |
| 11208 | #define B_EC_OD_REG_SYNC_NR_SYNC__M 0x1F | 11208 | #define B_EC_OD_REG_SYNC_NR_SYNC__M 0x1F |
| 11209 | #define B_EC_OD_REG_SYNC_IN_SYNC__B 5 | 11209 | #define B_EC_OD_REG_SYNC_IN_SYNC__B 5 |
| 11210 | #define B_EC_OD_REG_SYNC_IN_SYNC__W 4 | 11210 | #define B_EC_OD_REG_SYNC_IN_SYNC__W 4 |
| 11211 | #define B_EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 | 11211 | #define B_EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 |
| 11212 | #define B_EC_OD_REG_SYNC_OUT_SYNC__B 9 | 11212 | #define B_EC_OD_REG_SYNC_OUT_SYNC__B 9 |
| 11213 | #define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 | 11213 | #define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 |
| 11214 | #define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 | 11214 | #define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 |
| 11215 | 11215 | ||
| 11216 | #define B_EC_OD_REG_NOSYNC__A 0x2110004 | 11216 | #define B_EC_OD_REG_NOSYNC__A 0x2110004 |
| 11217 | #define B_EC_OD_REG_NOSYNC__W 8 | 11217 | #define B_EC_OD_REG_NOSYNC__W 8 |
| 11218 | #define B_EC_OD_REG_NOSYNC__M 0xFF | 11218 | #define B_EC_OD_REG_NOSYNC__M 0xFF |
| 11219 | 11219 | ||
| 11220 | #define B_EC_OD_DEINT_RAM__A 0x2120000 | 11220 | #define B_EC_OD_DEINT_RAM__A 0x2120000 |
| 11221 | 11221 | ||
| 11222 | #define B_EC_RS_SID 0x19 | 11222 | #define B_EC_RS_SID 0x19 |
| 11223 | 11223 | ||
| 11224 | #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 | 11224 | #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 |
| 11225 | #define B_EC_RS_REG_COMM_EXEC__W 3 | 11225 | #define B_EC_RS_REG_COMM_EXEC__W 3 |
| 11226 | #define B_EC_RS_REG_COMM_EXEC__M 0x7 | 11226 | #define B_EC_RS_REG_COMM_EXEC__M 0x7 |
| 11227 | #define B_EC_RS_REG_COMM_EXEC_CTL__B 0 | 11227 | #define B_EC_RS_REG_COMM_EXEC_CTL__B 0 |
| 11228 | #define B_EC_RS_REG_COMM_EXEC_CTL__W 3 | 11228 | #define B_EC_RS_REG_COMM_EXEC_CTL__W 3 |
| 11229 | #define B_EC_RS_REG_COMM_EXEC_CTL__M 0x7 | 11229 | #define B_EC_RS_REG_COMM_EXEC_CTL__M 0x7 |
| 11230 | #define B_EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 | 11230 | #define B_EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 |
| 11231 | #define B_EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 11231 | #define B_EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 11232 | #define B_EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 | 11232 | #define B_EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 11233 | 11233 | ||
| 11234 | #define B_EC_RS_REG_COMM_STATE__A 0x2130001 | 11234 | #define B_EC_RS_REG_COMM_STATE__A 0x2130001 |
| 11235 | #define B_EC_RS_REG_COMM_STATE__W 4 | 11235 | #define B_EC_RS_REG_COMM_STATE__W 4 |
| 11236 | #define B_EC_RS_REG_COMM_STATE__M 0xF | 11236 | #define B_EC_RS_REG_COMM_STATE__M 0xF |
| 11237 | #define B_EC_RS_REG_COMM_MB__A 0x2130002 | 11237 | #define B_EC_RS_REG_COMM_MB__A 0x2130002 |
| 11238 | #define B_EC_RS_REG_COMM_MB__W 2 | 11238 | #define B_EC_RS_REG_COMM_MB__W 2 |
| 11239 | #define B_EC_RS_REG_COMM_MB__M 0x3 | 11239 | #define B_EC_RS_REG_COMM_MB__M 0x3 |
| 11240 | #define B_EC_RS_REG_COMM_MB_CTR__B 0 | 11240 | #define B_EC_RS_REG_COMM_MB_CTR__B 0 |
| 11241 | #define B_EC_RS_REG_COMM_MB_CTR__W 1 | 11241 | #define B_EC_RS_REG_COMM_MB_CTR__W 1 |
| 11242 | #define B_EC_RS_REG_COMM_MB_CTR__M 0x1 | 11242 | #define B_EC_RS_REG_COMM_MB_CTR__M 0x1 |
| 11243 | #define B_EC_RS_REG_COMM_MB_CTR_OFF 0x0 | 11243 | #define B_EC_RS_REG_COMM_MB_CTR_OFF 0x0 |
| 11244 | #define B_EC_RS_REG_COMM_MB_CTR_ON 0x1 | 11244 | #define B_EC_RS_REG_COMM_MB_CTR_ON 0x1 |
| 11245 | #define B_EC_RS_REG_COMM_MB_OBS__B 1 | 11245 | #define B_EC_RS_REG_COMM_MB_OBS__B 1 |
| 11246 | #define B_EC_RS_REG_COMM_MB_OBS__W 1 | 11246 | #define B_EC_RS_REG_COMM_MB_OBS__W 1 |
| 11247 | #define B_EC_RS_REG_COMM_MB_OBS__M 0x2 | 11247 | #define B_EC_RS_REG_COMM_MB_OBS__M 0x2 |
| 11248 | #define B_EC_RS_REG_COMM_MB_OBS_OFF 0x0 | 11248 | #define B_EC_RS_REG_COMM_MB_OBS_OFF 0x0 |
| 11249 | #define B_EC_RS_REG_COMM_MB_OBS_ON 0x2 | 11249 | #define B_EC_RS_REG_COMM_MB_OBS_ON 0x2 |
| 11250 | 11250 | ||
| 11251 | #define B_EC_RS_REG_COMM_SERVICE0__A 0x2130003 | 11251 | #define B_EC_RS_REG_COMM_SERVICE0__A 0x2130003 |
| 11252 | #define B_EC_RS_REG_COMM_SERVICE0__W 16 | 11252 | #define B_EC_RS_REG_COMM_SERVICE0__W 16 |
| 11253 | #define B_EC_RS_REG_COMM_SERVICE0__M 0xFFFF | 11253 | #define B_EC_RS_REG_COMM_SERVICE0__M 0xFFFF |
| 11254 | #define B_EC_RS_REG_COMM_SERVICE1__A 0x2130004 | 11254 | #define B_EC_RS_REG_COMM_SERVICE1__A 0x2130004 |
| 11255 | #define B_EC_RS_REG_COMM_SERVICE1__W 16 | 11255 | #define B_EC_RS_REG_COMM_SERVICE1__W 16 |
| 11256 | #define B_EC_RS_REG_COMM_SERVICE1__M 0xFFFF | 11256 | #define B_EC_RS_REG_COMM_SERVICE1__M 0xFFFF |
| 11257 | #define B_EC_RS_REG_COMM_INT_STA__A 0x2130007 | 11257 | #define B_EC_RS_REG_COMM_INT_STA__A 0x2130007 |
| 11258 | #define B_EC_RS_REG_COMM_INT_STA__W 1 | 11258 | #define B_EC_RS_REG_COMM_INT_STA__W 1 |
| 11259 | #define B_EC_RS_REG_COMM_INT_STA__M 0x1 | 11259 | #define B_EC_RS_REG_COMM_INT_STA__M 0x1 |
| 11260 | #define B_EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 | 11260 | #define B_EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 |
| 11261 | #define B_EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 | 11261 | #define B_EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 |
| 11262 | #define B_EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 | 11262 | #define B_EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 |
| 11263 | 11263 | ||
| 11264 | #define B_EC_RS_REG_COMM_INT_MSK__A 0x2130008 | 11264 | #define B_EC_RS_REG_COMM_INT_MSK__A 0x2130008 |
| 11265 | #define B_EC_RS_REG_COMM_INT_MSK__W 1 | 11265 | #define B_EC_RS_REG_COMM_INT_MSK__W 1 |
| 11266 | #define B_EC_RS_REG_COMM_INT_MSK__M 0x1 | 11266 | #define B_EC_RS_REG_COMM_INT_MSK__M 0x1 |
| 11267 | #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 | 11267 | #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 |
| 11268 | #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 | 11268 | #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 |
| 11269 | #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 | 11269 | #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 |
| 11270 | 11270 | ||
| 11271 | #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 | 11271 | #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 |
| 11272 | #define B_EC_RS_REG_REQ_PCK_CNT__W 16 | 11272 | #define B_EC_RS_REG_REQ_PCK_CNT__W 16 |
| 11273 | #define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF | 11273 | #define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF |
| 11274 | #define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 | 11274 | #define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 |
| 11275 | 11275 | ||
| 11276 | #define B_EC_RS_REG_VAL__A 0x2130011 | 11276 | #define B_EC_RS_REG_VAL__A 0x2130011 |
| 11277 | #define B_EC_RS_REG_VAL__W 1 | 11277 | #define B_EC_RS_REG_VAL__W 1 |
| 11278 | #define B_EC_RS_REG_VAL__M 0x1 | 11278 | #define B_EC_RS_REG_VAL__M 0x1 |
| 11279 | #define B_EC_RS_REG_VAL_INIT 0x0 | 11279 | #define B_EC_RS_REG_VAL_INIT 0x0 |
| 11280 | #define B_EC_RS_REG_VAL_PCK 0x1 | 11280 | #define B_EC_RS_REG_VAL_PCK 0x1 |
| 11281 | 11281 | ||
| 11282 | #define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 | 11282 | #define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 |
| 11283 | #define B_EC_RS_REG_ERR_PCK_CNT__W 16 | 11283 | #define B_EC_RS_REG_ERR_PCK_CNT__W 16 |
| 11284 | #define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF | 11284 | #define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF |
| 11285 | #define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF | 11285 | #define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF |
| 11286 | 11286 | ||
| 11287 | #define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 | 11287 | #define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 |
| 11288 | #define B_EC_RS_REG_ERR_SMB_CNT__W 16 | 11288 | #define B_EC_RS_REG_ERR_SMB_CNT__W 16 |
| 11289 | #define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF | 11289 | #define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF |
| 11290 | #define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF | 11290 | #define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF |
| 11291 | 11291 | ||
| 11292 | #define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 | 11292 | #define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 |
| 11293 | #define B_EC_RS_REG_ERR_BIT_CNT__W 16 | 11293 | #define B_EC_RS_REG_ERR_BIT_CNT__W 16 |
| 11294 | #define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF | 11294 | #define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF |
| 11295 | #define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF | 11295 | #define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF |
| 11296 | 11296 | ||
| 11297 | #define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 | 11297 | #define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 |
| 11298 | #define B_EC_RS_REG_IN_PCK_CNT__W 16 | 11298 | #define B_EC_RS_REG_IN_PCK_CNT__W 16 |
| 11299 | #define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF | 11299 | #define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF |
| 11300 | #define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 | 11300 | #define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 |
| 11301 | 11301 | ||
| 11302 | #define B_EC_RS_EC_RAM__A 0x2140000 | 11302 | #define B_EC_RS_EC_RAM__A 0x2140000 |
| 11303 | 11303 | ||
| 11304 | #define B_EC_OC_SID 0x1A | 11304 | #define B_EC_OC_SID 0x1A |
| 11305 | 11305 | ||
| 11306 | #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 | 11306 | #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 |
| 11307 | #define B_EC_OC_REG_COMM_EXEC__W 3 | 11307 | #define B_EC_OC_REG_COMM_EXEC__W 3 |
| 11308 | #define B_EC_OC_REG_COMM_EXEC__M 0x7 | 11308 | #define B_EC_OC_REG_COMM_EXEC__M 0x7 |
| 11309 | #define B_EC_OC_REG_COMM_EXEC_CTL__B 0 | 11309 | #define B_EC_OC_REG_COMM_EXEC_CTL__B 0 |
| 11310 | #define B_EC_OC_REG_COMM_EXEC_CTL__W 3 | 11310 | #define B_EC_OC_REG_COMM_EXEC_CTL__W 3 |
| 11311 | #define B_EC_OC_REG_COMM_EXEC_CTL__M 0x7 | 11311 | #define B_EC_OC_REG_COMM_EXEC_CTL__M 0x7 |
| 11312 | #define B_EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 | 11312 | #define B_EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 |
| 11313 | #define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 11313 | #define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 11314 | #define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 | 11314 | #define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 11315 | #define B_EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 | 11315 | #define B_EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 |
| 11316 | 11316 | ||
| 11317 | #define B_EC_OC_REG_COMM_STATE__A 0x2150001 | 11317 | #define B_EC_OC_REG_COMM_STATE__A 0x2150001 |
| 11318 | #define B_EC_OC_REG_COMM_STATE__W 4 | 11318 | #define B_EC_OC_REG_COMM_STATE__W 4 |
| 11319 | #define B_EC_OC_REG_COMM_STATE__M 0xF | 11319 | #define B_EC_OC_REG_COMM_STATE__M 0xF |
| 11320 | 11320 | ||
| 11321 | #define B_EC_OC_REG_COMM_MB__A 0x2150002 | 11321 | #define B_EC_OC_REG_COMM_MB__A 0x2150002 |
| 11322 | #define B_EC_OC_REG_COMM_MB__W 2 | 11322 | #define B_EC_OC_REG_COMM_MB__W 2 |
| 11323 | #define B_EC_OC_REG_COMM_MB__M 0x3 | 11323 | #define B_EC_OC_REG_COMM_MB__M 0x3 |
| 11324 | #define B_EC_OC_REG_COMM_MB_CTR__B 0 | 11324 | #define B_EC_OC_REG_COMM_MB_CTR__B 0 |
| 11325 | #define B_EC_OC_REG_COMM_MB_CTR__W 1 | 11325 | #define B_EC_OC_REG_COMM_MB_CTR__W 1 |
| 11326 | #define B_EC_OC_REG_COMM_MB_CTR__M 0x1 | 11326 | #define B_EC_OC_REG_COMM_MB_CTR__M 0x1 |
| 11327 | #define B_EC_OC_REG_COMM_MB_CTR_OFF 0x0 | 11327 | #define B_EC_OC_REG_COMM_MB_CTR_OFF 0x0 |
| 11328 | #define B_EC_OC_REG_COMM_MB_CTR_ON 0x1 | 11328 | #define B_EC_OC_REG_COMM_MB_CTR_ON 0x1 |
| 11329 | #define B_EC_OC_REG_COMM_MB_OBS__B 1 | 11329 | #define B_EC_OC_REG_COMM_MB_OBS__B 1 |
| 11330 | #define B_EC_OC_REG_COMM_MB_OBS__W 1 | 11330 | #define B_EC_OC_REG_COMM_MB_OBS__W 1 |
| 11331 | #define B_EC_OC_REG_COMM_MB_OBS__M 0x2 | 11331 | #define B_EC_OC_REG_COMM_MB_OBS__M 0x2 |
| 11332 | #define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 | 11332 | #define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 |
| 11333 | #define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 | 11333 | #define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 |
| 11334 | 11334 | ||
| 11335 | #define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 | 11335 | #define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 |
| 11336 | #define B_EC_OC_REG_COMM_SERVICE0__W 10 | 11336 | #define B_EC_OC_REG_COMM_SERVICE0__W 10 |
| 11337 | #define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF | 11337 | #define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF |
| 11338 | 11338 | ||
| 11339 | #define B_EC_OC_REG_COMM_SERVICE1__A 0x2150004 | 11339 | #define B_EC_OC_REG_COMM_SERVICE1__A 0x2150004 |
| 11340 | #define B_EC_OC_REG_COMM_SERVICE1__W 11 | 11340 | #define B_EC_OC_REG_COMM_SERVICE1__W 11 |
| 11341 | #define B_EC_OC_REG_COMM_SERVICE1__M 0x7FF | 11341 | #define B_EC_OC_REG_COMM_SERVICE1__M 0x7FF |
| 11342 | 11342 | ||
| 11343 | #define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 | 11343 | #define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 |
| 11344 | #define B_EC_OC_REG_COMM_INT_STA__W 6 | 11344 | #define B_EC_OC_REG_COMM_INT_STA__W 6 |
| 11345 | #define B_EC_OC_REG_COMM_INT_STA__M 0x3F | 11345 | #define B_EC_OC_REG_COMM_INT_STA__M 0x3F |
| 11346 | #define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 | 11346 | #define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 |
| 11347 | #define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 | 11347 | #define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 |
| 11348 | #define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 | 11348 | #define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 |
| 11349 | #define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 | 11349 | #define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 |
| 11350 | #define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 | 11350 | #define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 |
| 11351 | #define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 | 11351 | #define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 |
| 11352 | #define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 | 11352 | #define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 |
| 11353 | #define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 | 11353 | #define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 |
| 11354 | #define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 | 11354 | #define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 |
| 11355 | #define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 | 11355 | #define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 |
| 11356 | #define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 | 11356 | #define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 |
| 11357 | #define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 | 11357 | #define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 |
| 11358 | #define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 | 11358 | #define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 |
| 11359 | #define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 | 11359 | #define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 |
| 11360 | #define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 | 11360 | #define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 |
| 11361 | #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 | 11361 | #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 |
| 11362 | #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 | 11362 | #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 |
| 11363 | #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 | 11363 | #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 |
| 11364 | 11364 | ||
| 11365 | #define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 | 11365 | #define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 |
| 11366 | #define B_EC_OC_REG_COMM_INT_MSK__W 6 | 11366 | #define B_EC_OC_REG_COMM_INT_MSK__W 6 |
| 11367 | #define B_EC_OC_REG_COMM_INT_MSK__M 0x3F | 11367 | #define B_EC_OC_REG_COMM_INT_MSK__M 0x3F |
| 11368 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 | 11368 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 |
| 11369 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 | 11369 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 |
| 11370 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 | 11370 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 |
| 11371 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 | 11371 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 |
| 11372 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 | 11372 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 |
| 11373 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 | 11373 | #define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 |
| 11374 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 | 11374 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 |
| 11375 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 | 11375 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 |
| 11376 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 | 11376 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 |
| 11377 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 | 11377 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 |
| 11378 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 | 11378 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 |
| 11379 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 | 11379 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 |
| 11380 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 | 11380 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 |
| 11381 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 | 11381 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 |
| 11382 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 | 11382 | #define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 |
| 11383 | #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 | 11383 | #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 |
| 11384 | #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 | 11384 | #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 |
| 11385 | #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 | 11385 | #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 |
| 11386 | 11386 | ||
| 11387 | #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 | 11387 | #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 |
| 11388 | #define B_EC_OC_REG_OC_MODE_LOP__W 16 | 11388 | #define B_EC_OC_REG_OC_MODE_LOP__W 16 |
| 11389 | #define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF | 11389 | #define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF |
| 11390 | #define B_EC_OC_REG_OC_MODE_LOP_INIT 0x0 | 11390 | #define B_EC_OC_REG_OC_MODE_LOP_INIT 0x0 |
| 11391 | 11391 | ||
| 11392 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 | 11392 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 |
| 11393 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 | 11393 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 |
| 11394 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 | 11394 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 |
| 11395 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 | 11395 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 |
| 11396 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 | 11396 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 |
| 11397 | 11397 | ||
| 11398 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 | 11398 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 |
| 11399 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 | 11399 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 |
| 11400 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 | 11400 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 |
| 11401 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 | 11401 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 |
| 11402 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 | 11402 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 |
| 11403 | 11403 | ||
| 11404 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 | 11404 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 |
| 11405 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 | 11405 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 |
| 11406 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 | 11406 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 |
| 11407 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 | 11407 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 |
| 11408 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 | 11408 | #define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 |
| 11409 | 11409 | ||
| 11410 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 | 11410 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 |
| 11411 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 | 11411 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 |
| 11412 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 | 11412 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 |
| 11413 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 | 11413 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 |
| 11414 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 | 11414 | #define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 |
| 11415 | 11415 | ||
| 11416 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 | 11416 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 |
| 11417 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 | 11417 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 |
| 11418 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 | 11418 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 |
| 11419 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 | 11419 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 |
| 11420 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 | 11420 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 |
| 11421 | 11421 | ||
| 11422 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 | 11422 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 |
| 11423 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 | 11423 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 |
| 11424 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 | 11424 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 |
| 11425 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 | 11425 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 |
| 11426 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 | 11426 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 |
| 11427 | 11427 | ||
| 11428 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 | 11428 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 |
| 11429 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 | 11429 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 |
| 11430 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 | 11430 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 |
| 11431 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 | 11431 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 |
| 11432 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 | 11432 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 |
| 11433 | 11433 | ||
| 11434 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 | 11434 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 |
| 11435 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 | 11435 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 |
| 11436 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 | 11436 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 |
| 11437 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 | 11437 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 |
| 11438 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 | 11438 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 |
| 11439 | 11439 | ||
| 11440 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 | 11440 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 |
| 11441 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 | 11441 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 |
| 11442 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 | 11442 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 |
| 11443 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 | 11443 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 |
| 11444 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 | 11444 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 |
| 11445 | 11445 | ||
| 11446 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 | 11446 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 |
| 11447 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 | 11447 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 |
| 11448 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 | 11448 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 |
| 11449 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 | 11449 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 |
| 11450 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 | 11450 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 |
| 11451 | 11451 | ||
| 11452 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 | 11452 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 |
| 11453 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 | 11453 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 |
| 11454 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 | 11454 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 |
| 11455 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 | 11455 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 |
| 11456 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 | 11456 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 |
| 11457 | 11457 | ||
| 11458 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 | 11458 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 |
| 11459 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 | 11459 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 |
| 11460 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 | 11460 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 |
| 11461 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 | 11461 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 |
| 11462 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 | 11462 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 |
| 11463 | 11463 | ||
| 11464 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 | 11464 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 |
| 11465 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 | 11465 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 |
| 11466 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 | 11466 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 |
| 11467 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 | 11467 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 |
| 11468 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 | 11468 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 |
| 11469 | 11469 | ||
| 11470 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 | 11470 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 |
| 11471 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 | 11471 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 |
| 11472 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 | 11472 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 |
| 11473 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 | 11473 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 |
| 11474 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 | 11474 | #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 |
| 11475 | 11475 | ||
| 11476 | #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 | 11476 | #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 |
| 11477 | #define B_EC_OC_REG_OC_MODE_HIP__W 15 | 11477 | #define B_EC_OC_REG_OC_MODE_HIP__W 15 |
| 11478 | #define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF | 11478 | #define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF |
| 11479 | #define B_EC_OC_REG_OC_MODE_HIP_INIT 0x5 | 11479 | #define B_EC_OC_REG_OC_MODE_HIP_INIT 0x5 |
| 11480 | 11480 | ||
| 11481 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 | 11481 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 |
| 11482 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 | 11482 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 |
| 11483 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 | 11483 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 |
| 11484 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 | 11484 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 |
| 11485 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 | 11485 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 |
| 11486 | 11486 | ||
| 11487 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 | 11487 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 |
| 11488 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 | 11488 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 |
| 11489 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 | 11489 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 |
| 11490 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 | 11490 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 |
| 11491 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 | 11491 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 |
| 11492 | 11492 | ||
| 11493 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 | 11493 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 |
| 11494 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 | 11494 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 |
| 11495 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 | 11495 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 |
| 11496 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 | 11496 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 |
| 11497 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 | 11497 | #define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 |
| 11498 | 11498 | ||
| 11499 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 | 11499 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 |
| 11500 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 | 11500 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 |
| 11501 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 | 11501 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 |
| 11502 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 | 11502 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 |
| 11503 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 | 11503 | #define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 |
| 11504 | 11504 | ||
| 11505 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 | 11505 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 |
| 11506 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 | 11506 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 |
| 11507 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 | 11507 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 |
| 11508 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 | 11508 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 |
| 11509 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 | 11509 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 |
| 11510 | 11510 | ||
| 11511 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 | 11511 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 |
| 11512 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 | 11512 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 |
| 11513 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 | 11513 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 |
| 11514 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 | 11514 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 |
| 11515 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 | 11515 | #define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 |
| 11516 | 11516 | ||
| 11517 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 | 11517 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 |
| 11518 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 | 11518 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 |
| 11519 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 | 11519 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 |
| 11520 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 | 11520 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 |
| 11521 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 | 11521 | #define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 |
| 11522 | 11522 | ||
| 11523 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 | 11523 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 |
| 11524 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 | 11524 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 |
| 11525 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 | 11525 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 |
| 11526 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 | 11526 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 |
| 11527 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 | 11527 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 |
| 11528 | 11528 | ||
| 11529 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 | 11529 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 |
| 11530 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 | 11530 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 |
| 11531 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 | 11531 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 |
| 11532 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 | 11532 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 |
| 11533 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 | 11533 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 |
| 11534 | 11534 | ||
| 11535 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 | 11535 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 |
| 11536 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 | 11536 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 |
| 11537 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 | 11537 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 |
| 11538 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 | 11538 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 |
| 11539 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 | 11539 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 |
| 11540 | 11540 | ||
| 11541 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 | 11541 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 |
| 11542 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 | 11542 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 |
| 11543 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 | 11543 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 |
| 11544 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 | 11544 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 |
| 11545 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 | 11545 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 |
| 11546 | 11546 | ||
| 11547 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 | 11547 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 |
| 11548 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 | 11548 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 |
| 11549 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 | 11549 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 |
| 11550 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 | 11550 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 |
| 11551 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 | 11551 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 |
| 11552 | 11552 | ||
| 11553 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 | 11553 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 |
| 11554 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 | 11554 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 |
| 11555 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 | 11555 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 |
| 11556 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 | 11556 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 |
| 11557 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 | 11557 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 |
| 11558 | 11558 | ||
| 11559 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 | 11559 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 |
| 11560 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 | 11560 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 |
| 11561 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 | 11561 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 |
| 11562 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 | 11562 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 |
| 11563 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 | 11563 | #define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 |
| 11564 | 11564 | ||
| 11565 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__B 14 | 11565 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__B 14 |
| 11566 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__W 1 | 11566 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__W 1 |
| 11567 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__M 0x4000 | 11567 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__M 0x4000 |
| 11568 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 | 11568 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 |
| 11569 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 | 11569 | #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 |
| 11570 | 11570 | ||
| 11571 | #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 | 11571 | #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 |
| 11572 | #define B_EC_OC_REG_OC_MPG_SIO__W 12 | 11572 | #define B_EC_OC_REG_OC_MPG_SIO__W 12 |
| 11573 | #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF | 11573 | #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF |
| 11574 | #define B_EC_OC_REG_OC_MPG_SIO_INIT 0xFFF | 11574 | #define B_EC_OC_REG_OC_MPG_SIO_INIT 0xFFF |
| 11575 | 11575 | ||
| 11576 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 | 11576 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 |
| 11577 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 | 11577 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 |
| 11578 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 | 11578 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 |
| 11579 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 | 11579 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 |
| 11580 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 | 11580 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 |
| 11581 | 11581 | ||
| 11582 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 | 11582 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 |
| 11583 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 | 11583 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 |
| 11584 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 | 11584 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 |
| 11585 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 | 11585 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 |
| 11586 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 | 11586 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 |
| 11587 | 11587 | ||
| 11588 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 | 11588 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 |
| 11589 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 | 11589 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 |
| 11590 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 | 11590 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 |
| 11591 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 | 11591 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 |
| 11592 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 | 11592 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 |
| 11593 | 11593 | ||
| 11594 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 | 11594 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 |
| 11595 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 | 11595 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 |
| 11596 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 | 11596 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 |
| 11597 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 | 11597 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 |
| 11598 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 | 11598 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 |
| 11599 | 11599 | ||
| 11600 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 | 11600 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 |
| 11601 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 | 11601 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 |
| 11602 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 | 11602 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 |
| 11603 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 | 11603 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 |
| 11604 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 | 11604 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 |
| 11605 | 11605 | ||
| 11606 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 | 11606 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 |
| 11607 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 | 11607 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 |
| 11608 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 | 11608 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 |
| 11609 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 | 11609 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 |
| 11610 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 | 11610 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 |
| 11611 | 11611 | ||
| 11612 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 | 11612 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 |
| 11613 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 | 11613 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 |
| 11614 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 | 11614 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 |
| 11615 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 | 11615 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 |
| 11616 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 | 11616 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 |
| 11617 | 11617 | ||
| 11618 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 | 11618 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 |
| 11619 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 | 11619 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 |
| 11620 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 | 11620 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 |
| 11621 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 | 11621 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 |
| 11622 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 | 11622 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 |
| 11623 | 11623 | ||
| 11624 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 | 11624 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 |
| 11625 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 | 11625 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 |
| 11626 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 | 11626 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 |
| 11627 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 | 11627 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 |
| 11628 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 | 11628 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 |
| 11629 | 11629 | ||
| 11630 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 | 11630 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 |
| 11631 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 | 11631 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 |
| 11632 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 | 11632 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 |
| 11633 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 | 11633 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 |
| 11634 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 | 11634 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 |
| 11635 | 11635 | ||
| 11636 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 | 11636 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 |
| 11637 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 | 11637 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 |
| 11638 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 | 11638 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 |
| 11639 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 | 11639 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 |
| 11640 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 | 11640 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 |
| 11641 | 11641 | ||
| 11642 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 | 11642 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 |
| 11643 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 | 11643 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 |
| 11644 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 | 11644 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 |
| 11645 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 | 11645 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 |
| 11646 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 | 11646 | #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 |
| 11647 | 11647 | ||
| 11648 | #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 | 11648 | #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 |
| 11649 | #define B_EC_OC_REG_DTO_INC_LOP__W 16 | 11649 | #define B_EC_OC_REG_DTO_INC_LOP__W 16 |
| 11650 | #define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF | 11650 | #define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF |
| 11651 | #define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 | 11651 | #define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 |
| 11652 | 11652 | ||
| 11653 | #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 | 11653 | #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 |
| 11654 | #define B_EC_OC_REG_DTO_INC_HIP__W 8 | 11654 | #define B_EC_OC_REG_DTO_INC_HIP__W 8 |
| 11655 | #define B_EC_OC_REG_DTO_INC_HIP__M 0xFF | 11655 | #define B_EC_OC_REG_DTO_INC_HIP__M 0xFF |
| 11656 | #define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 | 11656 | #define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 |
| 11657 | 11657 | ||
| 11658 | #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 | 11658 | #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 |
| 11659 | #define B_EC_OC_REG_SNC_ISC_LVL__W 12 | 11659 | #define B_EC_OC_REG_SNC_ISC_LVL__W 12 |
| 11660 | #define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF | 11660 | #define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF |
| 11661 | #define B_EC_OC_REG_SNC_ISC_LVL_INIT 0x422 | 11661 | #define B_EC_OC_REG_SNC_ISC_LVL_INIT 0x422 |
| 11662 | 11662 | ||
| 11663 | #define B_EC_OC_REG_SNC_ISC_LVL_ISC__B 0 | 11663 | #define B_EC_OC_REG_SNC_ISC_LVL_ISC__B 0 |
| 11664 | #define B_EC_OC_REG_SNC_ISC_LVL_ISC__W 4 | 11664 | #define B_EC_OC_REG_SNC_ISC_LVL_ISC__W 4 |
| 11665 | #define B_EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF | 11665 | #define B_EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF |
| 11666 | 11666 | ||
| 11667 | #define B_EC_OC_REG_SNC_ISC_LVL_OSC__B 4 | 11667 | #define B_EC_OC_REG_SNC_ISC_LVL_OSC__B 4 |
| 11668 | #define B_EC_OC_REG_SNC_ISC_LVL_OSC__W 4 | 11668 | #define B_EC_OC_REG_SNC_ISC_LVL_OSC__W 4 |
| 11669 | #define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 | 11669 | #define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 |
| 11670 | 11670 | ||
| 11671 | #define B_EC_OC_REG_SNC_ISC_LVL_NSC__B 8 | 11671 | #define B_EC_OC_REG_SNC_ISC_LVL_NSC__B 8 |
| 11672 | #define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 | 11672 | #define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 |
| 11673 | #define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 | 11673 | #define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 |
| 11674 | 11674 | ||
| 11675 | #define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 | 11675 | #define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 |
| 11676 | #define B_EC_OC_REG_SNC_NSC_LVL__W 8 | 11676 | #define B_EC_OC_REG_SNC_NSC_LVL__W 8 |
| 11677 | #define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF | 11677 | #define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF |
| 11678 | #define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 | 11678 | #define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 |
| 11679 | 11679 | ||
| 11680 | #define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 | 11680 | #define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 |
| 11681 | #define B_EC_OC_REG_SNC_SNC_MODE__W 2 | 11681 | #define B_EC_OC_REG_SNC_SNC_MODE__W 2 |
| 11682 | #define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 | 11682 | #define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 |
| 11683 | #define B_EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 | 11683 | #define B_EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 |
| 11684 | #define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 | 11684 | #define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 |
| 11685 | #define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 | 11685 | #define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 |
| 11686 | 11686 | ||
| 11687 | #define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A | 11687 | #define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A |
| 11688 | #define B_EC_OC_REG_SNC_PCK_NMB__W 16 | 11688 | #define B_EC_OC_REG_SNC_PCK_NMB__W 16 |
| 11689 | #define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF | 11689 | #define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF |
| 11690 | 11690 | ||
| 11691 | #define B_EC_OC_REG_SNC_PCK_CNT__A 0x215001B | 11691 | #define B_EC_OC_REG_SNC_PCK_CNT__A 0x215001B |
| 11692 | #define B_EC_OC_REG_SNC_PCK_CNT__W 16 | 11692 | #define B_EC_OC_REG_SNC_PCK_CNT__W 16 |
| 11693 | #define B_EC_OC_REG_SNC_PCK_CNT__M 0xFFFF | 11693 | #define B_EC_OC_REG_SNC_PCK_CNT__M 0xFFFF |
| 11694 | 11694 | ||
| 11695 | #define B_EC_OC_REG_SNC_PCK_ERR__A 0x215001C | 11695 | #define B_EC_OC_REG_SNC_PCK_ERR__A 0x215001C |
| 11696 | #define B_EC_OC_REG_SNC_PCK_ERR__W 16 | 11696 | #define B_EC_OC_REG_SNC_PCK_ERR__W 16 |
| 11697 | #define B_EC_OC_REG_SNC_PCK_ERR__M 0xFFFF | 11697 | #define B_EC_OC_REG_SNC_PCK_ERR__M 0xFFFF |
| 11698 | 11698 | ||
| 11699 | #define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D | 11699 | #define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D |
| 11700 | #define B_EC_OC_REG_TMD_TOP_MODE__W 2 | 11700 | #define B_EC_OC_REG_TMD_TOP_MODE__W 2 |
| 11701 | #define B_EC_OC_REG_TMD_TOP_MODE__M 0x3 | 11701 | #define B_EC_OC_REG_TMD_TOP_MODE__M 0x3 |
| 11702 | #define B_EC_OC_REG_TMD_TOP_MODE_INIT 0x3 | 11702 | #define B_EC_OC_REG_TMD_TOP_MODE_INIT 0x3 |
| 11703 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 | 11703 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 |
| 11704 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 | 11704 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 |
| 11705 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 | 11705 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 |
| 11706 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 | 11706 | #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 |
| 11707 | 11707 | ||
| 11708 | #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E | 11708 | #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E |
| 11709 | #define B_EC_OC_REG_TMD_TOP_CNT__W 10 | 11709 | #define B_EC_OC_REG_TMD_TOP_CNT__W 10 |
| 11710 | #define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF | 11710 | #define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF |
| 11711 | #define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 | 11711 | #define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 |
| 11712 | 11712 | ||
| 11713 | #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F | 11713 | #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F |
| 11714 | #define B_EC_OC_REG_TMD_HIL_MAR__W 10 | 11714 | #define B_EC_OC_REG_TMD_HIL_MAR__W 10 |
| 11715 | #define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF | 11715 | #define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF |
| 11716 | #define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 | 11716 | #define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 |
| 11717 | 11717 | ||
| 11718 | #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 | 11718 | #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 |
| 11719 | #define B_EC_OC_REG_TMD_LOL_MAR__W 10 | 11719 | #define B_EC_OC_REG_TMD_LOL_MAR__W 10 |
| 11720 | #define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF | 11720 | #define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF |
| 11721 | #define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 | 11721 | #define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 |
| 11722 | 11722 | ||
| 11723 | #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 | 11723 | #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 |
| 11724 | #define B_EC_OC_REG_TMD_CUR_CNT__W 4 | 11724 | #define B_EC_OC_REG_TMD_CUR_CNT__W 4 |
| 11725 | #define B_EC_OC_REG_TMD_CUR_CNT__M 0xF | 11725 | #define B_EC_OC_REG_TMD_CUR_CNT__M 0xF |
| 11726 | #define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 | 11726 | #define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 |
| 11727 | 11727 | ||
| 11728 | #define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 | 11728 | #define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 |
| 11729 | #define B_EC_OC_REG_TMD_IUR_CNT__W 4 | 11729 | #define B_EC_OC_REG_TMD_IUR_CNT__W 4 |
| 11730 | #define B_EC_OC_REG_TMD_IUR_CNT__M 0xF | 11730 | #define B_EC_OC_REG_TMD_IUR_CNT__M 0xF |
| 11731 | #define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 | 11731 | #define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 |
| 11732 | 11732 | ||
| 11733 | #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 | 11733 | #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 |
| 11734 | #define B_EC_OC_REG_AVR_ASH_CNT__W 4 | 11734 | #define B_EC_OC_REG_AVR_ASH_CNT__W 4 |
| 11735 | #define B_EC_OC_REG_AVR_ASH_CNT__M 0xF | 11735 | #define B_EC_OC_REG_AVR_ASH_CNT__M 0xF |
| 11736 | #define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 | 11736 | #define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 |
| 11737 | 11737 | ||
| 11738 | #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 | 11738 | #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 |
| 11739 | #define B_EC_OC_REG_AVR_BSH_CNT__W 4 | 11739 | #define B_EC_OC_REG_AVR_BSH_CNT__W 4 |
| 11740 | #define B_EC_OC_REG_AVR_BSH_CNT__M 0xF | 11740 | #define B_EC_OC_REG_AVR_BSH_CNT__M 0xF |
| 11741 | #define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 | 11741 | #define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 |
| 11742 | 11742 | ||
| 11743 | #define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 | 11743 | #define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 |
| 11744 | #define B_EC_OC_REG_AVR_AVE_LOP__W 16 | 11744 | #define B_EC_OC_REG_AVR_AVE_LOP__W 16 |
| 11745 | #define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF | 11745 | #define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF |
| 11746 | 11746 | ||
| 11747 | #define B_EC_OC_REG_AVR_AVE_HIP__A 0x2150026 | 11747 | #define B_EC_OC_REG_AVR_AVE_HIP__A 0x2150026 |
| 11748 | #define B_EC_OC_REG_AVR_AVE_HIP__W 5 | 11748 | #define B_EC_OC_REG_AVR_AVE_HIP__W 5 |
| 11749 | #define B_EC_OC_REG_AVR_AVE_HIP__M 0x1F | 11749 | #define B_EC_OC_REG_AVR_AVE_HIP__M 0x1F |
| 11750 | 11750 | ||
| 11751 | #define B_EC_OC_REG_RCN_MODE__A 0x2150027 | 11751 | #define B_EC_OC_REG_RCN_MODE__A 0x2150027 |
| 11752 | #define B_EC_OC_REG_RCN_MODE__W 3 | 11752 | #define B_EC_OC_REG_RCN_MODE__W 3 |
| 11753 | #define B_EC_OC_REG_RCN_MODE__M 0x7 | 11753 | #define B_EC_OC_REG_RCN_MODE__M 0x7 |
| 11754 | #define B_EC_OC_REG_RCN_MODE_INIT 0x7 | 11754 | #define B_EC_OC_REG_RCN_MODE_INIT 0x7 |
| 11755 | 11755 | ||
| 11756 | #define B_EC_OC_REG_RCN_MODE_MODE_0__B 0 | 11756 | #define B_EC_OC_REG_RCN_MODE_MODE_0__B 0 |
| 11757 | #define B_EC_OC_REG_RCN_MODE_MODE_0__W 1 | 11757 | #define B_EC_OC_REG_RCN_MODE_MODE_0__W 1 |
| 11758 | #define B_EC_OC_REG_RCN_MODE_MODE_0__M 0x1 | 11758 | #define B_EC_OC_REG_RCN_MODE_MODE_0__M 0x1 |
| 11759 | #define B_EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 | 11759 | #define B_EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 |
| 11760 | #define B_EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 | 11760 | #define B_EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 |
| 11761 | 11761 | ||
| 11762 | #define B_EC_OC_REG_RCN_MODE_MODE_1__B 1 | 11762 | #define B_EC_OC_REG_RCN_MODE_MODE_1__B 1 |
| 11763 | #define B_EC_OC_REG_RCN_MODE_MODE_1__W 1 | 11763 | #define B_EC_OC_REG_RCN_MODE_MODE_1__W 1 |
| 11764 | #define B_EC_OC_REG_RCN_MODE_MODE_1__M 0x2 | 11764 | #define B_EC_OC_REG_RCN_MODE_MODE_1__M 0x2 |
| 11765 | #define B_EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 | 11765 | #define B_EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 |
| 11766 | #define B_EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 | 11766 | #define B_EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 |
| 11767 | 11767 | ||
| 11768 | #define B_EC_OC_REG_RCN_MODE_MODE_2__B 2 | 11768 | #define B_EC_OC_REG_RCN_MODE_MODE_2__B 2 |
| 11769 | #define B_EC_OC_REG_RCN_MODE_MODE_2__W 1 | 11769 | #define B_EC_OC_REG_RCN_MODE_MODE_2__W 1 |
| 11770 | #define B_EC_OC_REG_RCN_MODE_MODE_2__M 0x4 | 11770 | #define B_EC_OC_REG_RCN_MODE_MODE_2__M 0x4 |
| 11771 | #define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 | 11771 | #define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 |
| 11772 | #define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 | 11772 | #define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 |
| 11773 | 11773 | ||
| 11774 | #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 | 11774 | #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 |
| 11775 | #define B_EC_OC_REG_RCN_CRA_LOP__W 16 | 11775 | #define B_EC_OC_REG_RCN_CRA_LOP__W 16 |
| 11776 | #define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF | 11776 | #define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF |
| 11777 | #define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 | 11777 | #define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 |
| 11778 | 11778 | ||
| 11779 | #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 | 11779 | #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 |
| 11780 | #define B_EC_OC_REG_RCN_CRA_HIP__W 8 | 11780 | #define B_EC_OC_REG_RCN_CRA_HIP__W 8 |
| 11781 | #define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF | 11781 | #define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF |
| 11782 | #define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 | 11782 | #define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 |
| 11783 | 11783 | ||
| 11784 | #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A | 11784 | #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A |
| 11785 | #define B_EC_OC_REG_RCN_CST_LOP__W 16 | 11785 | #define B_EC_OC_REG_RCN_CST_LOP__W 16 |
| 11786 | #define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF | 11786 | #define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF |
| 11787 | #define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 | 11787 | #define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 |
| 11788 | 11788 | ||
| 11789 | #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B | 11789 | #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B |
| 11790 | #define B_EC_OC_REG_RCN_CST_HIP__W 8 | 11790 | #define B_EC_OC_REG_RCN_CST_HIP__W 8 |
| 11791 | #define B_EC_OC_REG_RCN_CST_HIP__M 0xFF | 11791 | #define B_EC_OC_REG_RCN_CST_HIP__M 0xFF |
| 11792 | #define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 | 11792 | #define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 |
| 11793 | 11793 | ||
| 11794 | #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C | 11794 | #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C |
| 11795 | #define B_EC_OC_REG_RCN_SET_LVL__W 9 | 11795 | #define B_EC_OC_REG_RCN_SET_LVL__W 9 |
| 11796 | #define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF | 11796 | #define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF |
| 11797 | #define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF | 11797 | #define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF |
| 11798 | 11798 | ||
| 11799 | #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D | 11799 | #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D |
| 11800 | #define B_EC_OC_REG_RCN_GAI_LVL__W 4 | 11800 | #define B_EC_OC_REG_RCN_GAI_LVL__W 4 |
| 11801 | #define B_EC_OC_REG_RCN_GAI_LVL__M 0xF | 11801 | #define B_EC_OC_REG_RCN_GAI_LVL__M 0xF |
| 11802 | #define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA | 11802 | #define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA |
| 11803 | 11803 | ||
| 11804 | #define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E | 11804 | #define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E |
| 11805 | #define B_EC_OC_REG_RCN_DRA_LOP__W 16 | 11805 | #define B_EC_OC_REG_RCN_DRA_LOP__W 16 |
| 11806 | #define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF | 11806 | #define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF |
| 11807 | 11807 | ||
| 11808 | #define B_EC_OC_REG_RCN_DRA_HIP__A 0x215002F | 11808 | #define B_EC_OC_REG_RCN_DRA_HIP__A 0x215002F |
| 11809 | #define B_EC_OC_REG_RCN_DRA_HIP__W 8 | 11809 | #define B_EC_OC_REG_RCN_DRA_HIP__W 8 |
| 11810 | #define B_EC_OC_REG_RCN_DRA_HIP__M 0xFF | 11810 | #define B_EC_OC_REG_RCN_DRA_HIP__M 0xFF |
| 11811 | 11811 | ||
| 11812 | #define B_EC_OC_REG_RCN_DOF_LOP__A 0x2150030 | 11812 | #define B_EC_OC_REG_RCN_DOF_LOP__A 0x2150030 |
| 11813 | #define B_EC_OC_REG_RCN_DOF_LOP__W 16 | 11813 | #define B_EC_OC_REG_RCN_DOF_LOP__W 16 |
| 11814 | #define B_EC_OC_REG_RCN_DOF_LOP__M 0xFFFF | 11814 | #define B_EC_OC_REG_RCN_DOF_LOP__M 0xFFFF |
| 11815 | 11815 | ||
| 11816 | #define B_EC_OC_REG_RCN_DOF_HIP__A 0x2150031 | 11816 | #define B_EC_OC_REG_RCN_DOF_HIP__A 0x2150031 |
| 11817 | #define B_EC_OC_REG_RCN_DOF_HIP__W 8 | 11817 | #define B_EC_OC_REG_RCN_DOF_HIP__W 8 |
| 11818 | #define B_EC_OC_REG_RCN_DOF_HIP__M 0xFF | 11818 | #define B_EC_OC_REG_RCN_DOF_HIP__M 0xFF |
| 11819 | 11819 | ||
| 11820 | #define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 | 11820 | #define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 |
| 11821 | #define B_EC_OC_REG_RCN_CLP_LOP__W 16 | 11821 | #define B_EC_OC_REG_RCN_CLP_LOP__W 16 |
| 11822 | #define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF | 11822 | #define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF |
| 11823 | #define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 | 11823 | #define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 |
| 11824 | 11824 | ||
| 11825 | #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 | 11825 | #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 |
| 11826 | #define B_EC_OC_REG_RCN_CLP_HIP__W 8 | 11826 | #define B_EC_OC_REG_RCN_CLP_HIP__W 8 |
| 11827 | #define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF | 11827 | #define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF |
| 11828 | #define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 | 11828 | #define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 |
| 11829 | 11829 | ||
| 11830 | #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 | 11830 | #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 |
| 11831 | #define B_EC_OC_REG_RCN_MAP_LOP__W 16 | 11831 | #define B_EC_OC_REG_RCN_MAP_LOP__W 16 |
| 11832 | #define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF | 11832 | #define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF |
| 11833 | 11833 | ||
| 11834 | #define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 | 11834 | #define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 |
| 11835 | #define B_EC_OC_REG_RCN_MAP_HIP__W 8 | 11835 | #define B_EC_OC_REG_RCN_MAP_HIP__W 8 |
| 11836 | #define B_EC_OC_REG_RCN_MAP_HIP__M 0xFF | 11836 | #define B_EC_OC_REG_RCN_MAP_HIP__M 0xFF |
| 11837 | 11837 | ||
| 11838 | #define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 | 11838 | #define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 |
| 11839 | #define B_EC_OC_REG_OCR_MPG_UOS__W 12 | 11839 | #define B_EC_OC_REG_OCR_MPG_UOS__W 12 |
| 11840 | #define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF | 11840 | #define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF |
| 11841 | #define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 | 11841 | #define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 |
| 11842 | 11842 | ||
| 11843 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 | 11843 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 |
| 11844 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 | 11844 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 |
| 11845 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 | 11845 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 |
| 11846 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 | 11846 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 |
| 11847 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 | 11847 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 |
| 11848 | 11848 | ||
| 11849 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 | 11849 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 |
| 11850 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 | 11850 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 |
| 11851 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 | 11851 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 |
| 11852 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 | 11852 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 |
| 11853 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 | 11853 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 |
| 11854 | 11854 | ||
| 11855 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 | 11855 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 |
| 11856 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 | 11856 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 |
| 11857 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 | 11857 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 |
| 11858 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 | 11858 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 |
| 11859 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 | 11859 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 |
| 11860 | 11860 | ||
| 11861 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 | 11861 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 |
| 11862 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 | 11862 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 |
| 11863 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 | 11863 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 |
| 11864 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 | 11864 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 |
| 11865 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 | 11865 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 |
| 11866 | 11866 | ||
| 11867 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 | 11867 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 |
| 11868 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 | 11868 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 |
| 11869 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 | 11869 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 |
| 11870 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 | 11870 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 |
| 11871 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 | 11871 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 |
| 11872 | 11872 | ||
| 11873 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 | 11873 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 |
| 11874 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 | 11874 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 |
| 11875 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 | 11875 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 |
| 11876 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 | 11876 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 |
| 11877 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 | 11877 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 |
| 11878 | 11878 | ||
| 11879 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 | 11879 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 |
| 11880 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 | 11880 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 |
| 11881 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 | 11881 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 |
| 11882 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 | 11882 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 |
| 11883 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 | 11883 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 |
| 11884 | 11884 | ||
| 11885 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 | 11885 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 |
| 11886 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 | 11886 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 |
| 11887 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 | 11887 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 |
| 11888 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 | 11888 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 |
| 11889 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 | 11889 | #define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 |
| 11890 | 11890 | ||
| 11891 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR__B 8 | 11891 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR__B 8 |
| 11892 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR__W 1 | 11892 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR__W 1 |
| 11893 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 | 11893 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 |
| 11894 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 | 11894 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 |
| 11895 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 | 11895 | #define B_EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 |
| 11896 | 11896 | ||
| 11897 | #define B_EC_OC_REG_OCR_MPG_UOS_STR__B 9 | 11897 | #define B_EC_OC_REG_OCR_MPG_UOS_STR__B 9 |
| 11898 | #define B_EC_OC_REG_OCR_MPG_UOS_STR__W 1 | 11898 | #define B_EC_OC_REG_OCR_MPG_UOS_STR__W 1 |
| 11899 | #define B_EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 | 11899 | #define B_EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 |
| 11900 | #define B_EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 | 11900 | #define B_EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 |
| 11901 | #define B_EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 | 11901 | #define B_EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 |
| 11902 | 11902 | ||
| 11903 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL__B 10 | 11903 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL__B 10 |
| 11904 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL__W 1 | 11904 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL__W 1 |
| 11905 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 | 11905 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 |
| 11906 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 | 11906 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 |
| 11907 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 | 11907 | #define B_EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 |
| 11908 | 11908 | ||
| 11909 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK__B 11 | 11909 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK__B 11 |
| 11910 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK__W 1 | 11910 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK__W 1 |
| 11911 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 | 11911 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 |
| 11912 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 | 11912 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 |
| 11913 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 | 11913 | #define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 |
| 11914 | 11914 | ||
| 11915 | #define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 | 11915 | #define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 |
| 11916 | #define B_EC_OC_REG_OCR_MPG_WRI__W 12 | 11916 | #define B_EC_OC_REG_OCR_MPG_WRI__W 12 |
| 11917 | #define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF | 11917 | #define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF |
| 11918 | #define B_EC_OC_REG_OCR_MPG_WRI_INIT 0x0 | 11918 | #define B_EC_OC_REG_OCR_MPG_WRI_INIT 0x0 |
| 11919 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 | 11919 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 |
| 11920 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 | 11920 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 |
| 11921 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 | 11921 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 |
| 11922 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 | 11922 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 |
| 11923 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 | 11923 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 |
| 11924 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 | 11924 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 |
| 11925 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 | 11925 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 |
| 11926 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 | 11926 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 |
| 11927 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 | 11927 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 |
| 11928 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 | 11928 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 |
| 11929 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 | 11929 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 |
| 11930 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 | 11930 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 |
| 11931 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 | 11931 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 |
| 11932 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 | 11932 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 |
| 11933 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 | 11933 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 |
| 11934 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 | 11934 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 |
| 11935 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 | 11935 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 |
| 11936 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 | 11936 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 |
| 11937 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 | 11937 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 |
| 11938 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 | 11938 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 |
| 11939 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 | 11939 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 |
| 11940 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 | 11940 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 |
| 11941 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 | 11941 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 |
| 11942 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 | 11942 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 |
| 11943 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 | 11943 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 |
| 11944 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 | 11944 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 |
| 11945 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 | 11945 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 |
| 11946 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 | 11946 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 |
| 11947 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 | 11947 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 |
| 11948 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 | 11948 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 |
| 11949 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 | 11949 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 |
| 11950 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 | 11950 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 |
| 11951 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 | 11951 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 |
| 11952 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 | 11952 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 |
| 11953 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 | 11953 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 |
| 11954 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 | 11954 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 |
| 11955 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 | 11955 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 |
| 11956 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 | 11956 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 |
| 11957 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 | 11957 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 |
| 11958 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 | 11958 | #define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 |
| 11959 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR__B 8 | 11959 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR__B 8 |
| 11960 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR__W 1 | 11960 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR__W 1 |
| 11961 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 | 11961 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 |
| 11962 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 | 11962 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 |
| 11963 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 | 11963 | #define B_EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 |
| 11964 | #define B_EC_OC_REG_OCR_MPG_WRI_STR__B 9 | 11964 | #define B_EC_OC_REG_OCR_MPG_WRI_STR__B 9 |
| 11965 | #define B_EC_OC_REG_OCR_MPG_WRI_STR__W 1 | 11965 | #define B_EC_OC_REG_OCR_MPG_WRI_STR__W 1 |
| 11966 | #define B_EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 | 11966 | #define B_EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 |
| 11967 | #define B_EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 | 11967 | #define B_EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 |
| 11968 | #define B_EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 | 11968 | #define B_EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 |
| 11969 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL__B 10 | 11969 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL__B 10 |
| 11970 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL__W 1 | 11970 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL__W 1 |
| 11971 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 | 11971 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 |
| 11972 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 | 11972 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 |
| 11973 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 | 11973 | #define B_EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 |
| 11974 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK__B 11 | 11974 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK__B 11 |
| 11975 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK__W 1 | 11975 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK__W 1 |
| 11976 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 | 11976 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 |
| 11977 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 | 11977 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 |
| 11978 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 | 11978 | #define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 |
| 11979 | 11979 | ||
| 11980 | #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 | 11980 | #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 |
| 11981 | #define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 | 11981 | #define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 |
| 11982 | #define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF | 11982 | #define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF |
| 11983 | 11983 | ||
| 11984 | #define B_EC_OC_REG_OCR_MON_CNT__A 0x215003C | 11984 | #define B_EC_OC_REG_OCR_MON_CNT__A 0x215003C |
| 11985 | #define B_EC_OC_REG_OCR_MON_CNT__W 14 | 11985 | #define B_EC_OC_REG_OCR_MON_CNT__W 14 |
| 11986 | #define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF | 11986 | #define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF |
| 11987 | #define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 | 11987 | #define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 |
| 11988 | 11988 | ||
| 11989 | #define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D | 11989 | #define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D |
| 11990 | #define B_EC_OC_REG_OCR_MON_RDX__W 1 | 11990 | #define B_EC_OC_REG_OCR_MON_RDX__W 1 |
| 11991 | #define B_EC_OC_REG_OCR_MON_RDX__M 0x1 | 11991 | #define B_EC_OC_REG_OCR_MON_RDX__M 0x1 |
| 11992 | #define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 | 11992 | #define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 |
| 11993 | 11993 | ||
| 11994 | #define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E | 11994 | #define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E |
| 11995 | #define B_EC_OC_REG_OCR_MON_RD0__W 10 | 11995 | #define B_EC_OC_REG_OCR_MON_RD0__W 10 |
| 11996 | #define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF | 11996 | #define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF |
| 11997 | 11997 | ||
| 11998 | #define B_EC_OC_REG_OCR_MON_RD1__A 0x215003F | 11998 | #define B_EC_OC_REG_OCR_MON_RD1__A 0x215003F |
| 11999 | #define B_EC_OC_REG_OCR_MON_RD1__W 10 | 11999 | #define B_EC_OC_REG_OCR_MON_RD1__W 10 |
| 12000 | #define B_EC_OC_REG_OCR_MON_RD1__M 0x3FF | 12000 | #define B_EC_OC_REG_OCR_MON_RD1__M 0x3FF |
| 12001 | 12001 | ||
| 12002 | #define B_EC_OC_REG_OCR_MON_RD2__A 0x2150040 | 12002 | #define B_EC_OC_REG_OCR_MON_RD2__A 0x2150040 |
| 12003 | #define B_EC_OC_REG_OCR_MON_RD2__W 10 | 12003 | #define B_EC_OC_REG_OCR_MON_RD2__W 10 |
| 12004 | #define B_EC_OC_REG_OCR_MON_RD2__M 0x3FF | 12004 | #define B_EC_OC_REG_OCR_MON_RD2__M 0x3FF |
| 12005 | 12005 | ||
| 12006 | #define B_EC_OC_REG_OCR_MON_RD3__A 0x2150041 | 12006 | #define B_EC_OC_REG_OCR_MON_RD3__A 0x2150041 |
| 12007 | #define B_EC_OC_REG_OCR_MON_RD3__W 10 | 12007 | #define B_EC_OC_REG_OCR_MON_RD3__W 10 |
| 12008 | #define B_EC_OC_REG_OCR_MON_RD3__M 0x3FF | 12008 | #define B_EC_OC_REG_OCR_MON_RD3__M 0x3FF |
| 12009 | 12009 | ||
| 12010 | #define B_EC_OC_REG_OCR_MON_RD4__A 0x2150042 | 12010 | #define B_EC_OC_REG_OCR_MON_RD4__A 0x2150042 |
| 12011 | #define B_EC_OC_REG_OCR_MON_RD4__W 10 | 12011 | #define B_EC_OC_REG_OCR_MON_RD4__W 10 |
| 12012 | #define B_EC_OC_REG_OCR_MON_RD4__M 0x3FF | 12012 | #define B_EC_OC_REG_OCR_MON_RD4__M 0x3FF |
| 12013 | 12013 | ||
| 12014 | #define B_EC_OC_REG_OCR_MON_RD5__A 0x2150043 | 12014 | #define B_EC_OC_REG_OCR_MON_RD5__A 0x2150043 |
| 12015 | #define B_EC_OC_REG_OCR_MON_RD5__W 10 | 12015 | #define B_EC_OC_REG_OCR_MON_RD5__W 10 |
| 12016 | #define B_EC_OC_REG_OCR_MON_RD5__M 0x3FF | 12016 | #define B_EC_OC_REG_OCR_MON_RD5__M 0x3FF |
| 12017 | 12017 | ||
| 12018 | #define B_EC_OC_REG_OCR_INV_MON__A 0x2150044 | 12018 | #define B_EC_OC_REG_OCR_INV_MON__A 0x2150044 |
| 12019 | #define B_EC_OC_REG_OCR_INV_MON__W 12 | 12019 | #define B_EC_OC_REG_OCR_INV_MON__W 12 |
| 12020 | #define B_EC_OC_REG_OCR_INV_MON__M 0xFFF | 12020 | #define B_EC_OC_REG_OCR_INV_MON__M 0xFFF |
| 12021 | #define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 | 12021 | #define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 |
| 12022 | 12022 | ||
| 12023 | #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 | 12023 | #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 |
| 12024 | #define B_EC_OC_REG_IPR_INV_MPG__W 12 | 12024 | #define B_EC_OC_REG_IPR_INV_MPG__W 12 |
| 12025 | #define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF | 12025 | #define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF |
| 12026 | #define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 | 12026 | #define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 |
| 12027 | 12027 | ||
| 12028 | #define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 | 12028 | #define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 |
| 12029 | #define B_EC_OC_REG_IPR_MSR_SNC__W 6 | 12029 | #define B_EC_OC_REG_IPR_MSR_SNC__W 6 |
| 12030 | #define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F | 12030 | #define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F |
| 12031 | #define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 | 12031 | #define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 |
| 12032 | 12032 | ||
| 12033 | #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 | 12033 | #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 |
| 12034 | #define B_EC_OC_REG_DTO_CLKMODE__W 2 | 12034 | #define B_EC_OC_REG_DTO_CLKMODE__W 2 |
| 12035 | #define B_EC_OC_REG_DTO_CLKMODE__M 0x3 | 12035 | #define B_EC_OC_REG_DTO_CLKMODE__M 0x3 |
| 12036 | #define B_EC_OC_REG_DTO_CLKMODE_INIT 0x2 | 12036 | #define B_EC_OC_REG_DTO_CLKMODE_INIT 0x2 |
| 12037 | 12037 | ||
| 12038 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__B 0 | 12038 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__B 0 |
| 12039 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__W 1 | 12039 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__W 1 |
| 12040 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__M 0x1 | 12040 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__M 0x1 |
| 12041 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_EVEN_ODD 0x0 | 12041 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_EVEN_ODD 0x0 |
| 12042 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_ODD_EVEN 0x1 | 12042 | #define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_ODD_EVEN 0x1 |
| 12043 | 12043 | ||
| 12044 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__B 1 | 12044 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__B 1 |
| 12045 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__W 1 | 12045 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__W 1 |
| 12046 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__M 0x2 | 12046 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__M 0x2 |
| 12047 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 | 12047 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 |
| 12048 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 | 12048 | #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 |
| 12049 | 12049 | ||
| 12050 | #define B_EC_OC_REG_DTO_PER__A 0x2150048 | 12050 | #define B_EC_OC_REG_DTO_PER__A 0x2150048 |
| 12051 | #define B_EC_OC_REG_DTO_PER__W 8 | 12051 | #define B_EC_OC_REG_DTO_PER__W 8 |
| 12052 | #define B_EC_OC_REG_DTO_PER__M 0xFF | 12052 | #define B_EC_OC_REG_DTO_PER__M 0xFF |
| 12053 | #define B_EC_OC_REG_DTO_PER_INIT 0x6 | 12053 | #define B_EC_OC_REG_DTO_PER_INIT 0x6 |
| 12054 | 12054 | ||
| 12055 | #define B_EC_OC_REG_DTO_BUR__A 0x2150049 | 12055 | #define B_EC_OC_REG_DTO_BUR__A 0x2150049 |
| 12056 | #define B_EC_OC_REG_DTO_BUR__W 2 | 12056 | #define B_EC_OC_REG_DTO_BUR__W 2 |
| 12057 | #define B_EC_OC_REG_DTO_BUR__M 0x3 | 12057 | #define B_EC_OC_REG_DTO_BUR__M 0x3 |
| 12058 | #define B_EC_OC_REG_DTO_BUR_INIT 0x1 | 12058 | #define B_EC_OC_REG_DTO_BUR_INIT 0x1 |
| 12059 | #define B_EC_OC_REG_DTO_BUR_SELECT_1 0x0 | 12059 | #define B_EC_OC_REG_DTO_BUR_SELECT_1 0x0 |
| 12060 | #define B_EC_OC_REG_DTO_BUR_SELECT_188 0x1 | 12060 | #define B_EC_OC_REG_DTO_BUR_SELECT_188 0x1 |
| 12061 | #define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 | 12061 | #define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 |
| 12062 | #define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 | 12062 | #define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 |
| 12063 | 12063 | ||
| 12064 | #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A | 12064 | #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A |
| 12065 | #define B_EC_OC_REG_RCR_CLKMODE__W 3 | 12065 | #define B_EC_OC_REG_RCR_CLKMODE__W 3 |
| 12066 | #define B_EC_OC_REG_RCR_CLKMODE__M 0x7 | 12066 | #define B_EC_OC_REG_RCR_CLKMODE__M 0x7 |
| 12067 | #define B_EC_OC_REG_RCR_CLKMODE_INIT 0x0 | 12067 | #define B_EC_OC_REG_RCR_CLKMODE_INIT 0x0 |
| 12068 | 12068 | ||
| 12069 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__B 0 | 12069 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__B 0 |
| 12070 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__W 1 | 12070 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__W 1 |
| 12071 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__M 0x1 | 12071 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__M 0x1 |
| 12072 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_FRACIONAL 0x0 | 12072 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_FRACIONAL 0x0 |
| 12073 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_RATIONAL 0x1 | 12073 | #define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_RATIONAL 0x1 |
| 12074 | 12074 | ||
| 12075 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__B 1 | 12075 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__B 1 |
| 12076 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__W 1 | 12076 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__W 1 |
| 12077 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__M 0x2 | 12077 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__M 0x2 |
| 12078 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_FRACTIONAL 0x0 | 12078 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_FRACTIONAL 0x0 |
| 12079 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_RATIONAL 0x2 | 12079 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_RATIONAL 0x2 |
| 12080 | 12080 | ||
| 12081 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__B 2 | 12081 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__B 2 |
| 12082 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__W 1 | 12082 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__W 1 |
| 12083 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__M 0x4 | 12083 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__M 0x4 |
| 12084 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 | 12084 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 |
| 12085 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4 | 12085 | #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4 |
| 12086 | 12086 | ||
| 12087 | #define B_EC_OC_RAM__A 0x2160000 | 12087 | #define B_EC_OC_RAM__A 0x2160000 |
| 12088 | 12088 | ||
| 12089 | #define B_CC_SID 0x1B | 12089 | #define B_CC_SID 0x1B |
| 12090 | 12090 | ||
| 12091 | #define B_CC_COMM_EXEC__A 0x2400000 | 12091 | #define B_CC_COMM_EXEC__A 0x2400000 |
| 12092 | #define B_CC_COMM_EXEC__W 3 | 12092 | #define B_CC_COMM_EXEC__W 3 |
| 12093 | #define B_CC_COMM_EXEC__M 0x7 | 12093 | #define B_CC_COMM_EXEC__M 0x7 |
| 12094 | #define B_CC_COMM_EXEC_CTL__B 0 | 12094 | #define B_CC_COMM_EXEC_CTL__B 0 |
| 12095 | #define B_CC_COMM_EXEC_CTL__W 3 | 12095 | #define B_CC_COMM_EXEC_CTL__W 3 |
| 12096 | #define B_CC_COMM_EXEC_CTL__M 0x7 | 12096 | #define B_CC_COMM_EXEC_CTL__M 0x7 |
| 12097 | #define B_CC_COMM_EXEC_CTL_STOP 0x0 | 12097 | #define B_CC_COMM_EXEC_CTL_STOP 0x0 |
| 12098 | #define B_CC_COMM_EXEC_CTL_ACTIVE 0x1 | 12098 | #define B_CC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 12099 | #define B_CC_COMM_EXEC_CTL_HOLD 0x2 | 12099 | #define B_CC_COMM_EXEC_CTL_HOLD 0x2 |
| 12100 | #define B_CC_COMM_EXEC_CTL_STEP 0x3 | 12100 | #define B_CC_COMM_EXEC_CTL_STEP 0x3 |
| 12101 | #define B_CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 12101 | #define B_CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 12102 | #define B_CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 12102 | #define B_CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 12103 | 12103 | ||
| 12104 | #define B_CC_COMM_STATE__A 0x2400001 | 12104 | #define B_CC_COMM_STATE__A 0x2400001 |
| 12105 | #define B_CC_COMM_STATE__W 16 | 12105 | #define B_CC_COMM_STATE__W 16 |
| 12106 | #define B_CC_COMM_STATE__M 0xFFFF | 12106 | #define B_CC_COMM_STATE__M 0xFFFF |
| 12107 | #define B_CC_COMM_MB__A 0x2400002 | 12107 | #define B_CC_COMM_MB__A 0x2400002 |
| 12108 | #define B_CC_COMM_MB__W 16 | 12108 | #define B_CC_COMM_MB__W 16 |
| 12109 | #define B_CC_COMM_MB__M 0xFFFF | 12109 | #define B_CC_COMM_MB__M 0xFFFF |
| 12110 | #define B_CC_COMM_SERVICE0__A 0x2400003 | 12110 | #define B_CC_COMM_SERVICE0__A 0x2400003 |
| 12111 | #define B_CC_COMM_SERVICE0__W 16 | 12111 | #define B_CC_COMM_SERVICE0__W 16 |
| 12112 | #define B_CC_COMM_SERVICE0__M 0xFFFF | 12112 | #define B_CC_COMM_SERVICE0__M 0xFFFF |
| 12113 | #define B_CC_COMM_SERVICE1__A 0x2400004 | 12113 | #define B_CC_COMM_SERVICE1__A 0x2400004 |
| 12114 | #define B_CC_COMM_SERVICE1__W 16 | 12114 | #define B_CC_COMM_SERVICE1__W 16 |
| 12115 | #define B_CC_COMM_SERVICE1__M 0xFFFF | 12115 | #define B_CC_COMM_SERVICE1__M 0xFFFF |
| 12116 | #define B_CC_COMM_INT_STA__A 0x2400007 | 12116 | #define B_CC_COMM_INT_STA__A 0x2400007 |
| 12117 | #define B_CC_COMM_INT_STA__W 16 | 12117 | #define B_CC_COMM_INT_STA__W 16 |
| 12118 | #define B_CC_COMM_INT_STA__M 0xFFFF | 12118 | #define B_CC_COMM_INT_STA__M 0xFFFF |
| 12119 | #define B_CC_COMM_INT_MSK__A 0x2400008 | 12119 | #define B_CC_COMM_INT_MSK__A 0x2400008 |
| 12120 | #define B_CC_COMM_INT_MSK__W 16 | 12120 | #define B_CC_COMM_INT_MSK__W 16 |
| 12121 | #define B_CC_COMM_INT_MSK__M 0xFFFF | 12121 | #define B_CC_COMM_INT_MSK__M 0xFFFF |
| 12122 | 12122 | ||
| 12123 | #define B_CC_REG_COMM_EXEC__A 0x2410000 | 12123 | #define B_CC_REG_COMM_EXEC__A 0x2410000 |
| 12124 | #define B_CC_REG_COMM_EXEC__W 3 | 12124 | #define B_CC_REG_COMM_EXEC__W 3 |
| 12125 | #define B_CC_REG_COMM_EXEC__M 0x7 | 12125 | #define B_CC_REG_COMM_EXEC__M 0x7 |
| 12126 | #define B_CC_REG_COMM_EXEC_CTL__B 0 | 12126 | #define B_CC_REG_COMM_EXEC_CTL__B 0 |
| 12127 | #define B_CC_REG_COMM_EXEC_CTL__W 3 | 12127 | #define B_CC_REG_COMM_EXEC_CTL__W 3 |
| 12128 | #define B_CC_REG_COMM_EXEC_CTL__M 0x7 | 12128 | #define B_CC_REG_COMM_EXEC_CTL__M 0x7 |
| 12129 | #define B_CC_REG_COMM_EXEC_CTL_STOP 0x0 | 12129 | #define B_CC_REG_COMM_EXEC_CTL_STOP 0x0 |
| 12130 | #define B_CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 12130 | #define B_CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 12131 | #define B_CC_REG_COMM_EXEC_CTL_HOLD 0x2 | 12131 | #define B_CC_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 12132 | #define B_CC_REG_COMM_EXEC_CTL_STEP 0x3 | 12132 | #define B_CC_REG_COMM_EXEC_CTL_STEP 0x3 |
| 12133 | #define B_CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 12133 | #define B_CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 12134 | #define B_CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 12134 | #define B_CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 12135 | 12135 | ||
| 12136 | #define B_CC_REG_COMM_STATE__A 0x2410001 | 12136 | #define B_CC_REG_COMM_STATE__A 0x2410001 |
| 12137 | #define B_CC_REG_COMM_STATE__W 16 | 12137 | #define B_CC_REG_COMM_STATE__W 16 |
| 12138 | #define B_CC_REG_COMM_STATE__M 0xFFFF | 12138 | #define B_CC_REG_COMM_STATE__M 0xFFFF |
| 12139 | #define B_CC_REG_COMM_MB__A 0x2410002 | 12139 | #define B_CC_REG_COMM_MB__A 0x2410002 |
| 12140 | #define B_CC_REG_COMM_MB__W 16 | 12140 | #define B_CC_REG_COMM_MB__W 16 |
| 12141 | #define B_CC_REG_COMM_MB__M 0xFFFF | 12141 | #define B_CC_REG_COMM_MB__M 0xFFFF |
| 12142 | #define B_CC_REG_COMM_SERVICE0__A 0x2410003 | 12142 | #define B_CC_REG_COMM_SERVICE0__A 0x2410003 |
| 12143 | #define B_CC_REG_COMM_SERVICE0__W 16 | 12143 | #define B_CC_REG_COMM_SERVICE0__W 16 |
| 12144 | #define B_CC_REG_COMM_SERVICE0__M 0xFFFF | 12144 | #define B_CC_REG_COMM_SERVICE0__M 0xFFFF |
| 12145 | #define B_CC_REG_COMM_SERVICE1__A 0x2410004 | 12145 | #define B_CC_REG_COMM_SERVICE1__A 0x2410004 |
| 12146 | #define B_CC_REG_COMM_SERVICE1__W 16 | 12146 | #define B_CC_REG_COMM_SERVICE1__W 16 |
| 12147 | #define B_CC_REG_COMM_SERVICE1__M 0xFFFF | 12147 | #define B_CC_REG_COMM_SERVICE1__M 0xFFFF |
| 12148 | #define B_CC_REG_COMM_INT_STA__A 0x2410007 | 12148 | #define B_CC_REG_COMM_INT_STA__A 0x2410007 |
| 12149 | #define B_CC_REG_COMM_INT_STA__W 16 | 12149 | #define B_CC_REG_COMM_INT_STA__W 16 |
| 12150 | #define B_CC_REG_COMM_INT_STA__M 0xFFFF | 12150 | #define B_CC_REG_COMM_INT_STA__M 0xFFFF |
| 12151 | #define B_CC_REG_COMM_INT_MSK__A 0x2410008 | 12151 | #define B_CC_REG_COMM_INT_MSK__A 0x2410008 |
| 12152 | #define B_CC_REG_COMM_INT_MSK__W 16 | 12152 | #define B_CC_REG_COMM_INT_MSK__W 16 |
| 12153 | #define B_CC_REG_COMM_INT_MSK__M 0xFFFF | 12153 | #define B_CC_REG_COMM_INT_MSK__M 0xFFFF |
| 12154 | 12154 | ||
| 12155 | #define B_CC_REG_OSC_MODE__A 0x2410010 | 12155 | #define B_CC_REG_OSC_MODE__A 0x2410010 |
| 12156 | #define B_CC_REG_OSC_MODE__W 2 | 12156 | #define B_CC_REG_OSC_MODE__W 2 |
| 12157 | #define B_CC_REG_OSC_MODE__M 0x3 | 12157 | #define B_CC_REG_OSC_MODE__M 0x3 |
| 12158 | #define B_CC_REG_OSC_MODE_OHW 0x0 | 12158 | #define B_CC_REG_OSC_MODE_OHW 0x0 |
| 12159 | #define B_CC_REG_OSC_MODE_M20 0x1 | 12159 | #define B_CC_REG_OSC_MODE_M20 0x1 |
| 12160 | #define B_CC_REG_OSC_MODE_M48 0x2 | 12160 | #define B_CC_REG_OSC_MODE_M48 0x2 |
| 12161 | 12161 | ||
| 12162 | #define B_CC_REG_PLL_MODE__A 0x2410011 | 12162 | #define B_CC_REG_PLL_MODE__A 0x2410011 |
| 12163 | #define B_CC_REG_PLL_MODE__W 6 | 12163 | #define B_CC_REG_PLL_MODE__W 6 |
| 12164 | #define B_CC_REG_PLL_MODE__M 0x3F | 12164 | #define B_CC_REG_PLL_MODE__M 0x3F |
| 12165 | #define B_CC_REG_PLL_MODE_INIT 0xC | 12165 | #define B_CC_REG_PLL_MODE_INIT 0xC |
| 12166 | #define B_CC_REG_PLL_MODE_BYPASS__B 0 | 12166 | #define B_CC_REG_PLL_MODE_BYPASS__B 0 |
| 12167 | #define B_CC_REG_PLL_MODE_BYPASS__W 2 | 12167 | #define B_CC_REG_PLL_MODE_BYPASS__W 2 |
| 12168 | #define B_CC_REG_PLL_MODE_BYPASS__M 0x3 | 12168 | #define B_CC_REG_PLL_MODE_BYPASS__M 0x3 |
| 12169 | #define B_CC_REG_PLL_MODE_BYPASS_OHW 0x0 | 12169 | #define B_CC_REG_PLL_MODE_BYPASS_OHW 0x0 |
| 12170 | #define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 | 12170 | #define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 |
| 12171 | #define B_CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 | 12171 | #define B_CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 |
| 12172 | #define B_CC_REG_PLL_MODE_PUMP__B 2 | 12172 | #define B_CC_REG_PLL_MODE_PUMP__B 2 |
| 12173 | #define B_CC_REG_PLL_MODE_PUMP__W 3 | 12173 | #define B_CC_REG_PLL_MODE_PUMP__W 3 |
| 12174 | #define B_CC_REG_PLL_MODE_PUMP__M 0x1C | 12174 | #define B_CC_REG_PLL_MODE_PUMP__M 0x1C |
| 12175 | #define B_CC_REG_PLL_MODE_PUMP_OFF 0x0 | 12175 | #define B_CC_REG_PLL_MODE_PUMP_OFF 0x0 |
| 12176 | #define B_CC_REG_PLL_MODE_PUMP_CUR_08 0x4 | 12176 | #define B_CC_REG_PLL_MODE_PUMP_CUR_08 0x4 |
| 12177 | #define B_CC_REG_PLL_MODE_PUMP_CUR_09 0x8 | 12177 | #define B_CC_REG_PLL_MODE_PUMP_CUR_09 0x8 |
| 12178 | #define B_CC_REG_PLL_MODE_PUMP_CUR_10 0xC | 12178 | #define B_CC_REG_PLL_MODE_PUMP_CUR_10 0xC |
| 12179 | #define B_CC_REG_PLL_MODE_PUMP_CUR_11 0x10 | 12179 | #define B_CC_REG_PLL_MODE_PUMP_CUR_11 0x10 |
| 12180 | #define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 | 12180 | #define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 |
| 12181 | #define B_CC_REG_PLL_MODE_OUT_EN__B 5 | 12181 | #define B_CC_REG_PLL_MODE_OUT_EN__B 5 |
| 12182 | #define B_CC_REG_PLL_MODE_OUT_EN__W 1 | 12182 | #define B_CC_REG_PLL_MODE_OUT_EN__W 1 |
| 12183 | #define B_CC_REG_PLL_MODE_OUT_EN__M 0x20 | 12183 | #define B_CC_REG_PLL_MODE_OUT_EN__M 0x20 |
| 12184 | #define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 | 12184 | #define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 |
| 12185 | #define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 | 12185 | #define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 |
| 12186 | 12186 | ||
| 12187 | #define B_CC_REG_REF_DIVIDE__A 0x2410012 | 12187 | #define B_CC_REG_REF_DIVIDE__A 0x2410012 |
| 12188 | #define B_CC_REG_REF_DIVIDE__W 4 | 12188 | #define B_CC_REG_REF_DIVIDE__W 4 |
| 12189 | #define B_CC_REG_REF_DIVIDE__M 0xF | 12189 | #define B_CC_REG_REF_DIVIDE__M 0xF |
| 12190 | #define B_CC_REG_REF_DIVIDE_INIT 0xA | 12190 | #define B_CC_REG_REF_DIVIDE_INIT 0xA |
| 12191 | #define B_CC_REG_REF_DIVIDE_OHW 0x0 | 12191 | #define B_CC_REG_REF_DIVIDE_OHW 0x0 |
| 12192 | #define B_CC_REG_REF_DIVIDE_D01 0x1 | 12192 | #define B_CC_REG_REF_DIVIDE_D01 0x1 |
| 12193 | #define B_CC_REG_REF_DIVIDE_D02 0x2 | 12193 | #define B_CC_REG_REF_DIVIDE_D02 0x2 |
| 12194 | #define B_CC_REG_REF_DIVIDE_D03 0x3 | 12194 | #define B_CC_REG_REF_DIVIDE_D03 0x3 |
| 12195 | #define B_CC_REG_REF_DIVIDE_D04 0x4 | 12195 | #define B_CC_REG_REF_DIVIDE_D04 0x4 |
| 12196 | #define B_CC_REG_REF_DIVIDE_D05 0x5 | 12196 | #define B_CC_REG_REF_DIVIDE_D05 0x5 |
| 12197 | #define B_CC_REG_REF_DIVIDE_D06 0x6 | 12197 | #define B_CC_REG_REF_DIVIDE_D06 0x6 |
| 12198 | #define B_CC_REG_REF_DIVIDE_D07 0x7 | 12198 | #define B_CC_REG_REF_DIVIDE_D07 0x7 |
| 12199 | #define B_CC_REG_REF_DIVIDE_D08 0x8 | 12199 | #define B_CC_REG_REF_DIVIDE_D08 0x8 |
| 12200 | #define B_CC_REG_REF_DIVIDE_D09 0x9 | 12200 | #define B_CC_REG_REF_DIVIDE_D09 0x9 |
| 12201 | #define B_CC_REG_REF_DIVIDE_D10 0xA | 12201 | #define B_CC_REG_REF_DIVIDE_D10 0xA |
| 12202 | 12202 | ||
| 12203 | #define B_CC_REG_REF_DELAY__A 0x2410013 | 12203 | #define B_CC_REG_REF_DELAY__A 0x2410013 |
| 12204 | #define B_CC_REG_REF_DELAY__W 3 | 12204 | #define B_CC_REG_REF_DELAY__W 3 |
| 12205 | #define B_CC_REG_REF_DELAY__M 0x7 | 12205 | #define B_CC_REG_REF_DELAY__M 0x7 |
| 12206 | #define B_CC_REG_REF_DELAY_EDGE__B 0 | 12206 | #define B_CC_REG_REF_DELAY_EDGE__B 0 |
| 12207 | #define B_CC_REG_REF_DELAY_EDGE__W 1 | 12207 | #define B_CC_REG_REF_DELAY_EDGE__W 1 |
| 12208 | #define B_CC_REG_REF_DELAY_EDGE__M 0x1 | 12208 | #define B_CC_REG_REF_DELAY_EDGE__M 0x1 |
| 12209 | #define B_CC_REG_REF_DELAY_EDGE_POS 0x0 | 12209 | #define B_CC_REG_REF_DELAY_EDGE_POS 0x0 |
| 12210 | #define B_CC_REG_REF_DELAY_EDGE_NEG 0x1 | 12210 | #define B_CC_REG_REF_DELAY_EDGE_NEG 0x1 |
| 12211 | #define B_CC_REG_REF_DELAY_DELAY__B 1 | 12211 | #define B_CC_REG_REF_DELAY_DELAY__B 1 |
| 12212 | #define B_CC_REG_REF_DELAY_DELAY__W 2 | 12212 | #define B_CC_REG_REF_DELAY_DELAY__W 2 |
| 12213 | #define B_CC_REG_REF_DELAY_DELAY__M 0x6 | 12213 | #define B_CC_REG_REF_DELAY_DELAY__M 0x6 |
| 12214 | #define B_CC_REG_REF_DELAY_DELAY_DEL_0 0x0 | 12214 | #define B_CC_REG_REF_DELAY_DELAY_DEL_0 0x0 |
| 12215 | #define B_CC_REG_REF_DELAY_DELAY_DEL_3 0x2 | 12215 | #define B_CC_REG_REF_DELAY_DELAY_DEL_3 0x2 |
| 12216 | #define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 | 12216 | #define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 |
| 12217 | #define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 | 12217 | #define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 |
| 12218 | 12218 | ||
| 12219 | #define B_CC_REG_CLK_DELAY__A 0x2410014 | 12219 | #define B_CC_REG_CLK_DELAY__A 0x2410014 |
| 12220 | #define B_CC_REG_CLK_DELAY__W 5 | 12220 | #define B_CC_REG_CLK_DELAY__W 5 |
| 12221 | #define B_CC_REG_CLK_DELAY__M 0x1F | 12221 | #define B_CC_REG_CLK_DELAY__M 0x1F |
| 12222 | #define B_CC_REG_CLK_DELAY_DELAY__B 0 | 12222 | #define B_CC_REG_CLK_DELAY_DELAY__B 0 |
| 12223 | #define B_CC_REG_CLK_DELAY_DELAY__W 4 | 12223 | #define B_CC_REG_CLK_DELAY_DELAY__W 4 |
| 12224 | #define B_CC_REG_CLK_DELAY_DELAY__M 0xF | 12224 | #define B_CC_REG_CLK_DELAY_DELAY__M 0xF |
| 12225 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_00 0x0 | 12225 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_00 0x0 |
| 12226 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_05 0x1 | 12226 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_05 0x1 |
| 12227 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_10 0x2 | 12227 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_10 0x2 |
| 12228 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_15 0x3 | 12228 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_15 0x3 |
| 12229 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_20 0x4 | 12229 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_20 0x4 |
| 12230 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_25 0x5 | 12230 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_25 0x5 |
| 12231 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_30 0x6 | 12231 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_30 0x6 |
| 12232 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_35 0x7 | 12232 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_35 0x7 |
| 12233 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_40 0x8 | 12233 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_40 0x8 |
| 12234 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_45 0x9 | 12234 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_45 0x9 |
| 12235 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_50 0xA | 12235 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_50 0xA |
| 12236 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_55 0xB | 12236 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_55 0xB |
| 12237 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_60 0xC | 12237 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_60 0xC |
| 12238 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_65 0xD | 12238 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_65 0xD |
| 12239 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_70 0xE | 12239 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_70 0xE |
| 12240 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_75 0xF | 12240 | #define B_CC_REG_CLK_DELAY_DELAY_DEL_75 0xF |
| 12241 | #define B_CC_REG_CLK_DELAY_EDGE__B 4 | 12241 | #define B_CC_REG_CLK_DELAY_EDGE__B 4 |
| 12242 | #define B_CC_REG_CLK_DELAY_EDGE__W 1 | 12242 | #define B_CC_REG_CLK_DELAY_EDGE__W 1 |
| 12243 | #define B_CC_REG_CLK_DELAY_EDGE__M 0x10 | 12243 | #define B_CC_REG_CLK_DELAY_EDGE__M 0x10 |
| 12244 | #define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 | 12244 | #define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 |
| 12245 | #define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 | 12245 | #define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 |
| 12246 | 12246 | ||
| 12247 | #define B_CC_REG_PWD_MODE__A 0x2410015 | 12247 | #define B_CC_REG_PWD_MODE__A 0x2410015 |
| 12248 | #define B_CC_REG_PWD_MODE__W 2 | 12248 | #define B_CC_REG_PWD_MODE__W 2 |
| 12249 | #define B_CC_REG_PWD_MODE__M 0x3 | 12249 | #define B_CC_REG_PWD_MODE__M 0x3 |
| 12250 | #define B_CC_REG_PWD_MODE_UP 0x0 | 12250 | #define B_CC_REG_PWD_MODE_UP 0x0 |
| 12251 | #define B_CC_REG_PWD_MODE_DOWN_CLK 0x1 | 12251 | #define B_CC_REG_PWD_MODE_DOWN_CLK 0x1 |
| 12252 | #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 | 12252 | #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 |
| 12253 | #define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 | 12253 | #define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 |
| 12254 | 12254 | ||
| 12255 | #define B_CC_REG_SOFT_RST__A 0x2410016 | 12255 | #define B_CC_REG_SOFT_RST__A 0x2410016 |
| 12256 | #define B_CC_REG_SOFT_RST__W 2 | 12256 | #define B_CC_REG_SOFT_RST__W 2 |
| 12257 | #define B_CC_REG_SOFT_RST__M 0x3 | 12257 | #define B_CC_REG_SOFT_RST__M 0x3 |
| 12258 | #define B_CC_REG_SOFT_RST_SYS__B 0 | 12258 | #define B_CC_REG_SOFT_RST_SYS__B 0 |
| 12259 | #define B_CC_REG_SOFT_RST_SYS__W 1 | 12259 | #define B_CC_REG_SOFT_RST_SYS__W 1 |
| 12260 | #define B_CC_REG_SOFT_RST_SYS__M 0x1 | 12260 | #define B_CC_REG_SOFT_RST_SYS__M 0x1 |
| 12261 | #define B_CC_REG_SOFT_RST_OSC__B 1 | 12261 | #define B_CC_REG_SOFT_RST_OSC__B 1 |
| 12262 | #define B_CC_REG_SOFT_RST_OSC__W 1 | 12262 | #define B_CC_REG_SOFT_RST_OSC__W 1 |
| 12263 | #define B_CC_REG_SOFT_RST_OSC__M 0x2 | 12263 | #define B_CC_REG_SOFT_RST_OSC__M 0x2 |
| 12264 | 12264 | ||
| 12265 | #define B_CC_REG_UPDATE__A 0x2410017 | 12265 | #define B_CC_REG_UPDATE__A 0x2410017 |
| 12266 | #define B_CC_REG_UPDATE__W 16 | 12266 | #define B_CC_REG_UPDATE__W 16 |
| 12267 | #define B_CC_REG_UPDATE__M 0xFFFF | 12267 | #define B_CC_REG_UPDATE__M 0xFFFF |
| 12268 | #define B_CC_REG_UPDATE_KEY 0x3973 | 12268 | #define B_CC_REG_UPDATE_KEY 0x3973 |
| 12269 | 12269 | ||
| 12270 | #define B_CC_REG_PLL_LOCK__A 0x2410018 | 12270 | #define B_CC_REG_PLL_LOCK__A 0x2410018 |
| 12271 | #define B_CC_REG_PLL_LOCK__W 1 | 12271 | #define B_CC_REG_PLL_LOCK__W 1 |
| 12272 | #define B_CC_REG_PLL_LOCK__M 0x1 | 12272 | #define B_CC_REG_PLL_LOCK__M 0x1 |
| 12273 | #define B_CC_REG_PLL_LOCK_LOCK 0x1 | 12273 | #define B_CC_REG_PLL_LOCK_LOCK 0x1 |
| 12274 | 12274 | ||
| 12275 | #define B_CC_REG_JTAGID_L__A 0x2410019 | 12275 | #define B_CC_REG_JTAGID_L__A 0x2410019 |
| 12276 | #define B_CC_REG_JTAGID_L__W 16 | 12276 | #define B_CC_REG_JTAGID_L__W 16 |
| 12277 | #define B_CC_REG_JTAGID_L__M 0xFFFF | 12277 | #define B_CC_REG_JTAGID_L__M 0xFFFF |
| 12278 | #define B_CC_REG_JTAGID_L_INIT 0x0 | 12278 | #define B_CC_REG_JTAGID_L_INIT 0x0 |
| 12279 | 12279 | ||
| 12280 | #define B_CC_REG_JTAGID_H__A 0x241001A | 12280 | #define B_CC_REG_JTAGID_H__A 0x241001A |
| 12281 | #define B_CC_REG_JTAGID_H__W 16 | 12281 | #define B_CC_REG_JTAGID_H__W 16 |
| 12282 | #define B_CC_REG_JTAGID_H__M 0xFFFF | 12282 | #define B_CC_REG_JTAGID_H__M 0xFFFF |
| 12283 | #define B_CC_REG_JTAGID_H_INIT 0x0 | 12283 | #define B_CC_REG_JTAGID_H_INIT 0x0 |
| 12284 | 12284 | ||
| 12285 | #define B_CC_REG_DIVERSITY__A 0x241001B | 12285 | #define B_CC_REG_DIVERSITY__A 0x241001B |
| 12286 | #define B_CC_REG_DIVERSITY__W 1 | 12286 | #define B_CC_REG_DIVERSITY__W 1 |
| 12287 | #define B_CC_REG_DIVERSITY__M 0x1 | 12287 | #define B_CC_REG_DIVERSITY__M 0x1 |
| 12288 | #define B_CC_REG_DIVERSITY_INIT 0x0 | 12288 | #define B_CC_REG_DIVERSITY_INIT 0x0 |
| 12289 | 12289 | ||
| 12290 | #define B_CC_REG_BACKUP3V__A 0x241001C | 12290 | #define B_CC_REG_BACKUP3V__A 0x241001C |
| 12291 | #define B_CC_REG_BACKUP3V__W 1 | 12291 | #define B_CC_REG_BACKUP3V__W 1 |
| 12292 | #define B_CC_REG_BACKUP3V__M 0x1 | 12292 | #define B_CC_REG_BACKUP3V__M 0x1 |
| 12293 | #define B_CC_REG_BACKUP3V_INIT 0x0 | 12293 | #define B_CC_REG_BACKUP3V_INIT 0x0 |
| 12294 | 12294 | ||
| 12295 | #define B_CC_REG_DRV_IO__A 0x241001D | 12295 | #define B_CC_REG_DRV_IO__A 0x241001D |
| 12296 | #define B_CC_REG_DRV_IO__W 3 | 12296 | #define B_CC_REG_DRV_IO__W 3 |
| 12297 | #define B_CC_REG_DRV_IO__M 0x7 | 12297 | #define B_CC_REG_DRV_IO__M 0x7 |
| 12298 | #define B_CC_REG_DRV_IO_INIT 0x2 | 12298 | #define B_CC_REG_DRV_IO_INIT 0x2 |
| 12299 | 12299 | ||
| 12300 | #define B_CC_REG_DRV_MPG__A 0x241001E | 12300 | #define B_CC_REG_DRV_MPG__A 0x241001E |
| 12301 | #define B_CC_REG_DRV_MPG__W 3 | 12301 | #define B_CC_REG_DRV_MPG__W 3 |
| 12302 | #define B_CC_REG_DRV_MPG__M 0x7 | 12302 | #define B_CC_REG_DRV_MPG__M 0x7 |
| 12303 | #define B_CC_REG_DRV_MPG_INIT 0x2 | 12303 | #define B_CC_REG_DRV_MPG_INIT 0x2 |
| 12304 | 12304 | ||
| 12305 | #define B_CC_REG_DRV_I2C1__A 0x241001F | 12305 | #define B_CC_REG_DRV_I2C1__A 0x241001F |
| 12306 | #define B_CC_REG_DRV_I2C1__W 3 | 12306 | #define B_CC_REG_DRV_I2C1__W 3 |
| 12307 | #define B_CC_REG_DRV_I2C1__M 0x7 | 12307 | #define B_CC_REG_DRV_I2C1__M 0x7 |
| 12308 | #define B_CC_REG_DRV_I2C1_INIT 0x2 | 12308 | #define B_CC_REG_DRV_I2C1_INIT 0x2 |
| 12309 | 12309 | ||
| 12310 | #define B_CC_REG_DRV_I2C2__A 0x2410020 | 12310 | #define B_CC_REG_DRV_I2C2__A 0x2410020 |
| 12311 | #define B_CC_REG_DRV_I2C2__W 1 | 12311 | #define B_CC_REG_DRV_I2C2__W 1 |
| 12312 | #define B_CC_REG_DRV_I2C2__M 0x1 | 12312 | #define B_CC_REG_DRV_I2C2__M 0x1 |
| 12313 | #define B_CC_REG_DRV_I2C2_INIT 0x0 | 12313 | #define B_CC_REG_DRV_I2C2_INIT 0x0 |
| 12314 | 12314 | ||
| 12315 | #define B_LC_SID 0x1C | 12315 | #define B_LC_SID 0x1C |
| 12316 | 12316 | ||
| 12317 | #define B_LC_COMM_EXEC__A 0x2800000 | 12317 | #define B_LC_COMM_EXEC__A 0x2800000 |
| 12318 | #define B_LC_COMM_EXEC__W 3 | 12318 | #define B_LC_COMM_EXEC__W 3 |
| 12319 | #define B_LC_COMM_EXEC__M 0x7 | 12319 | #define B_LC_COMM_EXEC__M 0x7 |
| 12320 | #define B_LC_COMM_EXEC_CTL__B 0 | 12320 | #define B_LC_COMM_EXEC_CTL__B 0 |
| 12321 | #define B_LC_COMM_EXEC_CTL__W 3 | 12321 | #define B_LC_COMM_EXEC_CTL__W 3 |
| 12322 | #define B_LC_COMM_EXEC_CTL__M 0x7 | 12322 | #define B_LC_COMM_EXEC_CTL__M 0x7 |
| 12323 | #define B_LC_COMM_EXEC_CTL_STOP 0x0 | 12323 | #define B_LC_COMM_EXEC_CTL_STOP 0x0 |
| 12324 | #define B_LC_COMM_EXEC_CTL_ACTIVE 0x1 | 12324 | #define B_LC_COMM_EXEC_CTL_ACTIVE 0x1 |
| 12325 | #define B_LC_COMM_EXEC_CTL_HOLD 0x2 | 12325 | #define B_LC_COMM_EXEC_CTL_HOLD 0x2 |
| 12326 | #define B_LC_COMM_EXEC_CTL_STEP 0x3 | 12326 | #define B_LC_COMM_EXEC_CTL_STEP 0x3 |
| 12327 | #define B_LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 | 12327 | #define B_LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 |
| 12328 | #define B_LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 | 12328 | #define B_LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 |
| 12329 | 12329 | ||
| 12330 | #define B_LC_COMM_STATE__A 0x2800001 | 12330 | #define B_LC_COMM_STATE__A 0x2800001 |
| 12331 | #define B_LC_COMM_STATE__W 16 | 12331 | #define B_LC_COMM_STATE__W 16 |
| 12332 | #define B_LC_COMM_STATE__M 0xFFFF | 12332 | #define B_LC_COMM_STATE__M 0xFFFF |
| 12333 | #define B_LC_COMM_MB__A 0x2800002 | 12333 | #define B_LC_COMM_MB__A 0x2800002 |
| 12334 | #define B_LC_COMM_MB__W 16 | 12334 | #define B_LC_COMM_MB__W 16 |
| 12335 | #define B_LC_COMM_MB__M 0xFFFF | 12335 | #define B_LC_COMM_MB__M 0xFFFF |
| 12336 | #define B_LC_COMM_SERVICE0__A 0x2800003 | 12336 | #define B_LC_COMM_SERVICE0__A 0x2800003 |
| 12337 | #define B_LC_COMM_SERVICE0__W 16 | 12337 | #define B_LC_COMM_SERVICE0__W 16 |
| 12338 | #define B_LC_COMM_SERVICE0__M 0xFFFF | 12338 | #define B_LC_COMM_SERVICE0__M 0xFFFF |
| 12339 | #define B_LC_COMM_SERVICE1__A 0x2800004 | 12339 | #define B_LC_COMM_SERVICE1__A 0x2800004 |
| 12340 | #define B_LC_COMM_SERVICE1__W 16 | 12340 | #define B_LC_COMM_SERVICE1__W 16 |
| 12341 | #define B_LC_COMM_SERVICE1__M 0xFFFF | 12341 | #define B_LC_COMM_SERVICE1__M 0xFFFF |
| 12342 | #define B_LC_COMM_INT_STA__A 0x2800007 | 12342 | #define B_LC_COMM_INT_STA__A 0x2800007 |
| 12343 | #define B_LC_COMM_INT_STA__W 16 | 12343 | #define B_LC_COMM_INT_STA__W 16 |
| 12344 | #define B_LC_COMM_INT_STA__M 0xFFFF | 12344 | #define B_LC_COMM_INT_STA__M 0xFFFF |
| 12345 | #define B_LC_COMM_INT_MSK__A 0x2800008 | 12345 | #define B_LC_COMM_INT_MSK__A 0x2800008 |
| 12346 | #define B_LC_COMM_INT_MSK__W 16 | 12346 | #define B_LC_COMM_INT_MSK__W 16 |
| 12347 | #define B_LC_COMM_INT_MSK__M 0xFFFF | 12347 | #define B_LC_COMM_INT_MSK__M 0xFFFF |
| 12348 | 12348 | ||
| 12349 | #define B_LC_CT_REG_COMM_EXEC__A 0x2810000 | 12349 | #define B_LC_CT_REG_COMM_EXEC__A 0x2810000 |
| 12350 | #define B_LC_CT_REG_COMM_EXEC__W 3 | 12350 | #define B_LC_CT_REG_COMM_EXEC__W 3 |
| 12351 | #define B_LC_CT_REG_COMM_EXEC__M 0x7 | 12351 | #define B_LC_CT_REG_COMM_EXEC__M 0x7 |
| 12352 | #define B_LC_CT_REG_COMM_EXEC_CTL__B 0 | 12352 | #define B_LC_CT_REG_COMM_EXEC_CTL__B 0 |
| 12353 | #define B_LC_CT_REG_COMM_EXEC_CTL__W 3 | 12353 | #define B_LC_CT_REG_COMM_EXEC_CTL__W 3 |
| 12354 | #define B_LC_CT_REG_COMM_EXEC_CTL__M 0x7 | 12354 | #define B_LC_CT_REG_COMM_EXEC_CTL__M 0x7 |
| 12355 | #define B_LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 | 12355 | #define B_LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 |
| 12356 | #define B_LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 | 12356 | #define B_LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 12357 | #define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 | 12357 | #define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 |
| 12358 | #define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 | 12358 | #define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 |
| 12359 | 12359 | ||
| 12360 | #define B_LC_CT_REG_COMM_STATE__A 0x2810001 | 12360 | #define B_LC_CT_REG_COMM_STATE__A 0x2810001 |
| 12361 | #define B_LC_CT_REG_COMM_STATE__W 10 | 12361 | #define B_LC_CT_REG_COMM_STATE__W 10 |
| 12362 | #define B_LC_CT_REG_COMM_STATE__M 0x3FF | 12362 | #define B_LC_CT_REG_COMM_STATE__M 0x3FF |
| 12363 | #define B_LC_CT_REG_COMM_SERVICE0__A 0x2810003 | 12363 | #define B_LC_CT_REG_COMM_SERVICE0__A 0x2810003 |
| 12364 | #define B_LC_CT_REG_COMM_SERVICE0__W 16 | 12364 | #define B_LC_CT_REG_COMM_SERVICE0__W 16 |
| 12365 | #define B_LC_CT_REG_COMM_SERVICE0__M 0xFFFF | 12365 | #define B_LC_CT_REG_COMM_SERVICE0__M 0xFFFF |
| 12366 | #define B_LC_CT_REG_COMM_SERVICE1__A 0x2810004 | 12366 | #define B_LC_CT_REG_COMM_SERVICE1__A 0x2810004 |
| 12367 | #define B_LC_CT_REG_COMM_SERVICE1__W 16 | 12367 | #define B_LC_CT_REG_COMM_SERVICE1__W 16 |
| 12368 | #define B_LC_CT_REG_COMM_SERVICE1__M 0xFFFF | 12368 | #define B_LC_CT_REG_COMM_SERVICE1__M 0xFFFF |
| 12369 | #define B_LC_CT_REG_COMM_SERVICE1_LC__B 12 | 12369 | #define B_LC_CT_REG_COMM_SERVICE1_LC__B 12 |
| 12370 | #define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 | 12370 | #define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 |
| 12371 | #define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 | 12371 | #define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 |
| 12372 | 12372 | ||
| 12373 | #define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 | 12373 | #define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 |
| 12374 | #define B_LC_CT_REG_COMM_INT_STA__W 1 | 12374 | #define B_LC_CT_REG_COMM_INT_STA__W 1 |
| 12375 | #define B_LC_CT_REG_COMM_INT_STA__M 0x1 | 12375 | #define B_LC_CT_REG_COMM_INT_STA__M 0x1 |
| 12376 | #define B_LC_CT_REG_COMM_INT_STA_REQUEST__B 0 | 12376 | #define B_LC_CT_REG_COMM_INT_STA_REQUEST__B 0 |
| 12377 | #define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 | 12377 | #define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 |
| 12378 | #define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 | 12378 | #define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 |
| 12379 | 12379 | ||
| 12380 | #define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 | 12380 | #define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 |
| 12381 | #define B_LC_CT_REG_COMM_INT_MSK__W 1 | 12381 | #define B_LC_CT_REG_COMM_INT_MSK__W 1 |
| 12382 | #define B_LC_CT_REG_COMM_INT_MSK__M 0x1 | 12382 | #define B_LC_CT_REG_COMM_INT_MSK__M 0x1 |
| 12383 | #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 | 12383 | #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 |
| 12384 | #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 | 12384 | #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 |
| 12385 | #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 | 12385 | #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 |
| 12386 | 12386 | ||
| 12387 | #define B_LC_CT_REG_CTL_STK__AX 0x2810010 | 12387 | #define B_LC_CT_REG_CTL_STK__AX 0x2810010 |
| 12388 | #define B_LC_CT_REG_CTL_STK__XSZ 4 | 12388 | #define B_LC_CT_REG_CTL_STK__XSZ 4 |
| 12389 | #define B_LC_CT_REG_CTL_STK__W 10 | 12389 | #define B_LC_CT_REG_CTL_STK__W 10 |
| 12390 | #define B_LC_CT_REG_CTL_STK__M 0x3FF | 12390 | #define B_LC_CT_REG_CTL_STK__M 0x3FF |
| 12391 | 12391 | ||
| 12392 | #define B_LC_CT_REG_CTL_BPT_IDX__A 0x281001F | 12392 | #define B_LC_CT_REG_CTL_BPT_IDX__A 0x281001F |
| 12393 | #define B_LC_CT_REG_CTL_BPT_IDX__W 1 | 12393 | #define B_LC_CT_REG_CTL_BPT_IDX__W 1 |
| 12394 | #define B_LC_CT_REG_CTL_BPT_IDX__M 0x1 | 12394 | #define B_LC_CT_REG_CTL_BPT_IDX__M 0x1 |
| 12395 | 12395 | ||
| 12396 | #define B_LC_CT_REG_CTL_BPT__A 0x2810020 | 12396 | #define B_LC_CT_REG_CTL_BPT__A 0x2810020 |
| 12397 | #define B_LC_CT_REG_CTL_BPT__W 10 | 12397 | #define B_LC_CT_REG_CTL_BPT__W 10 |
| 12398 | #define B_LC_CT_REG_CTL_BPT__M 0x3FF | 12398 | #define B_LC_CT_REG_CTL_BPT__M 0x3FF |
| 12399 | 12399 | ||
| 12400 | #define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 | 12400 | #define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 |
| 12401 | #define B_LC_RA_RAM_PROC_DELAY_IF__W 16 | 12401 | #define B_LC_RA_RAM_PROC_DELAY_IF__W 16 |
| 12402 | #define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF | 12402 | #define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF |
| 12403 | #define B_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 | 12403 | #define B_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 |
| 12404 | #define B_LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 | 12404 | #define B_LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 |
| 12405 | #define B_LC_RA_RAM_PROC_DELAY_FS__W 16 | 12405 | #define B_LC_RA_RAM_PROC_DELAY_FS__W 16 |
| 12406 | #define B_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF | 12406 | #define B_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF |
| 12407 | #define B_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 | 12407 | #define B_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 |
| 12408 | #define B_LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 | 12408 | #define B_LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 |
| 12409 | #define B_LC_RA_RAM_LOCK_TH_CRMM__W 16 | 12409 | #define B_LC_RA_RAM_LOCK_TH_CRMM__W 16 |
| 12410 | #define B_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF | 12410 | #define B_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF |
| 12411 | #define B_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 | 12411 | #define B_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 |
| 12412 | #define B_LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 | 12412 | #define B_LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 |
| 12413 | #define B_LC_RA_RAM_LOCK_TH_SRMM__W 16 | 12413 | #define B_LC_RA_RAM_LOCK_TH_SRMM__W 16 |
| 12414 | #define B_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF | 12414 | #define B_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF |
| 12415 | #define B_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 | 12415 | #define B_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 |
| 12416 | #define B_LC_RA_RAM_LOCK_COUNT__A 0x282000A | 12416 | #define B_LC_RA_RAM_LOCK_COUNT__A 0x282000A |
| 12417 | #define B_LC_RA_RAM_LOCK_COUNT__W 16 | 12417 | #define B_LC_RA_RAM_LOCK_COUNT__W 16 |
| 12418 | #define B_LC_RA_RAM_LOCK_COUNT__M 0xFFFF | 12418 | #define B_LC_RA_RAM_LOCK_COUNT__M 0xFFFF |
| 12419 | #define B_LC_RA_RAM_CPRTOFS_NOM__A 0x282000B | 12419 | #define B_LC_RA_RAM_CPRTOFS_NOM__A 0x282000B |
| 12420 | #define B_LC_RA_RAM_CPRTOFS_NOM__W 16 | 12420 | #define B_LC_RA_RAM_CPRTOFS_NOM__W 16 |
| 12421 | #define B_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF | 12421 | #define B_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF |
| 12422 | #define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C | 12422 | #define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C |
| 12423 | #define B_LC_RA_RAM_IFINCR_NOM_L__W 16 | 12423 | #define B_LC_RA_RAM_IFINCR_NOM_L__W 16 |
| 12424 | #define B_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF | 12424 | #define B_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF |
| 12425 | #define B_LC_RA_RAM_IFINCR_NOM_H__A 0x282000D | 12425 | #define B_LC_RA_RAM_IFINCR_NOM_H__A 0x282000D |
| 12426 | #define B_LC_RA_RAM_IFINCR_NOM_H__W 16 | 12426 | #define B_LC_RA_RAM_IFINCR_NOM_H__W 16 |
| 12427 | #define B_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF | 12427 | #define B_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF |
| 12428 | #define B_LC_RA_RAM_FSINCR_NOM_L__A 0x282000E | 12428 | #define B_LC_RA_RAM_FSINCR_NOM_L__A 0x282000E |
| 12429 | #define B_LC_RA_RAM_FSINCR_NOM_L__W 16 | 12429 | #define B_LC_RA_RAM_FSINCR_NOM_L__W 16 |
| 12430 | #define B_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF | 12430 | #define B_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF |
| 12431 | #define B_LC_RA_RAM_FSINCR_NOM_H__A 0x282000F | 12431 | #define B_LC_RA_RAM_FSINCR_NOM_H__A 0x282000F |
| 12432 | #define B_LC_RA_RAM_FSINCR_NOM_H__W 16 | 12432 | #define B_LC_RA_RAM_FSINCR_NOM_H__W 16 |
| 12433 | #define B_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF | 12433 | #define B_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF |
| 12434 | #define B_LC_RA_RAM_MODE_2K__A 0x2820010 | 12434 | #define B_LC_RA_RAM_MODE_2K__A 0x2820010 |
| 12435 | #define B_LC_RA_RAM_MODE_2K__W 16 | 12435 | #define B_LC_RA_RAM_MODE_2K__W 16 |
| 12436 | #define B_LC_RA_RAM_MODE_2K__M 0xFFFF | 12436 | #define B_LC_RA_RAM_MODE_2K__M 0xFFFF |
| 12437 | #define B_LC_RA_RAM_MODE_GUARD__A 0x2820011 | 12437 | #define B_LC_RA_RAM_MODE_GUARD__A 0x2820011 |
| 12438 | #define B_LC_RA_RAM_MODE_GUARD__W 16 | 12438 | #define B_LC_RA_RAM_MODE_GUARD__W 16 |
| 12439 | #define B_LC_RA_RAM_MODE_GUARD__M 0xFFFF | 12439 | #define B_LC_RA_RAM_MODE_GUARD__M 0xFFFF |
| 12440 | #define B_LC_RA_RAM_MODE_GUARD_32 0x0 | 12440 | #define B_LC_RA_RAM_MODE_GUARD_32 0x0 |
| 12441 | #define B_LC_RA_RAM_MODE_GUARD_16 0x1 | 12441 | #define B_LC_RA_RAM_MODE_GUARD_16 0x1 |
| 12442 | #define B_LC_RA_RAM_MODE_GUARD_8 0x2 | 12442 | #define B_LC_RA_RAM_MODE_GUARD_8 0x2 |
| 12443 | #define B_LC_RA_RAM_MODE_GUARD_4 0x3 | 12443 | #define B_LC_RA_RAM_MODE_GUARD_4 0x3 |
| 12444 | 12444 | ||
| 12445 | #define B_LC_RA_RAM_MODE_ADJUST__A 0x2820012 | 12445 | #define B_LC_RA_RAM_MODE_ADJUST__A 0x2820012 |
| 12446 | #define B_LC_RA_RAM_MODE_ADJUST__W 16 | 12446 | #define B_LC_RA_RAM_MODE_ADJUST__W 16 |
| 12447 | #define B_LC_RA_RAM_MODE_ADJUST__M 0xFFFF | 12447 | #define B_LC_RA_RAM_MODE_ADJUST__M 0xFFFF |
| 12448 | #define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 | 12448 | #define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 |
| 12449 | #define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 | 12449 | #define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 |
| 12450 | #define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 | 12450 | #define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 |
| 12451 | #define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 | 12451 | #define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 |
| 12452 | #define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 | 12452 | #define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 |
| 12453 | #define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 | 12453 | #define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 |
| 12454 | #define B_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 | 12454 | #define B_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 |
| 12455 | #define B_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 | 12455 | #define B_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 |
| 12456 | #define B_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 | 12456 | #define B_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 |
| 12457 | #define B_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 | 12457 | #define B_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 |
| 12458 | #define B_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 | 12458 | #define B_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 |
| 12459 | #define B_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 | 12459 | #define B_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 |
| 12460 | #define B_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 | 12460 | #define B_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 |
| 12461 | #define B_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 | 12461 | #define B_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 |
| 12462 | #define B_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 | 12462 | #define B_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 |
| 12463 | #define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 | 12463 | #define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 |
| 12464 | #define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 | 12464 | #define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 |
| 12465 | #define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 | 12465 | #define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 |
| 12466 | #define B_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 | 12466 | #define B_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 |
| 12467 | #define B_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 | 12467 | #define B_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 |
| 12468 | #define B_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 | 12468 | #define B_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 |
| 12469 | #define B_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 | 12469 | #define B_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 |
| 12470 | #define B_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 | 12470 | #define B_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 |
| 12471 | #define B_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 | 12471 | #define B_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 |
| 12472 | #define B_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 | 12472 | #define B_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 |
| 12473 | #define B_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 | 12473 | #define B_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 |
| 12474 | #define B_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 | 12474 | #define B_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 |
| 12475 | #define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 | 12475 | #define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 |
| 12476 | #define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 | 12476 | #define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 |
| 12477 | #define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 | 12477 | #define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 |
| 12478 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 | 12478 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 |
| 12479 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 | 12479 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 |
| 12480 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 | 12480 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 |
| 12481 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 | 12481 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 |
| 12482 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 | 12482 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 |
| 12483 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 | 12483 | #define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 |
| 12484 | 12484 | ||
| 12485 | #define B_LC_RA_RAM_RC_STS__A 0x2820014 | 12485 | #define B_LC_RA_RAM_RC_STS__A 0x2820014 |
| 12486 | #define B_LC_RA_RAM_RC_STS__W 16 | 12486 | #define B_LC_RA_RAM_RC_STS__W 16 |
| 12487 | #define B_LC_RA_RAM_RC_STS__M 0xFFFF | 12487 | #define B_LC_RA_RAM_RC_STS__M 0xFFFF |
| 12488 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x2820018 | 12488 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x2820018 |
| 12489 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 | 12489 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 |
| 12490 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF | 12490 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF |
| 12491 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x2820019 | 12491 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x2820019 |
| 12492 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 | 12492 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 |
| 12493 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF | 12493 | #define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF |
| 12494 | #define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A | 12494 | #define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A |
| 12495 | #define B_LC_RA_RAM_FILTER_SYM_SET__W 16 | 12495 | #define B_LC_RA_RAM_FILTER_SYM_SET__W 16 |
| 12496 | #define B_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF | 12496 | #define B_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF |
| 12497 | #define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 | 12497 | #define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 |
| 12498 | #define B_LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B | 12498 | #define B_LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B |
| 12499 | #define B_LC_RA_RAM_FILTER_SYM_CUR__W 16 | 12499 | #define B_LC_RA_RAM_FILTER_SYM_CUR__W 16 |
| 12500 | #define B_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF | 12500 | #define B_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF |
| 12501 | #define B_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 | 12501 | #define B_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 |
| 12502 | #define B_LC_RA_RAM_DIVERSITY_DELAY__A 0x282001C | 12502 | #define B_LC_RA_RAM_DIVERSITY_DELAY__A 0x282001C |
| 12503 | #define B_LC_RA_RAM_DIVERSITY_DELAY__W 16 | 12503 | #define B_LC_RA_RAM_DIVERSITY_DELAY__W 16 |
| 12504 | #define B_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF | 12504 | #define B_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF |
| 12505 | #define B_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 | 12505 | #define B_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 |
| 12506 | #define B_LC_RA_RAM_MAX_ABS_EXP__A 0x282001D | 12506 | #define B_LC_RA_RAM_MAX_ABS_EXP__A 0x282001D |
| 12507 | #define B_LC_RA_RAM_MAX_ABS_EXP__W 16 | 12507 | #define B_LC_RA_RAM_MAX_ABS_EXP__W 16 |
| 12508 | #define B_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF | 12508 | #define B_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF |
| 12509 | #define B_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 | 12509 | #define B_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 |
| 12510 | #define B_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F | 12510 | #define B_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F |
| 12511 | #define B_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 | 12511 | #define B_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 |
| 12512 | #define B_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF | 12512 | #define B_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF |
| 12513 | #define B_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 | 12513 | #define B_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 |
| 12514 | #define B_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 | 12514 | #define B_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 |
| 12515 | #define B_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF | 12515 | #define B_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF |
| 12516 | #define B_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 | 12516 | #define B_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 |
| 12517 | #define B_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 | 12517 | #define B_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 |
| 12518 | #define B_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF | 12518 | #define B_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF |
| 12519 | #define B_LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 | 12519 | #define B_LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 |
| 12520 | #define B_LC_RA_RAM_ACTUAL_PHASE__W 16 | 12520 | #define B_LC_RA_RAM_ACTUAL_PHASE__W 16 |
| 12521 | #define B_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF | 12521 | #define B_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF |
| 12522 | #define B_LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 | 12522 | #define B_LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 |
| 12523 | #define B_LC_RA_RAM_ACTUAL_DELAY__W 16 | 12523 | #define B_LC_RA_RAM_ACTUAL_DELAY__W 16 |
| 12524 | #define B_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF | 12524 | #define B_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF |
| 12525 | #define B_LC_RA_RAM_ADJUST_CRMM__A 0x2820024 | 12525 | #define B_LC_RA_RAM_ADJUST_CRMM__A 0x2820024 |
| 12526 | #define B_LC_RA_RAM_ADJUST_CRMM__W 16 | 12526 | #define B_LC_RA_RAM_ADJUST_CRMM__W 16 |
| 12527 | #define B_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF | 12527 | #define B_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF |
| 12528 | #define B_LC_RA_RAM_ADJUST_SRMM__A 0x2820025 | 12528 | #define B_LC_RA_RAM_ADJUST_SRMM__A 0x2820025 |
| 12529 | #define B_LC_RA_RAM_ADJUST_SRMM__W 16 | 12529 | #define B_LC_RA_RAM_ADJUST_SRMM__W 16 |
| 12530 | #define B_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF | 12530 | #define B_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF |
| 12531 | #define B_LC_RA_RAM_ADJUST_PHASE__A 0x2820026 | 12531 | #define B_LC_RA_RAM_ADJUST_PHASE__A 0x2820026 |
| 12532 | #define B_LC_RA_RAM_ADJUST_PHASE__W 16 | 12532 | #define B_LC_RA_RAM_ADJUST_PHASE__W 16 |
| 12533 | #define B_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF | 12533 | #define B_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF |
| 12534 | #define B_LC_RA_RAM_ADJUST_DELAY__A 0x2820027 | 12534 | #define B_LC_RA_RAM_ADJUST_DELAY__A 0x2820027 |
| 12535 | #define B_LC_RA_RAM_ADJUST_DELAY__W 16 | 12535 | #define B_LC_RA_RAM_ADJUST_DELAY__W 16 |
| 12536 | #define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF | 12536 | #define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF |
| 12537 | 12537 | ||
| 12538 | #define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 | 12538 | #define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 |
| 12539 | #define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 | 12539 | #define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 |
| 12540 | #define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF | 12540 | #define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF |
| 12541 | #define B_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 | 12541 | #define B_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 |
| 12542 | #define B_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 | 12542 | #define B_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 |
| 12543 | #define B_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF | 12543 | #define B_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF |
| 12544 | #define B_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A | 12544 | #define B_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A |
| 12545 | #define B_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 | 12545 | #define B_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 |
| 12546 | #define B_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF | 12546 | #define B_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF |
| 12547 | #define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B | 12547 | #define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B |
| 12548 | #define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 | 12548 | #define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 |
| 12549 | #define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF | 12549 | #define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF |
| 12550 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C | 12550 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C |
| 12551 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 | 12551 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 |
| 12552 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF | 12552 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF |
| 12553 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D | 12553 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D |
| 12554 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 | 12554 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 |
| 12555 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF | 12555 | #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF |
| 12556 | 12556 | ||
| 12557 | #define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 | 12557 | #define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 |
| 12558 | #define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 | 12558 | #define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 |
| 12559 | #define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF | 12559 | #define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF |
| 12560 | #define B_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 | 12560 | #define B_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 |
| 12561 | #define B_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 | 12561 | #define B_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 |
| 12562 | #define B_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF | 12562 | #define B_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF |
| 12563 | #define B_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 | 12563 | #define B_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 |
| 12564 | #define B_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 | 12564 | #define B_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 |
| 12565 | #define B_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF | 12565 | #define B_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF |
| 12566 | #define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 | 12566 | #define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 |
| 12567 | #define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 | 12567 | #define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 |
| 12568 | #define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF | 12568 | #define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF |
| 12569 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 | 12569 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 |
| 12570 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 | 12570 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 |
| 12571 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF | 12571 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF |
| 12572 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 | 12572 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 |
| 12573 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 | 12573 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 |
| 12574 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF | 12574 | #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF |
| 12575 | 12575 | ||
| 12576 | #define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 | 12576 | #define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 |
| 12577 | #define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 | 12577 | #define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 |
| 12578 | #define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF | 12578 | #define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF |
| 12579 | #define B_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 | 12579 | #define B_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 |
| 12580 | #define B_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 | 12580 | #define B_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 |
| 12581 | #define B_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF | 12581 | #define B_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF |
| 12582 | #define B_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A | 12582 | #define B_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A |
| 12583 | #define B_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 | 12583 | #define B_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 |
| 12584 | #define B_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF | 12584 | #define B_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF |
| 12585 | #define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B | 12585 | #define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B |
| 12586 | #define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 | 12586 | #define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 |
| 12587 | #define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF | 12587 | #define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF |
| 12588 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C | 12588 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C |
| 12589 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 | 12589 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 |
| 12590 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF | 12590 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF |
| 12591 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D | 12591 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D |
| 12592 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 | 12592 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 |
| 12593 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF | 12593 | #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF |
| 12594 | 12594 | ||
| 12595 | #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 | 12595 | #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 |
| 12596 | #define B_LC_RA_RAM_FILTER_CRMM_A__W 16 | 12596 | #define B_LC_RA_RAM_FILTER_CRMM_A__W 16 |
| 12597 | #define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF | 12597 | #define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF |
| 12598 | #define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 | 12598 | #define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 |
| 12599 | #define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 | 12599 | #define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 |
| 12600 | #define B_LC_RA_RAM_FILTER_CRMM_B__W 16 | 12600 | #define B_LC_RA_RAM_FILTER_CRMM_B__W 16 |
| 12601 | #define B_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF | 12601 | #define B_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF |
| 12602 | #define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 | 12602 | #define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 |
| 12603 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 | 12603 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 |
| 12604 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 | 12604 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 |
| 12605 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__W 16 | 12605 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__W 16 |
| 12606 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF | 12606 | #define B_LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF |
| 12607 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 | 12607 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 |
| 12608 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 | 12608 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 |
| 12609 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__W 16 | 12609 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__W 16 |
| 12610 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF | 12610 | #define B_LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF |
| 12611 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 | 12611 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 |
| 12612 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 | 12612 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 |
| 12613 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 | 12613 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 |
| 12614 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF | 12614 | #define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF |
| 12615 | 12615 | ||
| 12616 | #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 | 12616 | #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 |
| 12617 | #define B_LC_RA_RAM_FILTER_SRMM_A__W 16 | 12617 | #define B_LC_RA_RAM_FILTER_SRMM_A__W 16 |
| 12618 | #define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF | 12618 | #define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF |
| 12619 | #define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 | 12619 | #define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 |
| 12620 | #define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 | 12620 | #define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 |
| 12621 | #define B_LC_RA_RAM_FILTER_SRMM_B__W 16 | 12621 | #define B_LC_RA_RAM_FILTER_SRMM_B__W 16 |
| 12622 | #define B_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF | 12622 | #define B_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF |
| 12623 | #define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 | 12623 | #define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 |
| 12624 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A | 12624 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A |
| 12625 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 | 12625 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 |
| 12626 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__W 16 | 12626 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__W 16 |
| 12627 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF | 12627 | #define B_LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF |
| 12628 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C | 12628 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C |
| 12629 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 | 12629 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 |
| 12630 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__W 16 | 12630 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__W 16 |
| 12631 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF | 12631 | #define B_LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF |
| 12632 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E | 12632 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E |
| 12633 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 | 12633 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 |
| 12634 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 | 12634 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 |
| 12635 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF | 12635 | #define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF |
| 12636 | 12636 | ||
| 12637 | #define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 | 12637 | #define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 |
| 12638 | #define B_LC_RA_RAM_FILTER_PHASE_A__W 16 | 12638 | #define B_LC_RA_RAM_FILTER_PHASE_A__W 16 |
| 12639 | #define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF | 12639 | #define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF |
| 12640 | #define B_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 | 12640 | #define B_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 |
| 12641 | #define B_LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 | 12641 | #define B_LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 |
| 12642 | #define B_LC_RA_RAM_FILTER_PHASE_B__W 16 | 12642 | #define B_LC_RA_RAM_FILTER_PHASE_B__W 16 |
| 12643 | #define B_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF | 12643 | #define B_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF |
| 12644 | #define B_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 | 12644 | #define B_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 |
| 12645 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 | 12645 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 |
| 12646 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 | 12646 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 |
| 12647 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__W 16 | 12647 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__W 16 |
| 12648 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF | 12648 | #define B_LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF |
| 12649 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 | 12649 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 |
| 12650 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 | 12650 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 |
| 12651 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__W 16 | 12651 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__W 16 |
| 12652 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF | 12652 | #define B_LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF |
| 12653 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 | 12653 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 |
| 12654 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 | 12654 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 |
| 12655 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 | 12655 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 |
| 12656 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF | 12656 | #define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF |
| 12657 | 12657 | ||
| 12658 | #define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 | 12658 | #define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 |
| 12659 | #define B_LC_RA_RAM_FILTER_DELAY_A__W 16 | 12659 | #define B_LC_RA_RAM_FILTER_DELAY_A__W 16 |
| 12660 | #define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF | 12660 | #define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF |
| 12661 | #define B_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 | 12661 | #define B_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 |
| 12662 | #define B_LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 | 12662 | #define B_LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 |
| 12663 | #define B_LC_RA_RAM_FILTER_DELAY_B__W 16 | 12663 | #define B_LC_RA_RAM_FILTER_DELAY_B__W 16 |
| 12664 | #define B_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF | 12664 | #define B_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF |
| 12665 | #define B_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 | 12665 | #define B_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 |
| 12666 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A | 12666 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A |
| 12667 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 | 12667 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 |
| 12668 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__W 16 | 12668 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__W 16 |
| 12669 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF | 12669 | #define B_LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF |
| 12670 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C | 12670 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C |
| 12671 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 | 12671 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 |
| 12672 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__W 16 | 12672 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__W 16 |
| 12673 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF | 12673 | #define B_LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF |
| 12674 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E | 12674 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E |
| 12675 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 | 12675 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 |
| 12676 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 | 12676 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 |
| 12677 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF | 12677 | #define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF |
| 12678 | 12678 | ||
| 12679 | #define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 | 12679 | #define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 |
| 12680 | #define B_LC_IF_RAM_TRP_BPT0__XSZ 2 | 12680 | #define B_LC_IF_RAM_TRP_BPT0__XSZ 2 |
| 12681 | #define B_LC_IF_RAM_TRP_BPT0__W 12 | 12681 | #define B_LC_IF_RAM_TRP_BPT0__W 12 |
| 12682 | #define B_LC_IF_RAM_TRP_BPT0__M 0xFFF | 12682 | #define B_LC_IF_RAM_TRP_BPT0__M 0xFFF |
| 12683 | 12683 | ||
| 12684 | #define B_LC_IF_RAM_TRP_STKU__AX 0x2830002 | 12684 | #define B_LC_IF_RAM_TRP_STKU__AX 0x2830002 |
| 12685 | #define B_LC_IF_RAM_TRP_STKU__XSZ 2 | 12685 | #define B_LC_IF_RAM_TRP_STKU__XSZ 2 |
| 12686 | #define B_LC_IF_RAM_TRP_STKU__W 12 | 12686 | #define B_LC_IF_RAM_TRP_STKU__W 12 |
| 12687 | #define B_LC_IF_RAM_TRP_STKU__M 0xFFF | 12687 | #define B_LC_IF_RAM_TRP_STKU__M 0xFFF |
| 12688 | 12688 | ||
| 12689 | #define B_LC_IF_RAM_TRP_WARM__AX 0x2830006 | 12689 | #define B_LC_IF_RAM_TRP_WARM__AX 0x2830006 |
| 12690 | #define B_LC_IF_RAM_TRP_WARM__XSZ 2 | 12690 | #define B_LC_IF_RAM_TRP_WARM__XSZ 2 |
| 12691 | #define B_LC_IF_RAM_TRP_WARM__W 12 | 12691 | #define B_LC_IF_RAM_TRP_WARM__W 12 |
| 12692 | #define B_LC_IF_RAM_TRP_WARM__M 0xFFF | 12692 | #define B_LC_IF_RAM_TRP_WARM__M 0xFFF |
| 12693 | 12693 | ||
| 12694 | #endif | 12694 | #endif |