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authorErnesto Ramos <ernesto@ti.com>2010-07-28 10:54:52 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-07-28 11:23:19 -0400
commita2c2272194ac8bfe5ae3ec91e722a766d931d324 (patch)
tree4b7705e020adc09403ecad709f438bca46df8e30 /drivers
parent3a8965fda925361c291cb03f7aced2e3e51116b9 (diff)
staging:ti dspbridge: fix bridge_brd_stop so IVA2 is set OFF
right now, bridge_brd_stop is not changing the IVA2 power state to OFF since PM_PWSTST_IVA2 is not 0 after calling this function. Signed-off-by: Ernesto Ramos <ernesto@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/tidspbridge/core/tiomap3430.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c
index 9673acba9913..77527bd752fe 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -639,11 +639,11 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
639 dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) & 639 dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
640 OMAP_POWERSTATEST_MASK; 640 OMAP_POWERSTATEST_MASK;
641 if (dsp_pwr_state != PWRDM_POWER_OFF) { 641 if (dsp_pwr_state != PWRDM_POWER_OFF) {
642 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
643 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
642 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE); 644 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
643 mdelay(10); 645 mdelay(10);
644 646
645 clk_status = dsp_clk_disable(DSP_CLK_IVA2);
646
647 /* IVA2 is not in OFF state */ 647 /* IVA2 is not in OFF state */
648 /* Set PM_PWSTCTRL_IVA2 to OFF */ 648 /* Set PM_PWSTCTRL_IVA2 to OFF */
649 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK, 649 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
@@ -651,8 +651,6 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
651 /* Set the SW supervised state transition for Sleep */ 651 /* Set the SW supervised state transition for Sleep */
652 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, 652 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
653 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); 653 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
654 } else {
655 clk_status = dsp_clk_disable(DSP_CLK_IVA2);
656 } 654 }
657 udelay(10); 655 udelay(10);
658 /* Release the Ext Base virtual Address as the next DSP Program 656 /* Release the Ext Base virtual Address as the next DSP Program
@@ -682,6 +680,8 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
682 (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | 680 (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
683 OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 681 OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
684 682
683 clk_status = dsp_clk_disable(DSP_CLK_IVA2);
684
685 return status; 685 return status;
686} 686}
687 687