diff options
author | Zhao Yakui <yakui.zhao@intel.com> | 2010-07-19 04:43:13 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-08-01 22:40:30 -0400 |
commit | 0d3a1beecfa54b938edf3ed046902f072e1e180a (patch) | |
tree | 1cf4fc59da3d35743984ab7c4ac6febd0c4989ea /drivers | |
parent | 1fc7947898e3c407a20e130458e30cc45aa3335c (diff) |
drm/i915: Always use the fixed panel timing for eDP
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2b99ab23dc8a..233e6fd89328 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -511,11 +511,37 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |||
511 | { | 511 | { |
512 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | 512 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
513 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | 513 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; |
514 | struct drm_device *dev = encoder->dev; | ||
515 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
514 | int lane_count, clock; | 516 | int lane_count, clock; |
515 | int max_lane_count = intel_dp_max_lane_count(intel_encoder); | 517 | int max_lane_count = intel_dp_max_lane_count(intel_encoder); |
516 | int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0; | 518 | int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0; |
517 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; | 519 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
518 | 520 | ||
521 | if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && | ||
522 | dev_priv->panel_fixed_mode) { | ||
523 | struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; | ||
524 | |||
525 | adjusted_mode->hdisplay = fixed_mode->hdisplay; | ||
526 | adjusted_mode->hsync_start = fixed_mode->hsync_start; | ||
527 | adjusted_mode->hsync_end = fixed_mode->hsync_end; | ||
528 | adjusted_mode->htotal = fixed_mode->htotal; | ||
529 | |||
530 | adjusted_mode->vdisplay = fixed_mode->vdisplay; | ||
531 | adjusted_mode->vsync_start = fixed_mode->vsync_start; | ||
532 | adjusted_mode->vsync_end = fixed_mode->vsync_end; | ||
533 | adjusted_mode->vtotal = fixed_mode->vtotal; | ||
534 | |||
535 | adjusted_mode->clock = fixed_mode->clock; | ||
536 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | ||
537 | |||
538 | /* | ||
539 | * the mode->clock is used to calculate the Data&Link M/N | ||
540 | * of the pipe. For the eDP the fixed clock should be used. | ||
541 | */ | ||
542 | mode->clock = dev_priv->panel_fixed_mode->clock; | ||
543 | } | ||
544 | |||
519 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { | 545 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
520 | for (clock = 0; clock <= max_clock; clock++) { | 546 | for (clock = 0; clock <= max_clock; clock++) { |
521 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); | 547 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |