Merge remote branch 'intel/drm-intel-next' of /ssd/git/drm-next into drm-core-next

* 'intel/drm-intel-next' of /ssd/git/drm-next: (230 commits)
  drm/i915: Clear the Ironlake dithering flags when the pipe doesn't want it.
  drm/agp/i915: trim stolen space to 32M
  drm/i915: Unset cursor if out-of-bounds upon mode change (v4)
  drm/i915: Unreference object not handle on creation
  drm/i915: Attempt to uncouple object after catastrophic failure in unbind
  drm/i915: Repeat unbinding during free if interrupted (v6)
  drm/i915: Refactor i915_gem_retire_requests()
  drm/i915: Warn if we run out of FIFO space for a mode
  drm/i915: Round up the watermark entries (v3)
  drm/i915: Typo in (unused) register mask for overlay.
  drm/i915: Check overlay stride errata for i830 and i845
  drm/i915: Validate the mode for eDP by using fixed panel size
  drm/i915: Always use the fixed panel timing for eDP
  drm/i915: Enable panel fitting for eDP
  drm/i915: Add fixed panel mode parsed from EDID for eDP without fixed mode in VBT
  drm/i915/sdvo: Set sync polarity based on actual mode
  drm/i915/hdmi: Set sync polarity based on actual mode
  drm/i915/pch: Set transcoder sync polarity for DP based on actual mode
  drm/i915: Initialize LVDS and eDP outputs before anything else
  drm/i915/dp: Correctly report eDP in the core connector type
  ...

86 files changed, 1621 insertions, 783 deletions

diff --git a/drivers/acpi/acpica/evxfevnt.c b/drivers/acpi/acpica/evxfevnt.c
index d97b8dce1668..18b3f1468b7d 100644
--- a/drivers/acpi/acpica/evxfevnt.c
+++ b/drivers/acpi/acpica/evxfevnt.c
@@ -70,6 +70,7 @@ acpi_ev_get_gpe_device(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
 acpi_status acpi_enable(void)
 {
         acpi_status status;
+        int retry;
 
         ACPI_FUNCTION_TRACE(acpi_enable);
 
@@ -98,16 +99,18 @@ acpi_status acpi_enable(void)
 
         /* Sanity check that transition succeeded */
 
-        if (acpi_hw_get_mode() != ACPI_SYS_MODE_ACPI) {
-                ACPI_ERROR((AE_INFO,
-                            "Hardware did not enter ACPI mode"));
-                return_ACPI_STATUS(AE_NO_HARDWARE_RESPONSE);
+        for (retry = 0; retry < 30000; ++retry) {
+                if (acpi_hw_get_mode() == ACPI_SYS_MODE_ACPI) {
+                        if (retry != 0)
+                                ACPI_WARNING((AE_INFO,
+                                "Platform took > %d00 usec to enter ACPI mode", retry));
+                        return_ACPI_STATUS(AE_OK);
+                }
+                acpi_os_stall(100);     /* 100 usec */
         }
 
-        ACPI_DEBUG_PRINT((ACPI_DB_INIT,
-                          "Transition to ACPI mode successful\n"));
-
-        return_ACPI_STATUS(AE_OK);
+        ACPI_ERROR((AE_INFO, "Hardware did not enter ACPI mode"));
+        return_ACPI_STATUS(AE_NO_HARDWARE_RESPONSE);
 }
 
 ACPI_EXPORT_SYMBOL(acpi_enable)
diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c
index 3026e3fa83ef..dc58402b0a17 100644
--- a/drivers/acpi/battery.c
+++ b/drivers/acpi/battery.c
@@ -868,9 +868,15 @@ static void acpi_battery_remove_fs(struct acpi_device *device)
 static void acpi_battery_notify(struct acpi_device *device, u32 event)
 {
         struct acpi_battery *battery = acpi_driver_data(device);
+#ifdef CONFIG_ACPI_SYSFS_POWER
+        struct device *old;
+#endif
 
         if (!battery)
                 return;
+#ifdef CONFIG_ACPI_SYSFS_POWER
+        old = battery->bat.dev;
+#endif
         acpi_battery_update(battery);
         acpi_bus_generate_proc_event(device, event,
                                      acpi_battery_present(battery));
@@ -879,7 +885,7 @@ static void acpi_battery_notify(struct acpi_device *device, u32 event)
                                         acpi_battery_present(battery));
 #ifdef CONFIG_ACPI_SYSFS_POWER
         /* acpi_battery_update could remove power_supply object */
-        if (battery->bat.dev)
+        if (old && battery->bat.dev)
                 power_supply_changed(&battery->bat);
 #endif
 }
diff --git a/drivers/acpi/blacklist.c b/drivers/acpi/blacklist.c
index 01381be05e96..2bb28b9d91c4 100644
--- a/drivers/acpi/blacklist.c
+++ b/drivers/acpi/blacklist.c
@@ -214,7 +214,7 @@ static struct dmi_system_id acpi_osi_dmi_table[] __initdata = {
         .ident = "Sony VGN-SR290J",
         .matches = {
                      DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
-                     DMI_MATCH(DMI_PRODUCT_NAME, "Sony VGN-SR290J"),
+                     DMI_MATCH(DMI_PRODUCT_NAME, "VGN-SR290J"),
                 },
         },
         {
diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c
index 51284351418f..e9699aaed109 100644
--- a/drivers/acpi/processor_core.c
+++ b/drivers/acpi/processor_core.c
@@ -223,7 +223,7 @@ static bool processor_physically_present(acpi_handle handle)
         type = (acpi_type == ACPI_TYPE_DEVICE) ? 1 : 0;
         cpuid = acpi_get_cpuid(handle, type, acpi_id);
 
-        if (cpuid == -1)
+        if ((cpuid == -1) && (num_possible_cpus() > 1))
                 return false;
 
         return true;
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index b1b385692f46..e9a8026d39f0 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -76,14 +76,19 @@ static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
 module_param(max_cstate, uint, 0000);
 static unsigned int nocst __read_mostly;
 module_param(nocst, uint, 0000);
+static int bm_check_disable __read_mostly;
+module_param(bm_check_disable, uint, 0000);
 
 static unsigned int latency_factor __read_mostly = 2;
 module_param(latency_factor, uint, 0644);
 
+#ifdef CONFIG_ACPI_PROCFS
 static u64 us_to_pm_timer_ticks(s64 t)
 {
         return div64_u64(t * PM_TIMER_FREQUENCY, 1000000);
 }
+#endif
+
 /*
  * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
  * For now disable this. Probably a bug somewhere else.
@@ -763,6 +768,9 @@ static int acpi_idle_bm_check(void)
 {
         u32 bm_status = 0;
 
+        if (bm_check_disable)
+                return 0;
+
         acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
         if (bm_status)
                 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
@@ -947,7 +955,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
         if (acpi_idle_suspend)
                 return(acpi_idle_enter_c1(dev, state));
 
-        if (acpi_idle_bm_check()) {
+        if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
                 if (dev->safe_state) {
                         dev->last_state = dev->safe_state;
                         return dev->safe_state->enter(dev, dev->safe_state);
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 5b7c52e4a00f..2862c781b372 100644
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -82,6 +82,20 @@ static int acpi_sleep_prepare(u32 acpi_state)
 static u32 acpi_target_sleep_state = ACPI_STATE_S0;
 
 /*
+ * The ACPI specification wants us to save NVS memory regions during hibernation
+ * and to restore them during the subsequent resume.  Windows does that also for
+ * suspend to RAM.  However, it is known that this mechanism does not work on
+ * all machines, so we allow the user to disable it with the help of the
+ * 'acpi_sleep=nonvs' kernel command line option.
+ */
+static bool nvs_nosave;
+
+void __init acpi_nvs_nosave(void)
+{
+        nvs_nosave = true;
+}
+
+/*
  * ACPI 1.0 wants us to execute _PTS before suspending devices, so we allow the
  * user to request that behavior by using the 'acpi_old_suspend_ordering'
  * kernel command line option that causes the following variable to be set.
@@ -197,8 +211,7 @@ static int acpi_suspend_begin(suspend_state_t pm_state)
         u32 acpi_state = acpi_suspend_states[pm_state];
         int error = 0;
 
-        error = suspend_nvs_alloc();
-
+        error = nvs_nosave ? 0 : suspend_nvs_alloc();
         if (error)
                 return error;
 
@@ -388,20 +401,6 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = {
 #endif /* CONFIG_SUSPEND */
 
 #ifdef CONFIG_HIBERNATION
-/*
- * The ACPI specification wants us to save NVS memory regions during hibernation
- * and to restore them during the subsequent resume.  However, it is not certain
- * if this mechanism is going to work on all machines, so we allow the user to
- * disable this mechanism using the 'acpi_sleep=s4_nonvs' kernel command line
- * option.
- */
-static bool s4_no_nvs;
-
-void __init acpi_s4_no_nvs(void)
-{
-        s4_no_nvs = true;
-}
-
 static unsigned long s4_hardware_signature;
 static struct acpi_table_facs *facs;
 static bool nosigcheck;
@@ -415,7 +414,7 @@ static int acpi_hibernation_begin(void)
 {
         int error;
 
-        error = s4_no_nvs ? 0 : suspend_nvs_alloc();
+        error = nvs_nosave ? 0 : suspend_nvs_alloc();
         if (!error) {
                 acpi_target_sleep_state = ACPI_STATE_S4;
                 acpi_sleep_tts_switch(acpi_target_sleep_state);
@@ -510,7 +509,7 @@ static int acpi_hibernation_begin_old(void)
         error = acpi_sleep_prepare(ACPI_STATE_S4);
 
         if (!error) {
-                if (!s4_no_nvs)
+                if (!nvs_nosave)
                         error = suspend_nvs_alloc();
                 if (!error)
                         acpi_target_sleep_state = ACPI_STATE_S4;
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 9630fbdf4e6c..9b9d3bd54e3a 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -673,7 +673,7 @@ static struct kobject *get_device_parent(struct device *dev,
                  */
                 if (parent == NULL)
                         parent_kobj = virtual_device_parent(dev);
-                else if (parent->class)
+                else if (parent->class && !dev->class->ns_type)
                         return &parent->kobj;
                 else
                         parent_kobj = &parent->kobj;
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index d836a71bf06d..5bbc7be203a6 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -816,9 +816,9 @@ static const struct intel_driver_description {
         { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
             "HD Graphics", NULL, &intel_i965_driver },
         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG,
-            "Sandybridge", NULL, &intel_i965_driver },
+            "Sandybridge", NULL, &intel_gen6_driver },
         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG,
-            "Sandybridge", NULL, &intel_i965_driver },
+            "Sandybridge", NULL, &intel_gen6_driver },
         { 0, 0, NULL, NULL, NULL }
 };
 
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 2547465d4658..c05e3e518268 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -60,6 +60,12 @@
 #define I810_PTE_LOCAL          0x00000002
 #define I810_PTE_VALID          0x00000001
 #define I830_PTE_SYSTEM_CACHED  0x00000006
+/* GT PTE cache control fields */
+#define GEN6_PTE_UNCACHED       0x00000002
+#define GEN6_PTE_LLC            0x00000004
+#define GEN6_PTE_LLC_MLC        0x00000006
+#define GEN6_PTE_GFDT           0x00000008
+
 #define I810_SMRAM_MISCC        0x70
 #define I810_GFX_MEM_WIN_SIZE   0x00010000
 #define I810_GFX_MEM_WIN_32M    0x00010000
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 9344216183a4..d22ffb811bf2 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -25,6 +25,10 @@
 #define USE_PCI_DMA_API 1
 #endif
 
+/* Max amount of stolen space, anything above will be returned to Linux */
+int intel_max_stolen = 32 * 1024 * 1024;
+EXPORT_SYMBOL(intel_max_stolen);
+
 static const struct aper_size_info_fixed intel_i810_sizes[] =
 {
         {64, 16384, 4},
@@ -104,7 +108,7 @@ static int intel_agp_map_memory(struct agp_memory *mem)
         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 
         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
-                return -ENOMEM;
+                goto err;
 
         mem->sg_list = sg = st.sgl;
 
@@ -113,11 +117,14 @@ static int intel_agp_map_memory(struct agp_memory *mem)
 
         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
-        if (unlikely(!mem->num_sg)) {
-                intel_agp_free_sglist(mem);
-                return -ENOMEM;
-        }
+        if (unlikely(!mem->num_sg))
+                goto err;
+
         return 0;
+
+err:
+        sg_free_table(&st);
+        return -ENOMEM;
 }
 
 static void intel_agp_unmap_memory(struct agp_memory *mem)
@@ -176,7 +183,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem,
         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
         {
-                cache_bits = I830_PTE_SYSTEM_CACHED;
+                cache_bits = GEN6_PTE_LLC_MLC;
         }
 
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -710,7 +717,12 @@ static void intel_i830_init_gtt_entries(void)
                         break;
                 }
         }
-        if (gtt_entries > 0) {
+        if (!local && gtt_entries > intel_max_stolen) {
+                dev_info(&agp_bridge->dev->dev,
+                         "detected %dK stolen memory, trimming to %dK\n",
+                         gtt_entries / KB(1), intel_max_stolen / KB(1));
+                gtt_entries = intel_max_stolen / KB(4);
+        } else if (gtt_entries > 0) {
                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
                        gtt_entries / KB(1), local ? "local" : "stolen");
                 gtt_entries /= KB(4);
@@ -797,6 +809,10 @@ static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 
         /* we have to call this as early as possible after the MMIO base address is known */
         intel_i830_init_gtt_entries();
+        if (intel_private.gtt_entries == 0) {
+                iounmap(intel_private.registers);
+                return -ENOMEM;
+        }
 
         agp_bridge->gatt_table = NULL;
 
@@ -1216,17 +1232,20 @@ static int intel_i915_get_gtt_size(void)
 
                 /* G33's GTT size defined in gmch_ctrl */
                 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
-                switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
-                case G33_PGETBL_SIZE_1M:
+                switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
+                case I830_GMCH_GMS_STOLEN_512:
+                        size = 512;
+                        break;
+                case I830_GMCH_GMS_STOLEN_1024:
                         size = 1024;
                         break;
-                case G33_PGETBL_SIZE_2M:
-                        size = 2048;
+                case I830_GMCH_GMS_STOLEN_8192:
+                        size = 8*1024;
                         break;
                 default:
                         dev_info(&agp_bridge->dev->dev,
                                  "unknown page table size 0x%x, assuming 512KB\n",
-                                (gmch_ctrl & G33_PGETBL_SIZE_MASK));
+                                (gmch_ctrl & I830_GMCH_GMS_MASK));
                         size = 512;
                 }
         } else {
@@ -1279,6 +1298,11 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
 
         /* we have to call this as early as possible after the MMIO base address is known */
         intel_i830_init_gtt_entries();
+        if (intel_private.gtt_entries == 0) {
+                iounmap(intel_private.gtt);
+                iounmap(intel_private.registers);
+                return -ENOMEM;
+        }
 
         agp_bridge->gatt_table = NULL;
 
@@ -1306,6 +1330,16 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
         return addr | bridge->driver->masks[type].mask;
 }
 
+static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
+                                            dma_addr_t addr, int type)
+{
+        /* Shift high bits down */
+        addr |= (addr >> 28) & 0xff;
+
+        /* Type checking must be done elsewhere */
+        return addr | bridge->driver->masks[type].mask;
+}
+
 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
 {
         u16 snb_gmch_ctl;
@@ -1387,6 +1421,11 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
 
         /* we have to call this as early as possible after the MMIO base address is known */
         intel_i830_init_gtt_entries();
+        if (intel_private.gtt_entries == 0) {
+                iounmap(intel_private.gtt);
+                iounmap(intel_private.registers);
+                return -ENOMEM;
+        }
 
         agp_bridge->gatt_table = NULL;
 
@@ -1514,6 +1553,39 @@ static const struct agp_bridge_driver intel_i965_driver = {
 #endif
 };
 
+static const struct agp_bridge_driver intel_gen6_driver = {
+        .owner                  = THIS_MODULE,
+        .aperture_sizes         = intel_i830_sizes,
+        .size_type              = FIXED_APER_SIZE,
+        .num_aperture_sizes     = 4,
+        .needs_scratch_page     = true,
+        .configure              = intel_i9xx_configure,
+        .fetch_size             = intel_i9xx_fetch_size,
+        .cleanup                = intel_i915_cleanup,
+        .mask_memory            = intel_gen6_mask_memory,
+        .masks                  = intel_i810_masks,
+        .agp_enable             = intel_i810_agp_enable,
+        .cache_flush            = global_cache_flush,
+        .create_gatt_table      = intel_i965_create_gatt_table,
+        .free_gatt_table        = intel_i830_free_gatt_table,
+        .insert_memory          = intel_i915_insert_entries,
+        .remove_memory          = intel_i915_remove_entries,
+        .alloc_by_type          = intel_i830_alloc_by_type,
+        .free_by_type           = intel_i810_free_by_type,
+        .agp_alloc_page         = agp_generic_alloc_page,
+        .agp_alloc_pages        = agp_generic_alloc_pages,
+        .agp_destroy_page       = agp_generic_destroy_page,
+        .agp_destroy_pages      = agp_generic_destroy_pages,
+        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
+        .chipset_flush          = intel_i915_chipset_flush,
+#ifdef USE_PCI_DMA_API
+        .agp_map_page           = intel_agp_map_page,
+        .agp_unmap_page         = intel_agp_unmap_page,
+        .agp_map_memory         = intel_agp_map_memory,
+        .agp_unmap_memory       = intel_agp_unmap_memory,
+#endif
+};
+
 static const struct agp_bridge_driver intel_g33_driver = {
         .owner                  = THIS_MODULE,
         .aperture_sizes         = intel_i830_sizes,
diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
index 24314a9cffe8..1030f8420137 100644
--- a/drivers/char/tpm/tpm_tis.c
+++ b/drivers/char/tpm/tpm_tis.c
@@ -623,7 +623,14 @@ static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
 
 static int tpm_tis_pnp_resume(struct pnp_dev *dev)
 {
-        return tpm_pm_resume(&dev->dev);
+        struct tpm_chip *chip = pnp_get_drvdata(dev);
+        int ret;
+
+        ret = tpm_pm_resume(&dev->dev);
+        if (!ret)
+                tpm_continue_selftest(chip);
+
+        return ret;
 }
 
 static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 063b2184caf5..938b74ea9ffb 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1077,6 +1077,7 @@ err_out_unregister:
 
 err_unlock_policy:
         unlock_policy_rwsem_write(cpu);
+        free_cpumask_var(policy->related_cpus);
 err_free_cpumask:
         free_cpumask_var(policy->cpus);
 err_free_policy:
@@ -1762,17 +1763,8 @@ static int __cpufreq_set_policy(struct cpufreq_policy *data,
                         dprintk("governor switch\n");
 
                         /* end old governor */
-                        if (data->governor) {
-                                /*
-                                 * Need to release the rwsem around governor
-                                 * stop due to lock dependency between
-                                 * cancel_delayed_work_sync and the read lock
-                                 * taken in the delayed work handler.
-                                 */
-                                unlock_policy_rwsem_write(data->cpu);
+                        if (data->governor)
                                 __cpufreq_governor(data, CPUFREQ_GOV_STOP);
-                                lock_policy_rwsem_write(data->cpu);
-                        }
 
                         /* start new governor */
                         data->governor = policy->governor;
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index cc9357da0e34..e0187d16dd7c 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -1300,7 +1300,7 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
                 if (devno == 0)
                         return -ENODEV;
 
-                i7core_printk(KERN_ERR,
+                i7core_printk(KERN_INFO,
                         "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
                         dev_descr->dev, dev_descr->func,
                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index f39b00a46eda..1052340e6802 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -336,6 +336,7 @@ static struct of_device_id mpc85xx_pci_err_of_match[] = {
         },
         {},
 };
+MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
 
 static struct of_platform_driver mpc85xx_pci_err_driver = {
         .probe = mpc85xx_pci_err_probe,
@@ -650,6 +651,7 @@ static struct of_device_id mpc85xx_l2_err_of_match[] = {
         { .compatible = "fsl,p2020-l2-cache-controller", },
         {},
 };
+MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
 
 static struct of_platform_driver mpc85xx_l2_err_driver = {
         .probe = mpc85xx_l2_err_probe,
@@ -1126,6 +1128,7 @@ static struct of_device_id mpc85xx_mc_err_of_match[] = {
         { .compatible = "fsl,p2020-memory-controller", },
         {},
 };
+MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
 
 static struct of_platform_driver mpc85xx_mc_err_driver = {
         .probe = mpc85xx_mc_err_probe,
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 3ca36542e338..4e51fe3c1fc4 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -893,10 +893,12 @@ EXPORT_SYMBOL_GPL(gpio_sysfs_set_active_low);
 void gpio_unexport(unsigned gpio)
 {
         struct gpio_desc        *desc;
-        int                     status = -EINVAL;
+        int                     status = 0;
 
-        if (!gpio_is_valid(gpio))
+        if (!gpio_is_valid(gpio)) {
+                status = -EINVAL;
                 goto done;
+        }
 
         mutex_lock(&sysfs_lock);
 
@@ -911,7 +913,6 @@ void gpio_unexport(unsigned gpio)
                         clear_bit(FLAG_EXPORT, &desc->flags);
                         put_device(dev);
                         device_unregister(dev);
-                        status = 0;
                 } else
                         status = -ENODEV;
         }
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 83d8072066cb..ea1d57291b0e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -864,8 +864,8 @@ drm_mode_std(struct drm_connector *connector, struct edid *edid,
                 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
                                     false);
                 mode->hdisplay = 1366;
-                mode->vsync_start = mode->vsync_start - 1;
-                mode->vsync_end = mode->vsync_end - 1;
+                mode->hsync_start = mode->hsync_start - 1;
+                mode->hsync_end = mode->hsync_end - 1;
                 return mode;
         }
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index aee83fa178f6..9214119c0154 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -605,6 +605,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
                 case FBC_NOT_TILED:
                         seq_printf(m, "scanout buffer not tiled");
                         break;
+                case FBC_MULTIPLE_PIPES:
+                        seq_printf(m, "multiple pipes are enabled");
+                        break;
                 default:
                         seq_printf(m, "unknown reason");
                 }
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 92898035845d..f19ffe87af3c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -41,6 +41,8 @@
 #include <linux/vga_switcheroo.h>
 #include <linux/slab.h>
 
+extern int intel_max_stolen; /* from AGP driver */
+
 /**
  * Sets up the hardware status page for devices that need a physical address
  * in the register.
@@ -1257,7 +1259,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
                 drm_mm_put_block(compressed_fb);
         }
 
-        if (!IS_GM45(dev)) {
+        if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
                                                     4096, 0);
                 if (!compressed_llb) {
@@ -1283,8 +1285,9 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 
         intel_disable_fbc(dev);
         dev_priv->compressed_fb = compressed_fb;
-
-        if (IS_GM45(dev)) {
+        if (IS_IRONLAKE_M(dev))
+                I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
+        else if (IS_GM45(dev)) {
                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
         } else {
                 I915_WRITE(FBC_CFB_BASE, cfb_base);
@@ -1292,7 +1295,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
                 dev_priv->compressed_llb = compressed_llb;
         }
 
-        DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
+        DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
                   ll_base, size >> 20);
 }
 
@@ -1301,7 +1304,7 @@ static void i915_cleanup_compression(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         drm_mm_put_block(dev_priv->compressed_fb);
-        if (!IS_GM45(dev))
+        if (dev_priv->compressed_llb)
                 drm_mm_put_block(dev_priv->compressed_llb);
 }
 
@@ -2105,6 +2108,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         if (ret)
                 goto out_iomapfree;
 
+        if (prealloc_size > intel_max_stolen) {
+                DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
+                         prealloc_size >> 20, intel_max_stolen >> 20);
+                prealloc_size = intel_max_stolen;
+        }
+
         dev_priv->wq = create_singlethread_workqueue("i915");
         if (dev_priv->wq == NULL) {
                 DRM_ERROR("Failed to create our workqueue.\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 65d3f3e8475b..5044f653e8ea 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -93,11 +93,11 @@ static const struct intel_device_info intel_i945gm_info = {
 };
 
 static const struct intel_device_info intel_i965g_info = {
-        .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
+        .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
-        .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
+        .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
         .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
         .has_hotplug = 1,
 };
@@ -114,7 +114,7 @@ static const struct intel_device_info intel_g45_info = {
 };
 
 static const struct intel_device_info intel_gm45_info = {
-        .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
+        .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,
         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
         .has_pipe_cxsr = 1,
         .has_hotplug = 1,
@@ -134,7 +134,7 @@ static const struct intel_device_info intel_ironlake_d_info = {
 
 static const struct intel_device_info intel_ironlake_m_info = {
         .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
-        .need_gfx_hws = 1, .has_rc6 = 1,
+        .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
         .has_hotplug = 1,
 };
 
@@ -148,33 +148,33 @@ static const struct intel_device_info intel_sandybridge_m_info = {
         .has_hotplug = 1, .is_gen6 = 1,
 };
 
-static const struct pci_device_id pciidlist[] = {
-        INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
-        INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
-        INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
+static const struct pci_device_id pciidlist[] = {               /* aka */
+        INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
+        INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
+        INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
-        INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
-        INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
-        INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
-        INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
-        INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
-        INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
-        INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
-        INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
-        INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
-        INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
-        INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
-        INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
-        INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
-        INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
-        INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
-        INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
-        INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
-        INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
-        INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
-        INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
-        INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
-        INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
+        INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
+        INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
+        INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
+        INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
+        INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
+        INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
+        INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
+        INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
+        INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
+        INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
+        INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
+        INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
+        INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
+        INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
+        INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
+        INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
+        INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
+        INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
+        INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
+        INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
+        INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
@@ -340,7 +340,7 @@ int i965_reset(struct drm_device *dev, u8 flags)
         /*
          * Clear request list
          */
-        i915_gem_retire_requests(dev, &dev_priv->render_ring);
+        i915_gem_retire_requests(dev);
 
         if (need_display)
                 i915_save_display(dev);
@@ -482,7 +482,7 @@ static int i915_pm_poweroff(struct device *dev)
         return i915_drm_freeze(drm_dev);
 }
 
-const struct dev_pm_ops i915_pm_ops = {
+static const struct dev_pm_ops i915_pm_ops = {
      .suspend = i915_pm_suspend,
      .resume = i915_pm_resume,
      .freeze = i915_pm_freeze,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d147ab2f5bfc..906663b9929e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -176,7 +176,8 @@ struct drm_i915_display_funcs {
         int (*get_display_clock_speed)(struct drm_device *dev);
         int (*get_fifo_size)(struct drm_device *dev, int plane);
         void (*update_wm)(struct drm_device *dev, int planea_clock,
-                          int planeb_clock, int sr_hdisplay, int pixel_size);
+                          int planeb_clock, int sr_hdisplay, int sr_htotal,
+                          int pixel_size);
         /* clock updates for mode set */
         /* cursor updates */
         /* render clock increase/decrease */
@@ -200,6 +201,8 @@ struct intel_device_info {
         u8 need_gfx_hws : 1;
         u8 is_g4x : 1;
         u8 is_pineview : 1;
+        u8 is_broadwater : 1;
+        u8 is_crestline : 1;
         u8 is_ironlake : 1;
         u8 is_gen6 : 1;
         u8 has_fbc : 1;
@@ -215,6 +218,7 @@ enum no_fbc_reason {
         FBC_MODE_TOO_LARGE, /* mode too large for compression */
         FBC_BAD_PLANE, /* fbc not supported on plane */
         FBC_NOT_TILED, /* buffer not tiled */
+        FBC_MULTIPLE_PIPES, /* more than one pipe active */
 };
 
 enum intel_pch {
@@ -222,6 +226,8 @@ enum intel_pch {
         PCH_CPT,        /* Cougarpoint PCH */
 };
 
+#define QUIRK_PIPEA_FORCE (1<<0)
+
 struct intel_fbdev;
 
 typedef struct drm_i915_private {
@@ -285,6 +291,8 @@ typedef struct drm_i915_private {
         struct timer_list hangcheck_timer;
         int hangcheck_count;
         uint32_t last_acthd;
+        uint32_t last_instdone;
+        uint32_t last_instdone1;
 
         struct drm_mm vram;
 
@@ -337,6 +345,8 @@ typedef struct drm_i915_private {
         /* PCH chipset type */
         enum intel_pch pch_type;
 
+        unsigned long quirks;
+
         /* Register state */
         bool modeset_on_lid;
         u8 saveLBB;
@@ -542,6 +552,14 @@ typedef struct drm_i915_private {
                 struct list_head fence_list;
 
                 /**
+                 * List of objects currently pending being freed.
+                 *
+                 * These objects are no longer in use, but due to a signal
+                 * we were prevented from freeing them at the appointed time.
+                 */
+                struct list_head deferred_free_list;
+
+                /**
                  * We leave the user IRQ off as much as possible,
                  * but this means that requests will finish and never
                  * be retired once the system goes idle. Set a timer to
@@ -672,7 +690,7 @@ struct drm_i915_gem_object {
          *
          * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
          */
-        int fence_reg : 5;
+        signed int fence_reg : 5;
 
         /**
          * Used for checking the object doesn't appear more than once
@@ -708,7 +726,7 @@ struct drm_i915_gem_object {
          *
          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
          * bits with absolutely no headroom. So use 4 bits. */
-        int pin_count : 4;
+        unsigned int pin_count : 4;
 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 
         /** AGP memory structure for our GTT binding. */
@@ -738,7 +756,7 @@ struct drm_i915_gem_object {
         uint32_t stride;
 
         /** Record of address bit 17 of each page at last unbind. */
-        long *bit_17;
+        unsigned long *bit_17;
 
         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
         uint32_t agp_type;
@@ -950,8 +968,7 @@ uint32_t i915_get_gem_seqno(struct drm_device *dev,
 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
-void i915_gem_retire_requests(struct drm_device *dev,
-                 struct intel_ring_buffer *ring);
+void i915_gem_retire_requests(struct drm_device *dev);
 void i915_gem_retire_work_handler(struct work_struct *work);
 void i915_gem_clflush_object(struct drm_gem_object *obj);
 int i915_gem_object_set_domain(struct drm_gem_object *obj,
@@ -981,7 +998,7 @@ void i915_gem_free_all_phys_object(struct drm_device *dev);
 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
 void i915_gem_object_put_pages(struct drm_gem_object *obj);
 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
-void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
+int i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
 
 void i915_gem_shrinker_init(void);
 void i915_gem_shrinker_exit(void);
@@ -1041,6 +1058,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 extern void i8xx_disable_fbc(struct drm_device *dev);
 extern void g4x_disable_fbc(struct drm_device *dev);
+extern void ironlake_disable_fbc(struct drm_device *dev);
 extern void intel_disable_fbc(struct drm_device *dev);
 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
 extern bool intel_fbc_enabled(struct drm_device *dev);
@@ -1130,6 +1148,8 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 #define IS_I965G(dev)           (INTEL_INFO(dev)->is_i965g)
 #define IS_I965GM(dev)          (INTEL_INFO(dev)->is_i965gm)
+#define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
+#define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 15d2d93aaca9..4efd4fd3b340 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,7 +35,7 @@
 #include <linux/swap.h>
 #include <linux/pci.h>
 
-static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
+static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
@@ -53,6 +53,7 @@ static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
                                 struct drm_i915_gem_pwrite *args,
                                 struct drm_file *file_priv);
+static void i915_gem_free_object_tail(struct drm_gem_object *obj);
 
 static LIST_HEAD(shrink_list);
 static DEFINE_SPINLOCK(shrink_list_lock);
@@ -127,8 +128,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
                 return -ENOMEM;
 
         ret = drm_gem_handle_create(file_priv, obj, &handle);
-        drm_gem_object_handle_unreference_unlocked(obj);
-
+        drm_gem_object_unreference_unlocked(obj);
         if (ret)
                 return ret;
 
@@ -1709,9 +1709,9 @@ i915_get_gem_seqno(struct drm_device *dev,
 /**
  * This function clears the request list as sequence numbers are passed.
  */
-void
-i915_gem_retire_requests(struct drm_device *dev,
-                struct intel_ring_buffer *ring)
+static void
+i915_gem_retire_requests_ring(struct drm_device *dev,
+                              struct intel_ring_buffer *ring)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
         uint32_t seqno;
@@ -1751,6 +1751,30 @@ i915_gem_retire_requests(struct drm_device *dev,
 }
 
 void
+i915_gem_retire_requests(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+
+        if (!list_empty(&dev_priv->mm.deferred_free_list)) {
+            struct drm_i915_gem_object *obj_priv, *tmp;
+
+            /* We must be careful that during unbind() we do not
+             * accidentally infinitely recurse into retire requests.
+             * Currently:
+             *   retire -> free -> unbind -> wait -> retire_ring
+             */
+            list_for_each_entry_safe(obj_priv, tmp,
+                                     &dev_priv->mm.deferred_free_list,
+                                     list)
+                    i915_gem_free_object_tail(&obj_priv->base);
+        }
+
+        i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
+        if (HAS_BSD(dev))
+                i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
+}
+
+void
 i915_gem_retire_work_handler(struct work_struct *work)
 {
         drm_i915_private_t *dev_priv;
@@ -1761,10 +1785,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
         dev = dev_priv->dev;
 
         mutex_lock(&dev->struct_mutex);
-        i915_gem_retire_requests(dev, &dev_priv->render_ring);
-
-        if (HAS_BSD(dev))
-                i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
+        i915_gem_retire_requests(dev);
 
         if (!dev_priv->mm.suspended &&
                 (!list_empty(&dev_priv->render_ring.request_list) ||
@@ -1832,7 +1853,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
          * a separate wait queue to handle that.
          */
         if (ret == 0)
-                i915_gem_retire_requests(dev, ring);
+                i915_gem_retire_requests_ring(dev, ring);
 
         return ret;
 }
@@ -1945,11 +1966,12 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
          * before we unbind.
          */
         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
-        if (ret) {
-                if (ret != -ERESTARTSYS)
-                        DRM_ERROR("set_domain failed: %d\n", ret);
+        if (ret == -ERESTARTSYS)
                 return ret;
-        }
+        /* Continue on if we fail due to EIO, the GPU is hung so we
+         * should be safe and we need to cleanup or else we might
+         * cause memory corruption through use-after-free.
+         */
 
         BUG_ON(obj_priv->active);
 
@@ -1985,7 +2007,7 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
 
         trace_i915_gem_object_unbind(obj);
 
-        return 0;
+        return ret;
 }
 
 static struct drm_gem_object *
@@ -2107,10 +2129,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size)
         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
         struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
         for (;;) {
-                i915_gem_retire_requests(dev, render_ring);
-
-                if (HAS_BSD(dev))
-                        i915_gem_retire_requests(dev, bsd_ring);
+                i915_gem_retire_requests(dev);
 
                 /* If there's an inactive buffer available now, grab it
                  * and be done.
@@ -2583,7 +2602,10 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
         if (!IS_I965G(dev)) {
                 int ret;
 
-                i915_gem_object_flush_gpu_write_domain(obj);
+                ret = i915_gem_object_flush_gpu_write_domain(obj);
+                if (ret != 0)
+                        return ret;
+
                 ret = i915_gem_object_wait_rendering(obj);
                 if (ret != 0)
                         return ret;
@@ -2731,7 +2753,7 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
 }
 
 /** Flushes any GPU write domain for the object if it's dirty. */
-static void
+static int
 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
 {
         struct drm_device *dev = obj->dev;
@@ -2739,17 +2761,18 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 
         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
-                return;
+                return 0;
 
         /* Queue the GPU write cache flushing we need. */
         old_write_domain = obj->write_domain;
         i915_gem_flush(dev, 0, obj->write_domain);
-        (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring);
-        BUG_ON(obj->write_domain);
+        if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
+                return -ENOMEM;
 
         trace_i915_gem_object_change_domain(obj,
                                             obj->read_domains,
                                             old_write_domain);
+        return 0;
 }
 
 /** Flushes the GTT write domain for the object if it's dirty. */
@@ -2793,9 +2816,11 @@ i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
                                             old_write_domain);
 }
 
-void
+int
 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
 {
+        int ret = 0;
+
         switch (obj->write_domain) {
         case I915_GEM_DOMAIN_GTT:
                 i915_gem_object_flush_gtt_write_domain(obj);
@@ -2804,9 +2829,11 @@ i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
                 i915_gem_object_flush_cpu_write_domain(obj);
                 break;
         default:
-                i915_gem_object_flush_gpu_write_domain(obj);
+                ret = i915_gem_object_flush_gpu_write_domain(obj);
                 break;
         }
+
+        return ret;
 }
 
 /**
@@ -2826,7 +2853,10 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
         if (obj_priv->gtt_space == NULL)
                 return -EINVAL;
 
-        i915_gem_object_flush_gpu_write_domain(obj);
+        ret = i915_gem_object_flush_gpu_write_domain(obj);
+        if (ret != 0)
+                return ret;
+
         /* Wait on any GPU rendering and flushing to occur. */
         ret = i915_gem_object_wait_rendering(obj);
         if (ret != 0)
@@ -2876,7 +2906,9 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
         if (obj_priv->gtt_space == NULL)
                 return -EINVAL;
 
-        i915_gem_object_flush_gpu_write_domain(obj);
+        ret = i915_gem_object_flush_gpu_write_domain(obj);
+        if (ret)
+                return ret;
 
         /* Wait on any GPU rendering and flushing to occur. */
         if (obj_priv->active) {
@@ -2924,7 +2956,10 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
         uint32_t old_write_domain, old_read_domains;
         int ret;
 
-        i915_gem_object_flush_gpu_write_domain(obj);
+        ret = i915_gem_object_flush_gpu_write_domain(obj);
+        if (ret)
+                return ret;
+
         /* Wait on any GPU rendering and flushing to occur. */
         ret = i915_gem_object_wait_rendering(obj);
         if (ret != 0)
@@ -3214,7 +3249,10 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
         if (offset == 0 && size == obj->size)
                 return i915_gem_object_set_to_cpu_domain(obj, 0);
 
-        i915_gem_object_flush_gpu_write_domain(obj);
+        ret = i915_gem_object_flush_gpu_write_domain(obj);
+        if (ret)
+                return ret;
+
         /* Wait on any GPU rendering and flushing to occur. */
         ret = i915_gem_object_wait_rendering(obj);
         if (ret != 0)
@@ -3645,6 +3683,7 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
         return ret;
 }
 
+
 int
 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                        struct drm_file *file_priv,
@@ -3792,7 +3831,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                                 unsigned long long total_size = 0;
                                 int num_fences = 0;
                                 for (i = 0; i < args->buffer_count; i++) {
-                                        obj_priv = object_list[i]->driver_private;
+                                        obj_priv = to_intel_bo(object_list[i]);
 
                                         total_size += object_list[i]->size;
                                         num_fences +=
@@ -4310,7 +4349,6 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
         struct drm_i915_gem_busy *args = data;
         struct drm_gem_object *obj;
         struct drm_i915_gem_object *obj_priv;
-        drm_i915_private_t *dev_priv = dev->dev_private;
 
         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
         if (obj == NULL) {
@@ -4325,10 +4363,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
          * actually unmasked, and our working set ends up being larger than
          * required.
          */
-        i915_gem_retire_requests(dev, &dev_priv->render_ring);
-
-        if (HAS_BSD(dev))
-                i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
+        i915_gem_retire_requests(dev);
 
         obj_priv = to_intel_bo(obj);
         /* Don't count being on the flushing list against the object being
@@ -4438,20 +4473,19 @@ int i915_gem_init_object(struct drm_gem_object *obj)
         return 0;
 }
 
-void i915_gem_free_object(struct drm_gem_object *obj)
+static void i915_gem_free_object_tail(struct drm_gem_object *obj)
 {
         struct drm_device *dev = obj->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
+        int ret;
 
-        trace_i915_gem_object_destroy(obj);
-
-        while (obj_priv->pin_count > 0)
-                i915_gem_object_unpin(obj);
-
-        if (obj_priv->phys_obj)
-                i915_gem_detach_phys_object(dev, obj);
-
-        i915_gem_object_unbind(obj);
+        ret = i915_gem_object_unbind(obj);
+        if (ret == -ERESTARTSYS) {
+                list_move(&obj_priv->list,
+                          &dev_priv->mm.deferred_free_list);
+                return;
+        }
 
         if (obj_priv->mmap_offset)
                 i915_gem_free_mmap_offset(obj);
@@ -4463,6 +4497,22 @@ void i915_gem_free_object(struct drm_gem_object *obj)
         kfree(obj_priv);
 }
 
+void i915_gem_free_object(struct drm_gem_object *obj)
+{
+        struct drm_device *dev = obj->dev;
+        struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
+
+        trace_i915_gem_object_destroy(obj);
+
+        while (obj_priv->pin_count > 0)
+                i915_gem_object_unpin(obj);
+
+        if (obj_priv->phys_obj)
+                i915_gem_detach_phys_object(dev, obj);
+
+        i915_gem_free_object_tail(obj);
+}
+
 /** Unbinds all inactive objects. */
 static int
 i915_gem_evict_from_inactive_list(struct drm_device *dev)
@@ -4686,9 +4736,19 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
         mutex_unlock(&dev->struct_mutex);
 
-        drm_irq_install(dev);
+        ret = drm_irq_install(dev);
+        if (ret)
+                goto cleanup_ringbuffer;
 
         return 0;
+
+cleanup_ringbuffer:
+        mutex_lock(&dev->struct_mutex);
+        i915_gem_cleanup_ringbuffer(dev);
+        dev_priv->mm.suspended = 1;
+        mutex_unlock(&dev->struct_mutex);
+
+        return ret;
 }
 
 int
@@ -4726,6 +4786,7 @@ i915_gem_load(struct drm_device *dev)
         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
+        INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
         if (HAS_BSD(dev)) {
@@ -5024,10 +5085,7 @@ rescan:
                         continue;
 
                 spin_unlock(&shrink_list_lock);
-                i915_gem_retire_requests(dev, &dev_priv->render_ring);
-
-                if (HAS_BSD(dev))
-                        i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
+                i915_gem_retire_requests(dev);
 
                 list_for_each_entry_safe(obj_priv, next_obj,
                                          &dev_priv->mm.inactive_list,
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 4b7c49d4257d..155719e4d16f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -333,8 +333,6 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                         i915_gem_release_mmap(obj);
 
                 if (ret != 0) {
-                        WARN(ret != -ERESTARTSYS,
-                             "failed to reset object for tiling switch");
                         args->tiling_mode = obj_priv->tiling_mode;
                         args->stride = obj_priv->stride;
                         goto err;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dba53d4b9fb3..85785a8844ed 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -171,10 +171,10 @@ void intel_enable_asle (struct drm_device *dev)
                 ironlake_enable_display_irq(dev_priv, DE_GSE);
         else {
                 i915_enable_pipestat(dev_priv, 1,
-                                     I915_LEGACY_BLC_EVENT_ENABLE);
+                                     PIPE_LEGACY_BLC_EVENT_ENABLE);
                 if (IS_I965G(dev))
                         i915_enable_pipestat(dev_priv, 0,
-                                             I915_LEGACY_BLC_EVENT_ENABLE);
+                                             PIPE_LEGACY_BLC_EVENT_ENABLE);
         }
 }
 
@@ -842,7 +842,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
         u32 iir, new_iir;
         u32 pipea_stats, pipeb_stats;
         u32 vblank_status;
-        u32 vblank_enable;
         int vblank = 0;
         unsigned long irqflags;
         int irq_received;
@@ -856,13 +855,10 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
         iir = I915_READ(IIR);
 
-        if (IS_I965G(dev)) {
-                vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
-                vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
-        } else {
-                vblank_status = I915_VBLANK_INTERRUPT_STATUS;
-                vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
-        }
+        if (IS_I965G(dev))
+                vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
+        else
+                vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 
         for (;;) {
                 irq_received = iir != 0;
@@ -966,8 +962,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                                 intel_finish_page_flip(dev, 1);
                 }
 
-                if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
-                    (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
+                if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
+                    (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
                     (iir & I915_ASLE_INTERRUPT))
                         opregion_asle_intr(dev);
 
@@ -1233,16 +1229,21 @@ void i915_hangcheck_elapsed(unsigned long data)
 {
         struct drm_device *dev = (struct drm_device *)data;
         drm_i915_private_t *dev_priv = dev->dev_private;
-        uint32_t acthd;
+        uint32_t acthd, instdone, instdone1;
 
         /* No reset support on this chip yet. */
         if (IS_GEN6(dev))
                 return;
 
-        if (!IS_I965G(dev))
+        if (!IS_I965G(dev)) {
                 acthd = I915_READ(ACTHD);
-        else
+                instdone = I915_READ(INSTDONE);
+                instdone1 = 0;
+        } else {
                 acthd = I915_READ(ACTHD_I965);
+                instdone = I915_READ(INSTDONE_I965);
+                instdone1 = I915_READ(INSTDONE1);
+        }
 
         /* If all work is done then ACTHD clearly hasn't advanced. */
         if (list_empty(&dev_priv->render_ring.request_list) ||
@@ -1253,21 +1254,24 @@ void i915_hangcheck_elapsed(unsigned long data)
                 return;
         }
 
-        if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
-                DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
-                i915_handle_error(dev, true);
-                return;
-        } 
+        if (dev_priv->last_acthd == acthd &&
+            dev_priv->last_instdone == instdone &&
+            dev_priv->last_instdone1 == instdone1) {
+                if (dev_priv->hangcheck_count++ > 1) {
+                        DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
+                        i915_handle_error(dev, true);
+                        return;
+                }
+        } else {
+                dev_priv->hangcheck_count = 0;
+
+                dev_priv->last_acthd = acthd;
+                dev_priv->last_instdone = instdone;
+                dev_priv->last_instdone1 = instdone1;
+        }
 
         /* Reset timer case chip hangs without another request being added */
         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
-
-        if (acthd != dev_priv->last_acthd)
-                dev_priv->hangcheck_count = 0;
-        else
-                dev_priv->hangcheck_count++;
-
-        dev_priv->last_acthd = acthd;
 }
 
 /* drm_dma.h hooks
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6d9b0288272a..281db6e5403a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -442,7 +442,7 @@
 #define GEN6_RENDER_IMR         0x20a8
 #define   GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT          (1 << 8)
 #define   GEN6_RENDER_PPGTT_PAGE_FAULT                  (1 << 7)
-#define   GEN6_RENDER TIMEOUT_COUNTER_EXPIRED           (1 << 6)
+#define   GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED           (1 << 6)
 #define   GEN6_RENDER_L3_PARITY_ERROR                   (1 << 5)
 #define   GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT     (1 << 4)
 #define   GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR       (1 << 3)
@@ -530,6 +530,21 @@
 #define DPFC_CHICKEN            0x3224
 #define   DPFC_HT_MODIFY        (1<<31)
 
+/* Framebuffer compression for Ironlake */
+#define ILK_DPFC_CB_BASE        0x43200
+#define ILK_DPFC_CONTROL        0x43208
+/* The bit 28-8 is reserved */
+#define   DPFC_RESERVED         (0x1FFFFF00)
+#define ILK_DPFC_RECOMP_CTL     0x4320c
+#define ILK_DPFC_STATUS         0x43210
+#define ILK_DPFC_FENCE_YOFF     0x43218
+#define ILK_DPFC_CHICKEN        0x43224
+#define ILK_FBC_RT_BASE         0x2128
+#define   ILK_FBC_RT_VALID      (1<<0)
+
+#define ILK_DISPLAY_CHICKEN1    0x42000
+#define   ILK_FBCQ_DIS          (1<<22)
+
 /*
  * GPIO regs
  */
@@ -595,32 +610,6 @@
 #define   DPLL_FPA01_P1_POST_DIV_MASK   0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW  0x00ff8000 /* Pineview */
 
-#define I915_FIFO_UNDERRUN_STATUS               (1UL<<31)
-#define I915_CRC_ERROR_ENABLE                   (1UL<<29)
-#define I915_CRC_DONE_ENABLE                    (1UL<<28)
-#define I915_GMBUS_EVENT_ENABLE                 (1UL<<27)
-#define I915_VSYNC_INTERRUPT_ENABLE             (1UL<<25)
-#define I915_DISPLAY_LINE_COMPARE_ENABLE        (1UL<<24)
-#define I915_DPST_EVENT_ENABLE                  (1UL<<23)
-#define I915_LEGACY_BLC_EVENT_ENABLE            (1UL<<22)
-#define I915_ODD_FIELD_INTERRUPT_ENABLE         (1UL<<21)
-#define I915_EVEN_FIELD_INTERRUPT_ENABLE        (1UL<<20)
-#define I915_START_VBLANK_INTERRUPT_ENABLE      (1UL<<18)       /* 965 or later */
-#define I915_VBLANK_INTERRUPT_ENABLE            (1UL<<17)
-#define I915_OVERLAY_UPDATED_ENABLE             (1UL<<16)
-#define I915_CRC_ERROR_INTERRUPT_STATUS         (1UL<<13)
-#define I915_CRC_DONE_INTERRUPT_STATUS          (1UL<<12)
-#define I915_GMBUS_INTERRUPT_STATUS             (1UL<<11)
-#define I915_VSYNC_INTERRUPT_STATUS             (1UL<<9)
-#define I915_DISPLAY_LINE_COMPARE_STATUS        (1UL<<8)
-#define I915_DPST_EVENT_STATUS                  (1UL<<7)
-#define I915_LEGACY_BLC_EVENT_STATUS            (1UL<<6)
-#define I915_ODD_FIELD_INTERRUPT_STATUS         (1UL<<5)
-#define I915_EVEN_FIELD_INTERRUPT_STATUS        (1UL<<4)
-#define I915_START_VBLANK_INTERRUPT_STATUS      (1UL<<2)        /* 965 or later */
-#define I915_VBLANK_INTERRUPT_STATUS            (1UL<<1)
-#define I915_OVERLAY_UPDATED_STATUS             (1UL<<0)
-
 #define SRX_INDEX               0x3c4
 #define SRX_DATA                0x3c5
 #define SR01                    1
@@ -2166,7 +2155,8 @@
 #define I830_FIFO_LINE_SIZE     32
 
 #define G4X_FIFO_SIZE           127
-#define I945_FIFO_SIZE          127 /* 945 & 965 */
+#define I965_FIFO_SIZE          512
+#define I945_FIFO_SIZE          127
 #define I915_FIFO_SIZE          95
 #define I855GM_FIFO_SIZE        127 /* In cachelines */
 #define I830_FIFO_SIZE          95
@@ -2185,6 +2175,9 @@
 #define PINEVIEW_CURSOR_DFT_WM  0
 #define PINEVIEW_CURSOR_GUARD_WM        5
 
+#define I965_CURSOR_FIFO        64
+#define I965_CURSOR_MAX_WM      32
+#define I965_CURSOR_DFT_WM      8
 
 /* define the Watermark register on Ironlake */
 #define WM0_PIPEA_ILK           0x45100
@@ -2212,6 +2205,9 @@
 #define ILK_DISPLAY_FIFO        128
 #define ILK_DISPLAY_MAXWM       64
 #define ILK_DISPLAY_DFTWM       8
+#define ILK_CURSOR_FIFO         32
+#define ILK_CURSOR_MAXWM        16
+#define ILK_CURSOR_DFTWM        8
 
 #define ILK_DISPLAY_SR_FIFO     512
 #define ILK_DISPLAY_MAX_SRWM    0x1ff
@@ -2510,6 +2506,10 @@
 #define  ILK_VSDPFD_FULL        (1<<21)
 #define ILK_DSPCLK_GATE         0x42020
 #define  ILK_DPARB_CLK_GATE     (1<<5)
+/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
+#define   ILK_CLK_FBC           (1<<7)
+#define   ILK_DPFC_DIS1         (1<<8)
+#define   ILK_DPFC_DIS2         (1<<9)
 
 #define DISP_ARB_CTL    0x45000
 #define  DISP_TILE_SURFACE_SWIZZLING    (1<<13)
@@ -2869,6 +2869,7 @@
 
 #define PCH_PP_STATUS           0xc7200
 #define PCH_PP_CONTROL          0xc7204
+#define  PANEL_UNLOCK_REGS      (0xabcd << 16)
 #define  EDP_FORCE_VDD          (1 << 3)
 #define  EDP_BLC_ENABLE         (1 << 2)
 #define  PANEL_POWER_RESET      (1 << 1)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 60a5800fba6e..6e2025274db5 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -602,7 +602,9 @@ void i915_save_display(struct drm_device *dev)
 
         /* Only save FBC state on the platform that supports FBC */
         if (I915_HAS_FBC(dev)) {
-                if (IS_GM45(dev)) {
+                if (IS_IRONLAKE_M(dev)) {
+                        dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
+                } else if (IS_GM45(dev)) {
                         dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
                 } else {
                         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
@@ -706,7 +708,10 @@ void i915_restore_display(struct drm_device *dev)
 
         /* only restore FBC info on the platform that supports FBC*/
         if (I915_HAS_FBC(dev)) {
-                if (IS_GM45(dev)) {
+                if (IS_IRONLAKE_M(dev)) {
+                        ironlake_disable_fbc(dev);
+                        I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
+                } else if (IS_GM45(dev)) {
                         g4x_disable_fbc(dev);
                         I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
                 } else {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f879589bead1..ae1718549eec 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -43,6 +43,7 @@
 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
 static void intel_update_watermarks(struct drm_device *dev);
 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
+static void intel_crtc_update_cursor(struct drm_crtc *crtc);
 
 typedef struct {
     /* given values */
@@ -323,6 +324,9 @@ struct intel_limit {
 #define IRONLAKE_DP_P1_MIN              1
 #define IRONLAKE_DP_P1_MAX              2
 
+/* FDI */
+#define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
+
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                     int target, int refclk, intel_clock_t *best_clock);
@@ -863,8 +867,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
         intel_clock_t clock;
         int max_n;
         bool found;
-        /* approximately equals target * 0.00488 */
-        int err_most = (target >> 8) + (target >> 10);
+        /* approximately equals target * 0.00585 */
+        int err_most = (target >> 8) + (target >> 9);
         found = false;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -1123,6 +1127,67 @@ static bool g4x_fbc_enabled(struct drm_device *dev)
         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 }
 
+static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_framebuffer *fb = crtc->fb;
+        struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+        struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
+                                               DPFC_CTL_PLANEB;
+        unsigned long stall_watermark = 200;
+        u32 dpfc_ctl;
+
+        dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
+        dev_priv->cfb_fence = obj_priv->fence_reg;
+        dev_priv->cfb_plane = intel_crtc->plane;
+
+        dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
+        dpfc_ctl &= DPFC_RESERVED;
+        dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
+        if (obj_priv->tiling_mode != I915_TILING_NONE) {
+                dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
+                I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
+        } else {
+                I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
+        }
+
+        I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
+        I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
+                   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
+                   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
+        I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
+        I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
+        /* enable it... */
+        I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
+                   DPFC_CTL_EN);
+
+        DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
+}
+
+void ironlake_disable_fbc(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 dpfc_ctl;
+
+        /* Disable compression */
+        dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
+        dpfc_ctl &= ~DPFC_CTL_EN;
+        I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
+        intel_wait_for_vblank(dev);
+
+        DRM_DEBUG_KMS("disabled FBC\n");
+}
+
+static bool ironlake_fbc_enabled(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+}
+
 bool intel_fbc_enabled(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1181,8 +1246,12 @@ static void intel_update_fbc(struct drm_crtc *crtc,
         struct drm_framebuffer *fb = crtc->fb;
         struct intel_framebuffer *intel_fb;
         struct drm_i915_gem_object *obj_priv;
+        struct drm_crtc *tmp_crtc;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         int plane = intel_crtc->plane;
+        int crtcs_enabled = 0;
+
+        DRM_DEBUG_KMS("\n");
 
         if (!i915_powersave)
                 return;
@@ -1200,10 +1269,21 @@ static void intel_update_fbc(struct drm_crtc *crtc,
          * If FBC is already on, we just have to verify that we can
          * keep it that way...
          * Need to disable if:
+         *   - more than one pipe is active
          *   - changing FBC params (stride, fence, mode)
          *   - new fb is too large to fit in compressed buffer
          *   - going to an unsupported config (interlace, pixel multiply, etc.)
          */
+        list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
+                if (tmp_crtc->enabled)
+                        crtcs_enabled++;
+        }
+        DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
+        if (crtcs_enabled > 1) {
+                DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
+                dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
+                goto out_disable;
+        }
         if (intel_fb->obj->size > dev_priv->cfb_size) {
                 DRM_DEBUG_KMS("framebuffer too large, disabling "
                                 "compression\n");
@@ -1256,7 +1336,7 @@ out_disable:
         }
 }
 
-static int
+int
 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
 {
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
@@ -1265,7 +1345,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
 
         switch (obj_priv->tiling_mode) {
         case I915_TILING_NONE:
-                alignment = 64 * 1024;
+                if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+                        alignment = 128 * 1024;
+                else if (IS_I965G(dev))
+                        alignment = 4 * 1024;
+                else
+                        alignment = 64 * 1024;
                 break;
         case I915_TILING_X:
                 /* pin() will align the object as required by fence */
@@ -1540,6 +1625,15 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
         u32 temp, tries = 0;
 
+        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+           for train result */
+        temp = I915_READ(fdi_rx_imr_reg);
+        temp &= ~FDI_RX_SYMBOL_LOCK;
+        temp &= ~FDI_RX_BIT_LOCK;
+        I915_WRITE(fdi_rx_imr_reg, temp);
+        I915_READ(fdi_rx_imr_reg);
+        udelay(150);
+
         /* enable CPU FDI TX and PCH FDI RX */
         temp = I915_READ(fdi_tx_reg);
         temp |= FDI_TX_ENABLE;
@@ -1557,16 +1651,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
         I915_READ(fdi_rx_reg);
         udelay(150);
 
-        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
-           for train result */
-        temp = I915_READ(fdi_rx_imr_reg);
-        temp &= ~FDI_RX_SYMBOL_LOCK;
-        temp &= ~FDI_RX_BIT_LOCK;
-        I915_WRITE(fdi_rx_imr_reg, temp);
-        I915_READ(fdi_rx_imr_reg);
-        udelay(150);
-
-        for (;;) {
+        for (tries = 0; tries < 5; tries++) {
                 temp = I915_READ(fdi_rx_iir_reg);
                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 
@@ -1576,14 +1661,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
                                    temp | FDI_RX_BIT_LOCK);
                         break;
                 }
-
-                tries++;
-
-                if (tries > 5) {
-                        DRM_DEBUG_KMS("FDI train 1 fail!\n");
-                        break;
-                }
         }
+        if (tries == 5)
+                DRM_DEBUG_KMS("FDI train 1 fail!\n");
 
         /* Train 2 */
         temp = I915_READ(fdi_tx_reg);
@@ -1599,7 +1679,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 
         tries = 0;
 
-        for (;;) {
+        for (tries = 0; tries < 5; tries++) {
                 temp = I915_READ(fdi_rx_iir_reg);
                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 
@@ -1609,14 +1689,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
                         DRM_DEBUG_KMS("FDI train 2 done.\n");
                         break;
                 }
-
-                tries++;
-
-                if (tries > 5) {
-                        DRM_DEBUG_KMS("FDI train 2 fail!\n");
-                        break;
-                }
         }
+        if (tries == 5)
+                DRM_DEBUG_KMS("FDI train 2 fail!\n");
 
         DRM_DEBUG_KMS("FDI train done\n");
 }
@@ -1641,6 +1716,15 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
         u32 temp, i;
 
+        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+           for train result */
+        temp = I915_READ(fdi_rx_imr_reg);
+        temp &= ~FDI_RX_SYMBOL_LOCK;
+        temp &= ~FDI_RX_BIT_LOCK;
+        I915_WRITE(fdi_rx_imr_reg, temp);
+        I915_READ(fdi_rx_imr_reg);
+        udelay(150);
+
         /* enable CPU FDI TX and PCH FDI RX */
         temp = I915_READ(fdi_tx_reg);
         temp |= FDI_TX_ENABLE;
@@ -1666,15 +1750,6 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
         I915_READ(fdi_rx_reg);
         udelay(150);
 
-        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
-           for train result */
-        temp = I915_READ(fdi_rx_imr_reg);
-        temp &= ~FDI_RX_SYMBOL_LOCK;
-        temp &= ~FDI_RX_BIT_LOCK;
-        I915_WRITE(fdi_rx_imr_reg, temp);
-        I915_READ(fdi_rx_imr_reg);
-        udelay(150);
-
         for (i = 0; i < 4; i++ ) {
                 temp = I915_READ(fdi_tx_reg);
                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -1829,7 +1904,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                 }
 
                 /* Enable panel fitting for LVDS */
-                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
+                    || HAS_eDP || intel_pch_has_edp(crtc)) {
                         temp = I915_READ(pf_ctl_reg);
                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
 
@@ -1924,9 +2000,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                                 reg = I915_READ(trans_dp_ctl);
                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
                                 reg = TRANS_DP_OUTPUT_ENABLE |
-                                      TRANS_DP_ENH_FRAMING |
-                                      TRANS_DP_VSYNC_ACTIVE_HIGH |
-                                      TRANS_DP_HSYNC_ACTIVE_HIGH;
+                                      TRANS_DP_ENH_FRAMING;
+
+                                if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
+                                      reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
+                                if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
+                                      reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
                                 switch (intel_trans_dp_port_sel(crtc)) {
                                 case PCH_DP_B:
@@ -1966,6 +2045,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                 intel_crtc_load_lut(crtc);
 
+                intel_update_fbc(crtc, &crtc->mode);
+
         break;
         case DRM_MODE_DPMS_OFF:
                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
@@ -1980,6 +2061,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                         I915_READ(dspbase_reg);
                 }
 
+                if (dev_priv->cfb_plane == plane &&
+                    dev_priv->display.disable_fbc)
+                        dev_priv->display.disable_fbc(dev);
+
                 i915_disable_vga(dev);
 
                 /* disable cpu pipe, disable after all planes disabled */
@@ -2256,6 +2341,11 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                         intel_wait_for_vblank(dev);
                 }
 
+                /* Don't disable pipe A or pipe A PLLs if needed */
+                if (pipeconf_reg == PIPEACONF &&
+                    (dev_priv->quirks & QUIRK_PIPEA_FORCE))
+                        goto skip_pipe_off;
+
                 /* Next, disable display pipes */
                 temp = I915_READ(pipeconf_reg);
                 if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -2271,7 +2361,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
                         I915_READ(dpll_reg);
                 }
-
+        skip_pipe_off:
                 /* Wait for the clocks to turn off. */
                 udelay(150);
                 break;
@@ -2354,11 +2444,9 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
         struct drm_device *dev = crtc->dev;
         if (HAS_PCH_SPLIT(dev)) {
                 /* FDI link clock is fixed at 2.7G */
-                if (mode->clock * 3 > 27000 * 4)
-                        return MODE_CLOCK_HIGH;
+                if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
+                        return false;
         }
-
-        drm_mode_set_crtcinfo(adjusted_mode, 0);
         return true;
 }
 
@@ -2539,6 +2627,20 @@ static struct intel_watermark_params g4x_wm_info = {
         2,
         G4X_FIFO_LINE_SIZE,
 };
+static struct intel_watermark_params g4x_cursor_wm_info = {
+        I965_CURSOR_FIFO,
+        I965_CURSOR_MAX_WM,
+        I965_CURSOR_DFT_WM,
+        2,
+        G4X_FIFO_LINE_SIZE,
+};
+static struct intel_watermark_params i965_cursor_wm_info = {
+        I965_CURSOR_FIFO,
+        I965_CURSOR_MAX_WM,
+        I965_CURSOR_DFT_WM,
+        2,
+        I915_FIFO_LINE_SIZE,
+};
 static struct intel_watermark_params i945_wm_info = {
         I945_FIFO_SIZE,
         I915_MAX_WM,
@@ -2576,6 +2678,14 @@ static struct intel_watermark_params ironlake_display_wm_info = {
         ILK_FIFO_LINE_SIZE
 };
 
+static struct intel_watermark_params ironlake_cursor_wm_info = {
+        ILK_CURSOR_FIFO,
+        ILK_CURSOR_MAXWM,
+        ILK_CURSOR_DFTWM,
+        2,
+        ILK_FIFO_LINE_SIZE
+};
+
 static struct intel_watermark_params ironlake_display_srwm_info = {
         ILK_DISPLAY_SR_FIFO,
         ILK_DISPLAY_MAX_SRWM,
@@ -2625,7 +2735,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
          */
         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
                 1000;
-        entries_required /= wm->cacheline_size;
+        entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 
         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
 
@@ -2636,8 +2746,14 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
         /* Don't promote wm_size to unsigned... */
         if (wm_size > (long)wm->max_wm)
                 wm_size = wm->max_wm;
-        if (wm_size <= 0)
+        if (wm_size <= 0) {
                 wm_size = wm->default_wm;
+                DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
+                          " entries required = %ld, available = %lu.\n",
+                          entries_required + wm->guard_size,
+                          wm->fifo_size);
+        }
+
         return wm_size;
 }
 
@@ -2746,11 +2862,9 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
         uint32_t dsparb = I915_READ(DSPARB);
         int size;
 
-        if (plane == 0)
-                size = dsparb & 0x7f;
-        else
-                size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
-                        (dsparb & 0x7f);
+        size = dsparb & 0x7f;
+        if (plane)
+                size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 
         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
                         plane ? "B" : "A", size);
@@ -2764,11 +2878,9 @@ static int i85x_get_fifo_size(struct drm_device *dev, int plane)
         uint32_t dsparb = I915_READ(DSPARB);
         int size;
 
-        if (plane == 0)
-                size = dsparb & 0x1ff;
-        else
-                size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
-                        (dsparb & 0x1ff);
+        size = dsparb & 0x1ff;
+        if (plane)
+                size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
         size >>= 1; /* Convert to cachelines */
 
         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
@@ -2809,7 +2921,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
 }
 
 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
-                          int planeb_clock, int sr_hdisplay, int pixel_size)
+                          int planeb_clock, int sr_hdisplay, int unused,
+                          int pixel_size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 reg;
@@ -2874,7 +2987,8 @@ static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
 }
 
 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
-                          int planeb_clock, int sr_hdisplay, int pixel_size)
+                          int planeb_clock, int sr_hdisplay, int sr_htotal,
+                          int pixel_size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         int total_size, cacheline_size;
@@ -2898,12 +3012,12 @@ static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
          */
         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
                 1000;
-        entries_required /= G4X_FIFO_LINE_SIZE;
+        entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
         planea_wm = entries_required + planea_params.guard_size;
 
         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
                 1000;
-        entries_required /= G4X_FIFO_LINE_SIZE;
+        entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
         planeb_wm = entries_required + planeb_params.guard_size;
 
         cursora_wm = cursorb_wm = 16;
@@ -2917,13 +3031,24 @@ static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
                 static const int sr_latency_ns = 12000;
 
                 sr_clock = planea_clock ? planea_clock : planeb_clock;
-                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+                line_time_us = ((sr_htotal * 1000) / sr_clock);
 
                 /* Use ns/us then divide to preserve precision */
-                sr_entries = (((sr_latency_ns / line_time_us) + 1) *
-                              pixel_size * sr_hdisplay) / 1000;
-                sr_entries = roundup(sr_entries / cacheline_size, 1);
-                DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
+                sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
+                              pixel_size * sr_hdisplay;
+                sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
+
+                entries_required = (((sr_latency_ns / line_time_us) +
+                                     1000) / 1000) * pixel_size * 64;
+                entries_required = DIV_ROUND_UP(entries_required,
+                                           g4x_cursor_wm_info.cacheline_size);
+                cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
+
+                if (cursor_sr > g4x_cursor_wm_info.max_wm)
+                        cursor_sr = g4x_cursor_wm_info.max_wm;
+                DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
+                              "cursor %d\n", sr_entries, cursor_sr);
+
                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
         } else {
                 /* Turn off self refresh if both pipes are enabled */
@@ -2948,11 +3073,13 @@ static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
 }
 
 static void i965_update_wm(struct drm_device *dev, int planea_clock,
-                           int planeb_clock, int sr_hdisplay, int pixel_size)
+                           int planeb_clock, int sr_hdisplay, int sr_htotal,
+                           int pixel_size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long line_time_us;
         int sr_clock, sr_entries, srwm = 1;
+        int cursor_sr = 16;
 
         /* Calc sr entries for one plane configs */
         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
@@ -2960,17 +3087,31 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
                 static const int sr_latency_ns = 12000;
 
                 sr_clock = planea_clock ? planea_clock : planeb_clock;
-                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+                line_time_us = ((sr_htotal * 1000) / sr_clock);
 
                 /* Use ns/us then divide to preserve precision */
-                sr_entries = (((sr_latency_ns / line_time_us) + 1) *
-                              pixel_size * sr_hdisplay) / 1000;
-                sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
+                sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
+                              pixel_size * sr_hdisplay;
+                sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
-                srwm = I945_FIFO_SIZE - sr_entries;
+                srwm = I965_FIFO_SIZE - sr_entries;
                 if (srwm < 0)
                         srwm = 1;
-                srwm &= 0x3f;
+                srwm &= 0x1ff;
+
+                sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
+                             pixel_size * 64;
+                sr_entries = DIV_ROUND_UP(sr_entries,
+                                          i965_cursor_wm_info.cacheline_size);
+                cursor_sr = i965_cursor_wm_info.fifo_size -
+                            (sr_entries + i965_cursor_wm_info.guard_size);
+
+                if (cursor_sr > i965_cursor_wm_info.max_wm)
+                        cursor_sr = i965_cursor_wm_info.max_wm;
+
+                DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
+                              "cursor %d\n", srwm, cursor_sr);
+
                 if (IS_I965GM(dev))
                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
         } else {
@@ -2987,10 +3128,13 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
                    (8 << 0));
         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
+        /* update cursor SR watermark */
+        I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 
 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
-                           int planeb_clock, int sr_hdisplay, int pixel_size)
+                           int planeb_clock, int sr_hdisplay, int sr_htotal,
+                           int pixel_size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         uint32_t fwater_lo;
@@ -3035,12 +3179,12 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
                 static const int sr_latency_ns = 6000;
 
                 sr_clock = planea_clock ? planea_clock : planeb_clock;
-                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+                line_time_us = ((sr_htotal * 1000) / sr_clock);
 
                 /* Use ns/us then divide to preserve precision */
-                sr_entries = (((sr_latency_ns / line_time_us) + 1) *
-                              pixel_size * sr_hdisplay) / 1000;
-                sr_entries = roundup(sr_entries / cacheline_size, 1);
+                sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
+                              pixel_size * sr_hdisplay;
+                sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
                 srwm = total_size - sr_entries;
                 if (srwm < 0)
@@ -3078,7 +3222,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
 }
 
 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
-                           int unused2, int pixel_size)
+                           int unused2, int unused3, int pixel_size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
@@ -3096,9 +3240,11 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
 }
 
 #define ILK_LP0_PLANE_LATENCY           700
+#define ILK_LP0_CURSOR_LATENCY          1300
 
 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
-                       int planeb_clock, int sr_hdisplay, int pixel_size)
+                       int planeb_clock, int sr_hdisplay, int sr_htotal,
+                       int pixel_size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
@@ -3106,20 +3252,48 @@ static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
         unsigned long line_time_us;
         int sr_clock, entries_required;
         u32 reg_value;
+        int line_count;
+        int planea_htotal = 0, planeb_htotal = 0;
+        struct drm_crtc *crtc;
+        struct intel_crtc *intel_crtc;
+
+        /* Need htotal for all active display plane */
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                intel_crtc = to_intel_crtc(crtc);
+                if (crtc->enabled) {
+                        if (intel_crtc->plane == 0)
+                                planea_htotal = crtc->mode.htotal;
+                        else
+                                planeb_htotal = crtc->mode.htotal;
+                }
+        }
 
         /* Calculate and update the watermark for plane A */
         if (planea_clock) {
                 entries_required = ((planea_clock / 1000) * pixel_size *
                                      ILK_LP0_PLANE_LATENCY) / 1000;
                 entries_required = DIV_ROUND_UP(entries_required,
-                                   ironlake_display_wm_info.cacheline_size);
+                                                ironlake_display_wm_info.cacheline_size);
                 planea_wm = entries_required +
                             ironlake_display_wm_info.guard_size;
 
                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
                         planea_wm = ironlake_display_wm_info.max_wm;
 
-                cursora_wm = 16;
+                /* Use the large buffer method to calculate cursor watermark */
+                line_time_us = (planea_htotal * 1000) / planea_clock;
+
+                /* Use ns/us then divide to preserve precision */
+                line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
+
+                /* calculate the cursor watermark for cursor A */
+                entries_required = line_count * 64 * pixel_size;
+                entries_required = DIV_ROUND_UP(entries_required,
+                                                ironlake_cursor_wm_info.cacheline_size);
+                cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
+                if (cursora_wm > ironlake_cursor_wm_info.max_wm)
+                        cursora_wm = ironlake_cursor_wm_info.max_wm;
+
                 reg_value = I915_READ(WM0_PIPEA_ILK);
                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
@@ -3133,14 +3307,27 @@ static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
                 entries_required = ((planeb_clock / 1000) * pixel_size *
                                      ILK_LP0_PLANE_LATENCY) / 1000;
                 entries_required = DIV_ROUND_UP(entries_required,
-                                   ironlake_display_wm_info.cacheline_size);
+                                                ironlake_display_wm_info.cacheline_size);
                 planeb_wm = entries_required +
                             ironlake_display_wm_info.guard_size;
 
                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
                         planeb_wm = ironlake_display_wm_info.max_wm;
 
-                cursorb_wm = 16;
+                /* Use the large buffer method to calculate cursor watermark */
+                line_time_us = (planeb_htotal * 1000) / planeb_clock;
+
+                /* Use ns/us then divide to preserve precision */
+                line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
+
+                /* calculate the cursor watermark for cursor B */
+                entries_required = line_count * 64 * pixel_size;
+                entries_required = DIV_ROUND_UP(entries_required,
+                                                ironlake_cursor_wm_info.cacheline_size);
+                cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
+                if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
+                        cursorb_wm = ironlake_cursor_wm_info.max_wm;
+
                 reg_value = I915_READ(WM0_PIPEB_ILK);
                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
@@ -3155,12 +3342,12 @@ static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
          * display plane is used.
          */
         if (!planea_clock || !planeb_clock) {
-                int line_count;
+
                 /* Read the self-refresh latency. The unit is 0.5us */
                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
 
                 sr_clock = planea_clock ? planea_clock : planeb_clock;
-                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+                line_time_us = ((sr_htotal * 1000) / sr_clock);
 
                 /* Use ns/us then divide to preserve precision */
                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
@@ -3169,14 +3356,14 @@ static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
                 /* calculate the self-refresh watermark for display plane */
                 entries_required = line_count * sr_hdisplay * pixel_size;
                 entries_required = DIV_ROUND_UP(entries_required,
-                                   ironlake_display_srwm_info.cacheline_size);
+                                                ironlake_display_srwm_info.cacheline_size);
                 sr_wm = entries_required +
                         ironlake_display_srwm_info.guard_size;
 
                 /* calculate the self-refresh watermark for display cursor */
                 entries_required = line_count * pixel_size * 64;
                 entries_required = DIV_ROUND_UP(entries_required,
-                                   ironlake_cursor_srwm_info.cacheline_size);
+                                                ironlake_cursor_srwm_info.cacheline_size);
                 cursor_wm = entries_required +
                             ironlake_cursor_srwm_info.guard_size;
 
@@ -3220,6 +3407,7 @@ static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
  *       bytes per pixel
  *   where
  *     line time = htotal / dotclock
+ *     surface width = hdisplay for normal plane and 64 for cursor
  *   and latency is assumed to be high, as above.
  *
  * The final value programmed to the register should always be rounded up,
@@ -3236,6 +3424,7 @@ static void intel_update_watermarks(struct drm_device *dev)
         int sr_hdisplay = 0;
         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
         int enabled = 0, pixel_size = 0;
+        int sr_htotal = 0;
 
         if (!dev_priv->display.update_wm)
                 return;
@@ -3256,6 +3445,7 @@ static void intel_update_watermarks(struct drm_device *dev)
                         }
                         sr_hdisplay = crtc->mode.hdisplay;
                         sr_clock = crtc->mode.clock;
+                        sr_htotal = crtc->mode.htotal;
                         if (crtc->fb)
                                 pixel_size = crtc->fb->bits_per_pixel / 8;
                         else
@@ -3267,7 +3457,7 @@ static void intel_update_watermarks(struct drm_device *dev)
                 return;
 
         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
-                                    sr_hdisplay, pixel_size);
+                                    sr_hdisplay, sr_htotal, pixel_size);
 }
 
 static int intel_crtc_mode_set(struct drm_crtc *crtc,
@@ -3386,6 +3576,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 return -EINVAL;
         }
 
+        /* Ensure that the cursor is valid for the new mode before changing... */
+        intel_crtc_update_cursor(crtc);
+
         if (is_lvds && dev_priv->lvds_downclock_avail) {
                 has_reduced_clock = limit->find_pll(limit, crtc,
                                                             dev_priv->lvds_downclock,
@@ -3452,7 +3645,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                                 temp |= PIPE_8BPC;
                         else
                                 temp |= PIPE_6BPC;
-                } else if (is_edp) {
+                } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
                         switch (dev_priv->edp_bpp/3) {
                         case 8:
                                 temp |= PIPE_8BPC;
@@ -3695,6 +3888,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 udelay(150);
         }
 
+        if (HAS_PCH_SPLIT(dev)) {
+                pipeconf &= ~PIPE_ENABLE_DITHER;
+                pipeconf &= ~PIPE_DITHER_TYPE_MASK;
+        }
+
         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
          * This is an exception to the general rule that mode_set doesn't turn
          * things on.
@@ -3741,11 +3939,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                                 } else
                                         lvds |= LVDS_ENABLE_DITHER;
                         } else {
-                                if (HAS_PCH_SPLIT(dev)) {
-                                        pipeconf &= ~PIPE_ENABLE_DITHER;
-                                        pipeconf &= ~PIPE_DITHER_TYPE_MASK;
-                                } else
+                                if (!HAS_PCH_SPLIT(dev)) {
                                         lvds &= ~LVDS_ENABLE_DITHER;
+                                }
                         }
                 }
                 I915_WRITE(lvds_reg, lvds);
@@ -3921,6 +4117,85 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
         }
 }
 
+/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
+static void intel_crtc_update_cursor(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int pipe = intel_crtc->pipe;
+        int x = intel_crtc->cursor_x;
+        int y = intel_crtc->cursor_y;
+        uint32_t base, pos;
+        bool visible;
+
+        pos = 0;
+
+        if (crtc->fb) {
+                base = intel_crtc->cursor_addr;
+                if (x > (int) crtc->fb->width)
+                        base = 0;
+
+                if (y > (int) crtc->fb->height)
+                        base = 0;
+        } else
+                base = 0;
+
+        if (x < 0) {
+                if (x + intel_crtc->cursor_width < 0)
+                        base = 0;
+
+                pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+                x = -x;
+        }
+        pos |= x << CURSOR_X_SHIFT;
+
+        if (y < 0) {
+                if (y + intel_crtc->cursor_height < 0)
+                        base = 0;
+
+                pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+                y = -y;
+        }
+        pos |= y << CURSOR_Y_SHIFT;
+
+        visible = base != 0;
+        if (!visible && !intel_crtc->cursor_visble)
+                return;
+
+        I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
+        if (intel_crtc->cursor_visble != visible) {
+                uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
+                if (base) {
+                        /* Hooray for CUR*CNTR differences */
+                        if (IS_MOBILE(dev) || IS_I9XX(dev)) {
+                                cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
+                                cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
+                                cntl |= pipe << 28; /* Connect to correct pipe */
+                        } else {
+                                cntl &= ~(CURSOR_FORMAT_MASK);
+                                cntl |= CURSOR_ENABLE;
+                                cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
+                        }
+                } else {
+                        if (IS_MOBILE(dev) || IS_I9XX(dev)) {
+                                cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
+                                cntl |= CURSOR_MODE_DISABLE;
+                        } else {
+                                cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
+                        }
+                }
+                I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
+
+                intel_crtc->cursor_visble = visible;
+        }
+        /* and commit changes on next vblank */
+        I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
+
+        if (visible)
+                intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
+}
+
 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
                                  struct drm_file *file_priv,
                                  uint32_t handle,
@@ -3931,11 +4206,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct drm_gem_object *bo;
         struct drm_i915_gem_object *obj_priv;
-        int pipe = intel_crtc->pipe;
-        uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
-        uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
-        uint32_t temp = I915_READ(control);
-        size_t addr;
+        uint32_t addr;
         int ret;
 
         DRM_DEBUG_KMS("\n");
@@ -3943,12 +4214,6 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
         /* if we want to turn off the cursor ignore width and height */
         if (!handle) {
                 DRM_DEBUG_KMS("cursor off\n");
-                if (IS_MOBILE(dev) || IS_I9XX(dev)) {
-                        temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
-                        temp |= CURSOR_MODE_DISABLE;
-                } else {
-                        temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
-                }
                 addr = 0;
                 bo = NULL;
                 mutex_lock(&dev->struct_mutex);
@@ -3990,7 +4255,8 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
 
                 addr = obj_priv->gtt_offset;
         } else {
-                ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
+                ret = i915_gem_attach_phys_object(dev, bo,
+                                                  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
                 if (ret) {
                         DRM_ERROR("failed to attach phys object\n");
                         goto fail_locked;
@@ -4001,21 +4267,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
         if (!IS_I9XX(dev))
                 I915_WRITE(CURSIZE, (height << 12) | width);
 
-        /* Hooray for CUR*CNTR differences */
-        if (IS_MOBILE(dev) || IS_I9XX(dev)) {
-                temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
-                temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
-                temp |= (pipe << 28); /* Connect to correct pipe */
-        } else {
-                temp &= ~(CURSOR_FORMAT_MASK);
-                temp |= CURSOR_ENABLE;
-                temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
-        }
-
  finish:
-        I915_WRITE(control, temp);
-        I915_WRITE(base, addr);
-
         if (intel_crtc->cursor_bo) {
                 if (dev_priv->info->cursor_needs_physical) {
                         if (intel_crtc->cursor_bo != bo)
@@ -4029,6 +4281,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         intel_crtc->cursor_addr = addr;
         intel_crtc->cursor_bo = bo;
+        intel_crtc->cursor_width = width;
+        intel_crtc->cursor_height = height;
+
+        intel_crtc_update_cursor(crtc);
 
         return 0;
 fail_unpin:
@@ -4042,34 +4298,12 @@ fail:
 
 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 {
-        struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        struct intel_framebuffer *intel_fb;
-        int pipe = intel_crtc->pipe;
-        uint32_t temp = 0;
-        uint32_t adder;
-
-        if (crtc->fb) {
-                intel_fb = to_intel_framebuffer(crtc->fb);
-                intel_mark_busy(dev, intel_fb->obj);
-        }
-
-        if (x < 0) {
-                temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
-                x = -x;
-        }
-        if (y < 0) {
-                temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
-                y = -y;
-        }
 
-        temp |= x << CURSOR_X_SHIFT;
-        temp |= y << CURSOR_Y_SHIFT;
+        intel_crtc->cursor_x = x;
+        intel_crtc->cursor_y = y;
 
-        adder = intel_crtc->cursor_addr;
-        I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
-        I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
+        intel_crtc_update_cursor(crtc);
 
         return 0;
 }
@@ -4413,7 +4647,8 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
 
                 /* Unlock panel regs */
-                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                           PANEL_UNLOCK_REGS);
 
                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
                 I915_WRITE(dpll_reg, dpll);
@@ -4456,7 +4691,8 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
 
                 /* Unlock panel regs */
-                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                           PANEL_UNLOCK_REGS);
 
                 dpll |= DISPLAY_RATE_SELECT_FPA1;
                 I915_WRITE(dpll_reg, dpll);
@@ -4698,7 +4934,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         struct drm_gem_object *obj;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_unpin_work *work;
-        unsigned long flags;
+        unsigned long flags, offset;
         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
         int ret, pipesrc;
         u32 flip_mask;
@@ -4730,27 +4966,22 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
         mutex_lock(&dev->struct_mutex);
         ret = intel_pin_and_fence_fb_obj(dev, obj);
-        if (ret != 0) {
-                mutex_unlock(&dev->struct_mutex);
-
-                spin_lock_irqsave(&dev->event_lock, flags);
-                intel_crtc->unpin_work = NULL;
-                spin_unlock_irqrestore(&dev->event_lock, flags);
-
-                kfree(work);
-
-                DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
-                                 to_intel_bo(obj));
-                return ret;
-        }
+        if (ret)
+                goto cleanup_work;
 
         /* Reference the objects for the scheduled work. */
         drm_gem_object_reference(work->old_fb_obj);
         drm_gem_object_reference(obj);
 
         crtc->fb = fb;
-        i915_gem_object_flush_write_domain(obj);
-        drm_vblank_get(dev, intel_crtc->pipe);
+        ret = i915_gem_object_flush_write_domain(obj);
+        if (ret)
+                goto cleanup_objs;
+
+        ret = drm_vblank_get(dev, intel_crtc->pipe);
+        if (ret)
+                goto cleanup_objs;
+
         obj_priv = to_intel_bo(obj);
         atomic_inc(&obj_priv->pending_flip);
         work->pending_flip_obj = obj;
@@ -4765,19 +4996,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                 while (I915_READ(ISR) & flip_mask)
                         ;
 
+        /* Offset into the new buffer for cases of shared fbs between CRTCs */
+        offset = obj_priv->gtt_offset;
+        offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
+
         BEGIN_LP_RING(4);
         if (IS_I965G(dev)) {
                 OUT_RING(MI_DISPLAY_FLIP |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
+                OUT_RING(offset | obj_priv->tiling_mode);
                 pipesrc = I915_READ(pipesrc_reg); 
                 OUT_RING(pipesrc & 0x0fff0fff);
         } else {
                 OUT_RING(MI_DISPLAY_FLIP_I915 |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(obj_priv->gtt_offset);
+                OUT_RING(offset);
                 OUT_RING(MI_NOOP);
         }
         ADVANCE_LP_RING();
@@ -4787,6 +5022,20 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         trace_i915_flip_request(intel_crtc->plane, obj);
 
         return 0;
+
+cleanup_objs:
+        drm_gem_object_unreference(work->old_fb_obj);
+        drm_gem_object_unreference(obj);
+cleanup_work:
+        mutex_unlock(&dev->struct_mutex);
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+        intel_crtc->unpin_work = NULL;
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+
+        kfree(work);
+
+        return ret;
 }
 
 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
@@ -4912,19 +5161,26 @@ static void intel_setup_outputs(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_encoder *encoder;
+        bool dpd_is_edp = false;
 
-        intel_crt_init(dev);
-
-        /* Set up integrated LVDS */
         if (IS_MOBILE(dev) && !IS_I830(dev))
                 intel_lvds_init(dev);
 
         if (HAS_PCH_SPLIT(dev)) {
-                int found;
+                dpd_is_edp = intel_dpd_is_edp(dev);
 
                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
                         intel_dp_init(dev, DP_A);
 
+                if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
+                        intel_dp_init(dev, PCH_DP_D);
+        }
+
+        intel_crt_init(dev);
+
+        if (HAS_PCH_SPLIT(dev)) {
+                int found;
+
                 if (I915_READ(HDMIB) & PORT_DETECTED) {
                         /* PCH SDVOB multiplex with HDMIB */
                         found = intel_sdvo_init(dev, PCH_SDVOB);
@@ -4943,7 +5199,7 @@ static void intel_setup_outputs(struct drm_device *dev)
                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
                         intel_dp_init(dev, PCH_DP_C);
 
-                if (I915_READ(PCH_DP_D) & DP_DETECTED)
+                if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
                         intel_dp_init(dev, PCH_DP_D);
 
         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
@@ -5352,6 +5608,26 @@ void intel_init_clock_gating(struct drm_device *dev)
                                         (I915_READ(DISP_ARB_CTL) |
                                                 DISP_FBC_WM_DIS));
                 }
+                /*
+                 * Based on the document from hardware guys the following bits
+                 * should be set unconditionally in order to enable FBC.
+                 * The bit 22 of 0x42000
+                 * The bit 22 of 0x42004
+                 * The bit 7,8,9 of 0x42020.
+                 */
+                if (IS_IRONLAKE_M(dev)) {
+                        I915_WRITE(ILK_DISPLAY_CHICKEN1,
+                                   I915_READ(ILK_DISPLAY_CHICKEN1) |
+                                   ILK_FBCQ_DIS);
+                        I915_WRITE(ILK_DISPLAY_CHICKEN2,
+                                   I915_READ(ILK_DISPLAY_CHICKEN2) |
+                                   ILK_DPARB_GATE);
+                        I915_WRITE(ILK_DSPCLK_GATE,
+                                   I915_READ(ILK_DSPCLK_GATE) |
+                                   ILK_DPFC_DIS1 |
+                                   ILK_DPFC_DIS2 |
+                                   ILK_CLK_FBC);
+                }
                 return;
         } else if (IS_G4X(dev)) {
                 uint32_t dspclk_gate;
@@ -5430,7 +5706,11 @@ static void intel_init_display(struct drm_device *dev)
                 dev_priv->display.dpms = i9xx_crtc_dpms;
 
         if (I915_HAS_FBC(dev)) {
-                if (IS_GM45(dev)) {
+                if (IS_IRONLAKE_M(dev)) {
+                        dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
+                        dev_priv->display.enable_fbc = ironlake_enable_fbc;
+                        dev_priv->display.disable_fbc = ironlake_disable_fbc;
+                } else if (IS_GM45(dev)) {
                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
                         dev_priv->display.enable_fbc = g4x_enable_fbc;
                         dev_priv->display.disable_fbc = g4x_disable_fbc;
@@ -5511,6 +5791,66 @@ static void intel_init_display(struct drm_device *dev)
         }
 }
 
+/*
+ * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
+ * resume, or other times.  This quirk makes sure that's the case for
+ * affected systems.
+ */
+static void quirk_pipea_force (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        dev_priv->quirks |= QUIRK_PIPEA_FORCE;
+        DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
+}
+
+struct intel_quirk {
+        int device;
+        int subsystem_vendor;
+        int subsystem_device;
+        void (*hook)(struct drm_device *dev);
+};
+
+struct intel_quirk intel_quirks[] = {
+        /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
+        { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
+        /* HP Mini needs pipe A force quirk (LP: #322104) */
+        { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
+
+        /* Thinkpad R31 needs pipe A force quirk */
+        { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
+        /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
+        { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
+
+        /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
+        { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
+        /* ThinkPad X40 needs pipe A force quirk */
+
+        /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
+        { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
+
+        /* 855 & before need to leave pipe A & dpll A up */
+        { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+        { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+};
+
+static void intel_init_quirks(struct drm_device *dev)
+{
+        struct pci_dev *d = dev->pdev;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
+                struct intel_quirk *q = &intel_quirks[i];
+
+                if (d->device == q->device &&
+                    (d->subsystem_vendor == q->subsystem_vendor ||
+                     q->subsystem_vendor == PCI_ANY_ID) &&
+                    (d->subsystem_device == q->subsystem_device ||
+                     q->subsystem_device == PCI_ANY_ID))
+                        q->hook(dev);
+        }
+}
+
 void intel_modeset_init(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5523,6 +5863,8 @@ void intel_modeset_init(struct drm_device *dev)
 
         dev->mode_config.funcs = (void *)&intel_mode_funcs;
 
+        intel_init_quirks(dev);
+
         intel_init_display(dev);
 
         if (IS_I965G(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1aac59e83bff..40be1fa65be1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -43,6 +43,7 @@
 #define DP_LINK_CONFIGURATION_SIZE      9
 
 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
+#define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp)
 
 struct intel_dp_priv {
         uint32_t output_reg;
@@ -56,6 +57,7 @@ struct intel_dp_priv {
         struct intel_encoder *intel_encoder;
         struct i2c_adapter adapter;
         struct i2c_algo_dp_aux_data algo;
+        bool is_pch_edp;
 };
 
 static void
@@ -128,8 +130,9 @@ intel_dp_link_required(struct drm_device *dev,
                        struct intel_encoder *intel_encoder, int pixel_clock)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 
-        if (IS_eDP(intel_encoder))
+        if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
                 return (pixel_clock * dev_priv->edp_bpp) / 8;
         else
                 return pixel_clock * 3;
@@ -147,9 +150,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
 {
         struct drm_encoder *encoder = intel_attached_encoder(connector);
         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
+        struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
+        struct drm_device *dev = connector->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 
+        if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
+            dev_priv->panel_fixed_mode) {
+                if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
+                        return MODE_PANEL;
+
+                if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
+                        return MODE_PANEL;
+        }
+
         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
            which are outside spec tolerances but somehow work by magic */
         if (!IS_eDP(intel_encoder) &&
@@ -508,11 +523,37 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 {
         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
         int lane_count, clock;
         int max_lane_count = intel_dp_max_lane_count(intel_encoder);
         int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 
+        if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
+            dev_priv->panel_fixed_mode) {
+                struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
+
+                adjusted_mode->hdisplay = fixed_mode->hdisplay;
+                adjusted_mode->hsync_start = fixed_mode->hsync_start;
+                adjusted_mode->hsync_end = fixed_mode->hsync_end;
+                adjusted_mode->htotal = fixed_mode->htotal;
+
+                adjusted_mode->vdisplay = fixed_mode->vdisplay;
+                adjusted_mode->vsync_start = fixed_mode->vsync_start;
+                adjusted_mode->vsync_end = fixed_mode->vsync_end;
+                adjusted_mode->vtotal = fixed_mode->vtotal;
+
+                adjusted_mode->clock = fixed_mode->clock;
+                drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
+
+                /*
+                 * the mode->clock is used to calculate the Data&Link M/N
+                 * of the pipe. For the eDP the fixed clock should be used.
+                 */
+                mode->clock = dev_priv->panel_fixed_mode->clock;
+        }
+
         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
                 for (clock = 0; clock <= max_clock; clock++) {
                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
@@ -531,7 +572,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
                 }
         }
 
-        if (IS_eDP(intel_encoder)) {
+        if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
                 /* okay we failed just pick the highest */
                 dp_priv->lane_count = max_lane_count;
                 dp_priv->link_bw = bws[max_clock];
@@ -563,14 +604,14 @@ intel_reduce_ratio(uint32_t *num, uint32_t *den)
 }
 
 static void
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
                      int nlanes,
                      int pixel_clock,
                      int link_clock,
                      struct intel_dp_m_n *m_n)
 {
         m_n->tu = 64;
-        m_n->gmch_m = pixel_clock * bytes_per_pixel;
+        m_n->gmch_m = (pixel_clock * bpp) >> 3;
         m_n->gmch_n = link_clock * nlanes;
         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
         m_n->link_m = pixel_clock;
@@ -578,6 +619,28 @@ intel_dp_compute_m_n(int bytes_per_pixel,
         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 }
 
+bool intel_pch_has_edp(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_mode_config *mode_config = &dev->mode_config;
+        struct drm_encoder *encoder;
+
+        list_for_each_entry(encoder, &mode_config->encoder_list, head) {
+                struct intel_encoder *intel_encoder;
+                struct intel_dp_priv *dp_priv;
+
+                if (!encoder || encoder->crtc != crtc)
+                        continue;
+
+                intel_encoder = enc_to_intel_encoder(encoder);
+                dp_priv = intel_encoder->dev_priv;
+
+                if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT)
+                        return dp_priv->is_pch_edp;
+        }
+        return false;
+}
+
 void
 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                  struct drm_display_mode *adjusted_mode)
@@ -587,7 +650,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
         struct drm_encoder *encoder;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        int lane_count = 4;
+        int lane_count = 4, bpp = 24;
         struct intel_dp_m_n m_n;
 
         /*
@@ -605,6 +668,8 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 
                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
                         lane_count = dp_priv->lane_count;
+                        if (IS_PCH_eDP(dp_priv))
+                                bpp = dev_priv->edp_bpp;
                         break;
                 }
         }
@@ -614,7 +679,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
          * the number of bytes_per_pixel post-LUT, which we always
          * set up for 8-bits of R/G/B, or 3 bytes total.
          */
-        intel_dp_compute_m_n(3, lane_count,
+        intel_dp_compute_m_n(bpp, lane_count,
                              mode->clock, adjusted_mode->clock, &m_n);
 
         if (HAS_PCH_SPLIT(dev)) {
@@ -717,6 +782,51 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
         }
 }
 
+static void ironlake_edp_panel_on (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+        u32 pp, pp_status;
+
+        pp_status = I915_READ(PCH_PP_STATUS);
+        if (pp_status & PP_ON)
+                return;
+
+        pp = I915_READ(PCH_PP_CONTROL);
+        pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+        do {
+                pp_status = I915_READ(PCH_PP_STATUS);
+        } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
+
+        if (time_after(jiffies, timeout))
+                DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
+
+        pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
+        I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
+static void ironlake_edp_panel_off (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+        u32 pp, pp_status;
+
+        pp = I915_READ(PCH_PP_CONTROL);
+        pp &= ~POWER_TARGET_ON;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+        do {
+                pp_status = I915_READ(PCH_PP_STATUS);
+        } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
+
+        if (time_after(jiffies, timeout))
+                DRM_DEBUG_KMS("panel off wait timed out\n");
+
+        /* Make sure VDD is enabled so DP AUX will work */
+        pp |= EDP_FORCE_VDD;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
 static void ironlake_edp_backlight_on (struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -751,14 +861,18 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
         if (mode != DRM_MODE_DPMS_ON) {
                 if (dp_reg & DP_PORT_EN) {
                         intel_dp_link_down(intel_encoder, dp_priv->DP);
-                        if (IS_eDP(intel_encoder))
+                        if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
                                 ironlake_edp_backlight_off(dev);
+                                ironlake_edp_panel_off(dev);
+                        }
                 }
         } else {
                 if (!(dp_reg & DP_PORT_EN)) {
                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
-                        if (IS_eDP(intel_encoder))
+                        if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
+                                ironlake_edp_panel_on(dev);
                                 ironlake_edp_backlight_on(dev);
+                        }
                 }
         }
         dp_priv->dpms_mode = mode;
@@ -1291,17 +1405,32 @@ static int intel_dp_get_modes(struct drm_connector *connector)
         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
         struct drm_device *dev = intel_encoder->enc.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
         int ret;
 
         /* We should parse the EDID data and find out if it has an audio sink
          */
 
         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
-        if (ret)
+        if (ret) {
+                if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
+                    !dev_priv->panel_fixed_mode) {
+                        struct drm_display_mode *newmode;
+                        list_for_each_entry(newmode, &connector->probed_modes,
+                                            head) {
+                                if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
+                                        dev_priv->panel_fixed_mode =
+                                                drm_mode_duplicate(dev, newmode);
+                                        break;
+                                }
+                        }
+                }
+
                 return ret;
+        }
 
         /* if eDP has no EDID, try to use fixed panel mode from VBT */
-        if (IS_eDP(intel_encoder)) {
+        if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
                 if (dev_priv->panel_fixed_mode != NULL) {
                         struct drm_display_mode *mode;
                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
@@ -1386,6 +1515,26 @@ intel_trans_dp_port_sel (struct drm_crtc *crtc)
         return -1;
 }
 
+/* check the VBT to see whether the eDP is on DP-D port */
+bool intel_dpd_is_edp(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct child_device_config *p_child;
+        int i;
+
+        if (!dev_priv->child_dev_num)
+                return false;
+
+        for (i = 0; i < dev_priv->child_dev_num; i++) {
+                p_child = dev_priv->child_dev + i;
+
+                if (p_child->dvo_port == PORT_IDPD &&
+                    p_child->device_type == DEVICE_TYPE_eDP)
+                        return true;
+        }
+        return false;
+}
+
 void
 intel_dp_init(struct drm_device *dev, int output_reg)
 {
@@ -1395,6 +1544,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
         struct intel_connector *intel_connector;
         struct intel_dp_priv *dp_priv;
         const char *name = NULL;
+        int type;
 
         intel_encoder = kcalloc(sizeof(struct intel_encoder) +
                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
@@ -1409,18 +1559,24 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 
         dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
 
+        if (HAS_PCH_SPLIT(dev) && (output_reg == PCH_DP_D))
+                if (intel_dpd_is_edp(dev))
+                        dp_priv->is_pch_edp = true;
+
+        if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
+                type = DRM_MODE_CONNECTOR_eDP;
+                intel_encoder->type = INTEL_OUTPUT_EDP;
+        } else {
+                type = DRM_MODE_CONNECTOR_DisplayPort;
+                intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+        }
+
         connector = &intel_connector->base;
-        drm_connector_init(dev, connector, &intel_dp_connector_funcs,
-                           DRM_MODE_CONNECTOR_DisplayPort);
+        drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
 
         connector->polled = DRM_CONNECTOR_POLL_HPD;
 
-        if (output_reg == DP_A)
-                intel_encoder->type = INTEL_OUTPUT_EDP;
-        else
-                intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
-
         if (output_reg == DP_B || output_reg == PCH_DP_B)
                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
         else if (output_reg == DP_C || output_reg == PCH_DP_C)
@@ -1479,7 +1635,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
         intel_encoder->ddc_bus = &dp_priv->adapter;
         intel_encoder->hot_plug = intel_dp_hot_plug;
 
-        if (output_reg == DP_A) {
+        if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
                 /* initialize panel mode from VBT if available for eDP */
                 if (dev_priv->lfp_lvds_vbt_mode) {
                         dev_priv->panel_fixed_mode =
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 72206f37c4fb..b2190148703a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -143,8 +143,6 @@ struct intel_crtc {
         struct drm_crtc base;
         enum pipe pipe;
         enum plane plane;
-        struct drm_gem_object *cursor_bo;
-        uint32_t cursor_addr;
         u8 lut_r[256], lut_g[256], lut_b[256];
         int dpms_mode;
         bool busy; /* is scanout buffer being updated frequently? */
@@ -153,6 +151,12 @@ struct intel_crtc {
         struct intel_overlay *overlay;
         struct intel_unpin_work *unpin_work;
         int fdi_lanes;
+
+        struct drm_gem_object *cursor_bo;
+        uint32_t cursor_addr;
+        int16_t cursor_x, cursor_y;
+        int16_t cursor_width, cursor_height;
+        bool cursor_visble;
 };
 
 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
@@ -179,6 +183,8 @@ extern void intel_dp_init(struct drm_device *dev, int dp_reg);
 void
 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                  struct drm_display_mode *adjusted_mode);
+extern bool intel_pch_has_edp(struct drm_crtc *crtc);
+extern bool intel_dpd_is_edp(struct drm_device *dev);
 extern void intel_edp_link_config (struct intel_encoder *, int *, int *);
 
 
@@ -215,6 +221,9 @@ extern void intel_init_clock_gating(struct drm_device *dev);
 extern void ironlake_enable_drps(struct drm_device *dev);
 extern void ironlake_disable_drps(struct drm_device *dev);
 
+extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
+                                      struct drm_gem_object *obj);
+
 extern int intel_framebuffer_init(struct drm_device *dev,
                                   struct intel_framebuffer *ifb,
                                   struct drm_mode_fb_cmd *mode_cmd,
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index c3c505244e07..3e18c9e7729b 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -98,7 +98,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
 
         mutex_lock(&dev->struct_mutex);
 
-        ret = i915_gem_object_pin(fbo, 64*1024);
+        ret = intel_pin_and_fence_fb_obj(dev, fbo);
         if (ret) {
                 DRM_ERROR("failed to pin fb: %d\n", ret);
                 goto out_unref;
@@ -236,7 +236,7 @@ int intel_fbdev_destroy(struct drm_device *dev,
 
         drm_framebuffer_cleanup(&ifb->base);
         if (ifb->obj)
-                drm_gem_object_unreference_unlocked(ifb->obj);
+                drm_gem_object_unreference(ifb->obj);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 83bd764b000e..197887ed1823 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -54,10 +54,11 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
         struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
         u32 sdvox;
 
-        sdvox = SDVO_ENCODING_HDMI |
-                SDVO_BORDER_ENABLE |
-                SDVO_VSYNC_ACTIVE_HIGH |
-                SDVO_HSYNC_ACTIVE_HIGH;
+        sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
+        if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+                sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
+        if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+                sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 
         if (hdmi_priv->has_hdmi_sink) {
                 sdvox |= SDVO_AUDIO_ENABLE;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 31df55f0a0a7..0a2e60059fb3 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -156,31 +156,73 @@ static int intel_lvds_mode_valid(struct drm_connector *connector,
         return MODE_OK;
 }
 
+static void
+centre_horizontally(struct drm_display_mode *mode,
+                    int width)
+{
+        u32 border, sync_pos, blank_width, sync_width;
+
+        /* keep the hsync and hblank widths constant */
+        sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
+        blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
+        sync_pos = (blank_width - sync_width + 1) / 2;
+
+        border = (mode->hdisplay - width + 1) / 2;
+        border += border & 1; /* make the border even */
+
+        mode->crtc_hdisplay = width;
+        mode->crtc_hblank_start = width + border;
+        mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
+
+        mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
+        mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
+}
+
+static void
+centre_vertically(struct drm_display_mode *mode,
+                  int height)
+{
+        u32 border, sync_pos, blank_width, sync_width;
+
+        /* keep the vsync and vblank widths constant */
+        sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
+        blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
+        sync_pos = (blank_width - sync_width + 1) / 2;
+
+        border = (mode->vdisplay - height + 1) / 2;
+
+        mode->crtc_vdisplay = height;
+        mode->crtc_vblank_start = height + border;
+        mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
+
+        mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
+        mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
+}
+
+static inline u32 panel_fitter_scaling(u32 source, u32 target)
+{
+        /*
+         * Floating point operation is not supported. So the FACTOR
+         * is defined, which can avoid the floating point computation
+         * when calculating the panel ratio.
+         */
+#define ACCURACY 12
+#define FACTOR (1 << ACCURACY)
+        u32 ratio = source * FACTOR / target;
+        return (FACTOR * ratio + FACTOR/2) / FACTOR;
+}
+
 static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                                   struct drm_display_mode *mode,
                                   struct drm_display_mode *adjusted_mode)
 {
-        /*
-         * float point operation is not supported . So the PANEL_RATIO_FACTOR
-         * is defined, which can avoid the float point computation when
-         * calculating the panel ratio.
-         */
-#define PANEL_RATIO_FACTOR 8192
         struct drm_device *dev = encoder->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
         struct drm_encoder *tmp_encoder;
         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
         struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
-        u32 pfit_control = 0, pfit_pgm_ratios = 0;
-        int left_border = 0, right_border = 0, top_border = 0;
-        int bottom_border = 0;
-        bool border = 0;
-        int panel_ratio, desired_ratio, vert_scale, horiz_scale;
-        int horiz_ratio, vert_ratio;
-        u32 hsync_width, vsync_width;
-        u32 hblank_width, vblank_width;
-        u32 hsync_pos, vsync_pos;
+        u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
 
         /* Should never happen!! */
         if (!IS_I965G(dev) && intel_crtc->pipe == 0) {
@@ -200,27 +242,25 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
         if (dev_priv->panel_fixed_mode == NULL)
                 return true;
         /*
-         * If we have timings from the BIOS for the panel, put them in
+         * We have timings from the BIOS for the panel, put them in
          * to the adjusted mode.  The CRTC will be set up for this mode,
          * with the panel scaling set up to source from the H/VDisplay
          * of the original mode.
          */
-        if (dev_priv->panel_fixed_mode != NULL) {
-                adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay;
-                adjusted_mode->hsync_start =
-                        dev_priv->panel_fixed_mode->hsync_start;
-                adjusted_mode->hsync_end =
-                        dev_priv->panel_fixed_mode->hsync_end;
-                adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal;
-                adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay;
-                adjusted_mode->vsync_start =
-                        dev_priv->panel_fixed_mode->vsync_start;
-                adjusted_mode->vsync_end =
-                        dev_priv->panel_fixed_mode->vsync_end;
-                adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
-                adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
-                drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
-        }
+        adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay;
+        adjusted_mode->hsync_start =
+                dev_priv->panel_fixed_mode->hsync_start;
+        adjusted_mode->hsync_end =
+                dev_priv->panel_fixed_mode->hsync_end;
+        adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal;
+        adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay;
+        adjusted_mode->vsync_start =
+                dev_priv->panel_fixed_mode->vsync_start;
+        adjusted_mode->vsync_end =
+                dev_priv->panel_fixed_mode->vsync_end;
+        adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
+        adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
+        drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 
         /* Make sure pre-965s set dither correctly */
         if (!IS_I965G(dev)) {
@@ -230,11 +270,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
 
         /* Native modes don't need fitting */
         if (adjusted_mode->hdisplay == mode->hdisplay &&
-                        adjusted_mode->vdisplay == mode->vdisplay) {
-                pfit_pgm_ratios = 0;
-                border = 0;
+            adjusted_mode->vdisplay == mode->vdisplay)
                 goto out;
-        }
 
         /* full screen scale for now */
         if (HAS_PCH_SPLIT(dev))
@@ -242,25 +279,9 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
 
         /* 965+ wants fuzzy fitting */
         if (IS_I965G(dev))
-                pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
-                                        PFIT_FILTER_FUZZY;
-
-        hsync_width = adjusted_mode->crtc_hsync_end -
-                                        adjusted_mode->crtc_hsync_start;
-        vsync_width = adjusted_mode->crtc_vsync_end -
-                                        adjusted_mode->crtc_vsync_start;
-        hblank_width = adjusted_mode->crtc_hblank_end -
-                                        adjusted_mode->crtc_hblank_start;
-        vblank_width = adjusted_mode->crtc_vblank_end -
-                                        adjusted_mode->crtc_vblank_start;
-        /*
-         * Deal with panel fitting options. Figure out how to stretch the
-         * image based on its aspect ratio & the current panel fitting mode.
-         */
-        panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR /
-                                adjusted_mode->vdisplay;
-        desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR /
-                                mode->vdisplay;
+                pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
+                                 PFIT_FILTER_FUZZY);
+
         /*
          * Enable automatic panel scaling for non-native modes so that they fill
          * the screen.  Should be enabled before the pipe is enabled, according
@@ -278,170 +299,63 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                  * For centered modes, we have to calculate border widths &
                  * heights and modify the values programmed into the CRTC.
                  */
-                left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2;
-                right_border = left_border;
-                if (mode->hdisplay & 1)
-                        right_border++;
-                top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2;
-                bottom_border = top_border;
-                if (mode->vdisplay & 1)
-                        bottom_border++;
-                /* Set active & border values */
-                adjusted_mode->crtc_hdisplay = mode->hdisplay;
-                /* Keep the boder be even */
-                if (right_border & 1)
-                        right_border++;
-                /* use the border directly instead of border minuse one */
-                adjusted_mode->crtc_hblank_start = mode->hdisplay +
-                                                right_border;
-                /* keep the blank width constant */
-                adjusted_mode->crtc_hblank_end =
-                        adjusted_mode->crtc_hblank_start + hblank_width;
-                /* get the hsync pos relative to hblank start */
-                hsync_pos = (hblank_width - hsync_width) / 2;
-                /* keep the hsync pos be even */
-                if (hsync_pos & 1)
-                        hsync_pos++;
-                adjusted_mode->crtc_hsync_start =
-                                adjusted_mode->crtc_hblank_start + hsync_pos;
-                /* keep the hsync width constant */
-                adjusted_mode->crtc_hsync_end =
-                                adjusted_mode->crtc_hsync_start + hsync_width;
-                adjusted_mode->crtc_vdisplay = mode->vdisplay;
-                /* use the border instead of border minus one */
-                adjusted_mode->crtc_vblank_start = mode->vdisplay +
-                                                bottom_border;
-                /* keep the vblank width constant */
-                adjusted_mode->crtc_vblank_end =
-                                adjusted_mode->crtc_vblank_start + vblank_width;
-                /* get the vsync start postion relative to vblank start */
-                vsync_pos = (vblank_width - vsync_width) / 2;
-                adjusted_mode->crtc_vsync_start =
-                                adjusted_mode->crtc_vblank_start + vsync_pos;
-                /* keep the vsync width constant */
-                adjusted_mode->crtc_vsync_end =
-                                adjusted_mode->crtc_vsync_start + vsync_width;
-                border = 1;
+                centre_horizontally(adjusted_mode, mode->hdisplay);
+                centre_vertically(adjusted_mode, mode->vdisplay);
+                border = LVDS_BORDER_ENABLE;
                 break;
+
         case DRM_MODE_SCALE_ASPECT:
-                /* Scale but preserve the spect ratio */
-                pfit_control |= PFIT_ENABLE;
+                /* Scale but preserve the aspect ratio */
                 if (IS_I965G(dev)) {
+                        u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
+                        u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
+
+                        pfit_control |= PFIT_ENABLE;
                         /* 965+ is easy, it does everything in hw */
-                        if (panel_ratio > desired_ratio)
+                        if (scaled_width > scaled_height)
                                 pfit_control |= PFIT_SCALING_PILLAR;
-                        else if (panel_ratio < desired_ratio)
+                        else if (scaled_width < scaled_height)
                                 pfit_control |= PFIT_SCALING_LETTER;
                         else
                                 pfit_control |= PFIT_SCALING_AUTO;
                 } else {
+                        u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
+                        u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
                         /*
                          * For earlier chips we have to calculate the scaling
                          * ratio by hand and program it into the
                          * PFIT_PGM_RATIO register
                          */
-                        u32 horiz_bits, vert_bits, bits = 12;
-                        horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/
-                                                adjusted_mode->hdisplay;
-                        vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/
-                                                adjusted_mode->vdisplay;
-                        horiz_scale = adjusted_mode->hdisplay *
-                                        PANEL_RATIO_FACTOR / mode->hdisplay;
-                        vert_scale = adjusted_mode->vdisplay *
-                                        PANEL_RATIO_FACTOR / mode->vdisplay;
-
-                        /* retain aspect ratio */
-                        if (panel_ratio > desired_ratio) { /* Pillar */
-                                u32 scaled_width;
-                                scaled_width = mode->hdisplay * vert_scale /
-                                                PANEL_RATIO_FACTOR;
-                                horiz_ratio = vert_ratio;
-                                pfit_control |= (VERT_AUTO_SCALE |
-                                                 VERT_INTERP_BILINEAR |
-                                                 HORIZ_INTERP_BILINEAR);
-                                /* Pillar will have left/right borders */
-                                left_border = (adjusted_mode->hdisplay -
-                                                scaled_width) / 2;
-                                right_border = left_border;
-                                if (mode->hdisplay & 1) /* odd resolutions */
-                                        right_border++;
-                                /* keep the border be even */
-                                if (right_border & 1)
-                                        right_border++;
-                                adjusted_mode->crtc_hdisplay = scaled_width;
-                                /* use border instead of border minus one */
-                                adjusted_mode->crtc_hblank_start =
-                                        scaled_width + right_border;
-                                /* keep the hblank width constant */
-                                adjusted_mode->crtc_hblank_end =
-                                        adjusted_mode->crtc_hblank_start +
-                                                        hblank_width;
-                                /*
-                                 * get the hsync start pos relative to
-                                 * hblank start
-                                 */
-                                hsync_pos = (hblank_width - hsync_width) / 2;
-                                /* keep the hsync_pos be even */
-                                if (hsync_pos & 1)
-                                        hsync_pos++;
-                                adjusted_mode->crtc_hsync_start =
-                                        adjusted_mode->crtc_hblank_start +
-                                                        hsync_pos;
-                                /* keept hsync width constant */
-                                adjusted_mode->crtc_hsync_end =
-                                        adjusted_mode->crtc_hsync_start +
-                                                        hsync_width;
-                                border = 1;
-                        } else if (panel_ratio < desired_ratio) { /* letter */
-                                u32 scaled_height = mode->vdisplay *
-                                        horiz_scale / PANEL_RATIO_FACTOR;
-                                vert_ratio = horiz_ratio;
-                                pfit_control |= (HORIZ_AUTO_SCALE |
-                                                 VERT_INTERP_BILINEAR |
-                                                 HORIZ_INTERP_BILINEAR);
-                                /* Letterbox will have top/bottom border */
-                                top_border = (adjusted_mode->vdisplay -
-                                        scaled_height) / 2;
-                                bottom_border = top_border;
-                                if (mode->vdisplay & 1)
-                                        bottom_border++;
-                                adjusted_mode->crtc_vdisplay = scaled_height;
-                                /* use border instead of border minus one */
-                                adjusted_mode->crtc_vblank_start =
-                                        scaled_height + bottom_border;
-                                /* keep the vblank width constant */
-                                adjusted_mode->crtc_vblank_end =
-                                        adjusted_mode->crtc_vblank_start +
-                                                        vblank_width;
-                                /*
-                                 * get the vsync start pos relative to
-                                 * vblank start
-                                 */
-                                vsync_pos = (vblank_width - vsync_width) / 2;
-                                adjusted_mode->crtc_vsync_start =
-                                        adjusted_mode->crtc_vblank_start +
-                                                        vsync_pos;
-                                /* keep the vsync width constant */
-                                adjusted_mode->crtc_vsync_end =
-                                        adjusted_mode->crtc_vsync_start +
-                                                        vsync_width;
-                                border = 1;
-                        } else {
-                        /* Aspects match, Let hw scale both directions */
-                                pfit_control |= (VERT_AUTO_SCALE |
-                                                 HORIZ_AUTO_SCALE |
+                        if (scaled_width > scaled_height) { /* pillar */
+                                centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
+
+                                border = LVDS_BORDER_ENABLE;
+                                if (mode->vdisplay != adjusted_mode->vdisplay) {
+                                        u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
+                                        pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
+                                                            bits << PFIT_VERT_SCALE_SHIFT);
+                                        pfit_control |= (PFIT_ENABLE |
+                                                         VERT_INTERP_BILINEAR |
+                                                         HORIZ_INTERP_BILINEAR);
+                                }
+                        } else if (scaled_width < scaled_height) { /* letter */
+                                centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
+
+                                border = LVDS_BORDER_ENABLE;
+                                if (mode->hdisplay != adjusted_mode->hdisplay) {
+                                        u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
+                                        pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
+                                                            bits << PFIT_VERT_SCALE_SHIFT);
+                                        pfit_control |= (PFIT_ENABLE |
+                                                         VERT_INTERP_BILINEAR |
+                                                         HORIZ_INTERP_BILINEAR);
+                                }
+                        } else
+                                /* Aspects match, Let hw scale both directions */
+                                pfit_control |= (PFIT_ENABLE |
+                                                 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
                                                  VERT_INTERP_BILINEAR |
                                                  HORIZ_INTERP_BILINEAR);
-                        }
-                        horiz_bits = (1 << bits) * horiz_ratio /
-                                        PANEL_RATIO_FACTOR;
-                        vert_bits = (1 << bits) * vert_ratio /
-                                        PANEL_RATIO_FACTOR;
-                        pfit_pgm_ratios =
-                                ((vert_bits << PFIT_VERT_SCALE_SHIFT) &
-                                                PFIT_VERT_SCALE_MASK) |
-                                ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) &
-                                                PFIT_HORIZ_SCALE_MASK);
                 }
                 break;
 
@@ -458,6 +372,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                                          VERT_INTERP_BILINEAR |
                                          HORIZ_INTERP_BILINEAR);
                 break;
+
         default:
                 break;
         }
@@ -465,14 +380,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
 out:
         lvds_priv->pfit_control = pfit_control;
         lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
-        /*
-         * When there exists the border, it means that the LVDS_BORDR
-         * should be enabled.
-         */
-        if (border)
-                dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE;
-        else
-                dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE);
+        dev_priv->lvds_border_bits = border;
+
         /*
          * XXX: It would be nice to support lower refresh rates on the
          * panels to reduce power consumption, and perhaps match the
@@ -599,6 +508,26 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
         return 0;
 }
 
+static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
+{
+        DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident);
+        return 1;
+}
+
+/* The GPU hangs up on these systems if modeset is performed on LID open */
+static const struct dmi_system_id intel_no_modeset_on_lid[] = {
+        {
+                .callback = intel_no_modeset_on_lid_dmi_callback,
+                .ident = "Toshiba Tecra A11",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
+                },
+        },
+
+        { }     /* terminating entry */
+};
+
 /*
  * Lid events. Note the use of 'modeset_on_lid':
  *  - we set it on lid close, and reset it on open
@@ -622,6 +551,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
          */
         if (connector)
                 connector->status = connector->funcs->detect(connector);
+        /* Don't force modeset on machines where it causes a GPU lockup */
+        if (dmi_check_system(intel_no_modeset_on_lid))
+                return NOTIFY_OK;
         if (!acpi_lid_open()) {
                 dev_priv->modeset_on_lid = 1;
                 return NOTIFY_OK;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index d7ad5139d17c..f26ec2f27d36 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -65,7 +65,7 @@
 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
-#define OCMD_BUF_TYPE_MASK      (Ox1<<5)
+#define OCMD_BUF_TYPE_MASK      (0x1<<5)
 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
 #define OCMD_TEST_MODE          (0x1<<4)
@@ -958,7 +958,7 @@ static int check_overlay_src(struct drm_device *dev,
             || rec->src_width < N_HORIZ_Y_TAPS*4)
                 return -EINVAL;
 
-        /* check alingment constrains */
+        /* check alignment constraints */
         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
                 case I915_OVERLAY_RGB:
                         /* not implemented */
@@ -990,7 +990,10 @@ static int check_overlay_src(struct drm_device *dev,
                 return -EINVAL;
 
         /* stride checking */
-        stride_mask = 63;
+        if (IS_I830(dev) || IS_845G(dev))
+                stride_mask = 255;
+        else
+                stride_mask = 63;
 
         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
                 return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 76993ac16cc1..8b2bfc005c59 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1237,9 +1237,11 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
 
         /* Set the SDVO control regs. */
         if (IS_I965G(dev)) {
-                sdvox |= SDVO_BORDER_ENABLE |
-                        SDVO_VSYNC_ACTIVE_HIGH |
-                        SDVO_HSYNC_ACTIVE_HIGH;
+                sdvox |= SDVO_BORDER_ENABLE;
+                if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+                        sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
+                if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+                        sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
         } else {
                 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
                 switch (sdvo_priv->sdvo_reg) {
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 6d553c29d106..d61ffbc381e5 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -476,7 +476,7 @@ static const struct tv_mode tv_modes[] = {
                 .vi_end_f1      = 20,               .vi_end_f2          = 21,
                 .nbr_end        = 240,
 
-                .burst_ena      = 8,
+                .burst_ena      = true,
                 .hburst_start   = 72,               .hburst_len         = 34,
                 .vburst_start_f1 = 9,               .vburst_end_f1      = 240,
                 .vburst_start_f2 = 10,              .vburst_end_f2      = 240,
@@ -896,8 +896,6 @@ static const struct tv_mode tv_modes[] = {
         },
 };
 
-#define NUM_TV_MODES sizeof(tv_modes) / sizeof (tv_modes[0])
-
 static void
 intel_tv_dpms(struct drm_encoder *encoder, int mode)
 {
@@ -1512,7 +1510,7 @@ intel_tv_set_property(struct drm_connector *connector, struct drm_property *prop
                 tv_priv->margin[TV_MARGIN_BOTTOM] = val;
                 changed = true;
         } else if (property == dev->mode_config.tv_mode_property) {
-                if (val >= NUM_TV_MODES) {
+                if (val >= ARRAY_SIZE(tv_modes)) {
                         ret = -EINVAL;
                         goto out;
                 }
@@ -1693,13 +1691,13 @@ intel_tv_init(struct drm_device *dev)
         connector->doublescan_allowed = false;
 
         /* Create TV properties then attach current values */
-        tv_format_names = kmalloc(sizeof(char *) * NUM_TV_MODES,
+        tv_format_names = kmalloc(sizeof(char *) * ARRAY_SIZE(tv_modes),
                                   GFP_KERNEL);
         if (!tv_format_names)
                 goto out;
-        for (i = 0; i < NUM_TV_MODES; i++)
+        for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
                 tv_format_names[i] = tv_modes[i].name;
-        drm_mode_create_tv_properties(dev, NUM_TV_MODES, tv_format_names);
+        drm_mode_create_tv_properties(dev, ARRAY_SIZE(tv_modes), tv_format_names);
 
         drm_connector_attach_property(connector, dev->mode_config.tv_mode_property,
                                    initial_mode);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index a3d25f419853..95f8b3a3c43d 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -335,6 +335,7 @@ static ssize_t radeon_get_pm_profile(struct device *dev,
         return snprintf(buf, PAGE_SIZE, "%s\n",
                         (cp == PM_PROFILE_AUTO) ? "auto" :
                         (cp == PM_PROFILE_LOW) ? "low" :
+                        (cp == PM_PROFILE_MID) ? "mid" :
                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 }
 
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4917af96bae1..2ed435bd4b6c 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -539,9 +539,13 @@ static int mmci_get_cd(struct mmc_host *mmc)
         if (host->gpio_cd == -ENOSYS)
                 status = host->plat->status(mmc_dev(host->mmc));
         else
-                status = gpio_get_value(host->gpio_cd);
+                status = !gpio_get_value(host->gpio_cd);
 
-        return !status;
+        /*
+         * Use positive logic throughout - status is zero for no card,
+         * non-zero for card inserted.
+         */
+        return status;
 }
 
 static const struct mmc_host_ops mmci_ops = {
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 8bd23687c530..bb0872a63315 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -1062,6 +1062,10 @@ struct bnx2x {
 
         /* used to synchronize stats collecting */
         int                     stats_state;
+
+        /* used for synchronization of concurrent threads statistics handling */
+        spinlock_t              stats_lock;
+
         /* used by dmae command loader */
         struct dmae_command     stats_dmae;
         int                     executer_idx;
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 57ff5b3bcce6..46167c081727 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -57,8 +57,8 @@
 #include "bnx2x_init_ops.h"
 #include "bnx2x_dump.h"
 
-#define DRV_MODULE_VERSION      "1.52.53-1"
-#define DRV_MODULE_RELDATE      "2010/18/04"
+#define DRV_MODULE_VERSION      "1.52.53-2"
+#define DRV_MODULE_RELDATE      "2010/21/07"
 #define BNX2X_BC_VER            0x040200
 
 #include <linux/firmware.h>
@@ -3789,6 +3789,8 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
                 struct eth_query_ramrod_data ramrod_data = {0};
                 int i, rc;
 
+                spin_lock_bh(&bp->stats_lock);
+
                 ramrod_data.drv_counter = bp->stats_counter++;
                 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
                 for_each_queue(bp, i)
@@ -3802,6 +3804,8 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
                         bp->spq_left++;
                         bp->stats_pending = 1;
                 }
+
+                spin_unlock_bh(&bp->stats_lock);
         }
 }
 
@@ -4367,6 +4371,14 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
         struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
         struct bnx2x_eth_stats *estats = &bp->eth_stats;
         int i;
+        u16 cur_stats_counter;
+
+        /* Make sure we use the value of the counter
+         * used for sending the last stats ramrod.
+         */
+        spin_lock_bh(&bp->stats_lock);
+        cur_stats_counter = bp->stats_counter - 1;
+        spin_unlock_bh(&bp->stats_lock);
 
         memcpy(&(fstats->total_bytes_received_hi),
                &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
@@ -4394,25 +4406,22 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
                 u32 diff;
 
                 /* are storm stats valid? */
-                if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
-                                                        bp->stats_counter) {
+                if (le16_to_cpu(xclient->stats_counter) != cur_stats_counter) {
                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
                            "  xstorm counter (0x%x) != stats_counter (0x%x)\n",
-                           i, xclient->stats_counter, bp->stats_counter);
+                           i, xclient->stats_counter, cur_stats_counter + 1);
                         return -1;
                 }
-                if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
-                                                        bp->stats_counter) {
+                if (le16_to_cpu(tclient->stats_counter) != cur_stats_counter) {
                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
                            "  tstorm counter (0x%x) != stats_counter (0x%x)\n",
-                           i, tclient->stats_counter, bp->stats_counter);
+                           i, tclient->stats_counter, cur_stats_counter + 1);
                         return -2;
                 }
-                if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) !=
-                                                        bp->stats_counter) {
+                if (le16_to_cpu(uclient->stats_counter) != cur_stats_counter) {
                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
                            "  ustorm counter (0x%x) != stats_counter (0x%x)\n",
-                           i, uclient->stats_counter, bp->stats_counter);
+                           i, uclient->stats_counter, cur_stats_counter + 1);
                         return -4;
                 }
 
@@ -4849,16 +4858,18 @@ static const struct {
 
 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
 {
-        enum bnx2x_stats_state state = bp->stats_state;
+        enum bnx2x_stats_state state;
 
         if (unlikely(bp->panic))
                 return;
 
-        bnx2x_stats_stm[state][event].action(bp);
+        /* Protect a state change flow */
+        spin_lock_bh(&bp->stats_lock);
+        state = bp->stats_state;
         bp->stats_state = bnx2x_stats_stm[state][event].next_state;
+        spin_unlock_bh(&bp->stats_lock);
 
-        /* Make sure the state has been "changed" */
-        smp_wmb();
+        bnx2x_stats_stm[state][event].action(bp);
 
         if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
                 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
@@ -9908,6 +9919,7 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
 
         mutex_init(&bp->port.phy_mutex);
         mutex_init(&bp->fw_mb_mutex);
+        spin_lock_init(&bp->stats_lock);
 #ifdef BCM_CNIC
         mutex_init(&bp->cnic_mutex);
 #endif
diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c
index df483076eda6..8d7dfd2f1e90 100644
--- a/drivers/net/bonding/bond_alb.c
+++ b/drivers/net/bonding/bond_alb.c
@@ -822,7 +822,7 @@ static int rlb_initialize(struct bonding *bond)
 
         /*initialize packet type*/
         pk_type->type = cpu_to_be16(ETH_P_ARP);
-        pk_type->dev = NULL;
+        pk_type->dev = bond->dev;
         pk_type->func = rlb_arp_recv;
 
         /* register to receive ARPs */
diff --git a/drivers/net/declance.c b/drivers/net/declance.c
index 1d973db27c32..d7de376d7178 100644
--- a/drivers/net/declance.c
+++ b/drivers/net/declance.c
@@ -1022,7 +1022,7 @@ static const struct net_device_ops lance_netdev_ops = {
         .ndo_set_mac_address    = eth_mac_addr,
 };
 
-static int __init dec_lance_probe(struct device *bdev, const int type)
+static int __devinit dec_lance_probe(struct device *bdev, const int type)
 {
         static unsigned version_printed;
         static const char fmt[] = "declance%d";
@@ -1326,7 +1326,7 @@ static void __exit dec_lance_platform_remove(void)
 }
 
 #ifdef CONFIG_TC
-static int __init dec_lance_tc_probe(struct device *dev);
+static int __devinit dec_lance_tc_probe(struct device *dev);
 static int __exit dec_lance_tc_remove(struct device *dev);
 
 static const struct tc_device_id dec_lance_tc_table[] = {
@@ -1345,7 +1345,7 @@ static struct tc_driver dec_lance_tc_driver = {
         },
 };
 
-static int __init dec_lance_tc_probe(struct device *dev)
+static int __devinit dec_lance_tc_probe(struct device *dev)
 {
         int status = dec_lance_probe(dev, PMAD_LANCE);
         if (!status)
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 3881918f5382..cea37e0837ff 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -1722,6 +1722,15 @@ static int __devinit igb_probe(struct pci_dev *pdev,
         u16 eeprom_apme_mask = IGB_EEPROM_APME;
         u32 part_num;
 
+        /* Catch broken hardware that put the wrong VF device ID in
+         * the PCIe SR-IOV capability.
+         */
+        if (pdev->is_virtfn) {
+                WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
+                     pci_name(pdev), pdev->vendor, pdev->device);
+                return -EINVAL;
+        }
+
         err = pci_enable_device_mem(pdev);
         if (err)
                 return err;
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 7b5d9764f317..74d9b6df3029 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -6492,6 +6492,15 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
 #endif
         u32 part_num, eec;
 
+        /* Catch broken hardware that put the wrong VF device ID in
+         * the PCIe SR-IOV capability.
+         */
+        if (pdev->is_virtfn) {
+                WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
+                     pci_name(pdev), pdev->vendor, pdev->device);
+                return -EINVAL;
+        }
+
         err = pci_enable_device_mem(pdev);
         if (err)
                 return err;
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 87e8d4cb4057..f15fe2cf72ae 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -499,7 +499,7 @@ static const struct net_device_ops macvlan_netdev_ops = {
         .ndo_validate_addr      = eth_validate_addr,
 };
 
-static void macvlan_setup(struct net_device *dev)
+void macvlan_common_setup(struct net_device *dev)
 {
         ether_setup(dev);
 
@@ -508,6 +508,12 @@ static void macvlan_setup(struct net_device *dev)
         dev->destructor         = free_netdev;
         dev->header_ops         = &macvlan_hard_header_ops,
         dev->ethtool_ops        = &macvlan_ethtool_ops;
+}
+EXPORT_SYMBOL_GPL(macvlan_common_setup);
+
+static void macvlan_setup(struct net_device *dev)
+{
+        macvlan_common_setup(dev);
         dev->tx_queue_len       = 0;
 }
 
@@ -705,7 +711,6 @@ int macvlan_link_register(struct rtnl_link_ops *ops)
         /* common fields */
         ops->priv_size          = sizeof(struct macvlan_dev);
         ops->get_tx_queues      = macvlan_get_tx_queues;
-        ops->setup              = macvlan_setup;
         ops->validate           = macvlan_validate;
         ops->maxtype            = IFLA_MACVLAN_MAX;
         ops->policy             = macvlan_policy;
@@ -719,6 +724,7 @@ EXPORT_SYMBOL_GPL(macvlan_link_register);
 
 static struct rtnl_link_ops macvlan_link_ops = {
         .kind           = "macvlan",
+        .setup          = macvlan_setup,
         .newlink        = macvlan_newlink,
         .dellink        = macvlan_dellink,
 };
diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c
index a8a94e2f6ddc..ff02b836c3c4 100644
--- a/drivers/net/macvtap.c
+++ b/drivers/net/macvtap.c
@@ -180,11 +180,18 @@ static int macvtap_forward(struct net_device *dev, struct sk_buff *skb)
 {
         struct macvtap_queue *q = macvtap_get_queue(dev, skb);
         if (!q)
-                return -ENOLINK;
+                goto drop;
+
+        if (skb_queue_len(&q->sk.sk_receive_queue) >= dev->tx_queue_len)
+                goto drop;
 
         skb_queue_tail(&q->sk.sk_receive_queue, skb);
         wake_up_interruptible_poll(sk_sleep(&q->sk), POLLIN | POLLRDNORM | POLLRDBAND);
-        return 0;
+        return NET_RX_SUCCESS;
+
+drop:
+        kfree_skb(skb);
+        return NET_RX_DROP;
 }
 
 /*
@@ -235,8 +242,15 @@ static void macvtap_dellink(struct net_device *dev,
         macvlan_dellink(dev, head);
 }
 
+static void macvtap_setup(struct net_device *dev)
+{
+        macvlan_common_setup(dev);
+        dev->tx_queue_len = TUN_READQ_SIZE;
+}
+
 static struct rtnl_link_ops macvtap_link_ops __read_mostly = {
         .kind           = "macvtap",
+        .setup          = macvtap_setup,
         .newlink        = macvtap_newlink,
         .dellink        = macvtap_dellink,
 };
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 5e52c75892df..7f3a53dcc6ef 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -65,7 +65,7 @@ static int debug_level = ERR_DBG;
 
 /* DEBUG message print. */
 #define DBG_PRINT(dbg_level, fmt, args...) do {                 \
-        if (dbg_level >= debug_level)                           \
+        if (dbg_level <= debug_level)                           \
                 pr_info(fmt, ##args);                           \
         } while (0)
 
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 6ad6fe706312..63042596f0cf 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -736,8 +736,18 @@ static __inline__ ssize_t tun_put_user(struct tun_struct *tun,
                                 gso.gso_type = VIRTIO_NET_HDR_GSO_TCPV6;
                         else if (sinfo->gso_type & SKB_GSO_UDP)
                                 gso.gso_type = VIRTIO_NET_HDR_GSO_UDP;
-                        else
-                                BUG();
+                        else {
+                                printk(KERN_ERR "tun: unexpected GSO type: "
+                                       "0x%x, gso_size %d, hdr_len %d\n",
+                                       sinfo->gso_type, gso.gso_size,
+                                       gso.hdr_len);
+                                print_hex_dump(KERN_ERR, "tun: ",
+                                               DUMP_PREFIX_NONE,
+                                               16, 1, skb->head,
+                                               min((int)gso.hdr_len, 64), true);
+                                WARN_ON_ONCE(1);
+                                return -EINVAL;
+                        }
                         if (sinfo->gso_type & SKB_GSO_TCP_ECN)
                                 gso.gso_type |= VIRTIO_NET_HDR_GSO_ECN;
                 } else
diff --git a/drivers/net/wimax/i2400m/i2400m-usb.h b/drivers/net/wimax/i2400m/i2400m-usb.h
index 2d7c96d7e865..eb80243e22df 100644
--- a/drivers/net/wimax/i2400m/i2400m-usb.h
+++ b/drivers/net/wimax/i2400m/i2400m-usb.h
@@ -152,6 +152,7 @@ enum {
         /* Device IDs */
         USB_DEVICE_ID_I6050 = 0x0186,
         USB_DEVICE_ID_I6050_2 = 0x0188,
+        USB_DEVICE_ID_I6250 = 0x0187,
 };
 
 
diff --git a/drivers/net/wimax/i2400m/usb.c b/drivers/net/wimax/i2400m/usb.c
index 0d5081d77dc0..d3365ac85dde 100644
--- a/drivers/net/wimax/i2400m/usb.c
+++ b/drivers/net/wimax/i2400m/usb.c
@@ -491,6 +491,7 @@ int i2400mu_probe(struct usb_interface *iface,
         switch (id->idProduct) {
         case USB_DEVICE_ID_I6050:
         case USB_DEVICE_ID_I6050_2:
+        case USB_DEVICE_ID_I6250:
                 i2400mu->i6050 = 1;
                 break;
         default:
@@ -739,6 +740,7 @@ static
 struct usb_device_id i2400mu_id_table[] = {
         { USB_DEVICE(0x8086, USB_DEVICE_ID_I6050) },
         { USB_DEVICE(0x8086, USB_DEVICE_ID_I6050_2) },
+        { USB_DEVICE(0x8086, USB_DEVICE_ID_I6250) },
         { USB_DEVICE(0x8086, 0x0181) },
         { USB_DEVICE(0x8086, 0x1403) },
         { USB_DEVICE(0x8086, 0x1405) },
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index ca6065b71b46..e3e52913d83a 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -844,9 +844,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
         int dma_type;
 
         if (edma)
-                dma_type = DMA_FROM_DEVICE;
-        else
                 dma_type = DMA_BIDIRECTIONAL;
+        else
+                dma_type = DMA_FROM_DEVICE;
 
         qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
         spin_lock_bh(&sc->rx.rxbuflock);
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index df4532e91b1a..f370476d5417 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -178,7 +178,6 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
                                unsigned long val,
                                struct cpufreq_freqs *freqs)
 {
-#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
         switch (val) {
         case CPUFREQ_PRECHANGE:
                 if (freqs->new > freqs->old) {
@@ -186,7 +185,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
                                "pre-updating\n",
                                freqs->new / 1000, (freqs->new / 100) % 10,
                                freqs->old / 1000, (freqs->old / 100) % 10);
-                        pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+                        pxa2xx_pcmcia_set_timing(skt);
                 }
                 break;
 
@@ -196,7 +195,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
                                "post-updating\n",
                                freqs->new / 1000, (freqs->new / 100) % 10,
                                freqs->old / 1000, (freqs->old / 100) % 10);
-                        pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+                        pxa2xx_pcmcia_set_timing(skt);
                 }
                 break;
         }
diff --git a/drivers/power/ds2782_battery.c b/drivers/power/ds2782_battery.c
index 2afbeec8b791..84d3c43cf2bc 100644
--- a/drivers/power/ds2782_battery.c
+++ b/drivers/power/ds2782_battery.c
@@ -43,10 +43,9 @@
 struct ds278x_info;
 
 struct ds278x_battery_ops {
-        int     (*get_current)(struct ds278x_info *info, int *current_uA);
-        int     (*get_voltage)(struct ds278x_info *info, int *voltage_uA);
-        int     (*get_capacity)(struct ds278x_info *info, int *capacity_uA);
-
+        int (*get_battery_current)(struct ds278x_info *info, int *current_uA);
+        int (*get_battery_voltage)(struct ds278x_info *info, int *voltage_uA);
+        int (*get_battery_capacity)(struct ds278x_info *info, int *capacity_uA);
 };
 
 #define to_ds278x_info(x) container_of(x, struct ds278x_info, battery)
@@ -213,11 +212,11 @@ static int ds278x_get_status(struct ds278x_info *info, int *status)
         int current_uA;
         int capacity;
 
-        err = info->ops->get_current(info, &current_uA);
+        err = info->ops->get_battery_current(info, &current_uA);
         if (err)
                 return err;
 
-        err = info->ops->get_capacity(info, &capacity);
+        err = info->ops->get_battery_capacity(info, &capacity);
         if (err)
                 return err;
 
@@ -246,15 +245,15 @@ static int ds278x_battery_get_property(struct power_supply *psy,
                 break;
 
         case POWER_SUPPLY_PROP_CAPACITY:
-                ret = info->ops->get_capacity(info, &val->intval);
+                ret = info->ops->get_battery_capacity(info, &val->intval);
                 break;
 
         case POWER_SUPPLY_PROP_VOLTAGE_NOW:
-                ret = info->ops->get_voltage(info, &val->intval);
+                ret = info->ops->get_battery_voltage(info, &val->intval);
                 break;
 
         case POWER_SUPPLY_PROP_CURRENT_NOW:
-                ret = info->ops->get_current(info, &val->intval);
+                ret = info->ops->get_battery_current(info, &val->intval);
                 break;
 
         case POWER_SUPPLY_PROP_TEMP:
@@ -307,14 +306,14 @@ enum ds278x_num_id {
 
 static struct ds278x_battery_ops ds278x_ops[] = {
         [DS2782] = {
-                .get_current  = ds2782_get_current,
-                .get_voltage  = ds2782_get_voltage,
-                .get_capacity = ds2782_get_capacity,
+                .get_battery_current  = ds2782_get_current,
+                .get_battery_voltage  = ds2782_get_voltage,
+                .get_battery_capacity = ds2782_get_capacity,
         },
         [DS2786] = {
-                .get_current  = ds2786_get_current,
-                .get_voltage  = ds2786_get_voltage,
-                .get_capacity = ds2786_get_capacity,
+                .get_battery_current  = ds2786_get_current,
+                .get_battery_voltage  = ds2786_get_voltage,
+                .get_battery_capacity = ds2786_get_capacity,
         }
 };
 
diff --git a/drivers/regulator/ab3100.c b/drivers/regulator/ab3100.c
index 7b14a67bdca2..11790990277a 100644
--- a/drivers/regulator/ab3100.c
+++ b/drivers/regulator/ab3100.c
@@ -286,7 +286,7 @@ static int ab3100_list_voltage_regulator(struct regulator_dev *reg,
 {
         struct ab3100_regulator *abreg = reg->reg_data;
 
-        if (selector > abreg->voltages_len)
+        if (selector >= abreg->voltages_len)
                 return -EINVAL;
         return abreg->typ_voltages[selector];
 }
@@ -318,7 +318,7 @@ static int ab3100_get_voltage_regulator(struct regulator_dev *reg)
         regval &= 0xE0;
         regval >>= 5;
 
-        if (regval > abreg->voltages_len) {
+        if (regval >= abreg->voltages_len) {
                 dev_err(&reg->dev,
                         "regulator register %02x contains an illegal voltage setting\n",
                         abreg->regreg);
diff --git a/drivers/regulator/tps6507x-regulator.c b/drivers/regulator/tps6507x-regulator.c
index 14b4576281c5..8152d65220f5 100644
--- a/drivers/regulator/tps6507x-regulator.c
+++ b/drivers/regulator/tps6507x-regulator.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/tps6507x.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/mfd/tps6507x.h>
@@ -101,9 +102,12 @@ struct tps_info {
         unsigned max_uV;
         u8 table_len;
         const u16 *table;
+
+        /* Does DCDC high or the low register defines output voltage? */
+        bool defdcdc_default;
 };
 
-static const struct tps_info tps6507x_pmic_regs[] = {
+static struct tps_info tps6507x_pmic_regs[] = {
         {
                 .name = "VDCDC1",
                 .min_uV = 725000,
@@ -145,7 +149,7 @@ struct tps6507x_pmic {
         struct regulator_desc desc[TPS6507X_NUM_REGULATOR];
         struct tps6507x_dev *mfd;
         struct regulator_dev *rdev[TPS6507X_NUM_REGULATOR];
-        const struct tps_info *info[TPS6507X_NUM_REGULATOR];
+        struct tps_info *info[TPS6507X_NUM_REGULATOR];
         struct mutex io_lock;
 };
 static inline int tps6507x_pmic_read(struct tps6507x_pmic *tps, u8 reg)
@@ -341,10 +345,16 @@ static int tps6507x_pmic_dcdc_get_voltage(struct regulator_dev *dev)
                 reg = TPS6507X_REG_DEFDCDC1;
                 break;
         case TPS6507X_DCDC_2:
-                reg = TPS6507X_REG_DEFDCDC2_LOW;
+                if (tps->info[dcdc]->defdcdc_default)
+                        reg = TPS6507X_REG_DEFDCDC2_HIGH;
+                else
+                        reg = TPS6507X_REG_DEFDCDC2_LOW;
                 break;
         case TPS6507X_DCDC_3:
-                reg = TPS6507X_REG_DEFDCDC3_LOW;
+                if (tps->info[dcdc]->defdcdc_default)
+                        reg = TPS6507X_REG_DEFDCDC3_HIGH;
+                else
+                        reg = TPS6507X_REG_DEFDCDC3_LOW;
                 break;
         default:
                 return -EINVAL;
@@ -370,10 +380,16 @@ static int tps6507x_pmic_dcdc_set_voltage(struct regulator_dev *dev,
                 reg = TPS6507X_REG_DEFDCDC1;
                 break;
         case TPS6507X_DCDC_2:
-                reg = TPS6507X_REG_DEFDCDC2_LOW;
+                if (tps->info[dcdc]->defdcdc_default)
+                        reg = TPS6507X_REG_DEFDCDC2_HIGH;
+                else
+                        reg = TPS6507X_REG_DEFDCDC2_LOW;
                 break;
         case TPS6507X_DCDC_3:
-                reg = TPS6507X_REG_DEFDCDC3_LOW;
+                if (tps->info[dcdc]->defdcdc_default)
+                        reg = TPS6507X_REG_DEFDCDC3_HIGH;
+                else
+                        reg = TPS6507X_REG_DEFDCDC3_LOW;
                 break;
         default:
                 return -EINVAL;
@@ -532,7 +548,7 @@ int tps6507x_pmic_probe(struct platform_device *pdev)
 {
         struct tps6507x_dev *tps6507x_dev = dev_get_drvdata(pdev->dev.parent);
         static int desc_id;
-        const struct tps_info *info = &tps6507x_pmic_regs[0];
+        struct tps_info *info = &tps6507x_pmic_regs[0];
         struct regulator_init_data *init_data;
         struct regulator_dev *rdev;
         struct tps6507x_pmic *tps;
@@ -569,6 +585,12 @@ int tps6507x_pmic_probe(struct platform_device *pdev)
         for (i = 0; i < TPS6507X_NUM_REGULATOR; i++, info++, init_data++) {
                 /* Register the regulators */
                 tps->info[i] = info;
+                if (init_data->driver_data) {
+                        struct tps6507x_reg_platform_data *data =
+                                                        init_data->driver_data;
+                        tps->info[i]->defdcdc_default = data->defdcdc_default;
+                }
+
                 tps->desc[i].name = info->name;
                 tps->desc[i].id = desc_id++;
                 tps->desc[i].n_voltages = num_voltages[i];
diff --git a/drivers/regulator/wm8350-regulator.c b/drivers/regulator/wm8350-regulator.c
index 723cd1fb4867..0e6ed7db9364 100644
--- a/drivers/regulator/wm8350-regulator.c
+++ b/drivers/regulator/wm8350-regulator.c
@@ -1495,7 +1495,7 @@ int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
         if (ret != 0) {
                 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
                         reg, ret);
-                platform_device_del(pdev);
+                platform_device_put(pdev);
                 wm8350->pmic.pdev[reg] = NULL;
         }
 
diff --git a/drivers/rtc/rtc-rx8581.c b/drivers/rtc/rtc-rx8581.c
index 9718aaaa8215..600b890a3c15 100644
--- a/drivers/rtc/rtc-rx8581.c
+++ b/drivers/rtc/rtc-rx8581.c
@@ -168,7 +168,7 @@ static int rx8581_set_datetime(struct i2c_client *client, struct rtc_time *tm)
                 return -EIO;
         }
 
-        err = i2c_smbus_write_byte_data(client, RX8581_REG_FLAG,
+        err = i2c_smbus_write_byte_data(client, RX8581_REG_CTRL,
                 (data | RX8581_CTRL_STOP));
         if (err < 0) {
                 dev_err(&client->dev, "Unable to write control register\n");
@@ -182,6 +182,20 @@ static int rx8581_set_datetime(struct i2c_client *client, struct rtc_time *tm)
                 return -EIO;
         }
 
+        /* get VLF and clear it */
+        data = i2c_smbus_read_byte_data(client, RX8581_REG_FLAG);
+        if (data < 0) {
+                dev_err(&client->dev, "Unable to read flag register\n");
+                return -EIO;
+        }
+
+        err = i2c_smbus_write_byte_data(client, RX8581_REG_FLAG,
+                (data & ~(RX8581_FLAG_VLF)));
+        if (err != 0) {
+                dev_err(&client->dev, "Unable to write flag register\n");
+                return -EIO;
+        }
+
         /* Restart the clock */
         data = i2c_smbus_read_byte_data(client, RX8581_REG_CTRL);
         if (data < 0) {
@@ -189,8 +203,8 @@ static int rx8581_set_datetime(struct i2c_client *client, struct rtc_time *tm)
                 return -EIO;
         }
 
-        err = i2c_smbus_write_byte_data(client, RX8581_REG_FLAG,
-                (data | ~(RX8581_CTRL_STOP)));
+        err = i2c_smbus_write_byte_data(client, RX8581_REG_CTRL,
+                (data & ~(RX8581_CTRL_STOP)));
         if (err != 0) {
                 dev_err(&client->dev, "Unable to write control register\n");
                 return -EIO;
diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
index e3dbeda97179..fd068bc1bd0a 100644
--- a/drivers/s390/scsi/zfcp_erp.c
+++ b/drivers/s390/scsi/zfcp_erp.c
@@ -714,6 +714,14 @@ static int zfcp_erp_adapter_strategy_open_fsf(struct zfcp_erp_action *act)
         if (zfcp_erp_adapter_strategy_open_fsf_xport(act) == ZFCP_ERP_FAILED)
                 return ZFCP_ERP_FAILED;
 
+        if (mempool_resize(act->adapter->pool.status_read_data,
+                           act->adapter->stat_read_buf_num, GFP_KERNEL))
+                return ZFCP_ERP_FAILED;
+
+        if (mempool_resize(act->adapter->pool.status_read_req,
+                           act->adapter->stat_read_buf_num, GFP_KERNEL))
+                return ZFCP_ERP_FAILED;
+
         atomic_set(&act->adapter->stat_miss, act->adapter->stat_read_buf_num);
         if (zfcp_status_read_refill(act->adapter))
                 return ZFCP_ERP_FAILED;
diff --git a/drivers/s390/scsi/zfcp_fsf.c b/drivers/s390/scsi/zfcp_fsf.c
index 9ac6a6e4a604..71663fb77310 100644
--- a/drivers/s390/scsi/zfcp_fsf.c
+++ b/drivers/s390/scsi/zfcp_fsf.c
@@ -496,7 +496,8 @@ static int zfcp_fsf_exchange_config_evaluate(struct zfcp_fsf_req *req)
 
         adapter->hydra_version = bottom->adapter_type;
         adapter->timer_ticks = bottom->timer_interval;
-        adapter->stat_read_buf_num = max(bottom->status_read_buf_num, (u16)16);
+        adapter->stat_read_buf_num = max(bottom->status_read_buf_num,
+                                         (u16)FSF_STATUS_READS_RECOM);
 
         if (fc_host_permanent_port_name(shost) == -1)
                 fc_host_permanent_port_name(shost) = fc_host_port_name(shost);
@@ -719,11 +720,6 @@ static struct zfcp_fsf_req *zfcp_fsf_req_create(struct zfcp_qdio *qdio,
         zfcp_qdio_req_init(adapter->qdio, &req->qdio_req, req->req_id, sbtype,
                            req->qtcb, sizeof(struct fsf_qtcb));
 
-        if (!(atomic_read(&adapter->status) & ZFCP_STATUS_ADAPTER_QDIOUP)) {
-                zfcp_fsf_req_free(req);
-                return ERR_PTR(-EIO);
-        }
-
         return req;
 }
 
@@ -981,7 +977,7 @@ static int zfcp_fsf_setup_ct_els_sbals(struct zfcp_fsf_req *req,
         }
 
         /* use single, unchained SBAL if it can hold the request */
-        if (zfcp_qdio_sg_one_sbale(sg_req) || zfcp_qdio_sg_one_sbale(sg_resp)) {
+        if (zfcp_qdio_sg_one_sbale(sg_req) && zfcp_qdio_sg_one_sbale(sg_resp)) {
                 zfcp_fsf_setup_ct_els_unchained(adapter->qdio, &req->qdio_req,
                                                 sg_req, sg_resp);
                 return 0;
diff --git a/drivers/s390/scsi/zfcp_qdio.c b/drivers/s390/scsi/zfcp_qdio.c
index 28117e130e2c..6fa5e0453176 100644
--- a/drivers/s390/scsi/zfcp_qdio.c
+++ b/drivers/s390/scsi/zfcp_qdio.c
@@ -251,7 +251,8 @@ static int zfcp_qdio_sbal_check(struct zfcp_qdio *qdio)
         struct zfcp_qdio_queue *req_q = &qdio->req_q;
 
         spin_lock_bh(&qdio->req_q_lock);
-        if (atomic_read(&req_q->count))
+        if (atomic_read(&req_q->count) ||
+            !(atomic_read(&qdio->adapter->status) & ZFCP_STATUS_ADAPTER_QDIOUP))
                 return 1;
         spin_unlock_bh(&qdio->req_q_lock);
         return 0;
@@ -274,8 +275,13 @@ int zfcp_qdio_sbal_get(struct zfcp_qdio *qdio)
         spin_unlock_bh(&qdio->req_q_lock);
         ret = wait_event_interruptible_timeout(qdio->req_q_wq,
                                zfcp_qdio_sbal_check(qdio), 5 * HZ);
+
+        if (!(atomic_read(&qdio->adapter->status) & ZFCP_STATUS_ADAPTER_QDIOUP))
+                return -EIO;
+
         if (ret > 0)
                 return 0;
+
         if (!ret) {
                 atomic_inc(&qdio->req_q_full);
                 /* assume hanging outbound queue, try queue recovery */
@@ -375,6 +381,8 @@ void zfcp_qdio_close(struct zfcp_qdio *qdio)
         atomic_clear_mask(ZFCP_STATUS_ADAPTER_QDIOUP, &qdio->adapter->status);
         spin_unlock_bh(&qdio->req_q_lock);
 
+        wake_up(&qdio->req_q_wq);
+
         qdio_shutdown(qdio->adapter->ccw_device,
                       QDIO_FLAG_CLEANUP_USING_CLEAR);
 
diff --git a/drivers/scsi/ibmvscsi/rpa_vscsi.c b/drivers/scsi/ibmvscsi/rpa_vscsi.c
index a864ccc0a342..989b9a8ba72d 100644
--- a/drivers/scsi/ibmvscsi/rpa_vscsi.c
+++ b/drivers/scsi/ibmvscsi/rpa_vscsi.c
@@ -277,6 +277,12 @@ static int rpavscsi_init_crq_queue(struct crq_queue *queue,
                 goto reg_crq_failed;
         }
 
+        queue->cur = 0;
+        spin_lock_init(&queue->lock);
+
+        tasklet_init(&hostdata->srp_task, (void *)rpavscsi_task,
+                     (unsigned long)hostdata);
+
         if (request_irq(vdev->irq,
                         rpavscsi_handle_event,
                         0, "ibmvscsi", (void *)hostdata) != 0) {
@@ -291,15 +297,10 @@ static int rpavscsi_init_crq_queue(struct crq_queue *queue,
                 goto req_irq_failed;
         }
 
-        queue->cur = 0;
-        spin_lock_init(&queue->lock);
-
-        tasklet_init(&hostdata->srp_task, (void *)rpavscsi_task,
-                     (unsigned long)hostdata);
-
         return retrc;
 
       req_irq_failed:
+        tasklet_kill(&hostdata->srp_task);
         do {
                 rc = plpar_hcall_norets(H_FREE_CRQ, vdev->unit_address);
         } while ((rc == H_BUSY) || (H_IS_LONG_BUSY(rc)));
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c
index 82ea4a8226b0..f820cffb7f00 100644
--- a/drivers/scsi/ipr.c
+++ b/drivers/scsi/ipr.c
@@ -1129,20 +1129,22 @@ static int ipr_is_same_device(struct ipr_resource_entry *res,
 }
 
 /**
- * ipr_format_resource_path - Format the resource path for printing.
+ * ipr_format_res_path - Format the resource path for printing.
  * @res_path:   resource path
  * @buf:        buffer
  *
  * Return value:
  *      pointer to buffer
  **/
-static char *ipr_format_resource_path(u8 *res_path, char *buffer)
+static char *ipr_format_res_path(u8 *res_path, char *buffer, int len)
 {
         int i;
+        char *p = buffer;
 
-        sprintf(buffer, "%02X", res_path[0]);
-        for (i=1; res_path[i] != 0xff; i++)
-                sprintf(buffer, "%s-%02X", buffer, res_path[i]);
+        res_path[0] = '\0';
+        p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
+        for (i = 1; res_path[i] != 0xff && ((i * 3) < len); i++)
+                p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
 
         return buffer;
 }
@@ -1187,7 +1189,8 @@ static void ipr_update_res_entry(struct ipr_resource_entry *res,
 
                 if (res->sdev && new_path)
                         sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
-                                    ipr_format_resource_path(&res->res_path[0], &buffer[0]));
+                                    ipr_format_res_path(res->res_path, buffer,
+                                                        sizeof(buffer)));
         } else {
                 res->flags = cfgtew->u.cfgte->flags;
                 if (res->flags & IPR_IS_IOA_RESOURCE)
@@ -1573,7 +1576,8 @@ static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg,
                 ipr_err_separator;
 
                 ipr_err("Device %d : %s", i + 1,
-                         ipr_format_resource_path(&dev_entry->res_path[0], &buffer[0]));
+                         ipr_format_res_path(dev_entry->res_path, buffer,
+                                             sizeof(buffer)));
                 ipr_log_ext_vpd(&dev_entry->vpd);
 
                 ipr_err("-----New Device Information-----\n");
@@ -1919,13 +1923,14 @@ static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb,
 
                         ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
                                      path_active_desc[i].desc, path_state_desc[j].desc,
-                                     ipr_format_resource_path(&fabric->res_path[0], &buffer[0]));
+                                     ipr_format_res_path(fabric->res_path, buffer,
+                                                         sizeof(buffer)));
                         return;
                 }
         }
 
         ipr_err("Path state=%02X Resource Path=%s\n", path_state,
-                ipr_format_resource_path(&fabric->res_path[0], &buffer[0]));
+                ipr_format_res_path(fabric->res_path, buffer, sizeof(buffer)));
 }
 
 static const struct {
@@ -2066,7 +2071,8 @@ static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
 
                         ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
                                      path_status_desc[j].desc, path_type_desc[i].desc,
-                                     ipr_format_resource_path(&cfg->res_path[0], &buffer[0]),
+                                     ipr_format_res_path(cfg->res_path, buffer,
+                                                         sizeof(buffer)),
                                      link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
                                      be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
                         return;
@@ -2074,7 +2080,7 @@ static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
         }
         ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
                      "WWN=%08X%08X\n", cfg->type_status,
-                     ipr_format_resource_path(&cfg->res_path[0], &buffer[0]),
+                     ipr_format_res_path(cfg->res_path, buffer, sizeof(buffer)),
                      link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
                      be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
 }
@@ -2139,7 +2145,7 @@ static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
 
         ipr_err("RAID %s Array Configuration: %s\n",
                 error->protection_level,
-                ipr_format_resource_path(&error->last_res_path[0], &buffer[0]));
+                ipr_format_res_path(error->last_res_path, buffer, sizeof(buffer)));
 
         ipr_err_separator;
 
@@ -2160,9 +2166,11 @@ static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
                 ipr_err("Array Member %d:\n", i);
                 ipr_log_ext_vpd(&array_entry->vpd);
                 ipr_err("Current Location: %s",
-                         ipr_format_resource_path(&array_entry->res_path[0], &buffer[0]));
+                         ipr_format_res_path(array_entry->res_path, buffer,
+                                             sizeof(buffer)));
                 ipr_err("Expected Location: %s",
-                         ipr_format_resource_path(&array_entry->expected_res_path[0], &buffer[0]));
+                         ipr_format_res_path(array_entry->expected_res_path,
+                                             buffer, sizeof(buffer)));
 
                 ipr_err_separator;
         }
@@ -4079,7 +4087,8 @@ static struct device_attribute ipr_adapter_handle_attr = {
 };
 
 /**
- * ipr_show_resource_path - Show the resource path for this device.
+ * ipr_show_resource_path - Show the resource path or the resource address for
+ *                          this device.
  * @dev:        device struct
  * @buf:        buffer
  *
@@ -4097,9 +4106,14 @@ static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribut
 
         spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
         res = (struct ipr_resource_entry *)sdev->hostdata;
-        if (res)
+        if (res && ioa_cfg->sis64)
                 len = snprintf(buf, PAGE_SIZE, "%s\n",
-                               ipr_format_resource_path(&res->res_path[0], &buffer[0]));
+                               ipr_format_res_path(res->res_path, buffer,
+                                                   sizeof(buffer)));
+        else if (res)
+                len = snprintf(buf, PAGE_SIZE, "%d:%d:%d:%d\n", ioa_cfg->host->host_no,
+                               res->bus, res->target, res->lun);
+
         spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
         return len;
 }
@@ -4351,7 +4365,8 @@ static int ipr_slave_configure(struct scsi_device *sdev)
                         scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
                 if (ioa_cfg->sis64)
                         sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
-                                    ipr_format_resource_path(&res->res_path[0], &buffer[0]));
+                                    ipr_format_res_path(res->res_path, buffer,
+                                                        sizeof(buffer)));
                 return 0;
         }
         spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h
index 9ecd2259eb39..b965f3587c9d 100644
--- a/drivers/scsi/ipr.h
+++ b/drivers/scsi/ipr.h
@@ -1684,8 +1684,9 @@ struct ipr_ucode_image_header {
         if (ipr_is_device(hostrcb)) {                                   \
                 if ((hostrcb)->ioa_cfg->sis64) {                        \
                         printk(KERN_ERR IPR_NAME ": %s: " fmt,          \
-                                ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
-                                        &hostrcb->rp_buffer[0]),        \
+                                ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
+                                        hostrcb->rp_buffer,             \
+                                        sizeof(hostrcb->rp_buffer)),    \
                                 __VA_ARGS__);                           \
                 } else {                                                \
                         ipr_ra_err((hostrcb)->ioa_cfg,                  \
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index eed3c2d8dd1c..a182def7007d 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -41,6 +41,7 @@
 #include <linux/uaccess.h>
 
 #include <asm/io.h>
+#include <asm/ioctls.h>
 
 #include <asm/mach/serial_at91.h>
 #include <mach/board.h>
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index 61d75507d5d0..162c95a088ed 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -1596,6 +1596,7 @@ static const struct usb_device_id acm_ids[] = {
         { NOKIA_PCSUITE_ACM_INFO(0x00e9), }, /* Nokia 5320 XpressMusic */
         { NOKIA_PCSUITE_ACM_INFO(0x0108), }, /* Nokia 5320 XpressMusic 2G */
         { NOKIA_PCSUITE_ACM_INFO(0x01f5), }, /* Nokia N97, RM-505 */
+        { NOKIA_PCSUITE_ACM_INFO(0x02e3), }, /* Nokia 5230, RM-588 */
 
         /* NOTE: non-Nokia COMM/ACM/0xff is likely MSFT RNDIS... NOT a modem! */
 
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 83e7bbbe97fa..70cccc75a362 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -1982,6 +1982,8 @@ static int hub_port_wait_reset(struct usb_hub *hub, int port1,
                     (portstatus & USB_PORT_STAT_ENABLE)) {
                         if (hub_is_wusb(hub))
                                 udev->speed = USB_SPEED_WIRELESS;
+                        else if (portstatus & USB_PORT_STAT_SUPER_SPEED)
+                                udev->speed = USB_SPEED_SUPER;
                         else if (portstatus & USB_PORT_STAT_HIGH_SPEED)
                                 udev->speed = USB_SPEED_HIGH;
                         else if (portstatus & USB_PORT_STAT_LOW_SPEED)
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index f22d03df8b17..db99c084df92 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -41,6 +41,10 @@ static const struct usb_device_id usb_quirk_list[] = {
         /* Philips PSC805 audio device */
         { USB_DEVICE(0x0471, 0x0155), .driver_info = USB_QUIRK_RESET_RESUME },
 
+        /* Artisman Watchdog Dongle */
+        { USB_DEVICE(0x04b4, 0x0526), .driver_info =
+                        USB_QUIRK_CONFIG_INTF_STRINGS },
+
         /* Roland SC-8820 */
         { USB_DEVICE(0x0582, 0x0007), .driver_info = USB_QUIRK_RESET_RESUME },
 
@@ -64,6 +68,9 @@ static const struct usb_device_id usb_quirk_list[] = {
         /* X-Rite/Gretag-Macbeth Eye-One Pro display colorimeter */
         { USB_DEVICE(0x0971, 0x2000), .driver_info = USB_QUIRK_NO_SET_INTF },
 
+        /* Broadcom BCM92035DGROM BT dongle */
+        { USB_DEVICE(0x0a5c, 0x2021), .driver_info = USB_QUIRK_RESET_RESUME },
+
         /* Action Semiconductor flash disk */
         { USB_DEVICE(0x10d6, 0x2200), .driver_info =
                         USB_QUIRK_STRING_FETCH_255 },
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 85b0d8921eae..980762453a9c 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -2561,7 +2561,7 @@ static void pxa_udc_shutdown(struct platform_device *_dev)
                 udc_disable(udc);
 }
 
-#ifdef CONFIG_CPU_PXA27x
+#ifdef CONFIG_PXA27x
 extern void pxa27x_clear_otgph(void);
 #else
 #define pxa27x_clear_otgph()   do {} while (0)
diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
index e724a051bfdd..ea2b3c7ebee5 100644
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -735,6 +735,10 @@ static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
         else
                 dev->ep0state = EP0_OUT_DATA_PHASE;
 
+        if (!dev->driver)
+                return;
+
+        /* deliver the request to the gadget driver */
         ret = dev->driver->setup(&dev->gadget, crq);
         if (ret < 0) {
                 if (dev->req_config) {
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index a18debdd79b8..418163894775 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -203,7 +203,7 @@ static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
         __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
 }
 
-#ifdef CONFIG_CPU_PXA27x
+#ifdef CONFIG_PXA27x
 extern void pxa27x_clear_otgph(void);
 #else
 #define pxa27x_clear_otgph()    do {} while (0)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index fd9e03afd91c..2eb658d26394 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -835,6 +835,27 @@ fail:
         return 0;
 }
 
+void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
+                struct usb_device *udev)
+{
+        struct xhci_virt_device *virt_dev;
+        struct xhci_ep_ctx      *ep0_ctx;
+        struct xhci_ring        *ep_ring;
+
+        virt_dev = xhci->devs[udev->slot_id];
+        ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
+        ep_ring = virt_dev->eps[0].ring;
+        /*
+         * FIXME we don't keep track of the dequeue pointer very well after a
+         * Set TR dequeue pointer, so we're setting the dequeue pointer of the
+         * host to our enqueue pointer.  This should only be called after a
+         * configured device has reset, so all control transfers should have
+         * been completed or cancelled before the reset.
+         */
+        ep0_ctx->deq = xhci_trb_virt_to_dma(ep_ring->enq_seg, ep_ring->enqueue);
+        ep0_ctx->deq |= ep_ring->cycle_state;
+}
+
 /* Setup an xHCI virtual device for a Set Address command */
 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 {
@@ -1002,7 +1023,7 @@ static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
         return EP_INTERVAL(interval);
 }
 
-/* The "Mult" field in the endpoint context is only set for SuperSpeed devices.
+/* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  * High speed endpoint descriptors can define "the number of additional
  * transaction opportunities per microframe", but that goes in the Max Burst
  * endpoint context field.
@@ -1010,7 +1031,8 @@ static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
 static inline u32 xhci_get_endpoint_mult(struct usb_device *udev,
                 struct usb_host_endpoint *ep)
 {
-        if (udev->speed != USB_SPEED_SUPER)
+        if (udev->speed != USB_SPEED_SUPER ||
+                        !usb_endpoint_xfer_isoc(&ep->desc))
                 return 0;
         return ep->ss_ep_comp.bmAttributes;
 }
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 94e6934edb09..bfc99a939455 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -2380,16 +2380,19 @@ static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
                 u32 field3, u32 field4, bool command_must_succeed)
 {
         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
+        int ret;
+
         if (!command_must_succeed)
                 reserved_trbs++;
 
-        if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
-                if (!in_interrupt())
-                        xhci_err(xhci, "ERR: No room for command on command ring\n");
+        ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
+                        reserved_trbs, GFP_ATOMIC);
+        if (ret < 0) {
+                xhci_err(xhci, "ERR: No room for command on command ring\n");
                 if (command_must_succeed)
                         xhci_err(xhci, "ERR: Reserved TRB counting for "
                                         "unfailable commands failed.\n");
-                return -ENOMEM;
+                return ret;
         }
         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
                         field4 | xhci->cmd_ring->cycle_state);
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 27345cd04da0..3998f72cd0c4 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -2134,6 +2134,8 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
         /* If this is a Set Address to an unconfigured device, setup ep 0 */
         if (!udev->config)
                 xhci_setup_addressable_virt_dev(xhci, udev);
+        else
+                xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
         /* Otherwise, assume the core has the device configured how it wants */
         xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
         xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 8b4b7d39f79c..6c7e3430ec93 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1292,6 +1292,8 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
+void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
+                struct usb_device *udev);
 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
diff --git a/drivers/usb/misc/sisusbvga/sisusb.c b/drivers/usb/misc/sisusbvga/sisusb.c
index 30d930386b65..d25814c172b2 100644
--- a/drivers/usb/misc/sisusbvga/sisusb.c
+++ b/drivers/usb/misc/sisusbvga/sisusb.c
@@ -2436,7 +2436,8 @@ sisusb_open(struct inode *inode, struct file *file)
         }
 
         if (!sisusb->devinit) {
-                if (sisusb->sisusb_dev->speed == USB_SPEED_HIGH) {
+                if (sisusb->sisusb_dev->speed == USB_SPEED_HIGH ||
+                    sisusb->sisusb_dev->speed == USB_SPEED_SUPER) {
                         if (sisusb_init_gfxdevice(sisusb, 0)) {
                                 mutex_unlock(&sisusb->lock);
                                 dev_err(&sisusb->sisusb_dev->dev, "Failed to initialize device\n");
@@ -3166,7 +3167,7 @@ static int sisusb_probe(struct usb_interface *intf,
 
         sisusb->present = 1;
 
-        if (dev->speed == USB_SPEED_HIGH) {
+        if (dev->speed == USB_SPEED_HIGH || dev->speed == USB_SPEED_SUPER) {
                 int initscreen = 1;
 #ifdef INCL_SISUSB_CON
                 if (sisusb_first_vc > 0 &&
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 05c077f8f9ac..3c48e77a0aa2 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -29,19 +29,6 @@ static void tusb_source_power(struct musb *musb, int is_on);
 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
 
-#ifdef CONFIG_PM
-/* REVISIT: These should be only needed if somebody implements off idle */
-void musb_platform_save_context(struct musb *musb,
-                        struct musb_context_registers *musb_context)
-{
-}
-
-void musb_platform_restore_context(struct musb *musb,
-                        struct musb_context_registers *musb_context)
-{
-}
-#endif
-
 /*
  * Checks the revision. We need to use the DMA register as 3.0 does not
  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index da7e334b0407..e298dc4baed7 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -691,6 +691,7 @@ static struct usb_device_id id_table_combined [] = {
         { USB_DEVICE(FTDI_VID, FTDI_NDI_AURORA_SCU_PID),
                 .driver_info = (kernel_ulong_t)&ftdi_NDI_device_quirk },
         { USB_DEVICE(TELLDUS_VID, TELLDUS_TELLSTICK_PID) },
+        { USB_DEVICE(RTSYSTEMS_VID, RTSYSTEMS_SERIAL_VX7_PID) },
         { USB_DEVICE(FTDI_VID, FTDI_MAXSTREAM_PID) },
         { USB_DEVICE(FTDI_VID, FTDI_PHI_FISCO_PID) },
         { USB_DEVICE(TML_VID, TML_USB_SERIAL_PID) },
@@ -737,6 +738,14 @@ static struct usb_device_id id_table_combined [] = {
         { USB_DEVICE(FTDI_VID, MJSG_SR_RADIO_PID) },
         { USB_DEVICE(FTDI_VID, MJSG_HD_RADIO_PID) },
         { USB_DEVICE(FTDI_VID, MJSG_XM_RADIO_PID) },
+        { USB_DEVICE(FTDI_VID, XVERVE_SIGNALYZER_ST_PID),
+                .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
+        { USB_DEVICE(FTDI_VID, XVERVE_SIGNALYZER_SLITE_PID),
+                .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
+        { USB_DEVICE(FTDI_VID, XVERVE_SIGNALYZER_SH2_PID),
+                .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
+        { USB_DEVICE(FTDI_VID, XVERVE_SIGNALYZER_SH4_PID),
+                .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
         { },                                    /* Optional parameter entry */
         { }                                     /* Terminating entry */
 };
diff --git a/drivers/usb/serial/ftdi_sio_ids.h b/drivers/usb/serial/ftdi_sio_ids.h
index bbc159a1df45..d01946db8fac 100644
--- a/drivers/usb/serial/ftdi_sio_ids.h
+++ b/drivers/usb/serial/ftdi_sio_ids.h
@@ -696,6 +696,12 @@
 #define TELLDUS_TELLSTICK_PID           0x0C30  /* RF control dongle 433 MHz using FT232RL */
 
 /*
+ * RT Systems programming cables for various ham radios
+ */
+#define RTSYSTEMS_VID                   0x2100  /* Vendor ID */
+#define RTSYSTEMS_SERIAL_VX7_PID        0x9e52  /* Serial converter for VX-7 Radios using FT232RL */
+
+/*
  * Bayer Ascensia Contour blood glucose meter USB-converter cable.
  * http://winglucofacts.com/cables/
  */
@@ -1017,3 +1023,12 @@
 #define MJSG_SR_RADIO_PID       0x9379
 #define MJSG_XM_RADIO_PID       0x937A
 #define MJSG_HD_RADIO_PID       0x937C
+
+/*
+ * Xverve Signalyzer tools (http://www.signalyzer.com/)
+ */
+#define XVERVE_SIGNALYZER_ST_PID        0xBCA0
+#define XVERVE_SIGNALYZER_SLITE_PID     0xBCA1
+#define XVERVE_SIGNALYZER_SH2_PID       0xBCA2
+#define XVERVE_SIGNALYZER_SH4_PID       0xBCA4
+
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index e280ad8e12f7..5cd30e4345c6 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -206,6 +206,7 @@ static void option_instat_callback(struct urb *urb);
 #define AMOI_PRODUCT_H01                        0x0800
 #define AMOI_PRODUCT_H01A                       0x7002
 #define AMOI_PRODUCT_H02                        0x0802
+#define AMOI_PRODUCT_SKYPEPHONE_S2              0x0407
 
 #define DELL_VENDOR_ID                          0x413C
 
@@ -302,6 +303,7 @@ static void option_instat_callback(struct urb *urb);
 #define QISDA_PRODUCT_H21_4512                  0x4512
 #define QISDA_PRODUCT_H21_4523                  0x4523
 #define QISDA_PRODUCT_H20_4515                  0x4515
+#define QISDA_PRODUCT_H20_4518                  0x4518
 #define QISDA_PRODUCT_H20_4519                  0x4519
 
 /* TLAYTECH PRODUCTS */
@@ -516,6 +518,7 @@ static const struct usb_device_id option_ids[] = {
         { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_H01) },
         { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_H01A) },
         { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_H02) },
+        { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_SKYPEPHONE_S2) },
 
         { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5700_MINICARD) },             /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO Mini-Card == Novatel Expedite EV620 CDMA/EV-DO */
         { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5500_MINICARD) },             /* Dell Wireless 5500 Mobile Broadband HSDPA Mini-Card == Novatel Expedite EU740 HSDPA/3G */
@@ -852,6 +855,7 @@ static const struct usb_device_id option_ids[] = {
         { USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H21_4512) },
         { USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H21_4523) },
         { USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H20_4515) },
+        { USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H20_4518) },
         { USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H20_4519) },
         { USB_DEVICE(TOSHIBA_VENDOR_ID, TOSHIBA_PRODUCT_G450) },
         { USB_DEVICE(TOSHIBA_VENDOR_ID, TOSHIBA_PRODUCT_HSDPA_MINICARD ) }, /* Toshiba 3G HSDPA == Novatel Expedite EU870D MiniCard */
diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c
index 93d72eb8cafc..cde67cacb2c3 100644
--- a/drivers/usb/serial/qcserial.c
+++ b/drivers/usb/serial/qcserial.c
@@ -51,6 +51,8 @@ static const struct usb_device_id id_table[] = {
         {USB_DEVICE(0x1f45, 0x0001)},   /* Unknown Gobi QDL device */
         {USB_DEVICE(0x413c, 0x8185)},   /* Dell Gobi 2000 QDL device (N0218, VU936) */
         {USB_DEVICE(0x413c, 0x8186)},   /* Dell Gobi 2000 Modem device (N0218, VU936) */
+        {USB_DEVICE(0x05c6, 0x9208)},   /* Generic Gobi 2000 QDL device */
+        {USB_DEVICE(0x05c6, 0x920b)},   /* Generic Gobi 2000 Modem device */
         {USB_DEVICE(0x05c6, 0x9224)},   /* Sony Gobi 2000 QDL device (N0279, VU730) */
         {USB_DEVICE(0x05c6, 0x9225)},   /* Sony Gobi 2000 Modem device (N0279, VU730) */
         {USB_DEVICE(0x05c6, 0x9244)},   /* Samsung Gobi 2000 QDL device (VL176) */
diff --git a/drivers/usb/serial/sierra.c b/drivers/usb/serial/sierra.c
index ef0bdb08d788..d47b56e9e8ce 100644
--- a/drivers/usb/serial/sierra.c
+++ b/drivers/usb/serial/sierra.c
@@ -245,6 +245,7 @@ static const struct usb_device_id id_table[] = {
         { USB_DEVICE(0x1199, 0x0021) }, /* Sierra Wireless AirCard 597E */
         { USB_DEVICE(0x1199, 0x0112) }, /* Sierra Wireless AirCard 580 */
         { USB_DEVICE(0x1199, 0x0120) }, /* Sierra Wireless USB Dongle 595U */
+        { USB_DEVICE(0x1199, 0x0301) }, /* Sierra Wireless USB Dongle 250U */
         /* Sierra Wireless C597 */
         { USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x0023, 0xFF, 0xFF, 0xFF) },
         /* Sierra Wireless T598 */
diff --git a/drivers/usb/storage/transport.c b/drivers/usb/storage/transport.c
index 44716427c51c..64ec073e89de 100644
--- a/drivers/usb/storage/transport.c
+++ b/drivers/usb/storage/transport.c
@@ -139,9 +139,7 @@ static int usb_stor_msg_common(struct us_data *us, int timeout)
 
         /* fill the common fields in the URB */
         us->current_urb->context = &urb_done;
-        us->current_urb->actual_length = 0;
-        us->current_urb->error_count = 0;
-        us->current_urb->status = 0;
+        us->current_urb->transfer_flags = 0;
 
         /* we assume that if transfer_buffer isn't us->iobuf then it
          * hasn't been mapped for DMA.  Yes, this is clunky, but it's
diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c
index 40f61320ce16..34b2fc472fe8 100644
--- a/drivers/video/au1100fb.c
+++ b/drivers/video/au1100fb.c
@@ -95,7 +95,7 @@ struct fb_bitfield rgb_bitfields[][4] =
         { { 8, 4, 0 },  { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
 };
 
-static struct fb_fix_screeninfo au1100fb_fix __initdata = {
+static struct fb_fix_screeninfo au1100fb_fix __devinitdata = {
         .id             = "AU1100 FB",
         .xpanstep       = 1,
         .ypanstep       = 1,
@@ -103,7 +103,7 @@ static struct fb_fix_screeninfo au1100fb_fix __initdata = {
         .accel          = FB_ACCEL_NONE,
 };
 
-static struct fb_var_screeninfo au1100fb_var __initdata = {
+static struct fb_var_screeninfo au1100fb_var __devinitdata = {
         .activate       = FB_ACTIVATE_NOW,
         .height         = -1,
         .width          = -1,
@@ -458,7 +458,7 @@ static struct fb_ops au1100fb_ops =
 
 /* AU1100 LCD controller device driver */
 
-static int __init au1100fb_drv_probe(struct platform_device *dev)
+static int __devinit au1100fb_drv_probe(struct platform_device *dev)
 {
         struct au1100fb_device *fbdev = NULL;
         struct resource *regs_res;
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c
index 3a561df2e8a2..0c1afd13ddd3 100644
--- a/drivers/video/cyber2000fb.c
+++ b/drivers/video/cyber2000fb.c
@@ -388,6 +388,7 @@ cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
                 pseudo_val |= convert_bitfield(red, &var->red);
                 pseudo_val |= convert_bitfield(green, &var->green);
                 pseudo_val |= convert_bitfield(blue, &var->blue);
+                ret = 0;
                 break;
         }
 
@@ -436,6 +437,8 @@ static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
         cyber2000fb_writeb(i | 4, 0x3cf, cfb);
         cyber2000fb_writeb(val, 0x3c6, cfb);
         cyber2000fb_writeb(i, 0x3cf, cfb);
+        /* prevent card lock-up observed on x86 with CyberPro 2000 */
+        cyber2000fb_readb(0x3cf, cfb);
 }
 
 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c
index 7d8c55d7fd28..ca3355e430bf 100644
--- a/drivers/video/gbefb.c
+++ b/drivers/video/gbefb.c
@@ -91,10 +91,10 @@ static uint32_t pseudo_palette[16];
 static uint32_t gbe_cmap[256];
 static int gbe_turned_on; /* 0 turned off, 1 turned on */
 
-static char *mode_option __initdata = NULL;
+static char *mode_option __devinitdata = NULL;
 
 /* default CRT mode */
-static struct fb_var_screeninfo default_var_CRT __initdata = {
+static struct fb_var_screeninfo default_var_CRT __devinitdata = {
         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
         .xres           = 640,
         .yres           = 480,
@@ -125,7 +125,7 @@ static struct fb_var_screeninfo default_var_CRT __initdata = {
 };
 
 /* default LCD mode */
-static struct fb_var_screeninfo default_var_LCD __initdata = {
+static struct fb_var_screeninfo default_var_LCD __devinitdata = {
         /* 1600x1024, 8 bpp */
         .xres           = 1600,
         .yres           = 1024,
@@ -157,7 +157,7 @@ static struct fb_var_screeninfo default_var_LCD __initdata = {
 
 /* default modedb mode */
 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
-static struct fb_videomode default_mode_CRT __initdata = {
+static struct fb_videomode default_mode_CRT __devinitdata = {
         .refresh        = 60,
         .xres           = 640,
         .yres           = 480,
@@ -172,7 +172,7 @@ static struct fb_videomode default_mode_CRT __initdata = {
         .vmode          = FB_VMODE_NONINTERLACED,
 };
 /* 1600x1024 SGI flatpanel 1600sw */
-static struct fb_videomode default_mode_LCD __initdata = {
+static struct fb_videomode default_mode_LCD __devinitdata = {
         /* 1600x1024, 8 bpp */
         .xres           = 1600,
         .yres           = 1024,
@@ -186,8 +186,8 @@ static struct fb_videomode default_mode_LCD __initdata = {
         .vmode          = FB_VMODE_NONINTERLACED,
 };
 
-static struct fb_videomode *default_mode __initdata = &default_mode_CRT;
-static struct fb_var_screeninfo *default_var __initdata = &default_var_CRT;
+static struct fb_videomode *default_mode __devinitdata = &default_mode_CRT;
+static struct fb_var_screeninfo *default_var __devinitdata = &default_var_CRT;
 
 static int flat_panel_enabled = 0;
 
@@ -1098,7 +1098,7 @@ static void gbefb_create_sysfs(struct device *dev)
  * Initialization
  */
 
-static int __init gbefb_setup(char *options)
+static int __devinit gbefb_setup(char *options)
 {
         char *this_opt;
 
diff --git a/drivers/video/pmag-ba-fb.c b/drivers/video/pmag-ba-fb.c
index 0f361b6100d2..0c69fa20251b 100644
--- a/drivers/video/pmag-ba-fb.c
+++ b/drivers/video/pmag-ba-fb.c
@@ -44,7 +44,7 @@ struct pmagbafb_par {
 };
 
 
-static struct fb_var_screeninfo pmagbafb_defined __initdata = {
+static struct fb_var_screeninfo pmagbafb_defined __devinitdata = {
         .xres           = 1024,
         .yres           = 864,
         .xres_virtual   = 1024,
@@ -68,7 +68,7 @@ static struct fb_var_screeninfo pmagbafb_defined __initdata = {
         .vmode          = FB_VMODE_NONINTERLACED,
 };
 
-static struct fb_fix_screeninfo pmagbafb_fix __initdata = {
+static struct fb_fix_screeninfo pmagbafb_fix __devinitdata = {
         .id             = "PMAG-BA",
         .smem_len       = (1024 * 1024),
         .type           = FB_TYPE_PACKED_PIXELS,
@@ -142,7 +142,7 @@ static void __init pmagbafb_erase_cursor(struct fb_info *info)
 }
 
 
-static int __init pmagbafb_probe(struct device *dev)
+static int __devinit pmagbafb_probe(struct device *dev)
 {
         struct tc_dev *tdev = to_tc_dev(dev);
         resource_size_t start, len;
diff --git a/drivers/video/pmagb-b-fb.c b/drivers/video/pmagb-b-fb.c
index 2de0806421b4..22fcb9a3d5c0 100644
--- a/drivers/video/pmagb-b-fb.c
+++ b/drivers/video/pmagb-b-fb.c
@@ -45,7 +45,7 @@ struct pmagbbfb_par {
 };
 
 
-static struct fb_var_screeninfo pmagbbfb_defined __initdata = {
+static struct fb_var_screeninfo pmagbbfb_defined __devinitdata = {
         .bits_per_pixel = 8,
         .red.length     = 8,
         .green.length   = 8,
@@ -58,7 +58,7 @@ static struct fb_var_screeninfo pmagbbfb_defined __initdata = {
         .vmode          = FB_VMODE_NONINTERLACED,
 };
 
-static struct fb_fix_screeninfo pmagbbfb_fix __initdata = {
+static struct fb_fix_screeninfo pmagbbfb_fix __devinitdata = {
         .id             = "PMAGB-BA",
         .smem_len       = (2048 * 1024),
         .type           = FB_TYPE_PACKED_PIXELS,
@@ -148,7 +148,7 @@ static void __init pmagbbfb_erase_cursor(struct fb_info *info)
 /*
  * Set up screen parameters.
  */
-static void __init pmagbbfb_screen_setup(struct fb_info *info)
+static void __devinit pmagbbfb_screen_setup(struct fb_info *info)
 {
         struct pmagbbfb_par *par = info->par;
 
@@ -180,9 +180,9 @@ static void __init pmagbbfb_screen_setup(struct fb_info *info)
 /*
  * Determine oscillator configuration.
  */
-static void __init pmagbbfb_osc_setup(struct fb_info *info)
+static void __devinit pmagbbfb_osc_setup(struct fb_info *info)
 {
-        static unsigned int pmagbbfb_freqs[] __initdata = {
+        static unsigned int pmagbbfb_freqs[] __devinitdata = {
                 130808, 119843, 104000, 92980, 74370, 72800,
                 69197, 66000, 65000, 50350, 36000, 32000, 25175
         };
@@ -247,7 +247,7 @@ static void __init pmagbbfb_osc_setup(struct fb_info *info)
 };
 
 
-static int __init pmagbbfb_probe(struct device *dev)
+static int __devinit pmagbbfb_probe(struct device *dev)
 {
         struct tc_dev *tdev = to_tc_dev(dev);
         resource_size_t start, len;
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index afe7e21dd0ae..1475ed6b575f 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -164,7 +164,8 @@ int virtqueue_add_buf_gfp(struct virtqueue *_vq,
                           gfp_t gfp)
 {
         struct vring_virtqueue *vq = to_vvq(_vq);
-        unsigned int i, avail, head, uninitialized_var(prev);
+        unsigned int i, avail, uninitialized_var(prev);
+        int head;
 
         START_USE(vq);
 
@@ -174,7 +175,7 @@ int virtqueue_add_buf_gfp(struct virtqueue *_vq,
          * buffers, then go indirect. FIXME: tune this threshold */
         if (vq->indirect && (out + in) > 1 && vq->num_free) {
                 head = vring_add_indirect(vq, sg, out, in, gfp);
-                if (head != vq->vring.num)
+                if (likely(head >= 0))
                         goto add_head;
         }