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authorDave Airlie <airlied@redhat.com>2011-03-24 06:21:45 -0400
committerDave Airlie <airlied@redhat.com>2011-03-24 06:21:45 -0400
commit2d370f502ac872dc9b4cd05f9922b260e2874ec1 (patch)
treee7447c934eae915f33851e939875d5dca2b3ea09 /drivers
parent64146f8b2af1ba77fe3c21d9d6d7213b9bb72b40 (diff)
parentf0c860246472248a534656d6cdbed5a36d1feb2e (diff)
Merge remote branch 'intel/drm-intel-fixes' of ../drm-next into drm-core-next
* 'intel/drm-intel-fixes' of ../drm-next: Revert "drm/i915: Don't save/restore hardware status page address register" drm/i915: Avoid unmapping pages from a NULL address space drm/i915: Fix use after free within tracepoint drm/i915: Restore missing command flush before interrupt on BLT ring drm/i915: Disable pagefaults along execbuffer relocation fast path drm/i915: Fix computation of pitch for dumb bo creator drm/i915: report correct render clock frequencies on SNB drm/i915/dp: Correct the order of deletion for ghost eDP devices drm/i915: Fix tiling corruption from pipelined fencing drm/i915: Re-enable self-refresh drm/i915: Prevent racy removal of request from client list drm/i915: skip redundant operations whilst enabling pipes and planes drm/i915: Remove surplus POSTING_READs before wait_for_vblank
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c8
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c70
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c21
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c6
-rw-r--r--drivers/gpu/drm/i915/intel_display.c39
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c4
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c109
8 files changed, 131 insertions, 127 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 09e0327fc6ce..87c8e29465e3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -892,7 +892,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
892 seq_printf(m, "Render p-state limit: %d\n", 892 seq_printf(m, "Render p-state limit: %d\n",
893 rp_state_limits & 0xff); 893 rp_state_limits & 0xff);
894 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> 894 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
895 GEN6_CAGF_SHIFT) * 100); 895 GEN6_CAGF_SHIFT) * 50);
896 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & 896 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
897 GEN6_CURICONT_MASK); 897 GEN6_CURICONT_MASK);
898 seq_printf(m, "RP CUR UP: %dus\n", rpcurup & 898 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
@@ -908,15 +908,15 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
908 908
909 max_freq = (rp_state_cap & 0xff0000) >> 16; 909 max_freq = (rp_state_cap & 0xff0000) >> 16;
910 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 910 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
911 max_freq * 100); 911 max_freq * 50);
912 912
913 max_freq = (rp_state_cap & 0xff00) >> 8; 913 max_freq = (rp_state_cap & 0xff00) >> 8;
914 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 914 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
915 max_freq * 100); 915 max_freq * 50);
916 916
917 max_freq = rp_state_cap & 0xff; 917 max_freq = rp_state_cap & 0xff;
918 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 918 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
919 max_freq * 100); 919 max_freq * 50);
920 920
921 __gen6_gt_force_wake_put(dev_priv); 921 __gen6_gt_force_wake_put(dev_priv);
922 } else { 922 } else {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 449650545bb4..5004724ea57e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -383,6 +383,7 @@ typedef struct drm_i915_private {
383 u32 saveDSPACNTR; 383 u32 saveDSPACNTR;
384 u32 saveDSPBCNTR; 384 u32 saveDSPBCNTR;
385 u32 saveDSPARB; 385 u32 saveDSPARB;
386 u32 saveHWS;
386 u32 savePIPEACONF; 387 u32 savePIPEACONF;
387 u32 savePIPEBCONF; 388 u32 savePIPEBCONF;
388 u32 savePIPEASRC; 389 u32 savePIPEASRC;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c4c2855d002d..7ce3f353af33 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -224,7 +224,7 @@ i915_gem_dumb_create(struct drm_file *file,
224 struct drm_mode_create_dumb *args) 224 struct drm_mode_create_dumb *args)
225{ 225{
226 /* have to work out size/pitch and return them */ 226 /* have to work out size/pitch and return them */
227 args->pitch = ALIGN(args->width & ((args->bpp + 1) / 8), 64); 227 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
228 args->size = args->pitch * args->height; 228 args->size = args->pitch * args->height;
229 return i915_gem_create(file, dev, 229 return i915_gem_create(file, dev,
230 args->size, &args->handle); 230 args->size, &args->handle);
@@ -1356,9 +1356,10 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1356 if (!obj->fault_mappable) 1356 if (!obj->fault_mappable)
1357 return; 1357 return;
1358 1358
1359 unmap_mapping_range(obj->base.dev->dev_mapping, 1359 if (obj->base.dev->dev_mapping)
1360 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, 1360 unmap_mapping_range(obj->base.dev->dev_mapping,
1361 obj->base.size, 1); 1361 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1362 obj->base.size, 1);
1362 1363
1363 obj->fault_mappable = false; 1364 obj->fault_mappable = false;
1364} 1365}
@@ -1796,8 +1797,10 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1796 return; 1797 return;
1797 1798
1798 spin_lock(&file_priv->mm.lock); 1799 spin_lock(&file_priv->mm.lock);
1799 list_del(&request->client_list); 1800 if (request->file_priv) {
1800 request->file_priv = NULL; 1801 list_del(&request->client_list);
1802 request->file_priv = NULL;
1803 }
1801 spin_unlock(&file_priv->mm.lock); 1804 spin_unlock(&file_priv->mm.lock);
1802} 1805}
1803 1806
@@ -2217,13 +2220,18 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
2217{ 2220{
2218 int ret; 2221 int ret;
2219 2222
2223 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2224 return 0;
2225
2220 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); 2226 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2221 2227
2222 ret = ring->flush(ring, invalidate_domains, flush_domains); 2228 ret = ring->flush(ring, invalidate_domains, flush_domains);
2223 if (ret) 2229 if (ret)
2224 return ret; 2230 return ret;
2225 2231
2226 i915_gem_process_flushing_list(ring, flush_domains); 2232 if (flush_domains & I915_GEM_GPU_DOMAINS)
2233 i915_gem_process_flushing_list(ring, flush_domains);
2234
2227 return 0; 2235 return 0;
2228} 2236}
2229 2237
@@ -2579,8 +2587,23 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2579 reg = &dev_priv->fence_regs[obj->fence_reg]; 2587 reg = &dev_priv->fence_regs[obj->fence_reg];
2580 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list); 2588 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2581 2589
2582 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) 2590 if (obj->tiling_changed) {
2583 pipelined = NULL; 2591 ret = i915_gem_object_flush_fence(obj, pipelined);
2592 if (ret)
2593 return ret;
2594
2595 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2596 pipelined = NULL;
2597
2598 if (pipelined) {
2599 reg->setup_seqno =
2600 i915_gem_next_request_seqno(pipelined);
2601 obj->last_fenced_seqno = reg->setup_seqno;
2602 obj->last_fenced_ring = pipelined;
2603 }
2604
2605 goto update;
2606 }
2584 2607
2585 if (!pipelined) { 2608 if (!pipelined) {
2586 if (reg->setup_seqno) { 2609 if (reg->setup_seqno) {
@@ -2599,31 +2622,6 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2599 ret = i915_gem_object_flush_fence(obj, pipelined); 2622 ret = i915_gem_object_flush_fence(obj, pipelined);
2600 if (ret) 2623 if (ret)
2601 return ret; 2624 return ret;
2602 } else if (obj->tiling_changed) {
2603 if (obj->fenced_gpu_access) {
2604 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2605 ret = i915_gem_flush_ring(obj->ring,
2606 0, obj->base.write_domain);
2607 if (ret)
2608 return ret;
2609 }
2610
2611 obj->fenced_gpu_access = false;
2612 }
2613 }
2614
2615 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2616 pipelined = NULL;
2617 BUG_ON(!pipelined && reg->setup_seqno);
2618
2619 if (obj->tiling_changed) {
2620 if (pipelined) {
2621 reg->setup_seqno =
2622 i915_gem_next_request_seqno(pipelined);
2623 obj->last_fenced_seqno = reg->setup_seqno;
2624 obj->last_fenced_ring = pipelined;
2625 }
2626 goto update;
2627 } 2625 }
2628 2626
2629 return 0; 2627 return 0;
@@ -3606,6 +3604,8 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3606 return; 3604 return;
3607 } 3605 }
3608 3606
3607 trace_i915_gem_object_destroy(obj);
3608
3609 if (obj->base.map_list.map) 3609 if (obj->base.map_list.map)
3610 i915_gem_free_mmap_offset(obj); 3610 i915_gem_free_mmap_offset(obj);
3611 3611
@@ -3615,8 +3615,6 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3615 kfree(obj->page_cpu_valid); 3615 kfree(obj->page_cpu_valid);
3616 kfree(obj->bit_17); 3616 kfree(obj->bit_17);
3617 kfree(obj); 3617 kfree(obj);
3618
3619 trace_i915_gem_object_destroy(obj);
3620} 3618}
3621 3619
3622void i915_gem_free_object(struct drm_gem_object *gem_obj) 3620void i915_gem_free_object(struct drm_gem_object *gem_obj)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 7ff7f933ddf1..20a4cc5b818f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -367,6 +367,10 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
367 uint32_t __iomem *reloc_entry; 367 uint32_t __iomem *reloc_entry;
368 void __iomem *reloc_page; 368 void __iomem *reloc_page;
369 369
370 /* We can't wait for rendering with pagefaults disabled */
371 if (obj->active && in_atomic())
372 return -EFAULT;
373
370 ret = i915_gem_object_set_to_gtt_domain(obj, 1); 374 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
371 if (ret) 375 if (ret)
372 return ret; 376 return ret;
@@ -440,15 +444,24 @@ i915_gem_execbuffer_relocate(struct drm_device *dev,
440 struct list_head *objects) 444 struct list_head *objects)
441{ 445{
442 struct drm_i915_gem_object *obj; 446 struct drm_i915_gem_object *obj;
443 int ret; 447 int ret = 0;
444 448
449 /* This is the fast path and we cannot handle a pagefault whilst
450 * holding the struct mutex lest the user pass in the relocations
451 * contained within a mmaped bo. For in such a case we, the page
452 * fault handler would call i915_gem_fault() and we would try to
453 * acquire the struct mutex again. Obviously this is bad and so
454 * lockdep complains vehemently.
455 */
456 pagefault_disable();
445 list_for_each_entry(obj, objects, exec_list) { 457 list_for_each_entry(obj, objects, exec_list) {
446 ret = i915_gem_execbuffer_relocate_object(obj, eb); 458 ret = i915_gem_execbuffer_relocate_object(obj, eb);
447 if (ret) 459 if (ret)
448 return ret; 460 break;
449 } 461 }
462 pagefault_enable();
450 463
451 return 0; 464 return ret;
452} 465}
453 466
454static int 467static int
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 7e992a8e9098..da474153a0a2 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -796,6 +796,9 @@ int i915_save_state(struct drm_device *dev)
796 796
797 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 797 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
798 798
799 /* Hardware status page */
800 dev_priv->saveHWS = I915_READ(HWS_PGA);
801
799 i915_save_display(dev); 802 i915_save_display(dev);
800 803
801 /* Interrupt state */ 804 /* Interrupt state */
@@ -842,6 +845,9 @@ int i915_restore_state(struct drm_device *dev)
842 845
843 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 846 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
844 847
848 /* Hardware status page */
849 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
850
845 i915_restore_display(dev); 851 i915_restore_display(dev);
846 852
847 /* Interrupt state */ 853 /* Interrupt state */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3106c0dc8389..432fc04c6bff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1516,9 +1516,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1516 1516
1517 reg = PIPECONF(pipe); 1517 reg = PIPECONF(pipe);
1518 val = I915_READ(reg); 1518 val = I915_READ(reg);
1519 val |= PIPECONF_ENABLE; 1519 if (val & PIPECONF_ENABLE)
1520 I915_WRITE(reg, val); 1520 return;
1521 POSTING_READ(reg); 1521
1522 I915_WRITE(reg, val | PIPECONF_ENABLE);
1522 intel_wait_for_vblank(dev_priv->dev, pipe); 1523 intel_wait_for_vblank(dev_priv->dev, pipe);
1523} 1524}
1524 1525
@@ -1552,9 +1553,10 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1552 1553
1553 reg = PIPECONF(pipe); 1554 reg = PIPECONF(pipe);
1554 val = I915_READ(reg); 1555 val = I915_READ(reg);
1555 val &= ~PIPECONF_ENABLE; 1556 if ((val & PIPECONF_ENABLE) == 0)
1556 I915_WRITE(reg, val); 1557 return;
1557 POSTING_READ(reg); 1558
1559 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1558 intel_wait_for_pipe_off(dev_priv->dev, pipe); 1560 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1559} 1561}
1560 1562
@@ -1577,9 +1579,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
1577 1579
1578 reg = DSPCNTR(plane); 1580 reg = DSPCNTR(plane);
1579 val = I915_READ(reg); 1581 val = I915_READ(reg);
1580 val |= DISPLAY_PLANE_ENABLE; 1582 if (val & DISPLAY_PLANE_ENABLE)
1581 I915_WRITE(reg, val); 1583 return;
1582 POSTING_READ(reg); 1584
1585 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1583 intel_wait_for_vblank(dev_priv->dev, pipe); 1586 intel_wait_for_vblank(dev_priv->dev, pipe);
1584} 1587}
1585 1588
@@ -1610,9 +1613,10 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
1610 1613
1611 reg = DSPCNTR(plane); 1614 reg = DSPCNTR(plane);
1612 val = I915_READ(reg); 1615 val = I915_READ(reg);
1613 val &= ~DISPLAY_PLANE_ENABLE; 1616 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1614 I915_WRITE(reg, val); 1617 return;
1615 POSTING_READ(reg); 1618
1619 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1616 intel_flush_display_plane(dev_priv, plane); 1620 intel_flush_display_plane(dev_priv, plane);
1617 intel_wait_for_vblank(dev_priv->dev, pipe); 1621 intel_wait_for_vblank(dev_priv->dev, pipe);
1618} 1622}
@@ -1769,7 +1773,6 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1769 return; 1773 return;
1770 1774
1771 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); 1775 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1772 POSTING_READ(DPFC_CONTROL);
1773 intel_wait_for_vblank(dev, intel_crtc->pipe); 1776 intel_wait_for_vblank(dev, intel_crtc->pipe);
1774 } 1777 }
1775 1778
@@ -1861,7 +1864,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1861 return; 1864 return;
1862 1865
1863 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); 1866 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1864 POSTING_READ(ILK_DPFC_CONTROL);
1865 intel_wait_for_vblank(dev, intel_crtc->pipe); 1867 intel_wait_for_vblank(dev, intel_crtc->pipe);
1866 } 1868 }
1867 1869
@@ -3883,10 +3885,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
3883 display, cursor); 3885 display, cursor);
3884} 3886}
3885 3887
3886static inline bool single_plane_enabled(unsigned int mask) 3888#define single_plane_enabled(mask) is_power_of_2(mask)
3887{
3888 return mask && (mask & -mask) == 0;
3889}
3890 3889
3891static void g4x_update_wm(struct drm_device *dev) 3890static void g4x_update_wm(struct drm_device *dev)
3892{ 3891{
@@ -5777,7 +5776,6 @@ static void intel_increase_pllclock(struct drm_crtc *crtc)
5777 5776
5778 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 5777 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5779 I915_WRITE(dpll_reg, dpll); 5778 I915_WRITE(dpll_reg, dpll);
5780 POSTING_READ(dpll_reg);
5781 intel_wait_for_vblank(dev, pipe); 5779 intel_wait_for_vblank(dev, pipe);
5782 5780
5783 dpll = I915_READ(dpll_reg); 5781 dpll = I915_READ(dpll_reg);
@@ -5821,7 +5819,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
5821 5819
5822 dpll |= DISPLAY_RATE_SELECT_FPA1; 5820 dpll |= DISPLAY_RATE_SELECT_FPA1;
5823 I915_WRITE(dpll_reg, dpll); 5821 I915_WRITE(dpll_reg, dpll);
5824 dpll = I915_READ(dpll_reg);
5825 intel_wait_for_vblank(dev, pipe); 5822 intel_wait_for_vblank(dev, pipe);
5826 dpll = I915_READ(dpll_reg); 5823 dpll = I915_READ(dpll_reg);
5827 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 5824 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
@@ -6933,7 +6930,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6933 DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); 6930 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6934 if (pcu_mbox & (1<<31)) { /* OC supported */ 6931 if (pcu_mbox & (1<<31)) { /* OC supported */
6935 max_freq = pcu_mbox & 0xff; 6932 max_freq = pcu_mbox & 0xff;
6936 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100); 6933 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
6937 } 6934 }
6938 6935
6939 /* In units of 100MHz */ 6936 /* In units of 100MHz */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d29e33f815d7..0daefca5cbb8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1957,9 +1957,9 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1957 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 1957 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1958 } else { 1958 } else {
1959 /* if this fails, presume the device is a ghost */ 1959 /* if this fails, presume the device is a ghost */
1960 DRM_ERROR("failed to retrieve link info\n"); 1960 DRM_INFO("failed to retrieve link info, disabling eDP\n");
1961 intel_dp_destroy(&intel_connector->base);
1962 intel_dp_encoder_destroy(&intel_dp->base.base); 1961 intel_dp_encoder_destroy(&intel_dp->base.base);
1962 intel_dp_destroy(&intel_connector->base);
1963 return; 1963 return;
1964 } 1964 }
1965 } 1965 }
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 789c47801ba8..e9e6f71418a4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -65,62 +65,60 @@ render_ring_flush(struct intel_ring_buffer *ring,
65 u32 cmd; 65 u32 cmd;
66 int ret; 66 int ret;
67 67
68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { 68 /*
69 * read/write caches:
70 *
71 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
72 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
73 * also flushed at 2d versus 3d pipeline switches.
74 *
75 * read-only caches:
76 *
77 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
78 * MI_READ_FLUSH is set, and is always flushed on 965.
79 *
80 * I915_GEM_DOMAIN_COMMAND may not exist?
81 *
82 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
83 * invalidated when MI_EXE_FLUSH is set.
84 *
85 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
86 * invalidated with every MI_FLUSH.
87 *
88 * TLBs:
89 *
90 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
91 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
92 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
93 * are flushed at any MI_FLUSH.
94 */
95
96 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
97 if ((invalidate_domains|flush_domains) &
98 I915_GEM_DOMAIN_RENDER)
99 cmd &= ~MI_NO_WRITE_FLUSH;
100 if (INTEL_INFO(dev)->gen < 4) {
69 /* 101 /*
70 * read/write caches: 102 * On the 965, the sampler cache always gets flushed
71 * 103 * and this bit is reserved.
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
75 *
76 * read-only caches:
77 *
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
80 *
81 * I915_GEM_DOMAIN_COMMAND may not exist?
82 *
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
85 *
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
88 *
89 * TLBs:
90 *
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
95 */ 104 */
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107 }
108 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
109 cmd |= MI_EXE_FLUSH;
96 110
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; 111 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
98 if ((invalidate_domains|flush_domains) & 112 (IS_G4X(dev) || IS_GEN5(dev)))
99 I915_GEM_DOMAIN_RENDER) 113 cmd |= MI_INVALIDATE_ISP;
100 cmd &= ~MI_NO_WRITE_FLUSH;
101 if (INTEL_INFO(dev)->gen < 4) {
102 /*
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
105 */
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108 }
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110 cmd |= MI_EXE_FLUSH;
111
112 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
113 (IS_G4X(dev) || IS_GEN5(dev)))
114 cmd |= MI_INVALIDATE_ISP;
115 114
116 ret = intel_ring_begin(ring, 2); 115 ret = intel_ring_begin(ring, 2);
117 if (ret) 116 if (ret)
118 return ret; 117 return ret;
119 118
120 intel_ring_emit(ring, cmd); 119 intel_ring_emit(ring, cmd);
121 intel_ring_emit(ring, MI_NOOP); 120 intel_ring_emit(ring, MI_NOOP);
122 intel_ring_advance(ring); 121 intel_ring_advance(ring);
123 }
124 122
125 return 0; 123 return 0;
126} 124}
@@ -568,9 +566,6 @@ bsd_ring_flush(struct intel_ring_buffer *ring,
568{ 566{
569 int ret; 567 int ret;
570 568
571 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
572 return 0;
573
574 ret = intel_ring_begin(ring, 2); 569 ret = intel_ring_begin(ring, 2);
575 if (ret) 570 if (ret)
576 return ret; 571 return ret;
@@ -1056,9 +1051,6 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
1056 uint32_t cmd; 1051 uint32_t cmd;
1057 int ret; 1052 int ret;
1058 1053
1059 if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0)
1060 return 0;
1061
1062 ret = intel_ring_begin(ring, 4); 1054 ret = intel_ring_begin(ring, 4);
1063 if (ret) 1055 if (ret)
1064 return ret; 1056 return ret;
@@ -1230,9 +1222,6 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
1230 uint32_t cmd; 1222 uint32_t cmd;
1231 int ret; 1223 int ret;
1232 1224
1233 if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0)
1234 return 0;
1235
1236 ret = blt_ring_begin(ring, 4); 1225 ret = blt_ring_begin(ring, 4);
1237 if (ret) 1226 if (ret)
1238 return ret; 1227 return ret;