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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-06-07 20:08:06 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-06-07 20:08:06 -0400
commitdf3872a9664667edae729361c9948b652de5c6f4 (patch)
treed191c1e6413f82b7a3f074a29b2d1fb92476d30f /drivers
parente5e3c84b70e58fc605635fd340fb8dba3cc59058 (diff)
parent4aa2e62c45b5ca08be2d0d3c0744d7585b56e860 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: (24 commits) xfrm: Add security check before flushing SAD/SPD [NET_SCHED]: Fix filter double free [NET]: Avoid duplicate netlink notification when changing link state [UDP]: Revert 2-pass hashing changes. [AF_UNIX]: Fix stream recvmsg() race. [NETFILTER]: nf_conntrack_amanda: fix textsearch_prepare() error check [NETFILTER]: ip_tables: fix compat related crash [NETFILTER]: nf_conntrack: fix helper module unload races [RTNETLINK]: ifindex 0 does not exist [NETLINK]: Mark netlink policies const [TCP] tcp_probe: Attach printf attribute properly to printl(). [TCP]: Use LIMIT_NETDEBUG in tcp_retransmit_timer(). [NET]: Merge dst_discard_in and dst_discard_out. [RFKILL]: Make rfkill->name const [IPV4]: Restore old behaviour of default config values [IPV4]: Add default config support after inetdev_init [IPV4]: Convert IPv4 devconf to an array [IPV4]: Only panic if inetdev_init fails for loopback [TCP]: Honour sk_bound_dev_if in tcp_v4_send_ack [BNX2]: Update version and reldate. ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/infiniband/hw/amso1100/c2.c2
-rw-r--r--drivers/net/bnx2.c61
-rw-r--r--drivers/net/bnx2.h1
3 files changed, 49 insertions, 15 deletions
diff --git a/drivers/infiniband/hw/amso1100/c2.c b/drivers/infiniband/hw/amso1100/c2.c
index 58bc272bd407..0aecea67f3e6 100644
--- a/drivers/infiniband/hw/amso1100/c2.c
+++ b/drivers/infiniband/hw/amso1100/c2.c
@@ -672,7 +672,7 @@ static int c2_up(struct net_device *netdev)
672 * rdma interface. 672 * rdma interface.
673 */ 673 */
674 in_dev = in_dev_get(netdev); 674 in_dev = in_dev_get(netdev);
675 in_dev->cnf.arp_ignore = 1; 675 IN_DEV_CONF_SET(in_dev, ARP_IGNORE, 1);
676 in_dev_put(in_dev); 676 in_dev_put(in_dev);
677 677
678 return 0; 678 return 0;
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index da7c3b0c533c..ce3ed67a878e 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -54,8 +54,8 @@
54 54
55#define DRV_MODULE_NAME "bnx2" 55#define DRV_MODULE_NAME "bnx2"
56#define PFX DRV_MODULE_NAME ": " 56#define PFX DRV_MODULE_NAME ": "
57#define DRV_MODULE_VERSION "1.5.10" 57#define DRV_MODULE_VERSION "1.5.11"
58#define DRV_MODULE_RELDATE "May 1, 2007" 58#define DRV_MODULE_RELDATE "June 4, 2007"
59 59
60#define RUN_AT(x) (jiffies + (x)) 60#define RUN_AT(x) (jiffies + (x))
61 61
@@ -1778,6 +1778,15 @@ bnx2_init_5709_context(struct bnx2 *bp)
1778 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); 1778 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
1779 val |= (BCM_PAGE_BITS - 8) << 16; 1779 val |= (BCM_PAGE_BITS - 8) << 16;
1780 REG_WR(bp, BNX2_CTX_COMMAND, val); 1780 REG_WR(bp, BNX2_CTX_COMMAND, val);
1781 for (i = 0; i < 10; i++) {
1782 val = REG_RD(bp, BNX2_CTX_COMMAND);
1783 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
1784 break;
1785 udelay(2);
1786 }
1787 if (val & BNX2_CTX_COMMAND_MEM_INIT)
1788 return -EBUSY;
1789
1781 for (i = 0; i < bp->ctx_pages; i++) { 1790 for (i = 0; i < bp->ctx_pages; i++) {
1782 int j; 1791 int j;
1783 1792
@@ -1811,6 +1820,7 @@ bnx2_init_context(struct bnx2 *bp)
1811 vcid = 96; 1820 vcid = 96;
1812 while (vcid) { 1821 while (vcid) {
1813 u32 vcid_addr, pcid_addr, offset; 1822 u32 vcid_addr, pcid_addr, offset;
1823 int i;
1814 1824
1815 vcid--; 1825 vcid--;
1816 1826
@@ -1831,16 +1841,20 @@ bnx2_init_context(struct bnx2 *bp)
1831 pcid_addr = vcid_addr; 1841 pcid_addr = vcid_addr;
1832 } 1842 }
1833 1843
1834 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); 1844 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
1835 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); 1845 vcid_addr += (i << PHY_CTX_SHIFT);
1846 pcid_addr += (i << PHY_CTX_SHIFT);
1836 1847
1837 /* Zero out the context. */ 1848 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1838 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 1849 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1839 CTX_WR(bp, 0x00, offset, 0); 1850
1840 } 1851 /* Zero out the context. */
1852 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
1853 CTX_WR(bp, 0x00, offset, 0);
1841 1854
1842 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); 1855 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1843 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); 1856 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1857 }
1844 } 1858 }
1845} 1859}
1846 1860
@@ -3691,9 +3705,11 @@ bnx2_init_chip(struct bnx2 *bp)
3691 3705
3692 /* Initialize context mapping and zero out the quick contexts. The 3706 /* Initialize context mapping and zero out the quick contexts. The
3693 * context block must have already been enabled. */ 3707 * context block must have already been enabled. */
3694 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3708 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3695 bnx2_init_5709_context(bp); 3709 rc = bnx2_init_5709_context(bp);
3696 else 3710 if (rc)
3711 return rc;
3712 } else
3697 bnx2_init_context(bp); 3713 bnx2_init_context(bp);
3698 3714
3699 if ((rc = bnx2_init_cpus(bp)) != 0) 3715 if ((rc = bnx2_init_cpus(bp)) != 0)
@@ -3772,7 +3788,10 @@ bnx2_init_chip(struct bnx2 *bp)
3772 REG_WR(bp, BNX2_HC_CMD_TICKS, 3788 REG_WR(bp, BNX2_HC_CMD_TICKS,
3773 (bp->cmd_ticks_int << 16) | bp->cmd_ticks); 3789 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3774 3790
3775 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00); 3791 if (CHIP_NUM(bp) == CHIP_NUM_5708)
3792 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
3793 else
3794 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3776 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3795 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3777 3796
3778 if (CHIP_ID(bp) == CHIP_ID_5706_A1) 3797 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
@@ -3799,6 +3818,11 @@ bnx2_init_chip(struct bnx2 *bp)
3799 /* Initialize the receive filter. */ 3818 /* Initialize the receive filter. */
3800 bnx2_set_rx_mode(bp->dev); 3819 bnx2_set_rx_mode(bp->dev);
3801 3820
3821 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3822 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
3823 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
3824 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
3825 }
3802 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, 3826 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3803 0); 3827 0);
3804 3828
@@ -4620,6 +4644,11 @@ bnx2_timer(unsigned long data)
4620 4644
4621 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); 4645 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4622 4646
4647 /* workaround occasional corrupted counters */
4648 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
4649 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
4650 BNX2_HC_COMMAND_STATS_NOW);
4651
4623 if (bp->phy_flags & PHY_SERDES_FLAG) { 4652 if (bp->phy_flags & PHY_SERDES_FLAG) {
4624 if (CHIP_NUM(bp) == CHIP_NUM_5706) 4653 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4625 bnx2_5706_serdes_timer(bp); 4654 bnx2_5706_serdes_timer(bp);
@@ -5417,6 +5446,10 @@ bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5417 0xff; 5446 0xff;
5418 5447
5419 bp->stats_ticks = coal->stats_block_coalesce_usecs; 5448 bp->stats_ticks = coal->stats_block_coalesce_usecs;
5449 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5450 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
5451 bp->stats_ticks = USEC_PER_SEC;
5452 }
5420 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00; 5453 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
5421 bp->stats_ticks &= 0xffff00; 5454 bp->stats_ticks &= 0xffff00;
5422 5455
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index bd6288d6350f..49a5de253b17 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -1373,6 +1373,7 @@ struct l2_fhdr {
1373#define BNX2_MISC_NEW_CORE_CTL 0x000008c8 1373#define BNX2_MISC_NEW_CORE_CTL 0x000008c8
1374#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0) 1374#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
1375#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1) 1375#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
1376#define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
1376#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2) 1377#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
1377#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16) 1378#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
1378 1379