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authorStephen Hemminger <shemminger@linux-foundation.org>2007-06-04 20:23:22 -0400
committerJeff Garzik <jeff@garzik.org>2007-07-08 22:16:42 -0400
commitfc99fe0618f355b708ce88fedaca9783072ac3d5 (patch)
tree0a45bc3f04fdef6f80f89aa2791bf17a120fa9ad /drivers
parent3ead5db7bcd343917e567c083f5faf45f5301664 (diff)
sky2: Add PCI device specfic register 4 & 5
Need to setup more PCI control control registers are on Yukon EX. Some of these also exist on Yukon EC-U as well. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/sky2.c18
-rw-r--r--drivers/net/sky2.h77
2 files changed, 89 insertions, 6 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 612257172b95..0bd74fe5c338 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -217,13 +217,19 @@ static void sky2_power_on(struct sky2_hw *hw)
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
218 218
219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) { 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
220 u32 reg1; 220 u32 reg;
221 221
222 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 222 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); 223 /* set all bits to 0 except bits 15..12 and 8 */
224 reg1 &= P_ASPM_CONTROL_MSK; 224 reg &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1); 225 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
226 sky2_pci_write32(hw, PCI_DEV_REG5, 0); 226
227 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
228 /* set all bits to 0 except bits 28 & 27 */
229 reg &= P_CTL_TIM_VMAIN_AV_MSK;
230 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
231
232 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
227 } 233 }
228} 234}
229 235
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index b8c4a3b5eadf..3caeddf893ef 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -14,6 +14,8 @@ enum {
14 PCI_DEV_REG3 = 0x80, 14 PCI_DEV_REG3 = 0x80,
15 PCI_DEV_REG4 = 0x84, 15 PCI_DEV_REG4 = 0x84,
16 PCI_DEV_REG5 = 0x88, 16 PCI_DEV_REG5 = 0x88,
17 PCI_CFG_REG_0 = 0x90,
18 PCI_CFG_REG_1 = 0x94,
17}; 19};
18 20
19enum { 21enum {
@@ -28,6 +30,7 @@ enum {
28enum pci_dev_reg_1 { 30enum pci_dev_reg_1 {
29 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 31 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
30 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 32 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
33 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
31 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 34 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
32 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 35 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
33 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 36 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
@@ -67,6 +70,80 @@ enum pci_dev_reg_4 {
67 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, 70 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
68}; 71};
69 72
73/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
74enum pci_dev_reg_5 {
75 /* Bit 31..27: for A3 & later */
76 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
77 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
78 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
79 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
80 /* Bit 26..16: Release Clock on Event */
81 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
82 P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */
83 P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */
84 P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */
85 P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */
86 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
87 P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */
88 P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
89 P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */
90 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
91 P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */
92
93 /* Bit 10.. 0: Mask for Gate Clock */
94 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
95 P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
96 P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */
97 P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */
98 P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */
99 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
100 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
101 P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
102 P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */
103 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
104 P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */
105
106 PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
107 P_REL_INT_FIFO_N_EMPTY |
108 P_REL_PCIE_EXIT_L1_ST |
109 P_REL_PCIE_RX_EX_IDLE |
110 P_GAT_GPHY_N_REC_PACKET |
111 P_GAT_INT_FIFO_EMPTY |
112 P_GAT_PCIE_ENTER_L1_ST |
113 P_GAT_PCIE_RX_EL_IDLE,
114};
115
116#/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
117enum pci_cfg_reg1 {
118 P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
119 /* Bit 23..21: Release Clock on Event */
120 P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */
121 P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */
122 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
123 /* Bit 20..18: Gate Clock on Event */
124 P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */
125 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
126 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
127 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
128 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
129
130 P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
131
132 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
133 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
134
135 PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
136 P_CF1_REL_LDR_NOT_FIN |
137 P_CF1_REL_VMAIN_AVLBL |
138 P_CF1_REL_PCIE_RESET |
139 P_CF1_GAT_LDR_NOT_FIN |
140 P_CF1_GAT_PCIE_RESET |
141 P_CF1_PRST_PHY_CLKREQ |
142 P_CF1_ENA_CFG_LDR_DONE |
143 P_CF1_ENA_TXBMU_RD_IDLE |
144 P_CF1_ENA_TXBMU_WR_IDLE,
145};
146
70 147
71#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 148#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
72 PCI_STATUS_SIG_SYSTEM_ERROR | \ 149 PCI_STATUS_SIG_SYSTEM_ERROR | \