diff options
author | Francisco Jerez <currojerez@riseup.net> | 2009-12-13 14:07:42 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-01-10 23:41:02 -0500 |
commit | 617e234b01757698ed5f8c9a5fbf12717b76e371 (patch) | |
tree | 75013aac9f6505b660efd157fcf5587dc752af83 /drivers | |
parent | 94fd163d86b049842856864cdeac318131ec576d (diff) |
drm/nouveau: Add cache_flush/pull fifo engine functions.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_state.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_fifo.c | 34 |
3 files changed, 48 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 5f8cbb79c499..48d0ad9434a8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -292,6 +292,8 @@ struct nouveau_fifo_engine { | |||
292 | void (*disable)(struct drm_device *); | 292 | void (*disable)(struct drm_device *); |
293 | void (*enable)(struct drm_device *); | 293 | void (*enable)(struct drm_device *); |
294 | bool (*reassign)(struct drm_device *, bool enable); | 294 | bool (*reassign)(struct drm_device *, bool enable); |
295 | bool (*cache_flush)(struct drm_device *dev); | ||
296 | bool (*cache_pull)(struct drm_device *dev, bool enable); | ||
295 | 297 | ||
296 | int (*channel_id)(struct drm_device *); | 298 | int (*channel_id)(struct drm_device *); |
297 | 299 | ||
@@ -889,6 +891,8 @@ extern int nv04_fifo_init(struct drm_device *); | |||
889 | extern void nv04_fifo_disable(struct drm_device *); | 891 | extern void nv04_fifo_disable(struct drm_device *); |
890 | extern void nv04_fifo_enable(struct drm_device *); | 892 | extern void nv04_fifo_enable(struct drm_device *); |
891 | extern bool nv04_fifo_reassign(struct drm_device *, bool); | 893 | extern bool nv04_fifo_reassign(struct drm_device *, bool); |
894 | extern bool nv04_fifo_cache_flush(struct drm_device *); | ||
895 | extern bool nv04_fifo_cache_pull(struct drm_device *, bool); | ||
892 | extern int nv04_fifo_channel_id(struct drm_device *); | 896 | extern int nv04_fifo_channel_id(struct drm_device *); |
893 | extern int nv04_fifo_create_context(struct nouveau_channel *); | 897 | extern int nv04_fifo_create_context(struct nouveau_channel *); |
894 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); | 898 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index e76ec2d207a9..9f988431f34c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c | |||
@@ -76,6 +76,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
76 | engine->fifo.disable = nv04_fifo_disable; | 76 | engine->fifo.disable = nv04_fifo_disable; |
77 | engine->fifo.enable = nv04_fifo_enable; | 77 | engine->fifo.enable = nv04_fifo_enable; |
78 | engine->fifo.reassign = nv04_fifo_reassign; | 78 | engine->fifo.reassign = nv04_fifo_reassign; |
79 | engine->fifo.cache_flush = nv04_fifo_cache_flush; | ||
80 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | ||
79 | engine->fifo.channel_id = nv04_fifo_channel_id; | 81 | engine->fifo.channel_id = nv04_fifo_channel_id; |
80 | engine->fifo.create_context = nv04_fifo_create_context; | 82 | engine->fifo.create_context = nv04_fifo_create_context; |
81 | engine->fifo.destroy_context = nv04_fifo_destroy_context; | 83 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
@@ -115,6 +117,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
115 | engine->fifo.disable = nv04_fifo_disable; | 117 | engine->fifo.disable = nv04_fifo_disable; |
116 | engine->fifo.enable = nv04_fifo_enable; | 118 | engine->fifo.enable = nv04_fifo_enable; |
117 | engine->fifo.reassign = nv04_fifo_reassign; | 119 | engine->fifo.reassign = nv04_fifo_reassign; |
120 | engine->fifo.cache_flush = nv04_fifo_cache_flush; | ||
121 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | ||
118 | engine->fifo.channel_id = nv10_fifo_channel_id; | 122 | engine->fifo.channel_id = nv10_fifo_channel_id; |
119 | engine->fifo.create_context = nv10_fifo_create_context; | 123 | engine->fifo.create_context = nv10_fifo_create_context; |
120 | engine->fifo.destroy_context = nv10_fifo_destroy_context; | 124 | engine->fifo.destroy_context = nv10_fifo_destroy_context; |
@@ -154,6 +158,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
154 | engine->fifo.disable = nv04_fifo_disable; | 158 | engine->fifo.disable = nv04_fifo_disable; |
155 | engine->fifo.enable = nv04_fifo_enable; | 159 | engine->fifo.enable = nv04_fifo_enable; |
156 | engine->fifo.reassign = nv04_fifo_reassign; | 160 | engine->fifo.reassign = nv04_fifo_reassign; |
161 | engine->fifo.cache_flush = nv04_fifo_cache_flush; | ||
162 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | ||
157 | engine->fifo.channel_id = nv10_fifo_channel_id; | 163 | engine->fifo.channel_id = nv10_fifo_channel_id; |
158 | engine->fifo.create_context = nv10_fifo_create_context; | 164 | engine->fifo.create_context = nv10_fifo_create_context; |
159 | engine->fifo.destroy_context = nv10_fifo_destroy_context; | 165 | engine->fifo.destroy_context = nv10_fifo_destroy_context; |
@@ -193,6 +199,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
193 | engine->fifo.disable = nv04_fifo_disable; | 199 | engine->fifo.disable = nv04_fifo_disable; |
194 | engine->fifo.enable = nv04_fifo_enable; | 200 | engine->fifo.enable = nv04_fifo_enable; |
195 | engine->fifo.reassign = nv04_fifo_reassign; | 201 | engine->fifo.reassign = nv04_fifo_reassign; |
202 | engine->fifo.cache_flush = nv04_fifo_cache_flush; | ||
203 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | ||
196 | engine->fifo.channel_id = nv10_fifo_channel_id; | 204 | engine->fifo.channel_id = nv10_fifo_channel_id; |
197 | engine->fifo.create_context = nv10_fifo_create_context; | 205 | engine->fifo.create_context = nv10_fifo_create_context; |
198 | engine->fifo.destroy_context = nv10_fifo_destroy_context; | 206 | engine->fifo.destroy_context = nv10_fifo_destroy_context; |
@@ -233,6 +241,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
233 | engine->fifo.disable = nv04_fifo_disable; | 241 | engine->fifo.disable = nv04_fifo_disable; |
234 | engine->fifo.enable = nv04_fifo_enable; | 242 | engine->fifo.enable = nv04_fifo_enable; |
235 | engine->fifo.reassign = nv04_fifo_reassign; | 243 | engine->fifo.reassign = nv04_fifo_reassign; |
244 | engine->fifo.cache_flush = nv04_fifo_cache_flush; | ||
245 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | ||
236 | engine->fifo.channel_id = nv10_fifo_channel_id; | 246 | engine->fifo.channel_id = nv10_fifo_channel_id; |
237 | engine->fifo.create_context = nv40_fifo_create_context; | 247 | engine->fifo.create_context = nv40_fifo_create_context; |
238 | engine->fifo.destroy_context = nv40_fifo_destroy_context; | 248 | engine->fifo.destroy_context = nv40_fifo_destroy_context; |
diff --git a/drivers/gpu/drm/nouveau/nv04_fifo.c b/drivers/gpu/drm/nouveau/nv04_fifo.c index 0c3cd53c7313..f31347b8c9b0 100644 --- a/drivers/gpu/drm/nouveau/nv04_fifo.c +++ b/drivers/gpu/drm/nouveau/nv04_fifo.c | |||
@@ -71,6 +71,40 @@ nv04_fifo_reassign(struct drm_device *dev, bool enable) | |||
71 | return (reassign == 1); | 71 | return (reassign == 1); |
72 | } | 72 | } |
73 | 73 | ||
74 | bool | ||
75 | nv04_fifo_cache_flush(struct drm_device *dev) | ||
76 | { | ||
77 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
78 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | ||
79 | uint64_t start = ptimer->read(dev); | ||
80 | |||
81 | do { | ||
82 | if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) == | ||
83 | nv_rd32(dev, NV03_PFIFO_CACHE1_PUT)) | ||
84 | return true; | ||
85 | |||
86 | } while (ptimer->read(dev) - start < 100000000); | ||
87 | |||
88 | NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n"); | ||
89 | |||
90 | return false; | ||
91 | } | ||
92 | |||
93 | bool | ||
94 | nv04_fifo_cache_pull(struct drm_device *dev, bool enable) | ||
95 | { | ||
96 | uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0); | ||
97 | |||
98 | if (enable) { | ||
99 | nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1); | ||
100 | } else { | ||
101 | nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1); | ||
102 | nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0); | ||
103 | } | ||
104 | |||
105 | return !!(pull & 1); | ||
106 | } | ||
107 | |||
74 | int | 108 | int |
75 | nv04_fifo_channel_id(struct drm_device *dev) | 109 | nv04_fifo_channel_id(struct drm_device *dev) |
76 | { | 110 | { |