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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2009-11-04 12:36:17 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-11-06 16:48:57 -0500
commit4d6f8b9f17626da48d6badc6ba259fbacc1413c3 (patch)
tree3e5c40a7d2df005815af7a3c3bf1b2d14224459b /drivers
parent5822e0701d9c29291f16cf170417071b702edeee (diff)
rt2800: prepare for rt2800lib addition
Part of preparations for later code unification. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c103
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c134
2 files changed, 133 insertions, 104 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index cae772ea5686..938f198f3562 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -97,7 +97,8 @@ static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
97 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word); 97 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1); 98 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0); 99 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); 100 if (rt2x00_intf_is_pci(rt2x00dev))
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
101 102
102 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 103 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
103 } 104 }
@@ -125,7 +126,8 @@ static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
125 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word); 126 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
126 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1); 127 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1); 128 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); 129 if (rt2x00_intf_is_pci(rt2x00dev))
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
129 131
130 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
131 133
@@ -253,12 +255,14 @@ static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
253{ 255{
254 u32 reg; 256 u32 reg;
255 257
256 /* 258 if (rt2x00_intf_is_pci(rt2x00dev)) {
257 * RT2880 and RT3052 don't support MCU requests. 259 /*
258 */ 260 * RT2880 and RT3052 don't support MCU requests.
259 if (rt2x00_rt(&rt2x00dev->chip, RT2880) || 261 */
260 rt2x00_rt(&rt2x00dev->chip, RT3052)) 262 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
261 return; 263 rt2x00_rt(&rt2x00dev->chip, RT3052))
264 return;
265 }
262 266
263 mutex_lock(&rt2x00dev->csr_mutex); 267 mutex_lock(&rt2x00dev->csr_mutex);
264 268
@@ -814,7 +818,8 @@ static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
814 switch ((int)ant->tx) { 818 switch ((int)ant->tx) {
815 case 1: 819 case 1:
816 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 820 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
817 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 821 if (rt2x00_intf_is_pci(rt2x00dev))
822 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
818 break; 823 break;
819 case 2: 824 case 2:
820 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 825 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
@@ -1480,7 +1485,8 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1480 u32 reg; 1485 u32 reg;
1481 unsigned int i; 1486 unsigned int i;
1482 1487
1483 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1488 if (rt2x00_intf_is_pci(rt2x00dev))
1489 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1484 1490
1485 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1491 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1486 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 1492 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
@@ -1803,7 +1809,8 @@ static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1803 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) 1809 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1804 rt2800_bbp_write(rt2x00dev, 84, 0x19); 1810 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1805 1811
1806 if (rt2x00_rt(&rt2x00dev->chip, RT3052)) { 1812 if (rt2x00_intf_is_pci(rt2x00dev) &&
1813 rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1807 rt2800_bbp_write(rt2x00dev, 31, 0x08); 1814 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1808 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 1815 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1809 rt2800_bbp_write(rt2x00dev, 80, 0x08); 1816 rt2800_bbp_write(rt2x00dev, 80, 0x08);
@@ -1887,10 +1894,12 @@ static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1887 u8 rfcsr; 1894 u8 rfcsr;
1888 u8 bbp; 1895 u8 bbp;
1889 1896
1890 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) && 1897 if (rt2x00_intf_is_pci(rt2x00dev)) {
1891 !rt2x00_rf(&rt2x00dev->chip, RF3021) && 1898 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1892 !rt2x00_rf(&rt2x00dev->chip, RF3022)) 1899 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1893 return 0; 1900 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1901 return 0;
1902 }
1894 1903
1895 /* 1904 /*
1896 * Init RF calibration. 1905 * Init RF calibration.
@@ -1902,36 +1911,38 @@ static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1902 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 1911 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1903 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1912 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1904 1913
1905 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 1914 if (rt2x00_intf_is_pci(rt2x00dev)) {
1906 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 1915 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1907 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 1916 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1908 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 1917 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1909 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1918 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1910 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1919 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1911 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1920 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1912 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 1921 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1913 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 1922 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1914 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1923 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1915 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 1924 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1916 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1925 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1917 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 1926 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1918 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 1927 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1919 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1928 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1920 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 1929 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1921 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 1930 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1922 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 1931 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1923 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 1932 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1924 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 1933 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1925 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 1934 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1926 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1935 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1927 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 1936 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1928 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 1937 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1929 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 1938 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1930 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1939 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1931 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 1940 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1932 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 1941 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1933 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 1942 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1934 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 1943 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1944 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1945 }
1935 1946
1936 /* 1947 /*
1937 * Set RX Filter calibration for 20MHz and 40MHz 1948 * Set RX Filter calibration for 20MHz and 40MHz
@@ -3005,6 +3016,8 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
3005{ 3016{
3006 int retval; 3017 int retval;
3007 3018
3019 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
3020
3008 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops; 3021 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
3009 3022
3010 /* 3023 /*
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 1383e55ff8ec..9aee3ab6589e 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -1050,7 +1050,8 @@ static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1050static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev) 1050static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1051{ 1051{
1052 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 1052 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1053 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) 1053 if (rt2x00_intf_is_usb(rt2x00dev) &&
1054 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1054 return 0x1c + (2 * rt2x00dev->lna_gain); 1055 return 0x1c + (2 * rt2x00dev->lna_gain);
1055 else 1056 else
1056 return 0x2e + rt2x00dev->lna_gain; 1057 return 0x2e + rt2x00dev->lna_gain;
@@ -1285,33 +1286,38 @@ static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1285 u32 reg; 1286 u32 reg;
1286 unsigned int i; 1287 unsigned int i;
1287 1288
1288 /* 1289 if (rt2x00_intf_is_usb(rt2x00dev)) {
1289 * Wait untill BBP and RF are ready. 1290 /*
1290 */ 1291 * Wait untill BBP and RF are ready.
1291 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1292 */
1292 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 1293 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1293 if (reg && reg != ~0) 1294 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1294 break; 1295 if (reg && reg != ~0)
1295 msleep(1); 1296 break;
1296 } 1297 msleep(1);
1298 }
1297 1299
1298 if (i == REGISTER_BUSY_COUNT) { 1300 if (i == REGISTER_BUSY_COUNT) {
1299 ERROR(rt2x00dev, "Unstable hardware.\n"); 1301 ERROR(rt2x00dev, "Unstable hardware.\n");
1300 return -EBUSY; 1302 return -EBUSY;
1301 } 1303 }
1302 1304
1303 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 1305 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1304 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000); 1306 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1307 reg & ~0x00002000);
1308 }
1305 1309
1306 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1310 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1307 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 1311 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1308 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1); 1312 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1309 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 1313 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1310 1314
1311 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000); 1315 if (rt2x00_intf_is_usb(rt2x00dev)) {
1316 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1312 1317
1313 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, 1318 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1314 USB_MODE_RESET, REGISTER_TIMEOUT); 1319 USB_MODE_RESET, REGISTER_TIMEOUT);
1320 }
1315 1321
1316 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 1322 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1317 1323
@@ -1343,7 +1349,8 @@ static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1343 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 1349 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1344 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1350 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1345 1351
1346 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) { 1352 if (rt2x00_intf_is_usb(rt2x00dev) &&
1353 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1347 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1354 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1348 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1355 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1349 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 1356 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
@@ -1461,19 +1468,21 @@ static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1461 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1468 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1462 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1469 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1463 1470
1464 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 1471 if (rt2x00_intf_is_usb(rt2x00dev)) {
1472 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1465 1473
1466 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 1474 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1467 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 1475 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1468 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 1476 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1469 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 1477 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1470 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 1478 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1471 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 1479 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1472 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 1480 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1473 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 1481 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1474 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 1482 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1475 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 1483 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1476 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 1484 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1485 }
1477 1486
1478 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f); 1487 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1479 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); 1488 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
@@ -1519,9 +1528,11 @@ static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1519 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0); 1528 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1520 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0); 1529 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1521 1530
1522 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg); 1531 if (rt2x00_intf_is_usb(rt2x00dev)) {
1523 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30); 1532 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1524 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg); 1533 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1534 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1535 }
1525 1536
1526 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg); 1537 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1527 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0); 1538 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
@@ -1650,11 +1661,11 @@ static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1650 rt2800_bbp_write(rt2x00dev, 73, 0x12); 1661 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1651 } 1662 }
1652 1663
1653 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) { 1664 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1654 rt2800_bbp_write(rt2x00dev, 84, 0x19); 1665 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1655 }
1656 1666
1657 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) { 1667 if (rt2x00_intf_is_usb(rt2x00dev) &&
1668 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1658 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1669 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1659 rt2800_bbp_write(rt2x00dev, 84, 0x99); 1670 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1660 rt2800_bbp_write(rt2x00dev, 105, 0x05); 1671 rt2800_bbp_write(rt2x00dev, 105, 0x05);
@@ -1738,7 +1749,8 @@ static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1738 u8 rfcsr; 1749 u8 rfcsr;
1739 u8 bbp; 1750 u8 bbp;
1740 1751
1741 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION) 1752 if (rt2x00_intf_is_usb(rt2x00dev) &&
1753 rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1742 return 0; 1754 return 0;
1743 1755
1744 /* 1756 /*
@@ -1751,26 +1763,28 @@ static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1751 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 1763 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1752 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1764 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1753 1765
1754 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1766 if (rt2x00_intf_is_usb(rt2x00dev)) {
1755 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1767 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1756 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1768 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1757 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 1769 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1758 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1770 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1759 rt2800_rfcsr_write(rt2x00dev, 10, 0x71); 1771 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1760 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1772 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1761 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 1773 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1762 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1774 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1763 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 1775 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1764 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 1776 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1765 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 1777 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1766 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 1778 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1767 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 1779 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1768 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 1780 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1769 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1781 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1770 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 1782 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1771 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1783 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1772 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 1784 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1773 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 1785 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1786 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1787 }
1774 1788
1775 /* 1789 /*
1776 * Set RX Filter calibration for 20MHz and 40MHz 1790 * Set RX Filter calibration for 20MHz and 40MHz
@@ -2644,6 +2658,8 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2644{ 2658{
2645 int retval; 2659 int retval;
2646 2660
2661 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
2662
2647 rt2x00dev->priv = (void *)&rt2800usb_rt2800_ops; 2663 rt2x00dev->priv = (void *)&rt2800usb_rt2800_ops;
2648 2664
2649 /* 2665 /*