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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2010-01-18 12:17:12 -0500
committerJeff Garzik <jgarzik@redhat.com>2010-03-01 14:58:46 -0500
commit460f5318460a9a3b2562d8055b9fb1c60b768e1f (patch)
tree7043ab4339aa826e307800e062ad8c663b0a954a /drivers
parentf777582f4963413320ce5fe1d1d3651a32075c07 (diff)
pata_via: store UDMA masks in via_isa_bridges table
* store UDMA masks in via_isa_bridges[] and while at it make "flags" field to be u8 instead of u16 * convert the driver to use UDMA masks from via_isa_bridges[] * remove no longer needed VIA_UDMA* defines Make some minor documentation and CodingStyle fixes while at it. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ata/pata_via.c204
1 files changed, 94 insertions, 110 deletions
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 82e75a1f1b95..6356377231fd 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -22,6 +22,7 @@
22 * VIA VT8233c - UDMA100 22 * VIA VT8233c - UDMA100
23 * VIA VT8235 - UDMA133 23 * VIA VT8235 - UDMA133
24 * VIA VT8237 - UDMA133 24 * VIA VT8237 - UDMA133
25 * VIA VT8237A - UDMA133
25 * VIA VT8237S - UDMA133 26 * VIA VT8237S - UDMA133
26 * VIA VT8251 - UDMA133 27 * VIA VT8251 - UDMA133
27 * 28 *
@@ -64,26 +65,15 @@
64#define DRV_NAME "pata_via" 65#define DRV_NAME "pata_via"
65#define DRV_VERSION "0.3.4" 66#define DRV_VERSION "0.3.4"
66 67
67/*
68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
69 * driver.
70 */
71
72enum { 68enum {
73 VIA_UDMA = 0x007, 69 VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */
74 VIA_UDMA_NONE = 0x000, 70 VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */
75 VIA_UDMA_33 = 0x001, 71 VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */
76 VIA_UDMA_66 = 0x002, 72 VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */
77 VIA_UDMA_100 = 0x003, 73 VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */
78 VIA_UDMA_133 = 0x004, 74 VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */
79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ 75 VIA_NO_ENABLES = 0x40, /* Has no enablebits */
80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ 76 VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */
81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
86 VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */
87}; 77};
88 78
89enum { 79enum {
@@ -99,40 +89,37 @@ static const struct via_isa_bridge {
99 u16 id; 89 u16 id;
100 u8 rev_min; 90 u8 rev_min;
101 u8 rev_max; 91 u8 rev_max;
102 u16 flags; 92 u8 udma_mask;
93 u8 flags;
103} via_isa_bridges[] = { 94} via_isa_bridges[] = {
104 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, 95 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
105 VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 96 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
106 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 | 97 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
107 VIA_BAD_AST | VIA_SATA_PATA }, 98 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
108 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, 99 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
109 VIA_UDMA_133 | VIA_BAD_AST }, 100 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
110 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 101 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
111 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 102 { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
112 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 103 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
113 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, 104 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
114 { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, 105 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
115 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 106 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
116 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 107 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
117 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 108 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
118 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 109 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
119 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, 110 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
120 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, 111 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
121 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, 112 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
122 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, 113 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
123 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, 114 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
124 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 115 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
125 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, 116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
126 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
127 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, 118 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
128 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, 119 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
129 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, 120 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
130 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, 121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
131 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, 122 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
132 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
133 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
134 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f,
135 VIA_UDMA_133 | VIA_BAD_AST },
136 { NULL } 123 { NULL }
137}; 124};
138 125
@@ -191,10 +178,10 @@ static int via_cable_detect(struct ata_port *ap) {
191 return ATA_CBL_SATA; 178 return ATA_CBL_SATA;
192 179
193 /* Early chips are 40 wire */ 180 /* Early chips are 40 wire */
194 if ((config->flags & VIA_UDMA) < VIA_UDMA_66) 181 if (config->udma_mask < ATA_UDMA4)
195 return ATA_CBL_PATA40; 182 return ATA_CBL_PATA40;
196 /* UDMA 66 chips have only drive side logic */ 183 /* UDMA 66 chips have only drive side logic */
197 else if ((config->flags & VIA_UDMA) < VIA_UDMA_100) 184 else if (config->udma_mask < ATA_UDMA5)
198 return ATA_CBL_PATA_UNK; 185 return ATA_CBL_PATA_UNK;
199 /* UDMA 100 or later */ 186 /* UDMA 100 or later */
200 pci_read_config_dword(pdev, 0x50, &ata66); 187 pci_read_config_dword(pdev, 0x50, &ata66);
@@ -233,7 +220,6 @@ static int via_pre_reset(struct ata_link *link, unsigned long deadline)
233 * @ap: ATA interface 220 * @ap: ATA interface
234 * @adev: ATA device 221 * @adev: ATA device
235 * @mode: ATA mode being programmed 222 * @mode: ATA mode being programmed
236 * @tdiv: Clocks per PCI clock
237 * @set_ast: Set to program address setup 223 * @set_ast: Set to program address setup
238 * @udma_type: UDMA mode/format of registers 224 * @udma_type: UDMA mode/format of registers
239 * 225 *
@@ -244,17 +230,27 @@ static int via_pre_reset(struct ata_link *link, unsigned long deadline)
244 * on the two channels. 230 * on the two channels.
245 */ 231 */
246 232
247static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) 233static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
234 int mode, int set_ast, int udma_type)
248{ 235{
249 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 236 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
250 struct ata_device *peer = ata_dev_pair(adev); 237 struct ata_device *peer = ata_dev_pair(adev);
251 struct ata_timing t, p; 238 struct ata_timing t, p;
252 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ 239 static int via_clock = 33333; /* Bus clock in kHZ */
253 unsigned long T = 1000000000 / via_clock; 240 unsigned long T = 1000000000 / via_clock;
254 unsigned long UT = T/tdiv; 241 unsigned long UT = T;
255 int ut; 242 int ut;
256 int offset = 3 - (2*ap->port_no) - adev->devno; 243 int offset = 3 - (2*ap->port_no) - adev->devno;
257 244
245 switch (udma_type) {
246 case ATA_UDMA4:
247 UT = T / 2; break;
248 case ATA_UDMA5:
249 UT = T / 3; break;
250 case ATA_UDMA6:
251 UT = T / 4; break;
252 }
253
258 /* Calculate the timing values we require */ 254 /* Calculate the timing values we require */
259 ata_timing_compute(adev, mode, &t, T, UT); 255 ata_timing_compute(adev, mode, &t, T, UT);
260 256
@@ -284,22 +280,20 @@ static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mo
284 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1)); 280 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
285 281
286 /* Load the UDMA bits according to type */ 282 /* Load the UDMA bits according to type */
287 switch(udma_type) { 283 switch (udma_type) {
288 default: 284 case ATA_UDMA2:
289 /* BUG() ? */ 285 default:
290 /* fall through */ 286 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
291 case 33: 287 break;
292 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; 288 case ATA_UDMA4:
293 break; 289 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
294 case 66: 290 break;
295 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; 291 case ATA_UDMA5:
296 break; 292 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
297 case 100: 293 break;
298 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 294 case ATA_UDMA6:
299 break; 295 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
300 case 133: 296 break;
301 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
302 break;
303 } 297 }
304 298
305 /* Set UDMA unless device is not UDMA capable */ 299 /* Set UDMA unless device is not UDMA capable */
@@ -325,22 +319,16 @@ static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
325{ 319{
326 const struct via_isa_bridge *config = ap->host->private_data; 320 const struct via_isa_bridge *config = ap->host->private_data;
327 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 321 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
328 int mode = config->flags & VIA_UDMA;
329 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
330 static u8 udma[5] = { 0, 33, 66, 100, 133 };
331 322
332 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); 323 via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);
333} 324}
334 325
335static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) 326static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
336{ 327{
337 const struct via_isa_bridge *config = ap->host->private_data; 328 const struct via_isa_bridge *config = ap->host->private_data;
338 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 329 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
339 int mode = config->flags & VIA_UDMA;
340 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
341 static u8 udma[5] = { 0, 33, 66, 100, 133 };
342 330
343 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); 331 via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);
344} 332}
345 333
346/** 334/**
@@ -604,33 +592,29 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
604 via_config_fifo(pdev, config->flags); 592 via_config_fifo(pdev, config->flags);
605 593
606 /* Clock set up */ 594 /* Clock set up */
607 switch(config->flags & VIA_UDMA) { 595 switch (config->udma_mask) {
608 case VIA_UDMA_NONE: 596 case 0x00:
609 if (config->flags & VIA_NO_UNMASK) 597 if (config->flags & VIA_NO_UNMASK)
610 ppi[0] = &via_mwdma_info_borked; 598 ppi[0] = &via_mwdma_info_borked;
611 else 599 else
612 ppi[0] = &via_mwdma_info; 600 ppi[0] = &via_mwdma_info;
613 break; 601 break;
614 case VIA_UDMA_33: 602 case ATA_UDMA2:
615 ppi[0] = &via_udma33_info; 603 ppi[0] = &via_udma33_info;
616 break; 604 break;
617 case VIA_UDMA_66: 605 case ATA_UDMA4:
618 ppi[0] = &via_udma66_info; 606 ppi[0] = &via_udma66_info;
619 /* The 66 MHz devices require we enable the clock */ 607 break;
620 pci_read_config_dword(pdev, 0x50, &timing); 608 case ATA_UDMA5:
621 timing |= 0x80008; 609 ppi[0] = &via_udma100_info;
622 pci_write_config_dword(pdev, 0x50, timing); 610 break;
623 break; 611 case ATA_UDMA6:
624 case VIA_UDMA_100: 612 ppi[0] = &via_udma133_info;
625 ppi[0] = &via_udma100_info; 613 break;
626 break; 614 default:
627 case VIA_UDMA_133: 615 WARN_ON(1);
628 ppi[0] = &via_udma133_info; 616 return -ENODEV;
629 break; 617 }
630 default:
631 WARN_ON(1);
632 return -ENODEV;
633 }
634 618
635 if (config->flags & VIA_BAD_CLK66) { 619 if (config->flags & VIA_BAD_CLK66) {
636 /* Disable the 66MHz clock on problem devices */ 620 /* Disable the 66MHz clock on problem devices */
@@ -667,7 +651,7 @@ static int via_reinit_one(struct pci_dev *pdev)
667 651
668 via_config_fifo(pdev, config->flags); 652 via_config_fifo(pdev, config->flags);
669 653
670 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { 654 if (config->udma_mask == ATA_UDMA4) {
671 /* The 66 MHz devices require we enable the clock */ 655 /* The 66 MHz devices require we enable the clock */
672 pci_read_config_dword(pdev, 0x50, &timing); 656 pci_read_config_dword(pdev, 0x50, &timing);
673 timing |= 0x80008; 657 timing |= 0x80008;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-03 00:39:49 -0400