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authorMichael Chan <mchan@broadcom.com>2007-10-17 22:26:15 -0400
committerDavid S. Miller <davem@davemloft.net>2007-10-17 22:26:15 -0400
commit239cd34327d12e84f5528caa7b11c9e651372c39 (patch)
treeccc48f92df8b887da38edeffb0c758545cf4e284 /drivers
parent8499fb594ad34ccde38058d7c3ae8093058b346a (diff)
[BNX2]: Fix Serdes WoL bug.
The bug is in the code in bnx2_set_power_state() that assumes copper devices when setting up WoL. This is no longer true after adding WoL support for Serdes devices. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2.c28
1 files changed, 19 insertions, 9 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 78ed633ceb82..2a79ffc4eea5 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -3079,14 +3079,18 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3079 autoneg = bp->autoneg; 3079 autoneg = bp->autoneg;
3080 advertising = bp->advertising; 3080 advertising = bp->advertising;
3081 3081
3082 bp->autoneg = AUTONEG_SPEED; 3082 if (bp->phy_port == PORT_TP) {
3083 bp->advertising = ADVERTISED_10baseT_Half | 3083 bp->autoneg = AUTONEG_SPEED;
3084 ADVERTISED_10baseT_Full | 3084 bp->advertising = ADVERTISED_10baseT_Half |
3085 ADVERTISED_100baseT_Half | 3085 ADVERTISED_10baseT_Full |
3086 ADVERTISED_100baseT_Full | 3086 ADVERTISED_100baseT_Half |
3087 ADVERTISED_Autoneg; 3087 ADVERTISED_100baseT_Full |
3088 ADVERTISED_Autoneg;
3089 }
3088 3090
3089 bnx2_setup_copper_phy(bp); 3091 spin_lock_bh(&bp->phy_lock);
3092 bnx2_setup_phy(bp, bp->phy_port);
3093 spin_unlock_bh(&bp->phy_lock);
3090 3094
3091 bp->autoneg = autoneg; 3095 bp->autoneg = autoneg;
3092 bp->advertising = advertising; 3096 bp->advertising = advertising;
@@ -3097,10 +3101,16 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3097 3101
3098 /* Enable port mode. */ 3102 /* Enable port mode. */
3099 val &= ~BNX2_EMAC_MODE_PORT; 3103 val &= ~BNX2_EMAC_MODE_PORT;
3100 val |= BNX2_EMAC_MODE_PORT_MII | 3104 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3101 BNX2_EMAC_MODE_MPKT_RCVD |
3102 BNX2_EMAC_MODE_ACPI_RCVD | 3105 BNX2_EMAC_MODE_ACPI_RCVD |
3103 BNX2_EMAC_MODE_MPKT; 3106 BNX2_EMAC_MODE_MPKT;
3107 if (bp->phy_port == PORT_TP)
3108 val |= BNX2_EMAC_MODE_PORT_MII;
3109 else {
3110 val |= BNX2_EMAC_MODE_PORT_GMII;
3111 if (bp->line_speed == SPEED_2500)
3112 val |= BNX2_EMAC_MODE_25G_MODE;
3113 }
3104 3114
3105 REG_WR(bp, BNX2_EMAC_MODE, val); 3115 REG_WR(bp, BNX2_EMAC_MODE, val);
3106 3116