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authorTomas Winkler <tomas.winkler@intel.com>2007-10-25 05:15:37 -0400
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:03:17 -0500
commitac17a947a4f47b642097d6814d6dcc60c297eb17 (patch)
treeca77e4c90f23631433548fb8a5a9a57611315b04 /drivers
parentaf7cca2a441f6e2ebeb2a920ef5af1bec8df96e8 (diff)
iwlwifi: replacing wording restricted to nic access in iwl-io
This patch replaces wording 'restricted' with more appropriate 'nic access' NIC access is grabbed to prevent NIC entering power save mode General cleanup of iwl-io.h Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c78
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c80
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.h146
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c74
-rw-r--r--drivers/net/wireless/iwlwifi/iwl4965-base.c82
5 files changed, 229 insertions, 231 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 077fa1023fe5..154f2a258db2 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -157,7 +157,7 @@ void iwl_disable_events(struct iwl_priv *priv)
157 return; 157 return;
158 } 158 }
159 159
160 ret = iwl_grab_restricted_access(priv); 160 ret = iwl_grab_nic_access(priv);
161 if (ret) { 161 if (ret) {
162 IWL_WARNING("Can not read from adapter at this time.\n"); 162 IWL_WARNING("Can not read from adapter at this time.\n");
163 return; 163 return;
@@ -165,18 +165,18 @@ void iwl_disable_events(struct iwl_priv *priv)
165 165
166 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32))); 166 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
167 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32))); 167 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
168 iwl_release_restricted_access(priv); 168 iwl_release_nic_access(priv);
169 169
170 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { 170 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
171 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n", 171 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
172 disable_ptr); 172 disable_ptr);
173 ret = iwl_grab_restricted_access(priv); 173 ret = iwl_grab_nic_access(priv);
174 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) 174 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
175 iwl_write_targ_mem(priv, 175 iwl_write_targ_mem(priv,
176 disable_ptr + (i * sizeof(u32)), 176 disable_ptr + (i * sizeof(u32)),
177 evt_disable[i]); 177 evt_disable[i]);
178 178
179 iwl_release_restricted_access(priv); 179 iwl_release_nic_access(priv);
180 } else { 180 } else {
181 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n"); 181 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
182 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n"); 182 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
@@ -720,7 +720,7 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
720 unsigned long flags; 720 unsigned long flags;
721 721
722 spin_lock_irqsave(&priv->lock, flags); 722 spin_lock_irqsave(&priv->lock, flags);
723 rc = iwl_grab_restricted_access(priv); 723 rc = iwl_grab_nic_access(priv);
724 if (rc) { 724 if (rc) {
725 spin_unlock_irqrestore(&priv->lock, flags); 725 spin_unlock_irqrestore(&priv->lock, flags);
726 return rc; 726 return rc;
@@ -735,19 +735,19 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
735 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 735 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
736 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 736 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
737 ~APMG_PS_CTRL_MSK_PWR_SRC); 737 ~APMG_PS_CTRL_MSK_PWR_SRC);
738 iwl_release_restricted_access(priv); 738 iwl_release_nic_access(priv);
739 739
740 iwl_poll_bit(priv, CSR_GPIO_IN, 740 iwl_poll_bit(priv, CSR_GPIO_IN,
741 CSR_GPIO_IN_VAL_VAUX_PWR_SRC, 741 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
742 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 742 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
743 } else 743 } else
744 iwl_release_restricted_access(priv); 744 iwl_release_nic_access(priv);
745 } else { 745 } else {
746 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 746 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
747 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 747 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
748 ~APMG_PS_CTRL_MSK_PWR_SRC); 748 ~APMG_PS_CTRL_MSK_PWR_SRC);
749 749
750 iwl_release_restricted_access(priv); 750 iwl_release_nic_access(priv);
751 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, 751 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
752 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ 752 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
753 } 753 }
@@ -762,18 +762,18 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
762 unsigned long flags; 762 unsigned long flags;
763 763
764 spin_lock_irqsave(&priv->lock, flags); 764 spin_lock_irqsave(&priv->lock, flags);
765 rc = iwl_grab_restricted_access(priv); 765 rc = iwl_grab_nic_access(priv);
766 if (rc) { 766 if (rc) {
767 spin_unlock_irqrestore(&priv->lock, flags); 767 spin_unlock_irqrestore(&priv->lock, flags);
768 return rc; 768 return rc;
769 } 769 }
770 770
771 iwl_write_restricted(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr); 771 iwl_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
772 iwl_write_restricted(priv, FH_RCSR_RPTR_ADDR(0), 772 iwl_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
773 priv->hw_setting.shared_phys + 773 priv->hw_setting.shared_phys +
774 offsetof(struct iwl_shared, rx_read_ptr[0])); 774 offsetof(struct iwl_shared, rx_read_ptr[0]));
775 iwl_write_restricted(priv, FH_RCSR_WPTR(0), 0); 775 iwl_write_direct32(priv, FH_RCSR_WPTR(0), 0);
776 iwl_write_restricted(priv, FH_RCSR_CONFIG(0), 776 iwl_write_direct32(priv, FH_RCSR_CONFIG(0),
777 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | 777 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
778 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | 778 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
779 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | 779 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
@@ -784,9 +784,9 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
784 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); 784 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
785 785
786 /* fake read to flush all prev I/O */ 786 /* fake read to flush all prev I/O */
787 iwl_read_restricted(priv, FH_RSSR_CTRL); 787 iwl_read_direct32(priv, FH_RSSR_CTRL);
788 788
789 iwl_release_restricted_access(priv); 789 iwl_release_nic_access(priv);
790 spin_unlock_irqrestore(&priv->lock, flags); 790 spin_unlock_irqrestore(&priv->lock, flags);
791 791
792 return 0; 792 return 0;
@@ -798,7 +798,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
798 unsigned long flags; 798 unsigned long flags;
799 799
800 spin_lock_irqsave(&priv->lock, flags); 800 spin_lock_irqsave(&priv->lock, flags);
801 rc = iwl_grab_restricted_access(priv); 801 rc = iwl_grab_nic_access(priv);
802 if (rc) { 802 if (rc) {
803 spin_unlock_irqrestore(&priv->lock, flags); 803 spin_unlock_irqrestore(&priv->lock, flags);
804 return rc; 804 return rc;
@@ -818,10 +818,10 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
818 iwl_write_prph(priv, SCD_TXF4MF_REG, 0x000004); 818 iwl_write_prph(priv, SCD_TXF4MF_REG, 0x000004);
819 iwl_write_prph(priv, SCD_TXF5MF_REG, 0x000005); 819 iwl_write_prph(priv, SCD_TXF5MF_REG, 0x000005);
820 820
821 iwl_write_restricted(priv, FH_TSSR_CBB_BASE, 821 iwl_write_direct32(priv, FH_TSSR_CBB_BASE,
822 priv->hw_setting.shared_phys); 822 priv->hw_setting.shared_phys);
823 823
824 iwl_write_restricted(priv, FH_TSSR_MSG_CONFIG, 824 iwl_write_direct32(priv, FH_TSSR_MSG_CONFIG,
825 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | 825 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
826 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | 826 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
827 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | 827 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
@@ -830,7 +830,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
830 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 830 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
831 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 831 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
832 832
833 iwl_release_restricted_access(priv); 833 iwl_release_nic_access(priv);
834 spin_unlock_irqrestore(&priv->lock, flags); 834 spin_unlock_irqrestore(&priv->lock, flags);
835 835
836 return 0; 836 return 0;
@@ -896,7 +896,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
896 return rc; 896 return rc;
897 } 897 }
898 898
899 rc = iwl_grab_restricted_access(priv); 899 rc = iwl_grab_nic_access(priv);
900 if (rc) { 900 if (rc) {
901 spin_unlock_irqrestore(&priv->lock, flags); 901 spin_unlock_irqrestore(&priv->lock, flags);
902 return rc; 902 return rc;
@@ -907,7 +907,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
907 udelay(20); 907 udelay(20);
908 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 908 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
909 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 909 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
910 iwl_release_restricted_access(priv); 910 iwl_release_nic_access(priv);
911 spin_unlock_irqrestore(&priv->lock, flags); 911 spin_unlock_irqrestore(&priv->lock, flags);
912 912
913 /* Determine HW type */ 913 /* Determine HW type */
@@ -998,13 +998,13 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
998 iwl_rx_queue_update_write_ptr(priv, rxq); 998 iwl_rx_queue_update_write_ptr(priv, rxq);
999 */ 999 */
1000 1000
1001 rc = iwl_grab_restricted_access(priv); 1001 rc = iwl_grab_nic_access(priv);
1002 if (rc) { 1002 if (rc) {
1003 spin_unlock_irqrestore(&priv->lock, flags); 1003 spin_unlock_irqrestore(&priv->lock, flags);
1004 return rc; 1004 return rc;
1005 } 1005 }
1006 iwl_write_restricted(priv, FH_RCSR_WPTR(0), rxq->write & ~7); 1006 iwl_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1007 iwl_release_restricted_access(priv); 1007 iwl_release_nic_access(priv);
1008 1008
1009 spin_unlock_irqrestore(&priv->lock, flags); 1009 spin_unlock_irqrestore(&priv->lock, flags);
1010 1010
@@ -1037,7 +1037,7 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
1037 unsigned long flags; 1037 unsigned long flags;
1038 1038
1039 spin_lock_irqsave(&priv->lock, flags); 1039 spin_lock_irqsave(&priv->lock, flags);
1040 if (iwl_grab_restricted_access(priv)) { 1040 if (iwl_grab_nic_access(priv)) {
1041 spin_unlock_irqrestore(&priv->lock, flags); 1041 spin_unlock_irqrestore(&priv->lock, flags);
1042 iwl_hw_txq_ctx_free(priv); 1042 iwl_hw_txq_ctx_free(priv);
1043 return; 1043 return;
@@ -1048,13 +1048,13 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
1048 1048
1049 /* reset TFD queues */ 1049 /* reset TFD queues */
1050 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { 1050 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
1051 iwl_write_restricted(priv, FH_TCSR_CONFIG(queue), 0x0); 1051 iwl_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1052 iwl_poll_restricted_bit(priv, FH_TSSR_TX_STATUS, 1052 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
1053 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue), 1053 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1054 1000); 1054 1000);
1055 } 1055 }
1056 1056
1057 iwl_release_restricted_access(priv); 1057 iwl_release_nic_access(priv);
1058 spin_unlock_irqrestore(&priv->lock, flags); 1058 spin_unlock_irqrestore(&priv->lock, flags);
1059 1059
1060 iwl_hw_txq_ctx_free(priv); 1060 iwl_hw_txq_ctx_free(priv);
@@ -1108,7 +1108,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
1108 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1108 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1109 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 1109 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1110 1110
1111 rc = iwl_grab_restricted_access(priv); 1111 rc = iwl_grab_nic_access(priv);
1112 if (!rc) { 1112 if (!rc) {
1113 iwl_write_prph(priv, APMG_CLK_CTRL_REG, 1113 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1114 APMG_CLK_VAL_BSM_CLK_RQT); 1114 APMG_CLK_VAL_BSM_CLK_RQT);
@@ -1133,7 +1133,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
1133 udelay(5); 1133 udelay(5);
1134 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, 1134 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1135 APMG_PS_CTRL_VAL_RESET_REQ); 1135 APMG_PS_CTRL_VAL_RESET_REQ);
1136 iwl_release_restricted_access(priv); 1136 iwl_release_nic_access(priv);
1137 } 1137 }
1138 1138
1139 /* Clear the 'host command active' bit... */ 1139 /* Clear the 'host command active' bit... */
@@ -2096,18 +2096,18 @@ int iwl_hw_rxq_stop(struct iwl_priv *priv)
2096 unsigned long flags; 2096 unsigned long flags;
2097 2097
2098 spin_lock_irqsave(&priv->lock, flags); 2098 spin_lock_irqsave(&priv->lock, flags);
2099 rc = iwl_grab_restricted_access(priv); 2099 rc = iwl_grab_nic_access(priv);
2100 if (rc) { 2100 if (rc) {
2101 spin_unlock_irqrestore(&priv->lock, flags); 2101 spin_unlock_irqrestore(&priv->lock, flags);
2102 return rc; 2102 return rc;
2103 } 2103 }
2104 2104
2105 iwl_write_restricted(priv, FH_RCSR_CONFIG(0), 0); 2105 iwl_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2106 rc = iwl_poll_restricted_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000); 2106 rc = iwl_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
2107 if (rc < 0) 2107 if (rc < 0)
2108 IWL_ERROR("Can't stop Rx DMA.\n"); 2108 IWL_ERROR("Can't stop Rx DMA.\n");
2109 2109
2110 iwl_release_restricted_access(priv); 2110 iwl_release_nic_access(priv);
2111 spin_unlock_irqrestore(&priv->lock, flags); 2111 spin_unlock_irqrestore(&priv->lock, flags);
2112 2112
2113 return 0; 2113 return 0;
@@ -2124,21 +2124,21 @@ int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2124 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); 2124 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2125 2125
2126 spin_lock_irqsave(&priv->lock, flags); 2126 spin_lock_irqsave(&priv->lock, flags);
2127 rc = iwl_grab_restricted_access(priv); 2127 rc = iwl_grab_nic_access(priv);
2128 if (rc) { 2128 if (rc) {
2129 spin_unlock_irqrestore(&priv->lock, flags); 2129 spin_unlock_irqrestore(&priv->lock, flags);
2130 return rc; 2130 return rc;
2131 } 2131 }
2132 iwl_write_restricted(priv, FH_CBCC_CTRL(txq_id), 0); 2132 iwl_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2133 iwl_write_restricted(priv, FH_CBCC_BASE(txq_id), 0); 2133 iwl_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
2134 2134
2135 iwl_write_restricted(priv, FH_TCSR_CONFIG(txq_id), 2135 iwl_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
2136 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | 2136 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2137 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | 2137 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2138 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2138 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2139 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2139 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2140 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2140 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2141 iwl_release_restricted_access(priv); 2141 iwl_release_nic_access(priv);
2142 2142
2143 /* fake read to flush all prev. writes */ 2143 /* fake read to flush all prev. writes */
2144 iwl_read32(priv, FH_TSSR_CBB_BASE); 2144 iwl_read32(priv, FH_TSSR_CBB_BASE);
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 5914657f1ca3..8e9810b72ace 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -139,20 +139,20 @@ int iwl_hw_rxq_stop(struct iwl_priv *priv)
139 unsigned long flags; 139 unsigned long flags;
140 140
141 spin_lock_irqsave(&priv->lock, flags); 141 spin_lock_irqsave(&priv->lock, flags);
142 rc = iwl_grab_restricted_access(priv); 142 rc = iwl_grab_nic_access(priv);
143 if (rc) { 143 if (rc) {
144 spin_unlock_irqrestore(&priv->lock, flags); 144 spin_unlock_irqrestore(&priv->lock, flags);
145 return rc; 145 return rc;
146 } 146 }
147 147
148 /* stop HW */ 148 /* stop HW */
149 iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 149 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
150 rc = iwl_poll_restricted_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, 150 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
151 (1 << 24), 1000); 151 (1 << 24), 1000);
152 if (rc < 0) 152 if (rc < 0)
153 IWL_ERROR("Can't stop Rx DMA.\n"); 153 IWL_ERROR("Can't stop Rx DMA.\n");
154 154
155 iwl_release_restricted_access(priv); 155 iwl_release_nic_access(priv);
156 spin_unlock_irqrestore(&priv->lock, flags); 156 spin_unlock_irqrestore(&priv->lock, flags);
157 157
158 return 0; 158 return 0;
@@ -196,7 +196,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
196 unsigned long flags; 196 unsigned long flags;
197 197
198 spin_lock_irqsave(&priv->lock, flags); 198 spin_lock_irqsave(&priv->lock, flags);
199 ret = iwl_grab_restricted_access(priv); 199 ret = iwl_grab_nic_access(priv);
200 if (ret) { 200 if (ret) {
201 spin_unlock_irqrestore(&priv->lock, flags); 201 spin_unlock_irqrestore(&priv->lock, flags);
202 return ret; 202 return ret;
@@ -217,7 +217,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
217 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 217 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
218 ~APMG_PS_CTRL_MSK_PWR_SRC); 218 ~APMG_PS_CTRL_MSK_PWR_SRC);
219 219
220 iwl_release_restricted_access(priv); 220 iwl_release_nic_access(priv);
221 spin_unlock_irqrestore(&priv->lock, flags); 221 spin_unlock_irqrestore(&priv->lock, flags);
222 222
223 return ret; 223 return ret;
@@ -229,24 +229,24 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
229 unsigned long flags; 229 unsigned long flags;
230 230
231 spin_lock_irqsave(&priv->lock, flags); 231 spin_lock_irqsave(&priv->lock, flags);
232 rc = iwl_grab_restricted_access(priv); 232 rc = iwl_grab_nic_access(priv);
233 if (rc) { 233 if (rc) {
234 spin_unlock_irqrestore(&priv->lock, flags); 234 spin_unlock_irqrestore(&priv->lock, flags);
235 return rc; 235 return rc;
236 } 236 }
237 237
238 /* stop HW */ 238 /* stop HW */
239 iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 239 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
240 240
241 iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 241 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
242 iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 242 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
243 rxq->dma_addr >> 8); 243 rxq->dma_addr >> 8);
244 244
245 iwl_write_restricted(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, 245 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
246 (priv->hw_setting.shared_phys + 246 (priv->hw_setting.shared_phys +
247 offsetof(struct iwl_shared, val0)) >> 4); 247 offsetof(struct iwl_shared, val0)) >> 4);
248 248
249 iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 249 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
250 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 250 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
251 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 251 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
252 IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K | 252 IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
@@ -258,7 +258,7 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
258 * iwl_write32(priv,CSR_INT_COAL_REG,0); 258 * iwl_write32(priv,CSR_INT_COAL_REG,0);
259 */ 259 */
260 260
261 iwl_release_restricted_access(priv); 261 iwl_release_nic_access(priv);
262 spin_unlock_irqrestore(&priv->lock, flags); 262 spin_unlock_irqrestore(&priv->lock, flags);
263 263
264 return 0; 264 return 0;
@@ -270,13 +270,13 @@ static int iwl4965_kw_init(struct iwl_priv *priv)
270 int rc; 270 int rc;
271 271
272 spin_lock_irqsave(&priv->lock, flags); 272 spin_lock_irqsave(&priv->lock, flags);
273 rc = iwl_grab_restricted_access(priv); 273 rc = iwl_grab_nic_access(priv);
274 if (rc) 274 if (rc)
275 goto out; 275 goto out;
276 276
277 iwl_write_restricted(priv, IWL_FH_KW_MEM_ADDR_REG, 277 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
278 priv->kw.dma_addr >> 4); 278 priv->kw.dma_addr >> 4);
279 iwl_release_restricted_access(priv); 279 iwl_release_nic_access(priv);
280out: 280out:
281 spin_unlock_irqrestore(&priv->lock, flags); 281 spin_unlock_irqrestore(&priv->lock, flags);
282 return rc; 282 return rc;
@@ -375,7 +375,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
375 375
376 spin_lock_irqsave(&priv->lock, flags); 376 spin_lock_irqsave(&priv->lock, flags);
377 377
378 rc = iwl_grab_restricted_access(priv); 378 rc = iwl_grab_nic_access(priv);
379 if (unlikely(rc)) { 379 if (unlikely(rc)) {
380 IWL_ERROR("TX reset failed"); 380 IWL_ERROR("TX reset failed");
381 spin_unlock_irqrestore(&priv->lock, flags); 381 spin_unlock_irqrestore(&priv->lock, flags);
@@ -383,7 +383,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
383 } 383 }
384 384
385 iwl_write_prph(priv, SCD_TXFACT, 0); 385 iwl_write_prph(priv, SCD_TXFACT, 0);
386 iwl_release_restricted_access(priv); 386 iwl_release_nic_access(priv);
387 spin_unlock_irqrestore(&priv->lock, flags); 387 spin_unlock_irqrestore(&priv->lock, flags);
388 388
389 rc = iwl4965_kw_init(priv); 389 rc = iwl4965_kw_init(priv);
@@ -441,7 +441,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
441 return rc; 441 return rc;
442 } 442 }
443 443
444 rc = iwl_grab_restricted_access(priv); 444 rc = iwl_grab_nic_access(priv);
445 if (rc) { 445 if (rc) {
446 spin_unlock_irqrestore(&priv->lock, flags); 446 spin_unlock_irqrestore(&priv->lock, flags);
447 return rc; 447 return rc;
@@ -459,7 +459,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
459 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 459 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
460 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 460 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
461 461
462 iwl_release_restricted_access(priv); 462 iwl_release_nic_access(priv);
463 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); 463 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
464 spin_unlock_irqrestore(&priv->lock, flags); 464 spin_unlock_irqrestore(&priv->lock, flags);
465 465
@@ -505,7 +505,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
505 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 505 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
506 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 506 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
507 507
508 rc = iwl_grab_restricted_access(priv); 508 rc = iwl_grab_nic_access(priv);
509 if (rc < 0) { 509 if (rc < 0) {
510 spin_unlock_irqrestore(&priv->lock, flags); 510 spin_unlock_irqrestore(&priv->lock, flags);
511 IWL_DEBUG_INFO("Failed to init the card\n"); 511 IWL_DEBUG_INFO("Failed to init the card\n");
@@ -519,7 +519,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
519 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, 519 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
520 APMG_PS_CTRL_VAL_RESET_REQ); 520 APMG_PS_CTRL_VAL_RESET_REQ);
521 521
522 iwl_release_restricted_access(priv); 522 iwl_release_nic_access(priv);
523 spin_unlock_irqrestore(&priv->lock, flags); 523 spin_unlock_irqrestore(&priv->lock, flags);
524 524
525 iwl_hw_card_show_info(priv); 525 iwl_hw_card_show_info(priv);
@@ -603,18 +603,18 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
603 /* reset TFD queues */ 603 /* reset TFD queues */
604 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) { 604 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
605 spin_lock_irqsave(&priv->lock, flags); 605 spin_lock_irqsave(&priv->lock, flags);
606 if (iwl_grab_restricted_access(priv)) { 606 if (iwl_grab_nic_access(priv)) {
607 spin_unlock_irqrestore(&priv->lock, flags); 607 spin_unlock_irqrestore(&priv->lock, flags);
608 continue; 608 continue;
609 } 609 }
610 610
611 iwl_write_restricted(priv, 611 iwl_write_direct32(priv,
612 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 612 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
613 0x0); 613 0x0);
614 iwl_poll_restricted_bit(priv, IWL_FH_TSSR_TX_STATUS_REG, 614 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
615 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE 615 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
616 (txq_id), 200); 616 (txq_id), 200);
617 iwl_release_restricted_access(priv); 617 iwl_release_nic_access(priv);
618 spin_unlock_irqrestore(&priv->lock, flags); 618 spin_unlock_irqrestore(&priv->lock, flags);
619 } 619 }
620 620
@@ -641,7 +641,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
641 641
642 udelay(10); 642 udelay(10);
643 643
644 rc = iwl_grab_restricted_access(priv); 644 rc = iwl_grab_nic_access(priv);
645 if (!rc) { 645 if (!rc) {
646 iwl_write_prph(priv, APMG_CLK_EN_REG, 646 iwl_write_prph(priv, APMG_CLK_EN_REG,
647 APMG_CLK_VAL_DMA_CLK_RQT | 647 APMG_CLK_VAL_DMA_CLK_RQT |
@@ -652,7 +652,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
652 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 652 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
653 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 653 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
654 654
655 iwl_release_restricted_access(priv); 655 iwl_release_nic_access(priv);
656 } 656 }
657 657
658 clear_bit(STATUS_HCMD_ACTIVE, &priv->status); 658 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
@@ -1581,7 +1581,7 @@ static void iwl4965_bg_txpower_work(struct work_struct *work)
1581 */ 1581 */
1582static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index) 1582static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1583{ 1583{
1584 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 1584 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1585 (index & 0xff) | (txq_id << 8)); 1585 (index & 0xff) | (txq_id << 8));
1586 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index); 1586 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
1587} 1587}
@@ -1648,7 +1648,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1648 priv->chain_noise_data.delta_gain_code[i] = 1648 priv->chain_noise_data.delta_gain_code[i] =
1649 CHAIN_NOISE_DELTA_GAIN_INIT_VAL; 1649 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1650#endif /* CONFIG_IWLWIFI_SENSITIVITY*/ 1650#endif /* CONFIG_IWLWIFI_SENSITIVITY*/
1651 rc = iwl_grab_restricted_access(priv); 1651 rc = iwl_grab_nic_access(priv);
1652 if (rc) { 1652 if (rc) {
1653 spin_unlock_irqrestore(&priv->lock, flags); 1653 spin_unlock_irqrestore(&priv->lock, flags);
1654 return rc; 1654 return rc;
@@ -1671,7 +1671,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1671 /* initiate the queues */ 1671 /* initiate the queues */
1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) { 1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0); 1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
1674 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 1674 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1675 iwl_write_targ_mem(priv, priv->scd_base_addr + 1675 iwl_write_targ_mem(priv, priv->scd_base_addr +
1676 SCD_CONTEXT_QUEUE_OFFSET(i), 1676 SCD_CONTEXT_QUEUE_OFFSET(i),
1677 (SCD_WIN_SIZE << 1677 (SCD_WIN_SIZE <<
@@ -1699,7 +1699,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1699 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 1699 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1700 } 1700 }
1701 1701
1702 iwl_release_restricted_access(priv); 1702 iwl_release_nic_access(priv);
1703 spin_unlock_irqrestore(&priv->lock, flags); 1703 spin_unlock_irqrestore(&priv->lock, flags);
1704 1704
1705 return 0; 1705 return 0;
@@ -2688,19 +2688,19 @@ int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2688 int txq_id = txq->q.id; 2688 int txq_id = txq->q.id;
2689 2689
2690 spin_lock_irqsave(&priv->lock, flags); 2690 spin_lock_irqsave(&priv->lock, flags);
2691 rc = iwl_grab_restricted_access(priv); 2691 rc = iwl_grab_nic_access(priv);
2692 if (rc) { 2692 if (rc) {
2693 spin_unlock_irqrestore(&priv->lock, flags); 2693 spin_unlock_irqrestore(&priv->lock, flags);
2694 return rc; 2694 return rc;
2695 } 2695 }
2696 2696
2697 iwl_write_restricted(priv, FH_MEM_CBBC_QUEUE(txq_id), 2697 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2698 txq->q.dma_addr >> 8); 2698 txq->q.dma_addr >> 8);
2699 iwl_write_restricted( 2699 iwl_write_direct32(
2700 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 2700 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2701 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2701 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2702 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); 2702 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2703 iwl_release_restricted_access(priv); 2703 iwl_release_nic_access(priv);
2704 spin_unlock_irqrestore(&priv->lock, flags); 2704 spin_unlock_irqrestore(&priv->lock, flags);
2705 2705
2706 return 0; 2706 return 0;
@@ -4188,7 +4188,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4188 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid); 4188 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
4189 4189
4190 spin_lock_irqsave(&priv->lock, flags); 4190 spin_lock_irqsave(&priv->lock, flags);
4191 rc = iwl_grab_restricted_access(priv); 4191 rc = iwl_grab_nic_access(priv);
4192 if (rc) { 4192 if (rc) {
4193 spin_unlock_irqrestore(&priv->lock, flags); 4193 spin_unlock_irqrestore(&priv->lock, flags);
4194 return rc; 4194 return rc;
@@ -4221,7 +4221,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4221 4221
4222 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 4222 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4223 4223
4224 iwl_release_restricted_access(priv); 4224 iwl_release_nic_access(priv);
4225 spin_unlock_irqrestore(&priv->lock, flags); 4225 spin_unlock_irqrestore(&priv->lock, flags);
4226 4226
4227 return 0; 4227 return 0;
@@ -4243,7 +4243,7 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4243 } 4243 }
4244 4244
4245 spin_lock_irqsave(&priv->lock, flags); 4245 spin_lock_irqsave(&priv->lock, flags);
4246 rc = iwl_grab_restricted_access(priv); 4246 rc = iwl_grab_nic_access(priv);
4247 if (rc) { 4247 if (rc) {
4248 spin_unlock_irqrestore(&priv->lock, flags); 4248 spin_unlock_irqrestore(&priv->lock, flags);
4249 return rc; 4249 return rc;
@@ -4262,7 +4262,7 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4262 iwl4965_txq_ctx_deactivate(priv, txq_id); 4262 iwl4965_txq_ctx_deactivate(priv, txq_id);
4263 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 4263 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4264 4264
4265 iwl_release_restricted_access(priv); 4265 iwl_release_nic_access(priv);
4266 spin_unlock_irqrestore(&priv->lock, flags); 4266 spin_unlock_irqrestore(&priv->lock, flags);
4267 4267
4268 return 0; 4268 return 0;
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h
index 5cdcfc43fa14..43afcda6f73e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-io.h
@@ -42,15 +42,14 @@
42 * check or debug information is printed when that function is called. 42 * check or debug information is printed when that function is called.
43 * 43 *
44 * A double __ prefix before an access function means that state is checked 44 * A double __ prefix before an access function means that state is checked
45 * (in the case of *restricted calls) and the current line number is printed 45 * and the current line number is printed in addition to any other debug output.
46 * in addition to any other debug output.
47 * 46 *
48 * The non-prefixed name is the #define that maps the caller into a 47 * The non-prefixed name is the #define that maps the caller into a
49 * #define that provides the caller's __LINE__ to the double prefix version. 48 * #define that provides the caller's __LINE__ to the double prefix version.
50 * 49 *
51 * If you wish to call the function without any debug or state checking, 50 * If you wish to call the function without any debug or state checking,
52 * you should use the single _ prefix version (as is used by dependent IO 51 * you should use the single _ prefix version (as is used by dependent IO
53 * routines, for example _iwl_read_restricted calls the non-check version of 52 * routines, for example _iwl_read_direct32 calls the non-check version of
54 * _iwl_read32.) 53 * _iwl_read32.)
55 * 54 *
56 * These declarations are *extremely* useful in quickly isolating code deltas 55 * These declarations are *extremely* useful in quickly isolating code deltas
@@ -65,8 +64,7 @@
65static inline void __iwl_write32(const char *f, u32 l, struct iwl_priv *iwl, 64static inline void __iwl_write32(const char *f, u32 l, struct iwl_priv *iwl,
66 u32 ofs, u32 val) 65 u32 ofs, u32 val)
67{ 66{
68 IWL_DEBUG_IO("write_direct32(0x%08X, 0x%08X) - %s %d\n", 67 IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
69 (u32) (ofs), (u32) (val), f, l);
70 _iwl_write32(iwl, ofs, val); 68 _iwl_write32(iwl, ofs, val);
71} 69}
72#define iwl_write32(iwl, ofs, val) \ 70#define iwl_write32(iwl, ofs, val) \
@@ -106,16 +104,16 @@ static inline int __iwl_poll_bit(const char *f, u32 l,
106 struct iwl_priv *priv, u32 addr, 104 struct iwl_priv *priv, u32 addr,
107 u32 bits, u32 mask, int timeout) 105 u32 bits, u32 mask, int timeout)
108{ 106{
109 int rc = _iwl_poll_bit(priv, addr, bits, mask, timeout); 107 int ret = _iwl_poll_bit(priv, addr, bits, mask, timeout);
110 if (unlikely(rc == -ETIMEDOUT)) 108 if (unlikely(ret == -ETIMEDOUT))
111 IWL_DEBUG_IO 109 IWL_DEBUG_IO
112 ("poll_bit(0x%08X, 0x%08X, 0x%08X) - timedout - %s %d\n", 110 ("poll_bit(0x%08X, 0x%08X, 0x%08X) - timedout - %s %d\n",
113 addr, bits, mask, f, l); 111 addr, bits, mask, f, l);
114 else 112 else
115 IWL_DEBUG_IO 113 IWL_DEBUG_IO
116 ("poll_bit(0x%08X, 0x%08X, 0x%08X) = 0x%08X - %s %d\n", 114 ("poll_bit(0x%08X, 0x%08X, 0x%08X) = 0x%08X - %s %d\n",
117 addr, bits, mask, rc, f, l); 115 addr, bits, mask, ret, f, l);
118 return rc; 116 return ret;
119} 117}
120#define iwl_poll_bit(iwl, addr, bits, mask, timeout) \ 118#define iwl_poll_bit(iwl, addr, bits, mask, timeout) \
121 __iwl_poll_bit(__FILE__, __LINE__, iwl, addr, bits, mask, timeout) 119 __iwl_poll_bit(__FILE__, __LINE__, iwl, addr, bits, mask, timeout)
@@ -157,9 +155,9 @@ static inline void __iwl_clear_bit(const char *f, u32 l,
157#define iwl_clear_bit(p, r, m) _iwl_clear_bit(p, r, m) 155#define iwl_clear_bit(p, r, m) _iwl_clear_bit(p, r, m)
158#endif 156#endif
159 157
160static inline int _iwl_grab_restricted_access(struct iwl_priv *priv) 158static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
161{ 159{
162 int rc; 160 int ret;
163 u32 gp_ctl; 161 u32 gp_ctl;
164 162
165#ifdef CONFIG_IWLWIFI_DEBUG 163#ifdef CONFIG_IWLWIFI_DEBUG
@@ -184,11 +182,11 @@ static inline int _iwl_grab_restricted_access(struct iwl_priv *priv)
184 182
185 /* this bit wakes up the NIC */ 183 /* this bit wakes up the NIC */
186 _iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 184 _iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
187 rc = _iwl_poll_bit(priv, CSR_GP_CNTRL, 185 ret = _iwl_poll_bit(priv, CSR_GP_CNTRL,
188 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 186 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
189 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 187 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
190 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50); 188 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50);
191 if (rc < 0) { 189 if (ret < 0) {
192 IWL_ERROR("MAC is in deep sleep!\n"); 190 IWL_ERROR("MAC is in deep sleep!\n");
193 return -EIO; 191 return -EIO;
194 } 192 }
@@ -200,25 +198,24 @@ static inline int _iwl_grab_restricted_access(struct iwl_priv *priv)
200} 198}
201 199
202#ifdef CONFIG_IWLWIFI_DEBUG 200#ifdef CONFIG_IWLWIFI_DEBUG
203static inline int __iwl_grab_restricted_access(const char *f, u32 l, 201static inline int __iwl_grab_nic_access(const char *f, u32 l,
204 struct iwl_priv *priv) 202 struct iwl_priv *priv)
205{ 203{
206 if (atomic_read(&priv->restrict_refcnt)) 204 if (atomic_read(&priv->restrict_refcnt))
207 IWL_DEBUG_INFO("Grabbing access while already held at " 205 IWL_DEBUG_INFO("Grabbing access while already held at "
208 "line %d.\n", l); 206 "line %d.\n", l);
209 207
210 IWL_DEBUG_IO("grabbing restricted access - %s %d\n", f, l); 208 IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l);
211 209 return _iwl_grab_nic_access(priv);
212 return _iwl_grab_restricted_access(priv);
213} 210}
214#define iwl_grab_restricted_access(priv) \ 211#define iwl_grab_nic_access(priv) \
215 __iwl_grab_restricted_access(__FILE__, __LINE__, priv) 212 __iwl_grab_nic_access(__FILE__, __LINE__, priv)
216#else 213#else
217#define iwl_grab_restricted_access(priv) \ 214#define iwl_grab_nic_access(priv) \
218 _iwl_grab_restricted_access(priv) 215 _iwl_grab_nic_access(priv)
219#endif 216#endif
220 217
221static inline void _iwl_release_restricted_access(struct iwl_priv *priv) 218static inline void _iwl_release_nic_access(struct iwl_priv *priv)
222{ 219{
223#ifdef CONFIG_IWLWIFI_DEBUG 220#ifdef CONFIG_IWLWIFI_DEBUG
224 if (atomic_dec_and_test(&priv->restrict_refcnt)) 221 if (atomic_dec_and_test(&priv->restrict_refcnt))
@@ -227,80 +224,80 @@ static inline void _iwl_release_restricted_access(struct iwl_priv *priv)
227 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 224 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
228} 225}
229#ifdef CONFIG_IWLWIFI_DEBUG 226#ifdef CONFIG_IWLWIFI_DEBUG
230static inline void __iwl_release_restricted_access(const char *f, u32 l, 227static inline void __iwl_release_nic_access(const char *f, u32 l,
231 struct iwl_priv *priv) 228 struct iwl_priv *priv)
232{ 229{
233 if (atomic_read(&priv->restrict_refcnt) <= 0) 230 if (atomic_read(&priv->restrict_refcnt) <= 0)
234 IWL_ERROR("Release unheld restricted access at line %d.\n", l); 231 IWL_ERROR("Release unheld nic access at line %d.\n", l);
235 232
236 IWL_DEBUG_IO("releasing restricted access - %s %d\n", f, l); 233 IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l);
237 _iwl_release_restricted_access(priv); 234 _iwl_release_nic_access(priv);
238} 235}
239#define iwl_release_restricted_access(priv) \ 236#define iwl_release_nic_access(priv) \
240 __iwl_release_restricted_access(__FILE__, __LINE__, priv) 237 __iwl_release_nic_access(__FILE__, __LINE__, priv)
241#else 238#else
242#define iwl_release_restricted_access(priv) \ 239#define iwl_release_nic_access(priv) \
243 _iwl_release_restricted_access(priv) 240 _iwl_release_nic_access(priv)
244#endif 241#endif
245 242
246static inline u32 _iwl_read_restricted(struct iwl_priv *priv, u32 reg) 243static inline u32 _iwl_read_direct32(struct iwl_priv *priv, u32 reg)
247{ 244{
248 return _iwl_read32(priv, reg); 245 return _iwl_read32(priv, reg);
249} 246}
250#ifdef CONFIG_IWLWIFI_DEBUG 247#ifdef CONFIG_IWLWIFI_DEBUG
251static inline u32 __iwl_read_restricted(const char *f, u32 l, 248static inline u32 __iwl_read_direct32(const char *f, u32 l,
252 struct iwl_priv *priv, u32 reg) 249 struct iwl_priv *priv, u32 reg)
253{ 250{
254 u32 value = _iwl_read_restricted(priv, reg); 251 u32 value = _iwl_read_direct32(priv, reg);
255 if (!atomic_read(&priv->restrict_refcnt)) 252 if (!atomic_read(&priv->restrict_refcnt))
256 IWL_ERROR("Unrestricted access from %s %d\n", f, l); 253 IWL_ERROR("Nic access not held from %s %d\n", f, l);
257 IWL_DEBUG_IO("read_restricted(0x%4X) = 0x%08x - %s %d \n", reg, value, 254 IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value,
258 f, l); 255 f, l);
259 return value; 256 return value;
260} 257}
261#define iwl_read_restricted(priv, reg) \ 258#define iwl_read_direct32(priv, reg) \
262 __iwl_read_restricted(__FILE__, __LINE__, priv, reg) 259 __iwl_read_direct32(__FILE__, __LINE__, priv, reg)
263#else 260#else
264#define iwl_read_restricted _iwl_read_restricted 261#define iwl_read_direct32 _iwl_read_direct32
265#endif 262#endif
266 263
267static inline void _iwl_write_restricted(struct iwl_priv *priv, 264static inline void _iwl_write_direct32(struct iwl_priv *priv,
268 u32 reg, u32 value) 265 u32 reg, u32 value)
269{ 266{
270 _iwl_write32(priv, reg, value); 267 _iwl_write32(priv, reg, value);
271} 268}
272#ifdef CONFIG_IWLWIFI_DEBUG 269#ifdef CONFIG_IWLWIFI_DEBUG
273static void __iwl_write_restricted(u32 line, 270static void __iwl_write_direct32(u32 line,
274 struct iwl_priv *priv, u32 reg, u32 value) 271 struct iwl_priv *priv, u32 reg, u32 value)
275{ 272{
276 if (!atomic_read(&priv->restrict_refcnt)) 273 if (!atomic_read(&priv->restrict_refcnt))
277 IWL_ERROR("Unrestricted access from line %d\n", line); 274 IWL_ERROR("Nic access not held from line %d\n", line);
278 _iwl_write_restricted(priv, reg, value); 275 _iwl_write_direct32(priv, reg, value);
279} 276}
280#define iwl_write_restricted(priv, reg, value) \ 277#define iwl_write_direct32(priv, reg, value) \
281 __iwl_write_restricted(__LINE__, priv, reg, value) 278 __iwl_write_direct32(__LINE__, priv, reg, value)
282#else 279#else
283#define iwl_write_restricted _iwl_write_restricted 280#define iwl_write_direct32 _iwl_write_direct32
284#endif 281#endif
285 282
286static inline void iwl_write_buffer_restricted(struct iwl_priv *priv, 283static inline void iwl_write_reg_buf(struct iwl_priv *priv,
287 u32 reg, u32 len, u32 *values) 284 u32 reg, u32 len, u32 *values)
288{ 285{
289 u32 count = sizeof(u32); 286 u32 count = sizeof(u32);
290 287
291 if ((priv != NULL) && (values != NULL)) { 288 if ((priv != NULL) && (values != NULL)) {
292 for (; 0 < len; len -= count, reg += count, values++) 289 for (; 0 < len; len -= count, reg += count, values++)
293 _iwl_write_restricted(priv, reg, *values); 290 _iwl_write_direct32(priv, reg, *values);
294 } 291 }
295} 292}
296 293
297static inline int _iwl_poll_restricted_bit(struct iwl_priv *priv, 294static inline int _iwl_poll_direct_bit(struct iwl_priv *priv,
298 u32 addr, u32 mask, int timeout) 295 u32 addr, u32 mask, int timeout)
299{ 296{
300 int i = 0; 297 int i = 0;
301 298
302 do { 299 do {
303 if ((_iwl_read_restricted(priv, addr) & mask) == mask) 300 if ((_iwl_read_direct32(priv, addr) & mask) == mask)
304 return i; 301 return i;
305 mdelay(10); 302 mdelay(10);
306 i += 10; 303 i += 10;
@@ -310,36 +307,36 @@ static inline int _iwl_poll_restricted_bit(struct iwl_priv *priv,
310} 307}
311 308
312#ifdef CONFIG_IWLWIFI_DEBUG 309#ifdef CONFIG_IWLWIFI_DEBUG
313static inline int __iwl_poll_restricted_bit(const char *f, u32 l, 310static inline int __iwl_poll_direct_bit(const char *f, u32 l,
314 struct iwl_priv *priv, 311 struct iwl_priv *priv,
315 u32 addr, u32 mask, int timeout) 312 u32 addr, u32 mask, int timeout)
316{ 313{
317 int rc = _iwl_poll_restricted_bit(priv, addr, mask, timeout); 314 int ret = _iwl_poll_direct_bit(priv, addr, mask, timeout);
318 315
319 if (unlikely(rc == -ETIMEDOUT)) 316 if (unlikely(ret == -ETIMEDOUT))
320 IWL_DEBUG_IO("poll_restricted_bit(0x%08X, 0x%08X) - " 317 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - "
321 "timedout - %s %d\n", addr, mask, f, l); 318 "timedout - %s %d\n", addr, mask, f, l);
322 else 319 else
323 IWL_DEBUG_IO("poll_restricted_bit(0x%08X, 0x%08X) = 0x%08X " 320 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) = 0x%08X "
324 "- %s %d\n", addr, mask, rc, f, l); 321 "- %s %d\n", addr, mask, ret, f, l);
325 return rc; 322 return ret;
326} 323}
327#define iwl_poll_restricted_bit(iwl, addr, mask, timeout) \ 324#define iwl_poll_direct_bit(iwl, addr, mask, timeout) \
328 __iwl_poll_restricted_bit(__FILE__, __LINE__, iwl, addr, mask, timeout) 325 __iwl_poll_direct_bit(__FILE__, __LINE__, iwl, addr, mask, timeout)
329#else 326#else
330#define iwl_poll_restricted_bit _iwl_poll_restricted_bit 327#define iwl_poll_direct_bit _iwl_poll_direct_bit
331#endif 328#endif
332 329
333static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg) 330static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg)
334{ 331{
335 _iwl_write_restricted(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 332 _iwl_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
336 return _iwl_read_restricted(priv, HBUS_TARG_PRPH_RDAT); 333 return _iwl_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
337} 334}
338#ifdef CONFIG_IWLWIFI_DEBUG 335#ifdef CONFIG_IWLWIFI_DEBUG
339static inline u32 __iwl_read_prph(u32 line, struct iwl_priv *priv, u32 reg) 336static inline u32 __iwl_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
340{ 337{
341 if (!atomic_read(&priv->restrict_refcnt)) 338 if (!atomic_read(&priv->restrict_refcnt))
342 IWL_ERROR("Unrestricted access from line %d\n", line); 339 IWL_ERROR("Nic access not held from line %d\n", line);
343 return _iwl_read_prph(priv, reg); 340 return _iwl_read_prph(priv, reg);
344} 341}
345 342
@@ -352,16 +349,16 @@ static inline u32 __iwl_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
352static inline void _iwl_write_prph(struct iwl_priv *priv, 349static inline void _iwl_write_prph(struct iwl_priv *priv,
353 u32 addr, u32 val) 350 u32 addr, u32 val)
354{ 351{
355 _iwl_write_restricted(priv, HBUS_TARG_PRPH_WADDR, 352 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WADDR,
356 ((addr & 0x0000FFFF) | (3 << 24))); 353 ((addr & 0x0000FFFF) | (3 << 24)));
357 _iwl_write_restricted(priv, HBUS_TARG_PRPH_WDAT, val); 354 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
358} 355}
359#ifdef CONFIG_IWLWIFI_DEBUG 356#ifdef CONFIG_IWLWIFI_DEBUG
360static inline void __iwl_write_prph(u32 line, struct iwl_priv *priv, 357static inline void __iwl_write_prph(u32 line, struct iwl_priv *priv,
361 u32 addr, u32 val) 358 u32 addr, u32 val)
362{ 359{
363 if (!atomic_read(&priv->restrict_refcnt)) 360 if (!atomic_read(&priv->restrict_refcnt))
364 IWL_ERROR("Unrestricted access from line %d\n", line); 361 IWL_ERROR("Nic access from line %d\n", line);
365 _iwl_write_prph(priv, addr, val); 362 _iwl_write_prph(priv, addr, val);
366} 363}
367 364
@@ -378,7 +375,8 @@ static inline void __iwl_set_bits_prph(u32 line, struct iwl_priv *priv,
378 u32 reg, u32 mask) 375 u32 reg, u32 mask)
379{ 376{
380 if (!atomic_read(&priv->restrict_refcnt)) 377 if (!atomic_read(&priv->restrict_refcnt))
381 IWL_ERROR("Unrestricted access from line %d\n", line); 378 IWL_ERROR("Nic access not held from line %d\n", line);
379
382 _iwl_set_bits_prph(priv, reg, mask); 380 _iwl_set_bits_prph(priv, reg, mask);
383} 381}
384#define iwl_set_bits_prph(priv, reg, mask) \ 382#define iwl_set_bits_prph(priv, reg, mask) \
@@ -395,7 +393,7 @@ static inline void __iwl_set_bits_mask_prph(u32 line,
395 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask) 393 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
396{ 394{
397 if (!atomic_read(&priv->restrict_refcnt)) 395 if (!atomic_read(&priv->restrict_refcnt))
398 IWL_ERROR("Unrestricted access from line %d\n", line); 396 IWL_ERROR("Nic access not held from line %d\n", line);
399 _iwl_set_bits_mask_prph(priv, reg, bits, mask); 397 _iwl_set_bits_mask_prph(priv, reg, bits, mask);
400} 398}
401#define iwl_set_bits_mask_prph(priv, reg, bits, mask) \ 399#define iwl_set_bits_mask_prph(priv, reg, bits, mask) \
@@ -413,21 +411,21 @@ static inline void iwl_clear_bits_prph(struct iwl_priv
413 411
414static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr) 412static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
415{ 413{
416 iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, addr); 414 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
417 return iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT); 415 return iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
418} 416}
419 417
420static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val) 418static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
421{ 419{
422 iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr); 420 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
423 iwl_write_restricted(priv, HBUS_TARG_MEM_WDAT, val); 421 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
424} 422}
425 423
426static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr, 424static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
427 u32 len, u32 *values) 425 u32 len, u32 *values)
428{ 426{
429 iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr); 427 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
430 for (; 0 < len; len -= sizeof(u32), values++) 428 for (; 0 < len; len -= sizeof(u32), values++)
431 iwl_write_restricted(priv, HBUS_TARG_MEM_WDAT, *values); 429 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
432} 430}
433#endif 431#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 96cb68ebc61b..8b570e0237c9 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -1563,7 +1563,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
1563 1563
1564 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT; 1564 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1565 i += IWL_EEPROM_ACCESS_DELAY) { 1565 i += IWL_EEPROM_ACCESS_DELAY) {
1566 r = _iwl_read_restricted(priv, CSR_EEPROM_REG); 1566 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
1567 if (r & CSR_EEPROM_REG_READ_VALID_MSK) 1567 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1568 break; 1568 break;
1569 udelay(IWL_EEPROM_ACCESS_DELAY); 1569 udelay(IWL_EEPROM_ACCESS_DELAY);
@@ -2996,8 +2996,8 @@ static void iwl_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2996 2996
2997 spin_lock_irqsave(&priv->lock, flags); 2997 spin_lock_irqsave(&priv->lock, flags);
2998 iwl_read32(priv, CSR_UCODE_DRV_GP1); 2998 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2999 if (!iwl_grab_restricted_access(priv)) 2999 if (!iwl_grab_nic_access(priv))
3000 iwl_release_restricted_access(priv); 3000 iwl_release_nic_access(priv);
3001 spin_unlock_irqrestore(&priv->lock, flags); 3001 spin_unlock_irqrestore(&priv->lock, flags);
3002 3002
3003 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { 3003 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
@@ -3954,13 +3954,13 @@ int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
3954 goto exit_unlock; 3954 goto exit_unlock;
3955 } 3955 }
3956 3956
3957 rc = iwl_grab_restricted_access(priv); 3957 rc = iwl_grab_nic_access(priv);
3958 if (rc) 3958 if (rc)
3959 goto exit_unlock; 3959 goto exit_unlock;
3960 3960
3961 iwl_write_restricted(priv, FH_RSCSR_CHNL0_WPTR, 3961 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
3962 q->write & ~0x7); 3962 q->write & ~0x7);
3963 iwl_release_restricted_access(priv); 3963 iwl_release_nic_access(priv);
3964 } else 3964 } else
3965 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); 3965 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
3966 3966
@@ -4352,12 +4352,12 @@ int iwl_tx_queue_update_write_ptr(struct iwl_priv *priv,
4352 } 4352 }
4353 4353
4354 /* restore this queue's parameters in nic hardware. */ 4354 /* restore this queue's parameters in nic hardware. */
4355 rc = iwl_grab_restricted_access(priv); 4355 rc = iwl_grab_nic_access(priv);
4356 if (rc) 4356 if (rc)
4357 return rc; 4357 return rc;
4358 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 4358 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
4359 txq->q.write_ptr | (txq_id << 8)); 4359 txq->q.write_ptr | (txq_id << 8));
4360 iwl_release_restricted_access(priv); 4360 iwl_release_nic_access(priv);
4361 4361
4362 /* else not in power-save mode, uCode will never sleep when we're 4362 /* else not in power-save mode, uCode will never sleep when we're
4363 * trying to tx (during RFKILL, we're not trying to tx). */ 4363 * trying to tx (during RFKILL, we're not trying to tx). */
@@ -4451,7 +4451,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
4451 return; 4451 return;
4452 } 4452 }
4453 4453
4454 rc = iwl_grab_restricted_access(priv); 4454 rc = iwl_grab_nic_access(priv);
4455 if (rc) { 4455 if (rc) {
4456 IWL_WARNING("Can not read from adapter at this time.\n"); 4456 IWL_WARNING("Can not read from adapter at this time.\n");
4457 return; 4457 return;
@@ -4490,7 +4490,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
4490 ilink1, ilink2, data1); 4490 ilink1, ilink2, data1);
4491 } 4491 }
4492 4492
4493 iwl_release_restricted_access(priv); 4493 iwl_release_nic_access(priv);
4494 4494
4495} 4495}
4496 4496
@@ -4499,7 +4499,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
4499/** 4499/**
4500 * iwl_print_event_log - Dump error event log to syslog 4500 * iwl_print_event_log - Dump error event log to syslog
4501 * 4501 *
4502 * NOTE: Must be called with iwl_grab_restricted_access() already obtained! 4502 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
4503 */ 4503 */
4504static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, 4504static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
4505 u32 num_events, u32 mode) 4505 u32 num_events, u32 mode)
@@ -4555,7 +4555,7 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
4555 return; 4555 return;
4556 } 4556 }
4557 4557
4558 rc = iwl_grab_restricted_access(priv); 4558 rc = iwl_grab_nic_access(priv);
4559 if (rc) { 4559 if (rc) {
4560 IWL_WARNING("Can not read from adapter at this time.\n"); 4560 IWL_WARNING("Can not read from adapter at this time.\n");
4561 return; 4561 return;
@@ -4572,7 +4572,7 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
4572 /* bail out if nothing in log */ 4572 /* bail out if nothing in log */
4573 if (size == 0) { 4573 if (size == 0) {
4574 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); 4574 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
4575 iwl_release_restricted_access(priv); 4575 iwl_release_nic_access(priv);
4576 return; 4576 return;
4577 } 4577 }
4578 4578
@@ -4588,7 +4588,7 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
4588 /* (then/else) start at top of log */ 4588 /* (then/else) start at top of log */
4589 iwl_print_event_log(priv, 0, next_entry, mode); 4589 iwl_print_event_log(priv, 0, next_entry, mode);
4590 4590
4591 iwl_release_restricted_access(priv); 4591 iwl_release_nic_access(priv);
4592} 4592}
4593 4593
4594/** 4594/**
@@ -4779,11 +4779,11 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
4779 IWL_DEBUG_ISR("Tx interrupt\n"); 4779 IWL_DEBUG_ISR("Tx interrupt\n");
4780 4780
4781 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); 4781 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4782 if (!iwl_grab_restricted_access(priv)) { 4782 if (!iwl_grab_nic_access(priv)) {
4783 iwl_write_restricted(priv, 4783 iwl_write_direct32(priv,
4784 FH_TCSR_CREDIT 4784 FH_TCSR_CREDIT
4785 (ALM_FH_SRVC_CHNL), 0x0); 4785 (ALM_FH_SRVC_CHNL), 0x0);
4786 iwl_release_restricted_access(priv); 4786 iwl_release_nic_access(priv);
4787 } 4787 }
4788 handled |= CSR_INT_BIT_FH_TX; 4788 handled |= CSR_INT_BIT_FH_TX;
4789 } 4789 }
@@ -5487,18 +5487,18 @@ static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 * image, u32 len)
5487 5487
5488 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 5488 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5489 5489
5490 rc = iwl_grab_restricted_access(priv); 5490 rc = iwl_grab_nic_access(priv);
5491 if (rc) 5491 if (rc)
5492 return rc; 5492 return rc;
5493 5493
5494 iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); 5494 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
5495 5495
5496 errcnt = 0; 5496 errcnt = 0;
5497 for (; len > 0; len -= sizeof(u32), image++) { 5497 for (; len > 0; len -= sizeof(u32), image++) {
5498 /* read data comes through single port, auto-incr addr */ 5498 /* read data comes through single port, auto-incr addr */
5499 /* NOTE: Use the debugless read so we don't flood kernel log 5499 /* NOTE: Use the debugless read so we don't flood kernel log
5500 * if IWL_DL_IO is set */ 5500 * if IWL_DL_IO is set */
5501 val = _iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT); 5501 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5502 if (val != le32_to_cpu(*image)) { 5502 if (val != le32_to_cpu(*image)) {
5503 IWL_ERROR("uCode INST section is invalid at " 5503 IWL_ERROR("uCode INST section is invalid at "
5504 "offset 0x%x, is 0x%x, s/b 0x%x\n", 5504 "offset 0x%x, is 0x%x, s/b 0x%x\n",
@@ -5510,7 +5510,7 @@ static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 * image, u32 len)
5510 } 5510 }
5511 } 5511 }
5512 5512
5513 iwl_release_restricted_access(priv); 5513 iwl_release_nic_access(priv);
5514 5514
5515 if (!errcnt) 5515 if (!errcnt)
5516 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n"); 5516 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
@@ -5533,7 +5533,7 @@ static int iwl_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
5533 5533
5534 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 5534 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5535 5535
5536 rc = iwl_grab_restricted_access(priv); 5536 rc = iwl_grab_nic_access(priv);
5537 if (rc) 5537 if (rc)
5538 return rc; 5538 return rc;
5539 5539
@@ -5541,9 +5541,9 @@ static int iwl_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
5541 /* read data comes through single port, auto-incr addr */ 5541 /* read data comes through single port, auto-incr addr */
5542 /* NOTE: Use the debugless read so we don't flood kernel log 5542 /* NOTE: Use the debugless read so we don't flood kernel log
5543 * if IWL_DL_IO is set */ 5543 * if IWL_DL_IO is set */
5544 iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, 5544 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
5545 i + RTC_INST_LOWER_BOUND); 5545 i + RTC_INST_LOWER_BOUND);
5546 val = _iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT); 5546 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5547 if (val != le32_to_cpu(*image)) { 5547 if (val != le32_to_cpu(*image)) {
5548#if 0 /* Enable this if you want to see details */ 5548#if 0 /* Enable this if you want to see details */
5549 IWL_ERROR("uCode INST section is invalid at " 5549 IWL_ERROR("uCode INST section is invalid at "
@@ -5557,7 +5557,7 @@ static int iwl_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
5557 } 5557 }
5558 } 5558 }
5559 5559
5560 iwl_release_restricted_access(priv); 5560 iwl_release_nic_access(priv);
5561 5561
5562 return rc; 5562 return rc;
5563} 5563}
@@ -5704,7 +5704,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
5704 inst_len = priv->ucode_init.len; 5704 inst_len = priv->ucode_init.len;
5705 data_len = priv->ucode_init_data.len; 5705 data_len = priv->ucode_init_data.len;
5706 5706
5707 rc = iwl_grab_restricted_access(priv); 5707 rc = iwl_grab_nic_access(priv);
5708 if (rc) 5708 if (rc)
5709 return rc; 5709 return rc;
5710 5710
@@ -5722,7 +5722,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
5722 5722
5723 rc = iwl_verify_bsm(priv); 5723 rc = iwl_verify_bsm(priv);
5724 if (rc) { 5724 if (rc) {
5725 iwl_release_restricted_access(priv); 5725 iwl_release_nic_access(priv);
5726 return rc; 5726 return rc;
5727 } 5727 }
5728 5728
@@ -5756,7 +5756,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
5756 iwl_write_prph(priv, BSM_WR_CTRL_REG, 5756 iwl_write_prph(priv, BSM_WR_CTRL_REG,
5757 BSM_WR_CTRL_REG_BIT_START_EN); 5757 BSM_WR_CTRL_REG_BIT_START_EN);
5758 5758
5759 iwl_release_restricted_access(priv); 5759 iwl_release_nic_access(priv);
5760 5760
5761 return 0; 5761 return 0;
5762} 5762}
@@ -5997,7 +5997,7 @@ static int iwl_set_ucode_ptrs(struct iwl_priv *priv)
5997 pdata = priv->ucode_data_backup.p_addr; 5997 pdata = priv->ucode_data_backup.p_addr;
5998 5998
5999 spin_lock_irqsave(&priv->lock, flags); 5999 spin_lock_irqsave(&priv->lock, flags);
6000 rc = iwl_grab_restricted_access(priv); 6000 rc = iwl_grab_nic_access(priv);
6001 if (rc) { 6001 if (rc) {
6002 spin_unlock_irqrestore(&priv->lock, flags); 6002 spin_unlock_irqrestore(&priv->lock, flags);
6003 return rc; 6003 return rc;
@@ -6014,7 +6014,7 @@ static int iwl_set_ucode_ptrs(struct iwl_priv *priv)
6014 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, 6014 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
6015 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 6015 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6016 6016
6017 iwl_release_restricted_access(priv); 6017 iwl_release_nic_access(priv);
6018 6018
6019 spin_unlock_irqrestore(&priv->lock, flags); 6019 spin_unlock_irqrestore(&priv->lock, flags);
6020 6020
@@ -6103,7 +6103,7 @@ static void iwl_alive_start(struct iwl_priv *priv)
6103 6103
6104 iwl_clear_stations_table(priv); 6104 iwl_clear_stations_table(priv);
6105 6105
6106 rc = iwl_grab_restricted_access(priv); 6106 rc = iwl_grab_nic_access(priv);
6107 if (rc) { 6107 if (rc) {
6108 IWL_WARNING("Can not read rfkill status from adapter\n"); 6108 IWL_WARNING("Can not read rfkill status from adapter\n");
6109 return; 6109 return;
@@ -6111,7 +6111,7 @@ static void iwl_alive_start(struct iwl_priv *priv)
6111 6111
6112 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); 6112 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
6113 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); 6113 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
6114 iwl_release_restricted_access(priv); 6114 iwl_release_nic_access(priv);
6115 6115
6116 if (rfkill & 0x1) { 6116 if (rfkill & 0x1) {
6117 clear_bit(STATUS_RF_KILL_HW, &priv->status); 6117 clear_bit(STATUS_RF_KILL_HW, &priv->status);
@@ -6273,10 +6273,10 @@ static void __iwl_down(struct iwl_priv *priv)
6273 iwl_hw_rxq_stop(priv); 6273 iwl_hw_rxq_stop(priv);
6274 6274
6275 spin_lock_irqsave(&priv->lock, flags); 6275 spin_lock_irqsave(&priv->lock, flags);
6276 if (!iwl_grab_restricted_access(priv)) { 6276 if (!iwl_grab_nic_access(priv)) {
6277 iwl_write_prph(priv, APMG_CLK_DIS_REG, 6277 iwl_write_prph(priv, APMG_CLK_DIS_REG,
6278 APMG_CLK_VAL_DMA_CLK_RQT); 6278 APMG_CLK_VAL_DMA_CLK_RQT);
6279 iwl_release_restricted_access(priv); 6279 iwl_release_nic_access(priv);
6280 } 6280 }
6281 spin_unlock_irqrestore(&priv->lock, flags); 6281 spin_unlock_irqrestore(&priv->lock, flags);
6282 6282
@@ -8673,10 +8673,10 @@ static void iwl_resume(struct iwl_priv *priv)
8673 spin_lock_irqsave(&priv->lock, flags); 8673 spin_lock_irqsave(&priv->lock, flags);
8674 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 8674 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
8675 8675
8676 if (!iwl_grab_restricted_access(priv)) { 8676 if (!iwl_grab_nic_access(priv)) {
8677 iwl_write_prph(priv, APMG_CLK_DIS_REG, 8677 iwl_write_prph(priv, APMG_CLK_DIS_REG,
8678 APMG_CLK_VAL_DMA_CLK_RQT); 8678 APMG_CLK_VAL_DMA_CLK_RQT);
8679 iwl_release_restricted_access(priv); 8679 iwl_release_nic_access(priv);
8680 } 8680 }
8681 spin_unlock_irqrestore(&priv->lock, flags); 8681 spin_unlock_irqrestore(&priv->lock, flags);
8682 8682
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl4965-base.c
index 5d19ce9bb1aa..5408b5379a4b 100644
--- a/drivers/net/wireless/iwlwifi/iwl4965-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl4965-base.c
@@ -1610,7 +1610,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
1610 1610
1611 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT; 1611 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1612 i += IWL_EEPROM_ACCESS_DELAY) { 1612 i += IWL_EEPROM_ACCESS_DELAY) {
1613 r = _iwl_read_restricted(priv, CSR_EEPROM_REG); 1613 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
1614 if (r & CSR_EEPROM_REG_READ_VALID_MSK) 1614 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1615 break; 1615 break;
1616 udelay(IWL_EEPROM_ACCESS_DELAY); 1616 udelay(IWL_EEPROM_ACCESS_DELAY);
@@ -3087,8 +3087,8 @@ static void iwl_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
3087 3087
3088 spin_lock_irqsave(&priv->lock, flags); 3088 spin_lock_irqsave(&priv->lock, flags);
3089 iwl_read32(priv, CSR_UCODE_DRV_GP1); 3089 iwl_read32(priv, CSR_UCODE_DRV_GP1);
3090 if (!iwl_grab_restricted_access(priv)) 3090 if (!iwl_grab_nic_access(priv))
3091 iwl_release_restricted_access(priv); 3091 iwl_release_nic_access(priv);
3092 spin_unlock_irqrestore(&priv->lock, flags); 3092 spin_unlock_irqrestore(&priv->lock, flags);
3093 3093
3094 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { 3094 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
@@ -4025,23 +4025,23 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv,
4025 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, 4025 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
4026 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 4026 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4027 4027
4028 if (!iwl_grab_restricted_access(priv)) { 4028 if (!iwl_grab_nic_access(priv)) {
4029 iwl_write_restricted( 4029 iwl_write_direct32(
4030 priv, HBUS_TARG_MBX_C, 4030 priv, HBUS_TARG_MBX_C,
4031 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 4031 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4032 4032
4033 iwl_release_restricted_access(priv); 4033 iwl_release_nic_access(priv);
4034 } 4034 }
4035 4035
4036 if (!(flags & RXON_CARD_DISABLED)) { 4036 if (!(flags & RXON_CARD_DISABLED)) {
4037 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, 4037 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
4038 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 4038 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4039 if (!iwl_grab_restricted_access(priv)) { 4039 if (!iwl_grab_nic_access(priv)) {
4040 iwl_write_restricted( 4040 iwl_write_direct32(
4041 priv, HBUS_TARG_MBX_C, 4041 priv, HBUS_TARG_MBX_C,
4042 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 4042 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4043 4043
4044 iwl_release_restricted_access(priv); 4044 iwl_release_nic_access(priv);
4045 } 4045 }
4046 } 4046 }
4047 4047
@@ -4049,8 +4049,8 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv,
4049 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, 4049 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
4050 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 4050 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
4051 iwl_read32(priv, CSR_UCODE_DRV_GP1); 4051 iwl_read32(priv, CSR_UCODE_DRV_GP1);
4052 if (!iwl_grab_restricted_access(priv)) 4052 if (!iwl_grab_nic_access(priv))
4053 iwl_release_restricted_access(priv); 4053 iwl_release_nic_access(priv);
4054 } 4054 }
4055 } 4055 }
4056 4056
@@ -4278,13 +4278,13 @@ int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
4278 goto exit_unlock; 4278 goto exit_unlock;
4279 } 4279 }
4280 4280
4281 rc = iwl_grab_restricted_access(priv); 4281 rc = iwl_grab_nic_access(priv);
4282 if (rc) 4282 if (rc)
4283 goto exit_unlock; 4283 goto exit_unlock;
4284 4284
4285 iwl_write_restricted(priv, FH_RSCSR_CHNL0_WPTR, 4285 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
4286 q->write & ~0x7); 4286 q->write & ~0x7);
4287 iwl_release_restricted_access(priv); 4287 iwl_release_nic_access(priv);
4288 } else 4288 } else
4289 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); 4289 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
4290 4290
@@ -4680,12 +4680,12 @@ int iwl_tx_queue_update_write_ptr(struct iwl_priv *priv,
4680 } 4680 }
4681 4681
4682 /* restore this queue's parameters in nic hardware. */ 4682 /* restore this queue's parameters in nic hardware. */
4683 rc = iwl_grab_restricted_access(priv); 4683 rc = iwl_grab_nic_access(priv);
4684 if (rc) 4684 if (rc)
4685 return rc; 4685 return rc;
4686 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 4686 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
4687 txq->q.write_ptr | (txq_id << 8)); 4687 txq->q.write_ptr | (txq_id << 8));
4688 iwl_release_restricted_access(priv); 4688 iwl_release_nic_access(priv);
4689 4689
4690 /* else not in power-save mode, uCode will never sleep when we're 4690 /* else not in power-save mode, uCode will never sleep when we're
4691 * trying to tx (during RFKILL, we're not trying to tx). */ 4691 * trying to tx (during RFKILL, we're not trying to tx). */
@@ -4779,7 +4779,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
4779 return; 4779 return;
4780 } 4780 }
4781 4781
4782 rc = iwl_grab_restricted_access(priv); 4782 rc = iwl_grab_nic_access(priv);
4783 if (rc) { 4783 if (rc) {
4784 IWL_WARNING("Can not read from adapter at this time.\n"); 4784 IWL_WARNING("Can not read from adapter at this time.\n");
4785 return; 4785 return;
@@ -4811,7 +4811,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
4811 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, 4811 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
4812 ilink1, ilink2); 4812 ilink1, ilink2);
4813 4813
4814 iwl_release_restricted_access(priv); 4814 iwl_release_nic_access(priv);
4815} 4815}
4816 4816
4817#define EVENT_START_OFFSET (4 * sizeof(u32)) 4817#define EVENT_START_OFFSET (4 * sizeof(u32))
@@ -4819,7 +4819,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
4819/** 4819/**
4820 * iwl_print_event_log - Dump error event log to syslog 4820 * iwl_print_event_log - Dump error event log to syslog
4821 * 4821 *
4822 * NOTE: Must be called with iwl_grab_restricted_access() already obtained! 4822 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
4823 */ 4823 */
4824static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, 4824static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
4825 u32 num_events, u32 mode) 4825 u32 num_events, u32 mode)
@@ -4875,7 +4875,7 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
4875 return; 4875 return;
4876 } 4876 }
4877 4877
4878 rc = iwl_grab_restricted_access(priv); 4878 rc = iwl_grab_nic_access(priv);
4879 if (rc) { 4879 if (rc) {
4880 IWL_WARNING("Can not read from adapter at this time.\n"); 4880 IWL_WARNING("Can not read from adapter at this time.\n");
4881 return; 4881 return;
@@ -4892,7 +4892,7 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
4892 /* bail out if nothing in log */ 4892 /* bail out if nothing in log */
4893 if (size == 0) { 4893 if (size == 0) {
4894 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); 4894 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
4895 iwl_release_restricted_access(priv); 4895 iwl_release_nic_access(priv);
4896 return; 4896 return;
4897 } 4897 }
4898 4898
@@ -4908,7 +4908,7 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
4908 /* (then/else) start at top of log */ 4908 /* (then/else) start at top of log */
4909 iwl_print_event_log(priv, 0, next_entry, mode); 4909 iwl_print_event_log(priv, 0, next_entry, mode);
4910 4910
4911 iwl_release_restricted_access(priv); 4911 iwl_release_nic_access(priv);
4912} 4912}
4913 4913
4914/** 4914/**
@@ -5865,18 +5865,18 @@ static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 * image, u32 len)
5865 5865
5866 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 5866 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5867 5867
5868 rc = iwl_grab_restricted_access(priv); 5868 rc = iwl_grab_nic_access(priv);
5869 if (rc) 5869 if (rc)
5870 return rc; 5870 return rc;
5871 5871
5872 iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); 5872 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
5873 5873
5874 errcnt = 0; 5874 errcnt = 0;
5875 for (; len > 0; len -= sizeof(u32), image++) { 5875 for (; len > 0; len -= sizeof(u32), image++) {
5876 /* read data comes through single port, auto-incr addr */ 5876 /* read data comes through single port, auto-incr addr */
5877 /* NOTE: Use the debugless read so we don't flood kernel log 5877 /* NOTE: Use the debugless read so we don't flood kernel log
5878 * if IWL_DL_IO is set */ 5878 * if IWL_DL_IO is set */
5879 val = _iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT); 5879 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5880 if (val != le32_to_cpu(*image)) { 5880 if (val != le32_to_cpu(*image)) {
5881 IWL_ERROR("uCode INST section is invalid at " 5881 IWL_ERROR("uCode INST section is invalid at "
5882 "offset 0x%x, is 0x%x, s/b 0x%x\n", 5882 "offset 0x%x, is 0x%x, s/b 0x%x\n",
@@ -5888,7 +5888,7 @@ static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 * image, u32 len)
5888 } 5888 }
5889 } 5889 }
5890 5890
5891 iwl_release_restricted_access(priv); 5891 iwl_release_nic_access(priv);
5892 5892
5893 if (!errcnt) 5893 if (!errcnt)
5894 IWL_DEBUG_INFO 5894 IWL_DEBUG_INFO
@@ -5912,7 +5912,7 @@ static int iwl_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
5912 5912
5913 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 5913 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5914 5914
5915 rc = iwl_grab_restricted_access(priv); 5915 rc = iwl_grab_nic_access(priv);
5916 if (rc) 5916 if (rc)
5917 return rc; 5917 return rc;
5918 5918
@@ -5920,9 +5920,9 @@ static int iwl_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
5920 /* read data comes through single port, auto-incr addr */ 5920 /* read data comes through single port, auto-incr addr */
5921 /* NOTE: Use the debugless read so we don't flood kernel log 5921 /* NOTE: Use the debugless read so we don't flood kernel log
5922 * if IWL_DL_IO is set */ 5922 * if IWL_DL_IO is set */
5923 iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, 5923 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
5924 i + RTC_INST_LOWER_BOUND); 5924 i + RTC_INST_LOWER_BOUND);
5925 val = _iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT); 5925 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5926 if (val != le32_to_cpu(*image)) { 5926 if (val != le32_to_cpu(*image)) {
5927#if 0 /* Enable this if you want to see details */ 5927#if 0 /* Enable this if you want to see details */
5928 IWL_ERROR("uCode INST section is invalid at " 5928 IWL_ERROR("uCode INST section is invalid at "
@@ -5936,7 +5936,7 @@ static int iwl_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
5936 } 5936 }
5937 } 5937 }
5938 5938
5939 iwl_release_restricted_access(priv); 5939 iwl_release_nic_access(priv);
5940 5940
5941 return rc; 5941 return rc;
5942} 5942}
@@ -6083,7 +6083,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
6083 inst_len = priv->ucode_init.len; 6083 inst_len = priv->ucode_init.len;
6084 data_len = priv->ucode_init_data.len; 6084 data_len = priv->ucode_init_data.len;
6085 6085
6086 rc = iwl_grab_restricted_access(priv); 6086 rc = iwl_grab_nic_access(priv);
6087 if (rc) 6087 if (rc)
6088 return rc; 6088 return rc;
6089 6089
@@ -6101,7 +6101,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
6101 6101
6102 rc = iwl_verify_bsm(priv); 6102 rc = iwl_verify_bsm(priv);
6103 if (rc) { 6103 if (rc) {
6104 iwl_release_restricted_access(priv); 6104 iwl_release_nic_access(priv);
6105 return rc; 6105 return rc;
6106 } 6106 }
6107 6107
@@ -6135,7 +6135,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
6135 iwl_write_prph(priv, BSM_WR_CTRL_REG, 6135 iwl_write_prph(priv, BSM_WR_CTRL_REG,
6136 BSM_WR_CTRL_REG_BIT_START_EN); 6136 BSM_WR_CTRL_REG_BIT_START_EN);
6137 6137
6138 iwl_release_restricted_access(priv); 6138 iwl_release_nic_access(priv);
6139 6139
6140 return 0; 6140 return 0;
6141} 6141}
@@ -6380,7 +6380,7 @@ static int iwl_set_ucode_ptrs(struct iwl_priv *priv)
6380 pdata = priv->ucode_data_backup.p_addr >> 4; 6380 pdata = priv->ucode_data_backup.p_addr >> 4;
6381 6381
6382 spin_lock_irqsave(&priv->lock, flags); 6382 spin_lock_irqsave(&priv->lock, flags);
6383 rc = iwl_grab_restricted_access(priv); 6383 rc = iwl_grab_nic_access(priv);
6384 if (rc) { 6384 if (rc) {
6385 spin_unlock_irqrestore(&priv->lock, flags); 6385 spin_unlock_irqrestore(&priv->lock, flags);
6386 return rc; 6386 return rc;
@@ -6397,7 +6397,7 @@ static int iwl_set_ucode_ptrs(struct iwl_priv *priv)
6397 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, 6397 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
6398 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 6398 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6399 6399
6400 iwl_release_restricted_access(priv); 6400 iwl_release_nic_access(priv);
6401 6401
6402 spin_unlock_irqrestore(&priv->lock, flags); 6402 spin_unlock_irqrestore(&priv->lock, flags);
6403 6403
@@ -6638,10 +6638,10 @@ static void __iwl_down(struct iwl_priv *priv)
6638 iwl_hw_rxq_stop(priv); 6638 iwl_hw_rxq_stop(priv);
6639 6639
6640 spin_lock_irqsave(&priv->lock, flags); 6640 spin_lock_irqsave(&priv->lock, flags);
6641 if (!iwl_grab_restricted_access(priv)) { 6641 if (!iwl_grab_nic_access(priv)) {
6642 iwl_write_prph(priv, APMG_CLK_DIS_REG, 6642 iwl_write_prph(priv, APMG_CLK_DIS_REG,
6643 APMG_CLK_VAL_DMA_CLK_RQT); 6643 APMG_CLK_VAL_DMA_CLK_RQT);
6644 iwl_release_restricted_access(priv); 6644 iwl_release_nic_access(priv);
6645 } 6645 }
6646 spin_unlock_irqrestore(&priv->lock, flags); 6646 spin_unlock_irqrestore(&priv->lock, flags);
6647 6647
@@ -9299,10 +9299,10 @@ static void iwl_resume(struct iwl_priv *priv)
9299 spin_lock_irqsave(&priv->lock, flags); 9299 spin_lock_irqsave(&priv->lock, flags);
9300 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 9300 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
9301 9301
9302 if (!iwl_grab_restricted_access(priv)) { 9302 if (!iwl_grab_nic_access(priv)) {
9303 iwl_write_prph(priv, APMG_CLK_DIS_REG, 9303 iwl_write_prph(priv, APMG_CLK_DIS_REG,
9304 APMG_CLK_VAL_DMA_CLK_RQT); 9304 APMG_CLK_VAL_DMA_CLK_RQT);
9305 iwl_release_restricted_access(priv); 9305 iwl_release_nic_access(priv);
9306 } 9306 }
9307 spin_unlock_irqrestore(&priv->lock, flags); 9307 spin_unlock_irqrestore(&priv->lock, flags);
9308 9308