diff options
author | Vladislav Zolotarov <vladz@broadcom.com> | 2010-04-18 21:13:33 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-04-19 16:17:07 -0400 |
commit | 02e3c6cb3f09ac10a1f16d16cf31c8ecaafd2c67 (patch) | |
tree | 563a25c47df8930f8c29e4041b0f1894d63e9018 /drivers | |
parent | 34f24c7fc095a2d884e634ff430ab0da6f2a0669 (diff) |
bnx2x: Increase DMAE max write size for 57711
Increase DMAE max write size for 57711 to the maximum allowed value.
Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/bnx2x.h | 2 | ||||
-rw-r--r-- | drivers/net/bnx2x_main.c | 9 |
2 files changed, 6 insertions, 5 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h index 694c8cd59e09..150bd08ed5be 100644 --- a/drivers/net/bnx2x.h +++ b/drivers/net/bnx2x.h | |||
@@ -1168,7 +1168,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, | |||
1168 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | 1168 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT |
1169 | 1169 | ||
1170 | #define DMAE_LEN32_RD_MAX 0x80 | 1170 | #define DMAE_LEN32_RD_MAX 0x80 |
1171 | #define DMAE_LEN32_WR_MAX 0x400 | 1171 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
1172 | 1172 | ||
1173 | #define DMAE_COMP_VAL 0xe0d0d0ae | 1173 | #define DMAE_COMP_VAL 0xe0d0d0ae |
1174 | 1174 | ||
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index d0884862b96c..3325592e5dab 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
@@ -352,13 +352,14 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) | |||
352 | void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, | 352 | void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
353 | u32 addr, u32 len) | 353 | u32 addr, u32 len) |
354 | { | 354 | { |
355 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); | ||
355 | int offset = 0; | 356 | int offset = 0; |
356 | 357 | ||
357 | while (len > DMAE_LEN32_WR_MAX) { | 358 | while (len > dmae_wr_max) { |
358 | bnx2x_write_dmae(bp, phys_addr + offset, | 359 | bnx2x_write_dmae(bp, phys_addr + offset, |
359 | addr + offset, DMAE_LEN32_WR_MAX); | 360 | addr + offset, dmae_wr_max); |
360 | offset += DMAE_LEN32_WR_MAX * 4; | 361 | offset += dmae_wr_max * 4; |
361 | len -= DMAE_LEN32_WR_MAX; | 362 | len -= dmae_wr_max; |
362 | } | 363 | } |
363 | 364 | ||
364 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | 365 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); |