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authorDaniel Glöckner <dg@emlix.com>2009-11-17 04:52:57 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2009-11-30 19:43:16 -0500
commit8d6499e5bde91ad05dea4f666bdfe79e65e7cf96 (patch)
treefa199bba40a29c2f46970dca3f325354362630cd /drivers
parent5542bc2ac7b52c021fc9c7a96329955491b7e763 (diff)
USB: musb: Fix CPPI IRQs not being signaled
On tx channel abort a cppi interrupt is generated for a short time by setting the lowest bit of the TCPPICOMPPTR register. It is then reset immediately by clearing the bit. When the interrupt handler is run, it does not detect an interrupt in the TCPPIMSKSR or RCPPIMSKSR registers and thus exits early without writing the TCPPIEOIR register. It appears that this inhibits further cppi interrupts until the handler is called by chance, f.ex. from davinci_interrupt(). By moving the unmasking of the interrupt below the writes to TCPPICOMPPTR, no interrupt is generated and no write to TCPPIEOIR is necessary. Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/musb/cppi_dma.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index c3577bbbae6c..ef2332a9941d 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -1442,11 +1442,6 @@ static int cppi_channel_abort(struct dma_channel *channel)
1442 musb_writew(regs, MUSB_TXCSR, value); 1442 musb_writew(regs, MUSB_TXCSR, value);
1443 musb_writew(regs, MUSB_TXCSR, value); 1443 musb_writew(regs, MUSB_TXCSR, value);
1444 1444
1445 /* re-enable interrupt */
1446 if (enabled)
1447 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
1448 (1 << cppi_ch->index));
1449
1450 /* While we scrub the TX state RAM, ensure that we clean 1445 /* While we scrub the TX state RAM, ensure that we clean
1451 * up any interrupt that's currently asserted: 1446 * up any interrupt that's currently asserted:
1452 * 1. Write to completion Ptr value 0x1(bit 0 set) 1447 * 1. Write to completion Ptr value 0x1(bit 0 set)
@@ -1459,6 +1454,11 @@ static int cppi_channel_abort(struct dma_channel *channel)
1459 cppi_reset_tx(tx_ram, 1); 1454 cppi_reset_tx(tx_ram, 1);
1460 musb_writel(&tx_ram->tx_complete, 0, 0); 1455 musb_writel(&tx_ram->tx_complete, 0, 0);
1461 1456
1457 /* re-enable interrupt */
1458 if (enabled)
1459 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
1460 (1 << cppi_ch->index));
1461
1462 cppi_dump_tx(5, cppi_ch, " (done teardown)"); 1462 cppi_dump_tx(5, cppi_ch, " (done teardown)");
1463 1463
1464 /* REVISIT tx side _should_ clean up the same way 1464 /* REVISIT tx side _should_ clean up the same way