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authorAuke Kok <auke-jan.h.kok@intel.com>2006-06-27 12:08:17 -0400
committerAuke Kok <juke-jan.h.kok@intel.com>2006-06-27 12:08:17 -0400
commitd37ea5d56293b7a883d2a993df5d8b9fb660ed3b (patch)
treeb0b5120c66c8fc44e93cc3e708de52c6eaed98ad /drivers
parentab7bc0ad72a12ef8eacc1560c9342aa567f3531d (diff)
e1000: add ich8lan core functions
This implements the core new functions needed for ich8's internal NIC. This includes: * ich8 specific read/write code * flash/nvm access code * software semaphore flag functions * 10/100 PHY (fe - no gigabit speed) support for low-end versions * A workaround for a powerdown sequence problem discovered that affects a small number of motherboard. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/e1000/e1000_hw.c1000
-rw-r--r--drivers/net/e1000/e1000_hw.h386
-rw-r--r--drivers/net/e1000/e1000_osdep.h13
3 files changed, 1392 insertions, 7 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 784f9505864a..a3f5ccdfafc6 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -3617,11 +3617,120 @@ e1000_phy_reset(struct e1000_hw *hw)
3617} 3617}
3618 3618
3619/****************************************************************************** 3619/******************************************************************************
3620* Work-around for 82566 power-down: on D3 entry-
3621* 1) disable gigabit link
3622* 2) write VR power-down enable
3623* 3) read it back
3624* if successful continue, else issue LCD reset and repeat
3625*
3626* hw - struct containing variables accessed by shared code
3627******************************************************************************/
3628void
3629e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3630{
3631 int32_t reg;
3632 uint16_t phy_data;
3633 int32_t retry = 0;
3634
3635 DEBUGFUNC("e1000_phy_powerdown_workaround");
3636
3637 if (hw->phy_type != e1000_phy_igp_3)
3638 return;
3639
3640 do {
3641 /* Disable link */
3642 reg = E1000_READ_REG(hw, PHY_CTRL);
3643 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3644 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3645
3646 /* Write VR power-down enable */
3647 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3648 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3649 IGP3_VR_CTRL_MODE_SHUT);
3650
3651 /* Read it back and test */
3652 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3653 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3654 break;
3655
3656 /* Issue PHY reset and repeat at most one more time */
3657 reg = E1000_READ_REG(hw, CTRL);
3658 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3659 retry++;
3660 } while (retry);
3661
3662 return;
3663
3664}
3665
3666/******************************************************************************
3667* Work-around for 82566 Kumeran PCS lock loss:
3668* On link status change (i.e. PCI reset, speed change) and link is up and
3669* speed is gigabit-
3670* 0) if workaround is optionally disabled do nothing
3671* 1) wait 1ms for Kumeran link to come up
3672* 2) check Kumeran Diagnostic register PCS lock loss bit
3673* 3) if not set the link is locked (all is good), otherwise...
3674* 4) reset the PHY
3675* 5) repeat up to 10 times
3676* Note: this is only called for IGP3 copper when speed is 1gb.
3677*
3678* hw - struct containing variables accessed by shared code
3679******************************************************************************/
3680int32_t
3681e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3682{
3683 int32_t ret_val;
3684 int32_t reg;
3685 int32_t cnt;
3686 uint16_t phy_data;
3687
3688 if (hw->kmrn_lock_loss_workaround_disabled)
3689 return E1000_SUCCESS;
3690
3691 /* Make sure link is up before proceeding. If not just return.
3692 * Attempting this while link is negotiating fouls up link
3693 * stability */
3694 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3695 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3696
3697 if (phy_data & MII_SR_LINK_STATUS) {
3698 for (cnt = 0; cnt < 10; cnt++) {
3699 /* read once to clear */
3700 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3701 if (ret_val)
3702 return ret_val;
3703 /* and again to get new status */
3704 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3705 if (ret_val)
3706 return ret_val;
3707
3708 /* check for PCS lock */
3709 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3710 return E1000_SUCCESS;
3711
3712 /* Issue PHY reset */
3713 e1000_phy_hw_reset(hw);
3714 msec_delay_irq(5);
3715 }
3716 /* Disable GigE link negotiation */
3717 reg = E1000_READ_REG(hw, PHY_CTRL);
3718 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3719 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3720
3721 /* unable to acquire PCS lock */
3722 return E1000_ERR_PHY;
3723 }
3724
3725 return E1000_SUCCESS;
3726}
3727
3728/******************************************************************************
3620* Probes the expected PHY address for known PHY IDs 3729* Probes the expected PHY address for known PHY IDs
3621* 3730*
3622* hw - Struct containing variables accessed by shared code 3731* hw - Struct containing variables accessed by shared code
3623******************************************************************************/ 3732******************************************************************************/
3624static int32_t 3733int32_t
3625e1000_detect_gig_phy(struct e1000_hw *hw) 3734e1000_detect_gig_phy(struct e1000_hw *hw)
3626{ 3735{
3627 int32_t phy_init_status, ret_val; 3736 int32_t phy_init_status, ret_val;
@@ -3804,6 +3913,53 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
3804} 3913}
3805 3914
3806/****************************************************************************** 3915/******************************************************************************
3916* Get PHY information from various PHY registers for ife PHY only.
3917*
3918* hw - Struct containing variables accessed by shared code
3919* phy_info - PHY information structure
3920******************************************************************************/
3921int32_t
3922e1000_phy_ife_get_info(struct e1000_hw *hw,
3923 struct e1000_phy_info *phy_info)
3924{
3925 int32_t ret_val;
3926 uint16_t phy_data, polarity;
3927
3928 DEBUGFUNC("e1000_phy_ife_get_info");
3929
3930 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3931 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3932
3933 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
3934 if (ret_val)
3935 return ret_val;
3936 phy_info->polarity_correction =
3937 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
3938 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
3939
3940 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
3941 ret_val = e1000_check_polarity(hw, &polarity);
3942 if (ret_val)
3943 return ret_val;
3944 } else {
3945 /* Polarity is forced. */
3946 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
3947 IFE_PSC_FORCE_POLARITY_SHIFT;
3948 }
3949 phy_info->cable_polarity = polarity;
3950
3951 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
3952 if (ret_val)
3953 return ret_val;
3954
3955 phy_info->mdix_mode =
3956 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
3957 IFE_PMC_MDIX_MODE_SHIFT;
3958
3959 return E1000_SUCCESS;
3960}
3961
3962/******************************************************************************
3807* Get PHY information from various PHY registers fot m88 PHY only. 3963* Get PHY information from various PHY registers fot m88 PHY only.
3808* 3964*
3809* hw - Struct containing variables accessed by shared code 3965* hw - Struct containing variables accessed by shared code
@@ -7630,4 +7786,846 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7630} 7786}
7631 7787
7632 7788
7789/******************************************************************************
7790 * Configure PCI-Ex no-snoop
7791 *
7792 * hw - Struct containing variables accessed by shared code.
7793 * no_snoop - Bitmap of no-snoop events.
7794 *
7795 * returns: E1000_SUCCESS
7796 *
7797 *****************************************************************************/
7798int32_t
7799e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
7800{
7801 uint32_t gcr_reg = 0;
7802
7803 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
7804
7805 if (hw->bus_type == e1000_bus_type_unknown)
7806 e1000_get_bus_info(hw);
7807
7808 if (hw->bus_type != e1000_bus_type_pci_express)
7809 return E1000_SUCCESS;
7810
7811 if (no_snoop) {
7812 gcr_reg = E1000_READ_REG(hw, GCR);
7813 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
7814 gcr_reg |= no_snoop;
7815 E1000_WRITE_REG(hw, GCR, gcr_reg);
7816 }
7817 if (hw->mac_type == e1000_ich8lan) {
7818 uint32_t ctrl_ext;
7819
7820 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
7821
7822 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
7823 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
7824 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
7825 }
7826
7827 return E1000_SUCCESS;
7828}
7829
7830/***************************************************************************
7831 *
7832 * Get software semaphore FLAG bit (SWFLAG).
7833 * SWFLAG is used to synchronize the access to all shared resource between
7834 * SW, FW and HW.
7835 *
7836 * hw: Struct containing variables accessed by shared code
7837 *
7838 ***************************************************************************/
7839int32_t
7840e1000_get_software_flag(struct e1000_hw *hw)
7841{
7842 int32_t timeout = PHY_CFG_TIMEOUT;
7843 uint32_t extcnf_ctrl;
7844
7845 DEBUGFUNC("e1000_get_software_flag");
7846
7847 if (hw->mac_type == e1000_ich8lan) {
7848 while (timeout) {
7849 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
7850 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
7851 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
7852
7853 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
7854 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
7855 break;
7856 msec_delay_irq(1);
7857 timeout--;
7858 }
7859
7860 if (!timeout) {
7861 DEBUGOUT("FW or HW locks the resource too long.\n");
7862 return -E1000_ERR_CONFIG;
7863 }
7864 }
7865
7866 return E1000_SUCCESS;
7867}
7868
7869/***************************************************************************
7870 *
7871 * Release software semaphore FLAG bit (SWFLAG).
7872 * SWFLAG is used to synchronize the access to all shared resource between
7873 * SW, FW and HW.
7874 *
7875 * hw: Struct containing variables accessed by shared code
7876 *
7877 ***************************************************************************/
7878void
7879e1000_release_software_flag(struct e1000_hw *hw)
7880{
7881 uint32_t extcnf_ctrl;
7882
7883 DEBUGFUNC("e1000_release_software_flag");
7884
7885 if (hw->mac_type == e1000_ich8lan) {
7886 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
7887 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
7888 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
7889 }
7890
7891 return;
7892}
7893
7894/***************************************************************************
7895 *
7896 * Disable dynamic power down mode in ife PHY.
7897 * It can be used to workaround band-gap problem.
7898 *
7899 * hw: Struct containing variables accessed by shared code
7900 *
7901 ***************************************************************************/
7902int32_t
7903e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
7904{
7905 uint16_t phy_data;
7906 int32_t ret_val = E1000_SUCCESS;
7907
7908 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
7909
7910 if (hw->phy_type == e1000_phy_ife) {
7911 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
7912 if (ret_val)
7913 return ret_val;
7914
7915 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
7916 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
7917 }
7918
7919 return ret_val;
7920}
7921
7922/***************************************************************************
7923 *
7924 * Enable dynamic power down mode in ife PHY.
7925 * It can be used to workaround band-gap problem.
7926 *
7927 * hw: Struct containing variables accessed by shared code
7928 *
7929 ***************************************************************************/
7930int32_t
7931e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
7932{
7933 uint16_t phy_data;
7934 int32_t ret_val = E1000_SUCCESS;
7935
7936 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
7937
7938 if (hw->phy_type == e1000_phy_ife) {
7939 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
7940 if (ret_val)
7941 return ret_val;
7942
7943 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
7944 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
7945 }
7946
7947 return ret_val;
7948}
7949
7950/******************************************************************************
7951 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
7952 * register.
7953 *
7954 * hw - Struct containing variables accessed by shared code
7955 * offset - offset of word in the EEPROM to read
7956 * data - word read from the EEPROM
7957 * words - number of words to read
7958 *****************************************************************************/
7959int32_t
7960e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
7961 uint16_t *data)
7962{
7963 int32_t error = E1000_SUCCESS;
7964 uint32_t flash_bank = 0;
7965 uint32_t act_offset = 0;
7966 uint32_t bank_offset = 0;
7967 uint16_t word = 0;
7968 uint16_t i = 0;
7969
7970 /* We need to know which is the valid flash bank. In the event
7971 * that we didn't allocate eeprom_shadow_ram, we may not be
7972 * managing flash_bank. So it cannot be trusted and needs
7973 * to be updated with each read.
7974 */
7975 /* Value of bit 22 corresponds to the flash bank we're on. */
7976 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
7977
7978 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
7979 bank_offset = flash_bank * (hw->flash_bank_size * 2);
7980
7981 error = e1000_get_software_flag(hw);
7982 if (error != E1000_SUCCESS)
7983 return error;
7984
7985 for (i = 0; i < words; i++) {
7986 if (hw->eeprom_shadow_ram != NULL &&
7987 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
7988 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
7989 } else {
7990 /* The NVM part needs a byte offset, hence * 2 */
7991 act_offset = bank_offset + ((offset + i) * 2);
7992 error = e1000_read_ich8_word(hw, act_offset, &word);
7993 if (error != E1000_SUCCESS)
7994 break;
7995 data[i] = word;
7996 }
7997 }
7998
7999 e1000_release_software_flag(hw);
8000
8001 return error;
8002}
8003
8004/******************************************************************************
8005 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8006 * register. Actually, writes are written to the shadow ram cache in the hw
8007 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8008 * the NVM, which occurs when the NVM checksum is updated.
8009 *
8010 * hw - Struct containing variables accessed by shared code
8011 * offset - offset of word in the EEPROM to write
8012 * words - number of words to write
8013 * data - words to write to the EEPROM
8014 *****************************************************************************/
8015int32_t
8016e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8017 uint16_t *data)
8018{
8019 uint32_t i = 0;
8020 int32_t error = E1000_SUCCESS;
8021
8022 error = e1000_get_software_flag(hw);
8023 if (error != E1000_SUCCESS)
8024 return error;
8025
8026 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8027 * allocated. Subsequent reads to the modified words are read from
8028 * this cached structure as well. Writes will only go into this
8029 * cached structure unless it's followed by a call to
8030 * e1000_update_eeprom_checksum() where it will commit the changes
8031 * and clear the "modified" field.
8032 */
8033 if (hw->eeprom_shadow_ram != NULL) {
8034 for (i = 0; i < words; i++) {
8035 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8036 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8037 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8038 } else {
8039 error = -E1000_ERR_EEPROM;
8040 break;
8041 }
8042 }
8043 } else {
8044 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8045 * as they don't perform any NVM writes. An attempt in doing so
8046 * will result in this error.
8047 */
8048 error = -E1000_ERR_EEPROM;
8049 }
8050
8051 e1000_release_software_flag(hw);
8052
8053 return error;
8054}
8055
8056/******************************************************************************
8057 * This function does initial flash setup so that a new read/write/erase cycle
8058 * can be started.
8059 *
8060 * hw - The pointer to the hw structure
8061 ****************************************************************************/
8062int32_t
8063e1000_ich8_cycle_init(struct e1000_hw *hw)
8064{
8065 union ich8_hws_flash_status hsfsts;
8066 int32_t error = E1000_ERR_EEPROM;
8067 int32_t i = 0;
8068
8069 DEBUGFUNC("e1000_ich8_cycle_init");
8070
8071 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8072
8073 /* May be check the Flash Des Valid bit in Hw status */
8074 if (hsfsts.hsf_status.fldesvalid == 0) {
8075 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8076 return error;
8077 }
8078
8079 /* Clear FCERR in Hw status by writing 1 */
8080 /* Clear DAEL in Hw status by writing a 1 */
8081 hsfsts.hsf_status.flcerr = 1;
8082 hsfsts.hsf_status.dael = 1;
8083
8084 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8085
8086 /* Either we should have a hardware SPI cycle in progress bit to check
8087 * against, in order to start a new cycle or FDONE bit should be changed
8088 * in the hardware so that it is 1 after harware reset, which can then be
8089 * used as an indication whether a cycle is in progress or has been
8090 * completed .. we should also have some software semaphore mechanism to
8091 * guard FDONE or the cycle in progress bit so that two threads access to
8092 * those bits can be sequentiallized or a way so that 2 threads dont
8093 * start the cycle at the same time */
8094
8095 if (hsfsts.hsf_status.flcinprog == 0) {
8096 /* There is no cycle running at present, so we can start a cycle */
8097 /* Begin by setting Flash Cycle Done. */
8098 hsfsts.hsf_status.flcdone = 1;
8099 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8100 error = E1000_SUCCESS;
8101 } else {
8102 /* otherwise poll for sometime so the current cycle has a chance
8103 * to end before giving up. */
8104 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8105 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8106 if (hsfsts.hsf_status.flcinprog == 0) {
8107 error = E1000_SUCCESS;
8108 break;
8109 }
8110 udelay(1);
8111 }
8112 if (error == E1000_SUCCESS) {
8113 /* Successful in waiting for previous cycle to timeout,
8114 * now set the Flash Cycle Done. */
8115 hsfsts.hsf_status.flcdone = 1;
8116 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8117 } else {
8118 DEBUGOUT("Flash controller busy, cannot get access");
8119 }
8120 }
8121 return error;
8122}
8123
8124/******************************************************************************
8125 * This function starts a flash cycle and waits for its completion
8126 *
8127 * hw - The pointer to the hw structure
8128 ****************************************************************************/
8129int32_t
8130e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8131{
8132 union ich8_hws_flash_ctrl hsflctl;
8133 union ich8_hws_flash_status hsfsts;
8134 int32_t error = E1000_ERR_EEPROM;
8135 uint32_t i = 0;
8136
8137 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8138 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8139 hsflctl.hsf_ctrl.flcgo = 1;
8140 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8141
8142 /* wait till FDONE bit is set to 1 */
8143 do {
8144 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8145 if (hsfsts.hsf_status.flcdone == 1)
8146 break;
8147 udelay(1);
8148 i++;
8149 } while (i < timeout);
8150 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8151 error = E1000_SUCCESS;
8152 }
8153 return error;
8154}
8155
8156/******************************************************************************
8157 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8158 *
8159 * hw - The pointer to the hw structure
8160 * index - The index of the byte or word to read.
8161 * size - Size of data to read, 1=byte 2=word
8162 * data - Pointer to the word to store the value read.
8163 *****************************************************************************/
8164int32_t
8165e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8166 uint32_t size, uint16_t* data)
8167{
8168 union ich8_hws_flash_status hsfsts;
8169 union ich8_hws_flash_ctrl hsflctl;
8170 uint32_t flash_linear_address;
8171 uint32_t flash_data = 0;
8172 int32_t error = -E1000_ERR_EEPROM;
8173 int32_t count = 0;
8174
8175 DEBUGFUNC("e1000_read_ich8_data");
8176
8177 if (size < 1 || size > 2 || data == 0x0 ||
8178 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8179 return error;
8180
8181 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8182 hw->flash_base_addr;
8183
8184 do {
8185 udelay(1);
8186 /* Steps */
8187 error = e1000_ich8_cycle_init(hw);
8188 if (error != E1000_SUCCESS)
8189 break;
8190
8191 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8192 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8193 hsflctl.hsf_ctrl.fldbcount = size - 1;
8194 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8195 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8196
8197 /* Write the last 24 bits of index into Flash Linear address field in
8198 * Flash Address */
8199 /* TODO: TBD maybe check the index against the size of flash */
8200
8201 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8202
8203 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8204
8205 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8206 * sequence a few more times, else read in (shift in) the Flash Data0,
8207 * the order is least significant byte first msb to lsb */
8208 if (error == E1000_SUCCESS) {
8209 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8210 if (size == 1) {
8211 *data = (uint8_t)(flash_data & 0x000000FF);
8212 } else if (size == 2) {
8213 *data = (uint16_t)(flash_data & 0x0000FFFF);
8214 }
8215 break;
8216 } else {
8217 /* If we've gotten here, then things are probably completely hosed,
8218 * but if the error condition is detected, it won't hurt to give
8219 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8220 */
8221 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8222 if (hsfsts.hsf_status.flcerr == 1) {
8223 /* Repeat for some time before giving up. */
8224 continue;
8225 } else if (hsfsts.hsf_status.flcdone == 0) {
8226 DEBUGOUT("Timeout error - flash cycle did not complete.");
8227 break;
8228 }
8229 }
8230 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8231
8232 return error;
8233}
8234
8235/******************************************************************************
8236 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8237 *
8238 * hw - The pointer to the hw structure
8239 * index - The index of the byte/word to read.
8240 * size - Size of data to read, 1=byte 2=word
8241 * data - The byte(s) to write to the NVM.
8242 *****************************************************************************/
8243int32_t
8244e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8245 uint16_t data)
8246{
8247 union ich8_hws_flash_status hsfsts;
8248 union ich8_hws_flash_ctrl hsflctl;
8249 uint32_t flash_linear_address;
8250 uint32_t flash_data = 0;
8251 int32_t error = -E1000_ERR_EEPROM;
8252 int32_t count = 0;
8253
8254 DEBUGFUNC("e1000_write_ich8_data");
8255
8256 if (size < 1 || size > 2 || data > size * 0xff ||
8257 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8258 return error;
8259
8260 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8261 hw->flash_base_addr;
8262
8263 do {
8264 udelay(1);
8265 /* Steps */
8266 error = e1000_ich8_cycle_init(hw);
8267 if (error != E1000_SUCCESS)
8268 break;
8269
8270 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8271 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8272 hsflctl.hsf_ctrl.fldbcount = size -1;
8273 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8274 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8275
8276 /* Write the last 24 bits of index into Flash Linear address field in
8277 * Flash Address */
8278 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8279
8280 if (size == 1)
8281 flash_data = (uint32_t)data & 0x00FF;
8282 else
8283 flash_data = (uint32_t)data;
8284
8285 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8286
8287 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8288 * sequence a few more times else done */
8289 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8290 if (error == E1000_SUCCESS) {
8291 break;
8292 } else {
8293 /* If we're here, then things are most likely completely hosed,
8294 * but if the error condition is detected, it won't hurt to give
8295 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8296 */
8297 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8298 if (hsfsts.hsf_status.flcerr == 1) {
8299 /* Repeat for some time before giving up. */
8300 continue;
8301 } else if (hsfsts.hsf_status.flcdone == 0) {
8302 DEBUGOUT("Timeout error - flash cycle did not complete.");
8303 break;
8304 }
8305 }
8306 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8307
8308 return error;
8309}
8310
8311/******************************************************************************
8312 * Reads a single byte from the NVM using the ICH8 flash access registers.
8313 *
8314 * hw - pointer to e1000_hw structure
8315 * index - The index of the byte to read.
8316 * data - Pointer to a byte to store the value read.
8317 *****************************************************************************/
8318int32_t
8319e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8320{
8321 int32_t status = E1000_SUCCESS;
8322 uint16_t word = 0;
8323
8324 status = e1000_read_ich8_data(hw, index, 1, &word);
8325 if (status == E1000_SUCCESS) {
8326 *data = (uint8_t)word;
8327 }
8328
8329 return status;
8330}
8331
8332/******************************************************************************
8333 * Writes a single byte to the NVM using the ICH8 flash access registers.
8334 * Performs verification by reading back the value and then going through
8335 * a retry algorithm before giving up.
8336 *
8337 * hw - pointer to e1000_hw structure
8338 * index - The index of the byte to write.
8339 * byte - The byte to write to the NVM.
8340 *****************************************************************************/
8341int32_t
8342e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8343{
8344 int32_t error = E1000_SUCCESS;
8345 int32_t program_retries;
8346 uint8_t temp_byte;
8347
8348 e1000_write_ich8_byte(hw, index, byte);
8349 udelay(100);
8350
8351 for (program_retries = 0; program_retries < 100; program_retries++) {
8352 e1000_read_ich8_byte(hw, index, &temp_byte);
8353 if (temp_byte == byte)
8354 break;
8355 udelay(10);
8356 e1000_write_ich8_byte(hw, index, byte);
8357 udelay(100);
8358 }
8359 if (program_retries == 100)
8360 error = E1000_ERR_EEPROM;
8361
8362 return error;
8363}
8364
8365/******************************************************************************
8366 * Writes a single byte to the NVM using the ICH8 flash access registers.
8367 *
8368 * hw - pointer to e1000_hw structure
8369 * index - The index of the byte to read.
8370 * data - The byte to write to the NVM.
8371 *****************************************************************************/
8372int32_t
8373e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8374{
8375 int32_t status = E1000_SUCCESS;
8376 uint16_t word = (uint16_t)data;
8377
8378 status = e1000_write_ich8_data(hw, index, 1, word);
8379
8380 return status;
8381}
8382
8383/******************************************************************************
8384 * Reads a word from the NVM using the ICH8 flash access registers.
8385 *
8386 * hw - pointer to e1000_hw structure
8387 * index - The starting byte index of the word to read.
8388 * data - Pointer to a word to store the value read.
8389 *****************************************************************************/
8390int32_t
8391e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8392{
8393 int32_t status = E1000_SUCCESS;
8394 status = e1000_read_ich8_data(hw, index, 2, data);
8395 return status;
8396}
8397
8398/******************************************************************************
8399 * Writes a word to the NVM using the ICH8 flash access registers.
8400 *
8401 * hw - pointer to e1000_hw structure
8402 * index - The starting byte index of the word to read.
8403 * data - The word to write to the NVM.
8404 *****************************************************************************/
8405int32_t
8406e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8407{
8408 int32_t status = E1000_SUCCESS;
8409 status = e1000_write_ich8_data(hw, index, 2, data);
8410 return status;
8411}
8412
8413/******************************************************************************
8414 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8415 * segment N is 4096 * N + flash_reg_addr.
8416 *
8417 * hw - pointer to e1000_hw structure
8418 * segment - 0 for first segment, 1 for second segment, etc.
8419 *****************************************************************************/
8420int32_t
8421e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8422{
8423 union ich8_hws_flash_status hsfsts;
8424 union ich8_hws_flash_ctrl hsflctl;
8425 uint32_t flash_linear_address;
8426 int32_t count = 0;
8427 int32_t error = E1000_ERR_EEPROM;
8428 int32_t iteration, seg_size;
8429 int32_t sector_size;
8430 int32_t j = 0;
8431 int32_t error_flag = 0;
8432
8433 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8434
8435 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8436 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8437 * consecutive sectors. The start index for the nth Hw sector can be
8438 * calculated as = segment * 4096 + n * 256
8439 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8440 * The start index for the nth Hw sector can be calculated
8441 * as = segment * 4096
8442 * 10: Error condition
8443 * 11: The Hw sector size is much bigger than the size asked to
8444 * erase...error condition */
8445 if (hsfsts.hsf_status.berasesz == 0x0) {
8446 /* Hw sector size 256 */
8447 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8448 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8449 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8450 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8451 iteration = 1;
8452 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8453 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8454 iteration = 1;
8455 } else {
8456 return error;
8457 }
8458
8459 for (j = 0; j < iteration ; j++) {
8460 do {
8461 count++;
8462 /* Steps */
8463 error = e1000_ich8_cycle_init(hw);
8464 if (error != E1000_SUCCESS) {
8465 error_flag = 1;
8466 break;
8467 }
8468
8469 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8470 * Control */
8471 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8472 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8473 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8474
8475 /* Write the last 24 bits of an index within the block into Flash
8476 * Linear address field in Flash Address. This probably needs to
8477 * be calculated here based off the on-chip segment size and the
8478 * software segment size assumed (4K) */
8479 /* TBD */
8480 flash_linear_address = segment * sector_size + j * seg_size;
8481 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8482 flash_linear_address += hw->flash_base_addr;
8483
8484 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8485
8486 error = e1000_ich8_flash_cycle(hw, 1000000);
8487 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8488 * sequence a few more times else Done */
8489 if (error == E1000_SUCCESS) {
8490 break;
8491 } else {
8492 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8493 if (hsfsts.hsf_status.flcerr == 1) {
8494 /* repeat for some time before giving up */
8495 continue;
8496 } else if (hsfsts.hsf_status.flcdone == 0) {
8497 error_flag = 1;
8498 break;
8499 }
8500 }
8501 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8502 if (error_flag == 1)
8503 break;
8504 }
8505 if (error_flag != 1)
8506 error = E1000_SUCCESS;
8507 return error;
8508}
8509
8510/******************************************************************************
8511 *
8512 * Reverse duplex setting without breaking the link.
8513 *
8514 * hw: Struct containing variables accessed by shared code
8515 *
8516 *****************************************************************************/
8517int32_t
8518e1000_duplex_reversal(struct e1000_hw *hw)
8519{
8520 int32_t ret_val;
8521 uint16_t phy_data;
8522
8523 if (hw->phy_type != e1000_phy_igp_3)
8524 return E1000_SUCCESS;
8525
8526 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8527 if (ret_val)
8528 return ret_val;
8529
8530 phy_data ^= MII_CR_FULL_DUPLEX;
8531
8532 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8533 if (ret_val)
8534 return ret_val;
8535
8536 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
8537 if (ret_val)
8538 return ret_val;
8539
8540 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
8541 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
8542
8543 return ret_val;
8544}
8545
8546int32_t
8547e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8548 uint32_t cnf_base_addr, uint32_t cnf_size)
8549{
8550 uint32_t ret_val = E1000_SUCCESS;
8551 uint16_t word_addr, reg_data, reg_addr;
8552 uint16_t i;
8553
8554 /* cnf_base_addr is in DWORD */
8555 word_addr = (uint16_t)(cnf_base_addr << 1);
8556
8557 /* cnf_size is returned in size of dwords */
8558 for (i = 0; i < cnf_size; i++) {
8559 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8560 if (ret_val)
8561 return ret_val;
8562
8563 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8564 if (ret_val)
8565 return ret_val;
8566
8567 ret_val = e1000_get_software_flag(hw);
8568 if (ret_val != E1000_SUCCESS)
8569 return ret_val;
8570
8571 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8572
8573 e1000_release_software_flag(hw);
8574 }
8575
8576 return ret_val;
8577}
8578
8579
8580int32_t
8581e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8582{
8583 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8584
8585 if (hw->phy_type != e1000_phy_igp_3)
8586 return E1000_SUCCESS;
8587
8588 /* Check if SW needs configure the PHY */
8589 reg_data = E1000_READ_REG(hw, FEXTNVM);
8590 if (!(reg_data & FEXTNVM_SW_CONFIG))
8591 return E1000_SUCCESS;
8592
8593 /* Wait for basic configuration completes before proceeding*/
8594 loop = 0;
8595 do {
8596 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8597 udelay(100);
8598 loop++;
8599 } while ((!reg_data) && (loop < 50));
8600
8601 /* Clear the Init Done bit for the next init event */
8602 reg_data = E1000_READ_REG(hw, STATUS);
8603 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8604 E1000_WRITE_REG(hw, STATUS, reg_data);
8605
8606 /* Make sure HW does not configure LCD from PHY extended configuration
8607 before SW configuration */
8608 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
8609 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8610 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
8611 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8612 cnf_size >>= 16;
8613 if (cnf_size) {
8614 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
8615 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
8616 /* cnf_base_addr is in DWORD */
8617 cnf_base_addr >>= 16;
8618
8619 /* Configure LCD from extended configuration region. */
8620 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
8621 cnf_size);
8622 if (ret_val)
8623 return ret_val;
8624 }
8625 }
8626
8627 return E1000_SUCCESS;
8628}
8629
8630
7633 8631
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 1908e0d3110c..f9341e3276b3 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -62,6 +62,7 @@ typedef enum {
62 e1000_82572, 62 e1000_82572,
63 e1000_82573, 63 e1000_82573,
64 e1000_80003es2lan, 64 e1000_80003es2lan,
65 e1000_ich8lan,
65 e1000_num_macs 66 e1000_num_macs
66} e1000_mac_type; 67} e1000_mac_type;
67 68
@@ -70,6 +71,7 @@ typedef enum {
70 e1000_eeprom_spi, 71 e1000_eeprom_spi,
71 e1000_eeprom_microwire, 72 e1000_eeprom_microwire,
72 e1000_eeprom_flash, 73 e1000_eeprom_flash,
74 e1000_eeprom_ich8,
73 e1000_eeprom_none, /* No NVM support */ 75 e1000_eeprom_none, /* No NVM support */
74 e1000_num_eeprom_types 76 e1000_num_eeprom_types
75} e1000_eeprom_type; 77} e1000_eeprom_type;
@@ -98,6 +100,11 @@ typedef enum {
98 e1000_fc_default = 0xFF 100 e1000_fc_default = 0xFF
99} e1000_fc_type; 101} e1000_fc_type;
100 102
103struct e1000_shadow_ram {
104 uint16_t eeprom_word;
105 boolean_t modified;
106};
107
101/* PCI bus types */ 108/* PCI bus types */
102typedef enum { 109typedef enum {
103 e1000_bus_type_unknown = 0, 110 e1000_bus_type_unknown = 0,
@@ -218,6 +225,8 @@ typedef enum {
218 e1000_phy_igp, 225 e1000_phy_igp,
219 e1000_phy_igp_2, 226 e1000_phy_igp_2,
220 e1000_phy_gg82563, 227 e1000_phy_gg82563,
228 e1000_phy_igp_3,
229 e1000_phy_ife,
221 e1000_phy_undefined = 0xFF 230 e1000_phy_undefined = 0xFF
222} e1000_phy_type; 231} e1000_phy_type;
223 232
@@ -313,6 +322,10 @@ int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy
313int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 322int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
314int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 323int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
315int32_t e1000_phy_reset(struct e1000_hw *hw); 324int32_t e1000_phy_reset(struct e1000_hw *hw);
325void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
326int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
327int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
328int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
316int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 329int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
317int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 330int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
318int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); 331int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
@@ -331,6 +344,7 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
331#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 344#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
332#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 345#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
333#define E1000_MNG_IAMT_MODE 0x3 346#define E1000_MNG_IAMT_MODE 0x3
347#define E1000_MNG_ICH_IAMT_MODE 0x2
334#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 348#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
335 349
336#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 350#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
@@ -388,6 +402,8 @@ int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
388int32_t e1000_read_mac_addr(struct e1000_hw * hw); 402int32_t e1000_read_mac_addr(struct e1000_hw * hw);
389int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 403int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
390void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 404void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
405void e1000_release_software_flag(struct e1000_hw *hw);
406int32_t e1000_get_software_flag(struct e1000_hw *hw);
391 407
392/* Filters (multicast, vlan, receive) */ 408/* Filters (multicast, vlan, receive) */
393void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count); 409void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
@@ -423,6 +439,29 @@ int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
423int32_t e1000_get_software_semaphore(struct e1000_hw *hw); 439int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
424void e1000_release_software_semaphore(struct e1000_hw *hw); 440void e1000_release_software_semaphore(struct e1000_hw *hw);
425int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 441int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
442int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
443
444int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
445 uint8_t *data);
446int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
447 uint8_t byte);
448int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
449 uint8_t byte);
450int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
451 uint16_t *data);
452int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
453 uint32_t size, uint16_t *data);
454int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
455 uint16_t words, uint16_t *data);
456int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
457 uint16_t words, uint16_t *data);
458int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment);
459
460
461#define E1000_READ_REG_IO(a, reg) \
462 e1000_read_reg_io((a), E1000_##reg)
463#define E1000_WRITE_REG_IO(a, reg, val) \
464 e1000_write_reg_io((a), E1000_##reg, val)
426 465
427/* PCI Device IDs */ 466/* PCI Device IDs */
428#define E1000_DEV_ID_82542 0x1000 467#define E1000_DEV_ID_82542 0x1000
@@ -447,6 +486,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
447#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 486#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
448#define E1000_DEV_ID_82541EI 0x1013 487#define E1000_DEV_ID_82541EI 0x1013
449#define E1000_DEV_ID_82541EI_MOBILE 0x1018 488#define E1000_DEV_ID_82541EI_MOBILE 0x1018
489#define E1000_DEV_ID_82541ER_LOM 0x1014
450#define E1000_DEV_ID_82541ER 0x1078 490#define E1000_DEV_ID_82541ER 0x1078
451#define E1000_DEV_ID_82547GI 0x1075 491#define E1000_DEV_ID_82547GI 0x1075
452#define E1000_DEV_ID_82541GI 0x1076 492#define E1000_DEV_ID_82541GI 0x1076
@@ -458,18 +498,28 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
458#define E1000_DEV_ID_82546GB_PCIE 0x108A 498#define E1000_DEV_ID_82546GB_PCIE 0x108A
459#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 499#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
460#define E1000_DEV_ID_82547EI 0x1019 500#define E1000_DEV_ID_82547EI 0x1019
501#define E1000_DEV_ID_82547EI_MOBILE 0x101A
461#define E1000_DEV_ID_82571EB_COPPER 0x105E 502#define E1000_DEV_ID_82571EB_COPPER 0x105E
462#define E1000_DEV_ID_82571EB_FIBER 0x105F 503#define E1000_DEV_ID_82571EB_FIBER 0x105F
463#define E1000_DEV_ID_82571EB_SERDES 0x1060 504#define E1000_DEV_ID_82571EB_SERDES 0x1060
464#define E1000_DEV_ID_82572EI_COPPER 0x107D 505#define E1000_DEV_ID_82572EI_COPPER 0x107D
465#define E1000_DEV_ID_82572EI_FIBER 0x107E 506#define E1000_DEV_ID_82572EI_FIBER 0x107E
466#define E1000_DEV_ID_82572EI_SERDES 0x107F 507#define E1000_DEV_ID_82572EI_SERDES 0x107F
508#define E1000_DEV_ID_82572EI 0x10B9
467#define E1000_DEV_ID_82573E 0x108B 509#define E1000_DEV_ID_82573E 0x108B
468#define E1000_DEV_ID_82573E_IAMT 0x108C 510#define E1000_DEV_ID_82573E_IAMT 0x108C
469#define E1000_DEV_ID_82573L 0x109A 511#define E1000_DEV_ID_82573L 0x109A
470#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 512#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
471#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 513#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
472#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 514#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
515#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
516#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
517
518#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
519#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
520#define E1000_DEV_ID_ICH8_IGP_C 0x104B
521#define E1000_DEV_ID_ICH8_IFE 0x104C
522#define E1000_DEV_ID_ICH8_IGP_M 0x104D
473 523
474 524
475#define NODE_ADDRESS_SIZE 6 525#define NODE_ADDRESS_SIZE 6
@@ -540,6 +590,14 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
540 E1000_IMS_RXSEQ | \ 590 E1000_IMS_RXSEQ | \
541 E1000_IMS_LSC) 591 E1000_IMS_LSC)
542 592
593/* Additional interrupts need to be handled for e1000_ich8lan:
594 DSW = The FW changed the status of the DISSW bit in FWSM
595 PHYINT = The LAN connected device generates an interrupt
596 EPRST = Manageability reset event */
597#define IMS_ICH8LAN_ENABLE_MASK (\
598 E1000_IMS_DSW | \
599 E1000_IMS_PHYINT | \
600 E1000_IMS_EPRST)
543 601
544/* Number of high/low register pairs in the RAR. The RAR (Receive Address 602/* Number of high/low register pairs in the RAR. The RAR (Receive Address
545 * Registers) holds the directed and multicast addresses that we monitor. We 603 * Registers) holds the directed and multicast addresses that we monitor. We
@@ -547,6 +605,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
547 * E1000_RAR_ENTRIES - 1 multicast addresses. 605 * E1000_RAR_ENTRIES - 1 multicast addresses.
548 */ 606 */
549#define E1000_RAR_ENTRIES 15 607#define E1000_RAR_ENTRIES 15
608#define E1000_RAR_ENTRIES_ICH8LAN 7
550 609
551#define MIN_NUMBER_OF_DESCRIPTORS 8 610#define MIN_NUMBER_OF_DESCRIPTORS 8
552#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 611#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
@@ -768,6 +827,9 @@ struct e1000_data_desc {
768#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 827#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
769#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 828#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
770 829
830#define E1000_NUM_UNICAST_ICH8LAN 7
831#define E1000_MC_TBL_SIZE_ICH8LAN 32
832
771 833
772/* Receive Address Register */ 834/* Receive Address Register */
773struct e1000_rar { 835struct e1000_rar {
@@ -777,6 +839,7 @@ struct e1000_rar {
777 839
778/* Number of entries in the Multicast Table Array (MTA). */ 840/* Number of entries in the Multicast Table Array (MTA). */
779#define E1000_NUM_MTA_REGISTERS 128 841#define E1000_NUM_MTA_REGISTERS 128
842#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
780 843
781/* IPv4 Address Table Entry */ 844/* IPv4 Address Table Entry */
782struct e1000_ipv4_at_entry { 845struct e1000_ipv4_at_entry {
@@ -787,6 +850,7 @@ struct e1000_ipv4_at_entry {
787/* Four wakeup IP addresses are supported */ 850/* Four wakeup IP addresses are supported */
788#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 851#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
789#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 852#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
853#define E1000_IP4AT_SIZE_ICH8LAN 3
790#define E1000_IP6AT_SIZE 1 854#define E1000_IP6AT_SIZE 1
791 855
792/* IPv6 Address Table Entry */ 856/* IPv6 Address Table Entry */
@@ -845,6 +909,7 @@ struct e1000_ffvt_entry {
845#define E1000_FLA 0x0001C /* Flash Access - RW */ 909#define E1000_FLA 0x0001C /* Flash Access - RW */
846#define E1000_MDIC 0x00020 /* MDI Control - RW */ 910#define E1000_MDIC 0x00020 /* MDI Control - RW */
847#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 911#define E1000_SCTL 0x00024 /* SerDes Control - RW */
912#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
848#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 913#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
849#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 914#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
850#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 915#define E1000_FCT 0x00030 /* Flow Control Type - RW */
@@ -873,6 +938,8 @@ struct e1000_ffvt_entry {
873#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 938#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
874#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 939#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
875#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 940#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
941#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
942#define FEXTNVM_SW_CONFIG 0x0001
876#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 943#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
877#define E1000_PBS 0x01008 /* Packet Buffer Size */ 944#define E1000_PBS 0x01008 /* Packet Buffer Size */
878#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 945#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
@@ -900,11 +967,13 @@ struct e1000_ffvt_entry {
900#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 967#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
901#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 968#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
902#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 969#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
903#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 970#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
971#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
904#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 972#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
905#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 973#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
906#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 974#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
907#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 975#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
976#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
908#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 977#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
909#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 978#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
910#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 979#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
@@ -1051,6 +1120,7 @@ struct e1000_ffvt_entry {
1051#define E1000_82542_FLA E1000_FLA 1120#define E1000_82542_FLA E1000_FLA
1052#define E1000_82542_MDIC E1000_MDIC 1121#define E1000_82542_MDIC E1000_MDIC
1053#define E1000_82542_SCTL E1000_SCTL 1122#define E1000_82542_SCTL E1000_SCTL
1123#define E1000_82542_FEXTNVM E1000_FEXTNVM
1054#define E1000_82542_FCAL E1000_FCAL 1124#define E1000_82542_FCAL E1000_FCAL
1055#define E1000_82542_FCAH E1000_FCAH 1125#define E1000_82542_FCAH E1000_FCAH
1056#define E1000_82542_FCT E1000_FCT 1126#define E1000_82542_FCT E1000_FCT
@@ -1074,6 +1144,19 @@ struct e1000_ffvt_entry {
1074#define E1000_82542_RDLEN0 E1000_82542_RDLEN 1144#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1075#define E1000_82542_RDH0 E1000_82542_RDH 1145#define E1000_82542_RDH0 E1000_82542_RDH
1076#define E1000_82542_RDT0 E1000_82542_RDT 1146#define E1000_82542_RDT0 E1000_82542_RDT
1147#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1148 * RX Control - RW */
1149#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1150#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1151#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1152#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1153#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1154#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1155#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1156#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1157#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1158#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1159#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1077#define E1000_82542_RDTR1 0x00130 1160#define E1000_82542_RDTR1 0x00130
1078#define E1000_82542_RDBAL1 0x00138 1161#define E1000_82542_RDBAL1 0x00138
1079#define E1000_82542_RDBAH1 0x0013C 1162#define E1000_82542_RDBAH1 0x0013C
@@ -1111,11 +1194,14 @@ struct e1000_ffvt_entry {
1111#define E1000_82542_FLOP E1000_FLOP 1194#define E1000_82542_FLOP E1000_FLOP
1112#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL 1195#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1113#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE 1196#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1197#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1114#define E1000_82542_ERT E1000_ERT 1198#define E1000_82542_ERT E1000_ERT
1115#define E1000_82542_RXDCTL E1000_RXDCTL 1199#define E1000_82542_RXDCTL E1000_RXDCTL
1200#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1116#define E1000_82542_RADV E1000_RADV 1201#define E1000_82542_RADV E1000_RADV
1117#define E1000_82542_RSRPD E1000_RSRPD 1202#define E1000_82542_RSRPD E1000_RSRPD
1118#define E1000_82542_TXDMAC E1000_TXDMAC 1203#define E1000_82542_TXDMAC E1000_TXDMAC
1204#define E1000_82542_KABGTXD E1000_KABGTXD
1119#define E1000_82542_TDFHS E1000_TDFHS 1205#define E1000_82542_TDFHS E1000_TDFHS
1120#define E1000_82542_TDFTS E1000_TDFTS 1206#define E1000_82542_TDFTS E1000_TDFTS
1121#define E1000_82542_TDFPC E1000_TDFPC 1207#define E1000_82542_TDFPC E1000_TDFPC
@@ -1311,13 +1397,16 @@ struct e1000_hw_stats {
1311 1397
1312/* Structure containing variables used by the shared code (e1000_hw.c) */ 1398/* Structure containing variables used by the shared code (e1000_hw.c) */
1313struct e1000_hw { 1399struct e1000_hw {
1314 uint8_t __iomem *hw_addr; 1400 uint8_t *hw_addr;
1315 uint8_t *flash_address; 1401 uint8_t *flash_address;
1316 e1000_mac_type mac_type; 1402 e1000_mac_type mac_type;
1317 e1000_phy_type phy_type; 1403 e1000_phy_type phy_type;
1318 uint32_t phy_init_script; 1404 uint32_t phy_init_script;
1319 e1000_media_type media_type; 1405 e1000_media_type media_type;
1320 void *back; 1406 void *back;
1407 struct e1000_shadow_ram *eeprom_shadow_ram;
1408 uint32_t flash_bank_size;
1409 uint32_t flash_base_addr;
1321 e1000_fc_type fc; 1410 e1000_fc_type fc;
1322 e1000_bus_speed bus_speed; 1411 e1000_bus_speed bus_speed;
1323 e1000_bus_width bus_width; 1412 e1000_bus_width bus_width;
@@ -1329,6 +1418,7 @@ struct e1000_hw {
1329 uint32_t asf_firmware_present; 1418 uint32_t asf_firmware_present;
1330 uint32_t eeprom_semaphore_present; 1419 uint32_t eeprom_semaphore_present;
1331 uint32_t swfw_sync_present; 1420 uint32_t swfw_sync_present;
1421 uint32_t swfwhw_semaphore_present;
1332 unsigned long io_base; 1422 unsigned long io_base;
1333 uint32_t phy_id; 1423 uint32_t phy_id;
1334 uint32_t phy_revision; 1424 uint32_t phy_revision;
@@ -1388,6 +1478,7 @@ struct e1000_hw {
1388 boolean_t in_ifs_mode; 1478 boolean_t in_ifs_mode;
1389 boolean_t mng_reg_access_disabled; 1479 boolean_t mng_reg_access_disabled;
1390 boolean_t leave_av_bit_off; 1480 boolean_t leave_av_bit_off;
1481 boolean_t kmrn_lock_loss_workaround_disabled;
1391}; 1482};
1392 1483
1393 1484
@@ -1436,6 +1527,7 @@ struct e1000_hw {
1436#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1527#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1437#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1528#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1438#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1529#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1530#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1439 1531
1440/* Device Status */ 1532/* Device Status */
1441#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1533#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
@@ -1450,6 +1542,8 @@ struct e1000_hw {
1450#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1542#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1451#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1543#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1452#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1544#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1545#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1546 by EEPROM/Flash */
1453#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1547#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1454#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1548#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1455#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1549#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
@@ -1507,6 +1601,10 @@ struct e1000_hw {
1507#define E1000_STM_OPCODE 0xDB00 1601#define E1000_STM_OPCODE 0xDB00
1508#define E1000_HICR_FW_RESET 0xC0 1602#define E1000_HICR_FW_RESET 0xC0
1509 1603
1604#define E1000_SHADOW_RAM_WORDS 2048
1605#define E1000_ICH8_NVM_SIG_WORD 0x13
1606#define E1000_ICH8_NVM_SIG_MASK 0xC0
1607
1510/* EEPROM Read */ 1608/* EEPROM Read */
1511#define E1000_EERD_START 0x00000001 /* Start Read */ 1609#define E1000_EERD_START 0x00000001 /* Start Read */
1512#define E1000_EERD_DONE 0x00000010 /* Read Done */ 1610#define E1000_EERD_DONE 0x00000010 /* Read Done */
@@ -1552,7 +1650,6 @@ struct e1000_hw {
1552#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1650#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1553#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1651#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1554#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1652#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1555#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1556#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1653#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1557#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1654#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1558#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1655#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
@@ -1592,12 +1689,31 @@ struct e1000_hw {
1592#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 1689#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1593 1690
1594/* In-Band Control */ 1691/* In-Band Control */
1692#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1595#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 1693#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1596 1694
1597/* Half-Duplex Control */ 1695/* Half-Duplex Control */
1598#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 1696#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1599#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 1697#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1600 1698
1699#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1700
1701#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1702#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1703
1704#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1705#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1706#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1707
1708#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1709
1710#define E1000_PHY_CTRL_SPD_EN 0x00000001
1711#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1712#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1713#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1714#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1715#define E1000_PHY_CTRL_B2B_EN 0x00000080
1716
1601/* LED Control */ 1717/* LED Control */
1602#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1718#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1603#define E1000_LEDCTL_LED0_MODE_SHIFT 0 1719#define E1000_LEDCTL_LED0_MODE_SHIFT 0
@@ -1667,6 +1783,9 @@ struct e1000_hw {
1667#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1783#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1668#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1784#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1669#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1785#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1786#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1787#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1788#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
1670 1789
1671/* Interrupt Cause Set */ 1790/* Interrupt Cause Set */
1672#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1791#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1693,6 +1812,9 @@ struct e1000_hw {
1693#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1812#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1694#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1813#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1695#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1814#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1815#define E1000_ICS_DSW E1000_ICR_DSW
1816#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1817#define E1000_ICS_EPRST E1000_ICR_EPRST
1696 1818
1697/* Interrupt Mask Set */ 1819/* Interrupt Mask Set */
1698#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1820#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1719,6 +1841,9 @@ struct e1000_hw {
1719#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1841#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1720#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1842#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1721#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1843#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1844#define E1000_IMS_DSW E1000_ICR_DSW
1845#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1846#define E1000_IMS_EPRST E1000_ICR_EPRST
1722 1847
1723/* Interrupt Mask Clear */ 1848/* Interrupt Mask Clear */
1724#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1849#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1745,6 +1870,9 @@ struct e1000_hw {
1745#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1870#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1746#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1871#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1747#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1872#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1873#define E1000_IMC_DSW E1000_ICR_DSW
1874#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1875#define E1000_IMC_EPRST E1000_ICR_EPRST
1748 1876
1749/* Receive Control */ 1877/* Receive Control */
1750#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1878#define E1000_RCTL_RST 0x00000001 /* Software reset */
@@ -1919,9 +2047,10 @@ struct e1000_hw {
1919#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 2047#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1920#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2048#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1921#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 2049#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1922#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000 2050#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
1923#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2051#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1924#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 2052#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2053#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1925 2054
1926/* Definitions for power management and wakeup registers */ 2055/* Definitions for power management and wakeup registers */
1927/* Wake Up Control */ 2056/* Wake Up Control */
@@ -2011,6 +2140,15 @@ struct e1000_hw {
2011#define E1000_FWSM_MODE_SHIFT 1 2140#define E1000_FWSM_MODE_SHIFT 1
2012#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2141#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2013 2142
2143#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2144#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2145#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2146#define E1000_FWSM_SKUEL_SHIFT 29
2147#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2148#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2149#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2150#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2151
2014/* FFLT Debug Register */ 2152/* FFLT Debug Register */
2015#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2153#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2016 2154
@@ -2083,6 +2221,8 @@ struct e1000_host_command_info {
2083 E1000_GCR_TXDSCW_NO_SNOOP | \ 2221 E1000_GCR_TXDSCW_NO_SNOOP | \
2084 E1000_GCR_TXDSCR_NO_SNOOP) 2222 E1000_GCR_TXDSCR_NO_SNOOP)
2085 2223
2224#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2225
2086#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2226#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2087/* Function Active and Power State to MNG */ 2227/* Function Active and Power State to MNG */
2088#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 2228#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
@@ -2141,8 +2281,10 @@ struct e1000_host_command_info {
2141#define EEPROM_PHY_CLASS_WORD 0x0007 2281#define EEPROM_PHY_CLASS_WORD 0x0007
2142#define EEPROM_INIT_CONTROL1_REG 0x000A 2282#define EEPROM_INIT_CONTROL1_REG 0x000A
2143#define EEPROM_INIT_CONTROL2_REG 0x000F 2283#define EEPROM_INIT_CONTROL2_REG 0x000F
2284#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2144#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 2285#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2145#define EEPROM_INIT_3GIO_3 0x001A 2286#define EEPROM_INIT_3GIO_3 0x001A
2287#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2146#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 2288#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2147#define EEPROM_CFG 0x0012 2289#define EEPROM_CFG 0x0012
2148#define EEPROM_FLASH_VERSION 0x0032 2290#define EEPROM_FLASH_VERSION 0x0032
@@ -2154,10 +2296,16 @@ struct e1000_host_command_info {
2154/* Word definitions for ID LED Settings */ 2296/* Word definitions for ID LED Settings */
2155#define ID_LED_RESERVED_0000 0x0000 2297#define ID_LED_RESERVED_0000 0x0000
2156#define ID_LED_RESERVED_FFFF 0xFFFF 2298#define ID_LED_RESERVED_FFFF 0xFFFF
2299#define ID_LED_RESERVED_82573 0xF746
2300#define ID_LED_DEFAULT_82573 0x1811
2157#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2301#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2158 (ID_LED_OFF1_OFF2 << 8) | \ 2302 (ID_LED_OFF1_OFF2 << 8) | \
2159 (ID_LED_DEF1_DEF2 << 4) | \ 2303 (ID_LED_DEF1_DEF2 << 4) | \
2160 (ID_LED_DEF1_DEF2)) 2304 (ID_LED_DEF1_DEF2))
2305#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2306 (ID_LED_DEF1_OFF2 << 8) | \
2307 (ID_LED_DEF1_ON2 << 4) | \
2308 (ID_LED_DEF1_DEF2))
2161#define ID_LED_DEF1_DEF2 0x1 2309#define ID_LED_DEF1_DEF2 0x1
2162#define ID_LED_DEF1_ON2 0x2 2310#define ID_LED_DEF1_ON2 0x2
2163#define ID_LED_DEF1_OFF2 0x3 2311#define ID_LED_DEF1_OFF2 0x3
@@ -2192,6 +2340,11 @@ struct e1000_host_command_info {
2192#define EEPROM_WORD0F_ASM_DIR 0x2000 2340#define EEPROM_WORD0F_ASM_DIR 0x2000
2193#define EEPROM_WORD0F_ANE 0x0800 2341#define EEPROM_WORD0F_ANE 0x0800
2194#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 2342#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2343#define EEPROM_WORD0F_LPLU 0x0001
2344
2345/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2346#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2347#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2195 2348
2196/* Mask bits for fields in Word 0x1a of the EEPROM */ 2349/* Mask bits for fields in Word 0x1a of the EEPROM */
2197#define EEPROM_WORD1A_ASPM_MASK 0x000C 2350#define EEPROM_WORD1A_ASPM_MASK 0x000C
@@ -2266,23 +2419,29 @@ struct e1000_host_command_info {
2266#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 2419#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2267#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 2420#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2268#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 2421#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2269#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000 2422#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2270 2423
2271#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF 2424#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2272#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 2425#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2273#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 2426#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2427#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2428#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2274 2429
2275/* PBA constants */ 2430/* PBA constants */
2431#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2276#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2432#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2277#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2433#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2278#define E1000_PBA_22K 0x0016 2434#define E1000_PBA_22K 0x0016
2279#define E1000_PBA_24K 0x0018 2435#define E1000_PBA_24K 0x0018
2280#define E1000_PBA_30K 0x001E 2436#define E1000_PBA_30K 0x001E
2281#define E1000_PBA_32K 0x0020 2437#define E1000_PBA_32K 0x0020
2438#define E1000_PBA_34K 0x0022
2282#define E1000_PBA_38K 0x0026 2439#define E1000_PBA_38K 0x0026
2283#define E1000_PBA_40K 0x0028 2440#define E1000_PBA_40K 0x0028
2284#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2441#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2285 2442
2443#define E1000_PBS_16K E1000_PBA_16K
2444
2286/* Flow Control Constants */ 2445/* Flow Control Constants */
2287#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 2446#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2288#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 2447#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
@@ -2337,7 +2496,7 @@ struct e1000_host_command_info {
2337/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2496/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2338#define AUTO_READ_DONE_TIMEOUT 10 2497#define AUTO_READ_DONE_TIMEOUT 10
2339/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2498/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2340#define PHY_CFG_TIMEOUT 40 2499#define PHY_CFG_TIMEOUT 100
2341 2500
2342#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2501#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2343 2502
@@ -3002,6 +3161,221 @@ struct e1000_host_command_info {
3002#define L1LXT971A_PHY_ID 0x001378E0 3161#define L1LXT971A_PHY_ID 0x001378E0
3003#define GG82563_E_PHY_ID 0x01410CA0 3162#define GG82563_E_PHY_ID 0x01410CA0
3004 3163
3164
3165/* Bits...
3166 * 15-5: page
3167 * 4-0: register offset
3168 */
3169#define PHY_PAGE_SHIFT 5
3170#define PHY_REG(page, reg) \
3171 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3172
3173#define IGP3_PHY_PORT_CTRL \
3174 PHY_REG(769, 17) /* Port General Configuration */
3175#define IGP3_PHY_RATE_ADAPT_CTRL \
3176 PHY_REG(769, 25) /* Rate Adapter Control Register */
3177
3178#define IGP3_KMRN_FIFO_CTRL_STATS \
3179 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3180#define IGP3_KMRN_POWER_MNG_CTRL \
3181 PHY_REG(770, 17) /* KMRN Power Management Control Register */
3182#define IGP3_KMRN_INBAND_CTRL \
3183 PHY_REG(770, 18) /* KMRN Inband Control Register */
3184#define IGP3_KMRN_DIAG \
3185 PHY_REG(770, 19) /* KMRN Diagnostic register */
3186#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3187#define IGP3_KMRN_ACK_TIMEOUT \
3188 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3189
3190#define IGP3_VR_CTRL \
3191 PHY_REG(776, 18) /* Voltage regulator control register */
3192#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3193
3194#define IGP3_CAPABILITY \
3195 PHY_REG(776, 19) /* IGP3 Capability Register */
3196
3197/* Capabilities for SKU Control */
3198#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3199#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3200#define IGP3_CAP_ASF 0x0004 /* Support ASF */
3201#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3202#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3203#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3204#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3205#define IGP3_CAP_RSS 0x0080 /* Support RSS */
3206#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3207#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3208
3209#define IGP3_PPC_JORDAN_EN 0x0001
3210#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
3211
3212#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
3213#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
3214#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3215#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3216
3217#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3218#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3219
3220#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3221#define IGP3_KMRN_EC_DIS_INBAND 0x0080
3222
3223#define IGP03E1000_E_PHY_ID 0x02A80390
3224#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3225#define IFE_PLUS_E_PHY_ID 0x02A80320
3226#define IFE_C_E_PHY_ID 0x02A80310
3227
3228#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3229#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3230#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3231#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
3232#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3233#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3234#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3235#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3236#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3237#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3238#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3239#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3240#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3241
3242#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
3243#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3244#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3245#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3246#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3247#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3248#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3249#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3250
3251#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
3252#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3253#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3254#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3255#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3256#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3257
3258#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3259#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3260#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3261#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */
3262#define IFE_PMC_MDIX_MODE_SHIFT 6
3263#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3264
3265#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3266#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3267#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3268#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3269#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3270#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3271#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3272#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3273#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3274#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3275#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3276
3277#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
3278#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
3279#define ICH8_FLASH_SEG_SIZE_256 256
3280#define ICH8_FLASH_SEG_SIZE_4K 4096
3281#define ICH8_FLASH_SEG_SIZE_64K 65536
3282
3283#define ICH8_CYCLE_READ 0x0
3284#define ICH8_CYCLE_RESERVED 0x1
3285#define ICH8_CYCLE_WRITE 0x2
3286#define ICH8_CYCLE_ERASE 0x3
3287
3288#define ICH8_FLASH_GFPREG 0x0000
3289#define ICH8_FLASH_HSFSTS 0x0004
3290#define ICH8_FLASH_HSFCTL 0x0006
3291#define ICH8_FLASH_FADDR 0x0008
3292#define ICH8_FLASH_FDATA0 0x0010
3293#define ICH8_FLASH_FRACC 0x0050
3294#define ICH8_FLASH_FREG0 0x0054
3295#define ICH8_FLASH_FREG1 0x0058
3296#define ICH8_FLASH_FREG2 0x005C
3297#define ICH8_FLASH_FREG3 0x0060
3298#define ICH8_FLASH_FPR0 0x0074
3299#define ICH8_FLASH_FPR1 0x0078
3300#define ICH8_FLASH_SSFSTS 0x0090
3301#define ICH8_FLASH_SSFCTL 0x0092
3302#define ICH8_FLASH_PREOP 0x0094
3303#define ICH8_FLASH_OPTYPE 0x0096
3304#define ICH8_FLASH_OPMENU 0x0098
3305
3306#define ICH8_FLASH_REG_MAPSIZE 0x00A0
3307#define ICH8_FLASH_SECTOR_SIZE 4096
3308#define ICH8_GFPREG_BASE_MASK 0x1FFF
3309#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3310
3311/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3312/* Offset 04h HSFSTS */
3313union ich8_hws_flash_status {
3314 struct ich8_hsfsts {
3315#ifdef E1000_BIG_ENDIAN
3316 uint16_t reserved2 :6;
3317 uint16_t fldesvalid :1;
3318 uint16_t flockdn :1;
3319 uint16_t flcdone :1;
3320 uint16_t flcerr :1;
3321 uint16_t dael :1;
3322 uint16_t berasesz :2;
3323 uint16_t flcinprog :1;
3324 uint16_t reserved1 :2;
3325#else
3326 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */
3327 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */
3328 uint16_t dael :1; /* bit 2 Direct Access error Log */
3329 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3330 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3331 uint16_t reserved1 :2; /* bit 13:6 Reserved */
3332 uint16_t reserved2 :6; /* bit 13:6 Reserved */
3333 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3334 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3335#endif
3336 } hsf_status;
3337 uint16_t regval;
3338};
3339
3340/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3341/* Offset 06h FLCTL */
3342union ich8_hws_flash_ctrl {
3343 struct ich8_hsflctl {
3344#ifdef E1000_BIG_ENDIAN
3345 uint16_t fldbcount :2;
3346 uint16_t flockdn :6;
3347 uint16_t flcgo :1;
3348 uint16_t flcycle :2;
3349 uint16_t reserved :5;
3350#else
3351 uint16_t flcgo :1; /* 0 Flash Cycle Go */
3352 uint16_t flcycle :2; /* 2:1 Flash Cycle */
3353 uint16_t reserved :5; /* 7:3 Reserved */
3354 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */
3355 uint16_t flockdn :6; /* 15:10 Reserved */
3356#endif
3357 } hsf_ctrl;
3358 uint16_t regval;
3359};
3360
3361/* ICH8 Flash Region Access Permissions */
3362union ich8_hws_flash_regacc {
3363 struct ich8_flracc {
3364#ifdef E1000_BIG_ENDIAN
3365 uint32_t gmwag :8;
3366 uint32_t gmrag :8;
3367 uint32_t grwa :8;
3368 uint32_t grra :8;
3369#else
3370 uint32_t grra :8; /* 0:7 GbE region Read Access */
3371 uint32_t grwa :8; /* 8:15 GbE region Write Access */
3372 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */
3373 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */
3374#endif
3375 } hsf_flregacc;
3376 uint16_t regval;
3377};
3378
3005/* Miscellaneous PHY bit definitions. */ 3379/* Miscellaneous PHY bit definitions. */
3006#define PHY_PREAMBLE 0xFFFFFFFF 3380#define PHY_PREAMBLE 0xFFFFFFFF
3007#define PHY_SOF 0x01 3381#define PHY_SOF 0x01
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index 048d052be29d..2d3e8b06cab0 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -127,4 +127,17 @@ typedef enum {
127 127
128#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 128#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
129 129
130#define E1000_WRITE_ICH8_REG(a, reg, value) ( \
131 writel((value), ((a)->flash_address + reg)))
132
133#define E1000_READ_ICH8_REG(a, reg) ( \
134 readl((a)->flash_address + reg))
135
136#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
137 writew((value), ((a)->flash_address + reg)))
138
139#define E1000_READ_ICH8_REG16(a, reg) ( \
140 readw((a)->flash_address + reg))
141
142
130#endif /* _E1000_OSDEP_H_ */ 143#endif /* _E1000_OSDEP_H_ */