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authorRabin Vincent <rabin.vincent@stericsson.com>2010-10-12 09:00:49 -0400
committerDan Williams <dan.j.williams@intel.com>2010-10-19 18:17:06 -0400
commitce2ca1252ba8688a4997b4104793540f4c28c0d8 (patch)
tree137b6098794fbb4270cc9c65936c89ff70ec7661 /drivers
parent9646b7985e906e5fcea9375f016b4519c8318c21 (diff)
ste_dma40: add variable to indicate valid dma_cfg
Since we want to reduce the amount of required channel configuration and remove channel_type, don't depend on it to indicate whether the configuration is valid. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/dma/ste_dma40.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 662d7e35f862..7bc535ee0a08 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -175,6 +175,7 @@ struct d40_base;
175 * @active: Active descriptor. 175 * @active: Active descriptor.
176 * @queue: Queued jobs. 176 * @queue: Queued jobs.
177 * @dma_cfg: The client configuration of this dma channel. 177 * @dma_cfg: The client configuration of this dma channel.
178 * @configured: whether the dma_cfg configuration is valid
178 * @base: Pointer to the device instance struct. 179 * @base: Pointer to the device instance struct.
179 * @src_def_cfg: Default cfg register setting for src. 180 * @src_def_cfg: Default cfg register setting for src.
180 * @dst_def_cfg: Default cfg register setting for dst. 181 * @dst_def_cfg: Default cfg register setting for dst.
@@ -198,6 +199,7 @@ struct d40_chan {
198 struct list_head active; 199 struct list_head active;
199 struct list_head queue; 200 struct list_head queue;
200 struct stedma40_chan_cfg dma_cfg; 201 struct stedma40_chan_cfg dma_cfg;
202 bool configured;
201 struct d40_base *base; 203 struct d40_base *base;
202 /* Default register configurations */ 204 /* Default register configurations */
203 u32 src_def_cfg; 205 u32 src_def_cfg;
@@ -1518,8 +1520,7 @@ static int d40_free_dma(struct d40_chan *d40c)
1518 return res; 1520 return res;
1519 } 1521 }
1520 d40c->phy_chan = NULL; 1522 d40c->phy_chan = NULL;
1521 /* Invalidate channel type */ 1523 d40c->configured = false;
1522 d40c->dma_cfg.channel_type = 0;
1523 d40c->base->lookup_phy_chans[phy->num] = NULL; 1524 d40c->base->lookup_phy_chans[phy->num] = NULL;
1524 1525
1525 return 0; 1526 return 0;
@@ -1704,6 +1705,9 @@ bool stedma40_filter(struct dma_chan *chan, void *data)
1704 } else 1705 } else
1705 err = d40_config_memcpy(d40c); 1706 err = d40_config_memcpy(d40c);
1706 1707
1708 if (!err)
1709 d40c->configured = true;
1710
1707 return err == 0; 1711 return err == 0;
1708} 1712}
1709EXPORT_SYMBOL(stedma40_filter); 1713EXPORT_SYMBOL(stedma40_filter);
@@ -1720,12 +1724,8 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
1720 1724
1721 d40c->completed = chan->cookie = 1; 1725 d40c->completed = chan->cookie = 1;
1722 1726
1723 /* 1727 /* If no dma configuration is set use default configuration (memcpy) */
1724 * If no dma configuration is set (channel_type == 0) 1728 if (!d40c->configured) {
1725 * use default configuration (memcpy)
1726 */
1727 if (d40c->dma_cfg.channel_type == 0) {
1728
1729 err = d40_config_memcpy(d40c); 1729 err = d40_config_memcpy(d40c);
1730 if (err) { 1730 if (err) {
1731 dev_err(&d40c->chan.dev->device, 1731 dev_err(&d40c->chan.dev->device,