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authorravinandan.arakali@neterion.com <ravinandan.arakali@neterion.com>2005-10-17 21:26:20 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-18 16:58:27 -0400
commitad4ebed00fbf570411edbf6eb6c391e16b71df25 (patch)
tree37f236700d5e831fee6bf8494cd57753231ddf14 /drivers
parent59aee3c2a1e69fe5062bd1facb72d6fcea3f3f8f (diff)
[PATCH] S2io: Offline diagnostics fixes
This patch fixes the following bugs with offline diagnostics code(run with "ethtool -t"). 1. After running offline diagnostics, adapter would report corrupted packets on receive. This was because of adapter not being brought out of "RLDRAM test mode". 2. Current EEPROM test works only for Xframe I. Since Xframe II uses different interface(SPI), support for this interface has been added. Also, since SPI supports write access to all areas of EEPROM, negative testing is done only for Xframe I. 3. Return values from subfunctions of offline diagnostics have been corrected. 4. In register test, expected value from rx_queue_cfg register is made to depend on adapter type. 5. After the test, need to restore values at EEPROM offsets 0x4F0 and 0x7F0. These locations were modified as part of test. 6. Use macro SPECIAL_REG_WRITE for write access to mc_rldram_test_ctrl register. Also, couple of unnecessary writes to mc_rldram_test_ctrl have been removed. Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/s2io-regs.h11
-rw-r--r--drivers/net/s2io.c231
2 files changed, 162 insertions, 80 deletions
diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
index 7cefe5507b9e..00179bc3437f 100644
--- a/drivers/net/s2io-regs.h
+++ b/drivers/net/s2io-regs.h
@@ -814,6 +814,17 @@ typedef struct _XENA_dev_config {
814 u64 rxgxs_ber_0; /* CHANGED */ 814 u64 rxgxs_ber_0; /* CHANGED */
815 u64 rxgxs_ber_1; /* CHANGED */ 815 u64 rxgxs_ber_1; /* CHANGED */
816 816
817 u64 spi_control;
818#define SPI_CONTROL_KEY(key) vBIT(key,0,4)
819#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
820#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
821#define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
822#define SPI_CONTROL_SEL1 BIT(4)
823#define SPI_CONTROL_REQ BIT(7)
824#define SPI_CONTROL_NACK BIT(5)
825#define SPI_CONTROL_DONE BIT(6)
826 u64 spi_data;
827#define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
817} XENA_dev_config_t; 828} XENA_dev_config_t;
818 829
819#define XENA_REG_SPACE sizeof(XENA_dev_config_t) 830#define XENA_REG_SPACE sizeof(XENA_dev_config_t)
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index fcf61107046e..30fbaf04773f 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -4378,29 +4378,53 @@ static int s2io_ethtool_setpause_data(struct net_device *dev,
4378 */ 4378 */
4379 4379
4380#define S2IO_DEV_ID 5 4380#define S2IO_DEV_ID 5
4381static int read_eeprom(nic_t * sp, int off, u32 * data) 4381static int read_eeprom(nic_t * sp, int off, u64 * data)
4382{ 4382{
4383 int ret = -1; 4383 int ret = -1;
4384 u32 exit_cnt = 0; 4384 u32 exit_cnt = 0;
4385 u64 val64; 4385 u64 val64;
4386 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4386 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4387 4387
4388 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | 4388 if (sp->device_type == XFRAME_I_DEVICE) {
4389 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ | 4389 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4390 I2C_CONTROL_CNTL_START; 4390 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4391 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); 4391 I2C_CONTROL_CNTL_START;
4392 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4392 4393
4393 while (exit_cnt < 5) { 4394 while (exit_cnt < 5) {
4394 val64 = readq(&bar0->i2c_control); 4395 val64 = readq(&bar0->i2c_control);
4395 if (I2C_CONTROL_CNTL_END(val64)) { 4396 if (I2C_CONTROL_CNTL_END(val64)) {
4396 *data = I2C_CONTROL_GET_DATA(val64); 4397 *data = I2C_CONTROL_GET_DATA(val64);
4397 ret = 0; 4398 ret = 0;
4398 break; 4399 break;
4400 }
4401 msleep(50);
4402 exit_cnt++;
4399 } 4403 }
4400 msleep(50);
4401 exit_cnt++;
4402 } 4404 }
4403 4405
4406 if (sp->device_type == XFRAME_II_DEVICE) {
4407 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4408 SPI_CONTROL_BYTECNT(0x3) |
4409 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4410 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4411 val64 |= SPI_CONTROL_REQ;
4412 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4413 while (exit_cnt < 5) {
4414 val64 = readq(&bar0->spi_control);
4415 if (val64 & SPI_CONTROL_NACK) {
4416 ret = 1;
4417 break;
4418 } else if (val64 & SPI_CONTROL_DONE) {
4419 *data = readq(&bar0->spi_data);
4420 *data &= 0xffffff;
4421 ret = 0;
4422 break;
4423 }
4424 msleep(50);
4425 exit_cnt++;
4426 }
4427 }
4404 return ret; 4428 return ret;
4405} 4429}
4406 4430
@@ -4419,28 +4443,53 @@ static int read_eeprom(nic_t * sp, int off, u32 * data)
4419 * 0 on success, -1 on failure. 4443 * 0 on success, -1 on failure.
4420 */ 4444 */
4421 4445
4422static int write_eeprom(nic_t * sp, int off, u32 data, int cnt) 4446static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4423{ 4447{
4424 int exit_cnt = 0, ret = -1; 4448 int exit_cnt = 0, ret = -1;
4425 u64 val64; 4449 u64 val64;
4426 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4450 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4427 4451
4428 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | 4452 if (sp->device_type == XFRAME_I_DEVICE) {
4429 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) | 4453 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4430 I2C_CONTROL_CNTL_START; 4454 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4431 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); 4455 I2C_CONTROL_CNTL_START;
4456 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4457
4458 while (exit_cnt < 5) {
4459 val64 = readq(&bar0->i2c_control);
4460 if (I2C_CONTROL_CNTL_END(val64)) {
4461 if (!(val64 & I2C_CONTROL_NACK))
4462 ret = 0;
4463 break;
4464 }
4465 msleep(50);
4466 exit_cnt++;
4467 }
4468 }
4432 4469
4433 while (exit_cnt < 5) { 4470 if (sp->device_type == XFRAME_II_DEVICE) {
4434 val64 = readq(&bar0->i2c_control); 4471 int write_cnt = (cnt == 8) ? 0 : cnt;
4435 if (I2C_CONTROL_CNTL_END(val64)) { 4472 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4436 if (!(val64 & I2C_CONTROL_NACK)) 4473
4474 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4475 SPI_CONTROL_BYTECNT(write_cnt) |
4476 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4477 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4478 val64 |= SPI_CONTROL_REQ;
4479 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4480 while (exit_cnt < 5) {
4481 val64 = readq(&bar0->spi_control);
4482 if (val64 & SPI_CONTROL_NACK) {
4483 ret = 1;
4484 break;
4485 } else if (val64 & SPI_CONTROL_DONE) {
4437 ret = 0; 4486 ret = 0;
4438 break; 4487 break;
4488 }
4489 msleep(50);
4490 exit_cnt++;
4439 } 4491 }
4440 msleep(50);
4441 exit_cnt++;
4442 } 4492 }
4443
4444 return ret; 4493 return ret;
4445} 4494}
4446 4495
@@ -4460,7 +4509,8 @@ static int write_eeprom(nic_t * sp, int off, u32 data, int cnt)
4460static int s2io_ethtool_geeprom(struct net_device *dev, 4509static int s2io_ethtool_geeprom(struct net_device *dev,
4461 struct ethtool_eeprom *eeprom, u8 * data_buf) 4510 struct ethtool_eeprom *eeprom, u8 * data_buf)
4462{ 4511{
4463 u32 data, i, valid; 4512 u32 i, valid;
4513 u64 data;
4464 nic_t *sp = dev->priv; 4514 nic_t *sp = dev->priv;
4465 4515
4466 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16); 4516 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
@@ -4498,7 +4548,7 @@ static int s2io_ethtool_seeprom(struct net_device *dev,
4498 u8 * data_buf) 4548 u8 * data_buf)
4499{ 4549{
4500 int len = eeprom->len, cnt = 0; 4550 int len = eeprom->len, cnt = 0;
4501 u32 valid = 0, data; 4551 u64 valid = 0, data;
4502 nic_t *sp = dev->priv; 4552 nic_t *sp = dev->priv;
4503 4553
4504 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) { 4554 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
@@ -4546,7 +4596,7 @@ static int s2io_ethtool_seeprom(struct net_device *dev,
4546static int s2io_register_test(nic_t * sp, uint64_t * data) 4596static int s2io_register_test(nic_t * sp, uint64_t * data)
4547{ 4597{
4548 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4598 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4549 u64 val64 = 0; 4599 u64 val64 = 0, exp_val;
4550 int fail = 0; 4600 int fail = 0;
4551 4601
4552 val64 = readq(&bar0->pif_rd_swapper_fb); 4602 val64 = readq(&bar0->pif_rd_swapper_fb);
@@ -4562,7 +4612,11 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
4562 } 4612 }
4563 4613
4564 val64 = readq(&bar0->rx_queue_cfg); 4614 val64 = readq(&bar0->rx_queue_cfg);
4565 if (val64 != 0x0808080808080808ULL) { 4615 if (sp->device_type == XFRAME_II_DEVICE)
4616 exp_val = 0x0404040404040404ULL;
4617 else
4618 exp_val = 0x0808080808080808ULL;
4619 if (val64 != exp_val) {
4566 fail = 1; 4620 fail = 1;
4567 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n"); 4621 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
4568 } 4622 }
@@ -4590,7 +4644,7 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
4590 } 4644 }
4591 4645
4592 *data = fail; 4646 *data = fail;
4593 return 0; 4647 return fail;
4594} 4648}
4595 4649
4596/** 4650/**
@@ -4609,58 +4663,83 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
4609static int s2io_eeprom_test(nic_t * sp, uint64_t * data) 4663static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
4610{ 4664{
4611 int fail = 0; 4665 int fail = 0;
4612 u32 ret_data; 4666 u64 ret_data, org_4F0, org_7F0;
4667 u8 saved_4F0 = 0, saved_7F0 = 0;
4668 struct net_device *dev = sp->dev;
4613 4669
4614 /* Test Write Error at offset 0 */ 4670 /* Test Write Error at offset 0 */
4615 if (!write_eeprom(sp, 0, 0, 3)) 4671 /* Note that SPI interface allows write access to all areas
4616 fail = 1; 4672 * of EEPROM. Hence doing all negative testing only for Xframe I.
4673 */
4674 if (sp->device_type == XFRAME_I_DEVICE)
4675 if (!write_eeprom(sp, 0, 0, 3))
4676 fail = 1;
4677
4678 /* Save current values at offsets 0x4F0 and 0x7F0 */
4679 if (!read_eeprom(sp, 0x4F0, &org_4F0))
4680 saved_4F0 = 1;
4681 if (!read_eeprom(sp, 0x7F0, &org_7F0))
4682 saved_7F0 = 1;
4617 4683
4618 /* Test Write at offset 4f0 */ 4684 /* Test Write at offset 4f0 */
4619 if (write_eeprom(sp, 0x4F0, 0x01234567, 3)) 4685 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
4620 fail = 1; 4686 fail = 1;
4621 if (read_eeprom(sp, 0x4F0, &ret_data)) 4687 if (read_eeprom(sp, 0x4F0, &ret_data))
4622 fail = 1; 4688 fail = 1;
4623 4689
4624 if (ret_data != 0x01234567) 4690 if (ret_data != 0x012345) {
4691 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
4625 fail = 1; 4692 fail = 1;
4693 }
4626 4694
4627 /* Reset the EEPROM data go FFFF */ 4695 /* Reset the EEPROM data go FFFF */
4628 write_eeprom(sp, 0x4F0, 0xFFFFFFFF, 3); 4696 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
4629 4697
4630 /* Test Write Request Error at offset 0x7c */ 4698 /* Test Write Request Error at offset 0x7c */
4631 if (!write_eeprom(sp, 0x07C, 0, 3)) 4699 if (sp->device_type == XFRAME_I_DEVICE)
4632 fail = 1; 4700 if (!write_eeprom(sp, 0x07C, 0, 3))
4701 fail = 1;
4633 4702
4634 /* Test Write Request at offset 0x7fc */ 4703 /* Test Write Request at offset 0x7f0 */
4635 if (write_eeprom(sp, 0x7FC, 0x01234567, 3)) 4704 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
4636 fail = 1; 4705 fail = 1;
4637 if (read_eeprom(sp, 0x7FC, &ret_data)) 4706 if (read_eeprom(sp, 0x7F0, &ret_data))
4638 fail = 1; 4707 fail = 1;
4639 4708
4640 if (ret_data != 0x01234567) 4709 if (ret_data != 0x012345) {
4710 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
4641 fail = 1; 4711 fail = 1;
4712 }
4642 4713
4643 /* Reset the EEPROM data go FFFF */ 4714 /* Reset the EEPROM data go FFFF */
4644 write_eeprom(sp, 0x7FC, 0xFFFFFFFF, 3); 4715 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
4645 4716
4646 /* Test Write Error at offset 0x80 */ 4717 if (sp->device_type == XFRAME_I_DEVICE) {
4647 if (!write_eeprom(sp, 0x080, 0, 3)) 4718 /* Test Write Error at offset 0x80 */
4648 fail = 1; 4719 if (!write_eeprom(sp, 0x080, 0, 3))
4720 fail = 1;
4649 4721
4650 /* Test Write Error at offset 0xfc */ 4722 /* Test Write Error at offset 0xfc */
4651 if (!write_eeprom(sp, 0x0FC, 0, 3)) 4723 if (!write_eeprom(sp, 0x0FC, 0, 3))
4652 fail = 1; 4724 fail = 1;
4653 4725
4654 /* Test Write Error at offset 0x100 */ 4726 /* Test Write Error at offset 0x100 */
4655 if (!write_eeprom(sp, 0x100, 0, 3)) 4727 if (!write_eeprom(sp, 0x100, 0, 3))
4656 fail = 1; 4728 fail = 1;
4657 4729
4658 /* Test Write Error at offset 4ec */ 4730 /* Test Write Error at offset 4ec */
4659 if (!write_eeprom(sp, 0x4EC, 0, 3)) 4731 if (!write_eeprom(sp, 0x4EC, 0, 3))
4660 fail = 1; 4732 fail = 1;
4733 }
4734
4735 /* Restore values at offsets 0x4F0 and 0x7F0 */
4736 if (saved_4F0)
4737 write_eeprom(sp, 0x4F0, org_4F0, 3);
4738 if (saved_7F0)
4739 write_eeprom(sp, 0x7F0, org_7F0, 3);
4661 4740
4662 *data = fail; 4741 *data = fail;
4663 return 0; 4742 return fail;
4664} 4743}
4665 4744
4666/** 4745/**
@@ -4742,7 +4821,7 @@ static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4742{ 4821{
4743 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4822 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4744 u64 val64; 4823 u64 val64;
4745 int cnt, iteration = 0, test_pass = 0; 4824 int cnt, iteration = 0, test_fail = 0;
4746 4825
4747 val64 = readq(&bar0->adapter_control); 4826 val64 = readq(&bar0->adapter_control);
4748 val64 &= ~ADAPTER_ECC_EN; 4827 val64 &= ~ADAPTER_ECC_EN;
@@ -4750,7 +4829,7 @@ static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4750 4829
4751 val64 = readq(&bar0->mc_rldram_test_ctrl); 4830 val64 = readq(&bar0->mc_rldram_test_ctrl);
4752 val64 |= MC_RLDRAM_TEST_MODE; 4831 val64 |= MC_RLDRAM_TEST_MODE;
4753 writeq(val64, &bar0->mc_rldram_test_ctrl); 4832 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4754 4833
4755 val64 = readq(&bar0->mc_rldram_mrs); 4834 val64 = readq(&bar0->mc_rldram_mrs);
4756 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; 4835 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
@@ -4778,17 +4857,12 @@ static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4778 } 4857 }
4779 writeq(val64, &bar0->mc_rldram_test_d2); 4858 writeq(val64, &bar0->mc_rldram_test_d2);
4780 4859
4781 val64 = (u64) (0x0000003fffff0000ULL); 4860 val64 = (u64) (0x0000003ffffe0100ULL);
4782 writeq(val64, &bar0->mc_rldram_test_add); 4861 writeq(val64, &bar0->mc_rldram_test_add);
4783 4862
4784 4863 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
4785 val64 = MC_RLDRAM_TEST_MODE; 4864 MC_RLDRAM_TEST_GO;
4786 writeq(val64, &bar0->mc_rldram_test_ctrl); 4865 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4787
4788 val64 |=
4789 MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
4790 MC_RLDRAM_TEST_GO;
4791 writeq(val64, &bar0->mc_rldram_test_ctrl);
4792 4866
4793 for (cnt = 0; cnt < 5; cnt++) { 4867 for (cnt = 0; cnt < 5; cnt++) {
4794 val64 = readq(&bar0->mc_rldram_test_ctrl); 4868 val64 = readq(&bar0->mc_rldram_test_ctrl);
@@ -4800,11 +4874,8 @@ static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4800 if (cnt == 5) 4874 if (cnt == 5)
4801 break; 4875 break;
4802 4876
4803 val64 = MC_RLDRAM_TEST_MODE; 4877 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
4804 writeq(val64, &bar0->mc_rldram_test_ctrl); 4878 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4805
4806 val64 |= MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
4807 writeq(val64, &bar0->mc_rldram_test_ctrl);
4808 4879
4809 for (cnt = 0; cnt < 5; cnt++) { 4880 for (cnt = 0; cnt < 5; cnt++) {
4810 val64 = readq(&bar0->mc_rldram_test_ctrl); 4881 val64 = readq(&bar0->mc_rldram_test_ctrl);
@@ -4817,18 +4888,18 @@ static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4817 break; 4888 break;
4818 4889
4819 val64 = readq(&bar0->mc_rldram_test_ctrl); 4890 val64 = readq(&bar0->mc_rldram_test_ctrl);
4820 if (val64 & MC_RLDRAM_TEST_PASS) 4891 if (!(val64 & MC_RLDRAM_TEST_PASS))
4821 test_pass = 1; 4892 test_fail = 1;
4822 4893
4823 iteration++; 4894 iteration++;
4824 } 4895 }
4825 4896
4826 if (!test_pass) 4897 *data = test_fail;
4827 *data = 1;
4828 else
4829 *data = 0;
4830 4898
4831 return 0; 4899 /* Bring the adapter out of test mode */
4900 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
4901
4902 return test_fail;
4832} 4903}
4833 4904
4834/** 4905/**