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authorKristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>2007-08-08 10:57:08 -0400
committerJeff Garzik <jeff@garzik.org>2007-10-12 14:55:37 -0400
commit7c9ef8e418374aec0a62e64d9b40d457634fd039 (patch)
tree6a9c30266aa97b38515647cdc404cb7d3c512e15 /drivers
parentd830d1731fa5906aad20c228ac8b73005b13d468 (diff)
AVR32 PATA driver
Updated and simplified driver. Use only register transfer timing for both data and register transfers. This gives poorer performance in PIO1 and 2, but should not be a problem in PIO3 and 4, correct me if I'm wrong :) The driver works very we'll but I still wonder about the interrupts. I have an interrupt line, that works nicely when POLLING flag is not set. The problem is the number of interrupts that eat away my CPU cycles. When using the POLLING flag there seem to be some interrupts that dosen't get cleared. Furthermore the device dosen't drive INTRQ high, it stays at 2.5 volts and generates a lot of interrupts due to ripple / noise. What to do? Signed-off-by: Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ata/Kconfig9
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/pata_at32.c441
3 files changed, 451 insertions, 0 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index a427945f0bb1..2cd0e7476718 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -199,6 +199,15 @@ config PATA_ARTOP
199 199
200 If unsure, say N. 200 If unsure, say N.
201 201
202config PATA_AT32
203 tristate "Atmel AVR32 PATA support (Experimental)"
204 depends on AVR32 && PLATFORM_AT32AP && EXPERIMENTAL
205 help
206 This option enables support for the IDE devices on the
207 Atmel AT32AP platform.
208
209 If unsure, say N.
210
202config PATA_ATIIXP 211config PATA_ATIIXP
203 tristate "ATI PATA support (Experimental)" 212 tristate "ATI PATA support (Experimental)"
204 depends on PCI && EXPERIMENTAL 213 depends on PCI && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index c2ecba5f0b47..4eb7fb44be3f 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
21obj-$(CONFIG_PATA_ALI) += pata_ali.o 21obj-$(CONFIG_PATA_ALI) += pata_ali.o
22obj-$(CONFIG_PATA_AMD) += pata_amd.o 22obj-$(CONFIG_PATA_AMD) += pata_amd.o
23obj-$(CONFIG_PATA_ARTOP) += pata_artop.o 23obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
24obj-$(CONFIG_PATA_AT32) += pata_at32.o
24obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o 25obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
25obj-$(CONFIG_PATA_CMD640_PCI) += pata_cmd640.o 26obj-$(CONFIG_PATA_CMD640_PCI) += pata_cmd640.o
26obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o 27obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
diff --git a/drivers/ata/pata_at32.c b/drivers/ata/pata_at32.c
new file mode 100644
index 000000000000..bb250a48e27c
--- /dev/null
+++ b/drivers/ata/pata_at32.c
@@ -0,0 +1,441 @@
1/*
2 * AVR32 SMC/CFC PATA Driver
3 *
4 * Copyright (C) 2007 Atmel Norway
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 */
10
11#define DEBUG
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <scsi/scsi_host.h>
22#include <linux/ata.h>
23#include <linux/libata.h>
24#include <linux/err.h>
25#include <linux/io.h>
26
27#include <asm/arch/board.h>
28#include <asm/arch/smc.h>
29
30#define DRV_NAME "pata_at32"
31#define DRV_VERSION "0.0.2"
32
33/*
34 * CompactFlash controller memory layout relative to the base address:
35 *
36 * Attribute memory: 0000 0000 -> 003f ffff
37 * Common memory: 0040 0000 -> 007f ffff
38 * I/O memory: 0080 0000 -> 00bf ffff
39 * True IDE Mode: 00c0 0000 -> 00df ffff
40 * Alt IDE Mode: 00e0 0000 -> 00ff ffff
41 *
42 * Only True IDE and Alt True IDE mode are needed for this driver.
43 *
44 * True IDE mode => CS0 = 0, CS1 = 1 (cmd, error, stat, etc)
45 * Alt True IDE mode => CS0 = 1, CS1 = 0 (ctl, alt_stat)
46 */
47#define CF_IDE_OFFSET 0x00c00000
48#define CF_ALT_IDE_OFFSET 0x00e00000
49#define CF_RES_SIZE 2048
50
51/*
52 * Define DEBUG_BUS if you are doing debugging of your own EBI -> PATA
53 * adaptor with a logic analyzer or similar.
54 */
55#undef DEBUG_BUS
56
57/*
58 * ATA PIO modes
59 *
60 * Name | Mb/s | Min cycle time | Mask
61 * --------+-------+----------------+--------
62 * Mode 0 | 3.3 | 600 ns | 0x01
63 * Mode 1 | 5.2 | 383 ns | 0x03
64 * Mode 2 | 8.3 | 240 ns | 0x07
65 * Mode 3 | 11.1 | 180 ns | 0x0f
66 * Mode 4 | 16.7 | 120 ns | 0x1f
67 */
68#define PIO_MASK (0x1f)
69
70/*
71 * Struct containing private information about device.
72 */
73struct at32_ide_info {
74 unsigned int irq;
75 struct resource res_ide;
76 struct resource res_alt;
77 void __iomem *ide_addr;
78 void __iomem *alt_addr;
79 unsigned int cs;
80 struct smc_config smc;
81};
82
83/*
84 * Setup SMC for the given ATA timing.
85 */
86static int pata_at32_setup_timing(struct device *dev,
87 struct at32_ide_info *info,
88 const struct ata_timing *timing)
89{
90 /* These two values are found through testing */
91 const int min_recover = 25;
92 const int ncs_hold = 15;
93
94 struct smc_config *smc = &info->smc;
95
96 int active;
97 int recover;
98
99 /* Total cycle time */
100 smc->read_cycle = timing->cyc8b;
101
102 /* DIOR <= CFIOR timings */
103 smc->nrd_setup = timing->setup;
104 smc->nrd_pulse = timing->act8b;
105
106 /* Compute recover, extend total cycle if needed */
107 active = smc->nrd_setup + smc->nrd_pulse;
108 recover = smc->read_cycle - active;
109
110 if (recover < min_recover) {
111 smc->read_cycle = active + min_recover;
112 recover = min_recover;
113 }
114
115 /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
116 smc->ncs_read_setup = 0;
117 smc->ncs_read_pulse = active + ncs_hold;
118
119 /* Write timings same as read timings */
120 smc->write_cycle = smc->read_cycle;
121 smc->nwe_setup = smc->nrd_setup;
122 smc->nwe_pulse = smc->nrd_pulse;
123 smc->ncs_write_setup = smc->ncs_read_setup;
124 smc->ncs_write_pulse = smc->ncs_read_pulse;
125
126 /* Do some debugging output */
127 dev_dbg(dev, "SMC: C=%d S=%d P=%d R=%d NCSS=%d NCSP=%d NCSR=%d\n",
128 smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
129 recover, smc->ncs_read_setup, smc->ncs_read_pulse,
130 smc->read_cycle - smc->ncs_read_pulse);
131
132 /* Finally, configure the SMC */
133 return smc_set_configuration(info->cs, smc);
134}
135
136/*
137 * Procedures for libATA.
138 */
139static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev)
140{
141 struct ata_timing timing;
142 struct at32_ide_info *info = ap->host->private_data;
143
144 int ret;
145
146 /* Compute ATA timing */
147 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
148 if (ret) {
149 dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret);
150 return;
151 }
152
153 /* Setup SMC to ATA timing */
154 ret = pata_at32_setup_timing(ap->dev, info, &timing);
155 if (ret) {
156 dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret);
157 return;
158 }
159}
160
161static void pata_at32_irq_clear(struct ata_port *ap)
162{
163 /* No DMA controller yet */
164}
165
166static struct scsi_host_template at32_sht = {
167 .module = THIS_MODULE,
168 .name = DRV_NAME,
169 .ioctl = ata_scsi_ioctl,
170 .queuecommand = ata_scsi_queuecmd,
171 .can_queue = ATA_DEF_QUEUE,
172 .this_id = ATA_SHT_THIS_ID,
173 .sg_tablesize = LIBATA_MAX_PRD,
174 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
175 .emulated = ATA_SHT_EMULATED,
176 .use_clustering = ATA_SHT_USE_CLUSTERING,
177 .proc_name = DRV_NAME,
178 .dma_boundary = ATA_DMA_BOUNDARY,
179 .slave_configure = ata_scsi_slave_config,
180 .slave_destroy = ata_scsi_slave_destroy,
181 .bios_param = ata_std_bios_param,
182};
183
184static struct ata_port_operations at32_port_ops = {
185 .port_disable = ata_port_disable,
186 .set_piomode = pata_at32_set_piomode,
187 .tf_load = ata_tf_load,
188 .tf_read = ata_tf_read,
189 .exec_command = ata_exec_command,
190 .check_status = ata_check_status,
191 .dev_select = ata_std_dev_select,
192
193 .freeze = ata_bmdma_freeze,
194 .thaw = ata_bmdma_thaw,
195 .error_handler = ata_bmdma_error_handler,
196 .post_internal_cmd = ata_bmdma_post_internal_cmd,
197 .cable_detect = ata_cable_40wire,
198
199 .qc_prep = ata_qc_prep,
200 .qc_issue = ata_qc_issue_prot,
201
202 .data_xfer = ata_data_xfer,
203
204 .irq_clear = pata_at32_irq_clear,
205 .irq_on = ata_irq_on,
206 .irq_ack = ata_irq_ack,
207
208 .port_start = ata_sff_port_start,
209};
210
211static int __init pata_at32_init_one(struct device *dev,
212 struct at32_ide_info *info)
213{
214 struct ata_host *host;
215 struct ata_port *ap;
216
217 host = ata_host_alloc(dev, 1);
218 if (!host)
219 return -ENOMEM;
220
221 ap = host->ports[0];
222
223 /* Setup ATA bindings */
224 ap->ops = &at32_port_ops;
225 ap->pio_mask = PIO_MASK;
226 ap->flags = ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS
227 | ATA_FLAG_PIO_POLLING;
228
229 /*
230 * Since all 8-bit taskfile transfers has to go on the lower
231 * byte of the data bus and there is a bug in the SMC that
232 * makes it impossible to alter the bus width during runtime,
233 * we need to hardwire the address signals as follows:
234 *
235 * A_IDE(2:0) <= A_EBI(3:1)
236 *
237 * This makes all addresses on the EBI even, thus all data
238 * will be on the lower byte of the data bus. All addresses
239 * used by libATA need to be altered according to this.
240 */
241 ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1);
242 ap->ioaddr.ctl_addr = info->alt_addr + (0x06 << 1);
243
244 ap->ioaddr.data_addr = info->ide_addr + (ATA_REG_DATA << 1);
245 ap->ioaddr.error_addr = info->ide_addr + (ATA_REG_ERR << 1);
246 ap->ioaddr.feature_addr = info->ide_addr + (ATA_REG_FEATURE << 1);
247 ap->ioaddr.nsect_addr = info->ide_addr + (ATA_REG_NSECT << 1);
248 ap->ioaddr.lbal_addr = info->ide_addr + (ATA_REG_LBAL << 1);
249 ap->ioaddr.lbam_addr = info->ide_addr + (ATA_REG_LBAM << 1);
250 ap->ioaddr.lbah_addr = info->ide_addr + (ATA_REG_LBAH << 1);
251 ap->ioaddr.device_addr = info->ide_addr + (ATA_REG_DEVICE << 1);
252 ap->ioaddr.status_addr = info->ide_addr + (ATA_REG_STATUS << 1);
253 ap->ioaddr.command_addr = info->ide_addr + (ATA_REG_CMD << 1);
254
255 /* Set info as private data of ATA host */
256 host->private_data = info;
257
258 /* Register ATA device and return */
259 return ata_host_activate(host, info->irq, ata_interrupt,
260 IRQF_SHARED | IRQF_TRIGGER_RISING,
261 &at32_sht);
262}
263
264/*
265 * This function may come in handy for people analyzing their own
266 * EBI -> PATA adaptors.
267 */
268#ifdef DEBUG_BUS
269
270static void __init pata_at32_debug_bus(struct device *dev,
271 struct at32_ide_info *info)
272{
273 const int d1 = 0xff;
274 const int d2 = 0x00;
275
276 int i;
277
278 /* Write 8-bit values (registers) */
279 iowrite8(d1, info->alt_addr + (0x06 << 1));
280 iowrite8(d2, info->alt_addr + (0x06 << 1));
281
282 for (i = 0; i < 8; i++) {
283 iowrite8(d1, info->ide_addr + (i << 1));
284 iowrite8(d2, info->ide_addr + (i << 1));
285 }
286
287 /* Write 16 bit values (data) */
288 iowrite16(d1, info->ide_addr);
289 iowrite16(d1 << 8, info->ide_addr);
290
291 iowrite16(d1, info->ide_addr);
292 iowrite16(d1 << 8, info->ide_addr);
293}
294
295#endif
296
297static int __init pata_at32_probe(struct platform_device *pdev)
298{
299 const struct ata_timing initial_timing =
300 {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
301
302 struct device *dev = &pdev->dev;
303 struct at32_ide_info *info;
304 struct ide_platform_data *board = pdev->dev.platform_data;
305 struct resource *res;
306
307 int irq;
308 int ret;
309
310 if (!board)
311 return -ENXIO;
312
313 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
314 if (!res)
315 return -ENXIO;
316
317 /* Retrive IRQ */
318 irq = platform_get_irq(pdev, 0);
319 if (irq < 0)
320 return irq;
321
322 /* Setup struct containing private infomation */
323 info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL);
324 if (!info)
325 return -ENOMEM;
326
327 memset(info, 0, sizeof(struct at32_ide_info));
328
329 info->irq = irq;
330 info->cs = board->cs;
331
332 /* Request memory resources */
333 info->res_ide.start = res->start + CF_IDE_OFFSET;
334 info->res_ide.end = info->res_ide.start + CF_RES_SIZE - 1;
335 info->res_ide.name = "ide";
336 info->res_ide.flags = IORESOURCE_MEM;
337
338 ret = request_resource(res, &info->res_ide);
339 if (ret)
340 goto err_req_res_ide;
341
342 info->res_alt.start = res->start + CF_ALT_IDE_OFFSET;
343 info->res_alt.end = info->res_alt.start + CF_RES_SIZE - 1;
344 info->res_alt.name = "alt";
345 info->res_alt.flags = IORESOURCE_MEM;
346
347 ret = request_resource(res, &info->res_alt);
348 if (ret)
349 goto err_req_res_alt;
350
351 /* Setup non-timing elements of SMC */
352 info->smc.bus_width = 2; /* 16 bit data bus */
353 info->smc.nrd_controlled = 1; /* Sample data on rising edge of NRD */
354 info->smc.nwe_controlled = 0; /* Drive data on falling edge of NCS */
355 info->smc.nwait_mode = 3; /* NWAIT is in READY mode */
356 info->smc.byte_write = 0; /* Byte select access type */
357 info->smc.tdf_mode = 0; /* TDF optimization disabled */
358 info->smc.tdf_cycles = 0; /* No TDF wait cycles */
359
360 /* Setup ATA timing */
361 ret = pata_at32_setup_timing(dev, info, &initial_timing);
362 if (ret)
363 goto err_setup_timing;
364
365 /* Setup ATA addresses */
366 ret = -ENOMEM;
367 info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
368 info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
369 if (!info->ide_addr || !info->alt_addr)
370 goto err_ioremap;
371
372#ifdef DEBUG_BUS
373 pata_at32_debug_bus(dev, info);
374#endif
375
376 /* Register ATA device */
377 ret = pata_at32_init_one(dev, info);
378 if (ret)
379 goto err_ata_device;
380
381 return 0;
382
383 err_ata_device:
384 err_ioremap:
385 err_setup_timing:
386 release_resource(&info->res_alt);
387 err_req_res_alt:
388 release_resource(&info->res_ide);
389 err_req_res_ide:
390 kfree(info);
391
392 return ret;
393}
394
395static int __exit pata_at32_remove(struct platform_device *pdev)
396{
397 struct ata_host *host = platform_get_drvdata(pdev);
398 struct at32_ide_info *info;
399
400 if (!host)
401 return 0;
402
403 info = host->private_data;
404 ata_host_detach(host);
405
406 if (!info)
407 return 0;
408
409 release_resource(&info->res_ide);
410 release_resource(&info->res_alt);
411
412 kfree(info);
413
414 return 0;
415}
416
417static struct platform_driver pata_at32_driver = {
418 .remove = __exit_p(pata_at32_remove),
419 .driver = {
420 .name = "at32_ide",
421 .owner = THIS_MODULE,
422 },
423};
424
425static int __init pata_at32_init(void)
426{
427 return platform_driver_probe(&pata_at32_driver, pata_at32_probe);
428}
429
430static void __exit pata_at32_exit(void)
431{
432 platform_driver_unregister(&pata_at32_driver);
433}
434
435module_init(pata_at32_init);
436module_exit(pata_at32_exit);
437
438MODULE_LICENSE("GPL");
439MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver");
440MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>");
441MODULE_VERSION(DRV_VERSION);