aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorJames Bottomley <James.Bottomley@steeleye.com>2007-07-30 10:52:25 -0400
committerJames Bottomley <jejb@mulgrave.localdomain>2007-07-31 11:44:26 -0400
commit142009a3df39ecd4e96601d8bdabbe0c5f6e2f4e (patch)
treef5a546967d2d9932fae7c96b82146cf2020b22df /drivers
parent28f85009e0cf6a5232cd285131eac3dfe26d9e3a (diff)
[SCSI] aic7xxx: cap maxsync according to correct card limits
Not doing this can cause cards less than u160 capable to send out PPR offers to devices they can't then deliver on ... causing some devices to get a bit confused. Fix by capping the start syncrate at the appropriate level according to the card capabilities. Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_core.c22
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/scsi/aic7xxx/aic7xxx_core.c b/drivers/scsi/aic7xxx/aic7xxx_core.c
index 75733b09f27a..f350b5e89e76 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_core.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_core.c
@@ -1701,7 +1701,16 @@ ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1701 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1701 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1702 && maxsync < AHC_SYNCRATE_ULTRA2) 1702 && maxsync < AHC_SYNCRATE_ULTRA2)
1703 maxsync = AHC_SYNCRATE_ULTRA2; 1703 maxsync = AHC_SYNCRATE_ULTRA2;
1704 1704
1705 /* Now set the maxsync based on the card capabilities
1706 * DT is already done above */
1707 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
1708 && maxsync < AHC_SYNCRATE_ULTRA)
1709 maxsync = AHC_SYNCRATE_ULTRA;
1710 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
1711 && maxsync < AHC_SYNCRATE_FAST)
1712 maxsync = AHC_SYNCRATE_FAST;
1713
1705 for (syncrate = &ahc_syncrates[maxsync]; 1714 for (syncrate = &ahc_syncrates[maxsync];
1706 syncrate->rate != NULL; 1715 syncrate->rate != NULL;
1707 syncrate++) { 1716 syncrate++) {
@@ -1765,6 +1774,17 @@ ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1765 else 1774 else
1766 scsirate &= SXFR; 1775 scsirate &= SXFR;
1767 1776
1777 /* now set maxsync based on card capabilities */
1778 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
1779 maxsync = AHC_SYNCRATE_ULTRA2;
1780 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
1781 && maxsync < AHC_SYNCRATE_ULTRA)
1782 maxsync = AHC_SYNCRATE_ULTRA;
1783 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
1784 && maxsync < AHC_SYNCRATE_FAST)
1785 maxsync = AHC_SYNCRATE_FAST;
1786
1787
1768 syncrate = &ahc_syncrates[maxsync]; 1788 syncrate = &ahc_syncrates[maxsync];
1769 while (syncrate->rate != NULL) { 1789 while (syncrate->rate != NULL) {
1770 1790