diff options
author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-06-22 12:33:51 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-06-22 12:33:51 -0400 |
commit | ef7994fa2aecd8d1fb0d75034caa050ff908d26a (patch) | |
tree | aa7bbe9499256ced149dce70891de5eedf33c283 /drivers | |
parent | ad8686bc05adc2b8301d749f5958bd904f3a46ee (diff) | |
parent | a497c3ba1d97fc69c1e78e7b96435ba8c2cb42ee (diff) |
Merge 3.16-rc2 into staging-next
We want the staging fixes here as well.
Diffstat (limited to 'drivers')
151 files changed, 3337 insertions, 1469 deletions
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 63407d264885..9cb65b0e7597 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c | |||
@@ -34,6 +34,9 @@ ACPI_MODULE_NAME("acpi_lpss"); | |||
34 | 34 | ||
35 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | 35 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ |
36 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) | 36 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
37 | #define LPSS_RESETS 0x04 | ||
38 | #define LPSS_RESETS_RESET_FUNC BIT(0) | ||
39 | #define LPSS_RESETS_RESET_APB BIT(1) | ||
37 | #define LPSS_GENERAL 0x08 | 40 | #define LPSS_GENERAL 0x08 |
38 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | 41 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) |
39 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) | 42 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
@@ -99,6 +102,17 @@ static void lpss_uart_setup(struct lpss_private_data *pdata) | |||
99 | writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset); | 102 | writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset); |
100 | } | 103 | } |
101 | 104 | ||
105 | static void lpss_i2c_setup(struct lpss_private_data *pdata) | ||
106 | { | ||
107 | unsigned int offset; | ||
108 | u32 val; | ||
109 | |||
110 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | ||
111 | val = readl(pdata->mmio_base + offset); | ||
112 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | ||
113 | writel(val, pdata->mmio_base + offset); | ||
114 | } | ||
115 | |||
102 | static struct lpss_device_desc lpt_dev_desc = { | 116 | static struct lpss_device_desc lpt_dev_desc = { |
103 | .clk_required = true, | 117 | .clk_required = true, |
104 | .prv_offset = 0x800, | 118 | .prv_offset = 0x800, |
@@ -171,6 +185,7 @@ static struct lpss_device_desc byt_i2c_dev_desc = { | |||
171 | .prv_offset = 0x800, | 185 | .prv_offset = 0x800, |
172 | .save_ctx = true, | 186 | .save_ctx = true, |
173 | .shared_clock = &i2c_clock, | 187 | .shared_clock = &i2c_clock, |
188 | .setup = lpss_i2c_setup, | ||
174 | }; | 189 | }; |
175 | 190 | ||
176 | #else | 191 | #else |
diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index e48fc98e71c4..0d7116f34b95 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <linux/jiffies.h> | 32 | #include <linux/jiffies.h> |
33 | #include <linux/async.h> | 33 | #include <linux/async.h> |
34 | #include <linux/dmi.h> | 34 | #include <linux/dmi.h> |
35 | #include <linux/delay.h> | ||
35 | #include <linux/slab.h> | 36 | #include <linux/slab.h> |
36 | #include <linux/suspend.h> | 37 | #include <linux/suspend.h> |
37 | #include <asm/unaligned.h> | 38 | #include <asm/unaligned.h> |
@@ -70,6 +71,7 @@ MODULE_DESCRIPTION("ACPI Battery Driver"); | |||
70 | MODULE_LICENSE("GPL"); | 71 | MODULE_LICENSE("GPL"); |
71 | 72 | ||
72 | static int battery_bix_broken_package; | 73 | static int battery_bix_broken_package; |
74 | static int battery_notification_delay_ms; | ||
73 | static unsigned int cache_time = 1000; | 75 | static unsigned int cache_time = 1000; |
74 | module_param(cache_time, uint, 0644); | 76 | module_param(cache_time, uint, 0644); |
75 | MODULE_PARM_DESC(cache_time, "cache time in milliseconds"); | 77 | MODULE_PARM_DESC(cache_time, "cache time in milliseconds"); |
@@ -930,7 +932,10 @@ static ssize_t acpi_battery_write_alarm(struct file *file, | |||
930 | goto end; | 932 | goto end; |
931 | } | 933 | } |
932 | alarm_string[count] = '\0'; | 934 | alarm_string[count] = '\0'; |
933 | battery->alarm = simple_strtol(alarm_string, NULL, 0); | 935 | if (kstrtoint(alarm_string, 0, &battery->alarm)) { |
936 | result = -EINVAL; | ||
937 | goto end; | ||
938 | } | ||
934 | result = acpi_battery_set_alarm(battery); | 939 | result = acpi_battery_set_alarm(battery); |
935 | end: | 940 | end: |
936 | if (!result) | 941 | if (!result) |
@@ -1062,6 +1067,14 @@ static void acpi_battery_notify(struct acpi_device *device, u32 event) | |||
1062 | if (!battery) | 1067 | if (!battery) |
1063 | return; | 1068 | return; |
1064 | old = battery->bat.dev; | 1069 | old = battery->bat.dev; |
1070 | /* | ||
1071 | * On Acer Aspire V5-573G notifications are sometimes triggered too | ||
1072 | * early. For example, when AC is unplugged and notification is | ||
1073 | * triggered, battery state is still reported as "Full", and changes to | ||
1074 | * "Discharging" only after short delay, without any notification. | ||
1075 | */ | ||
1076 | if (battery_notification_delay_ms > 0) | ||
1077 | msleep(battery_notification_delay_ms); | ||
1065 | if (event == ACPI_BATTERY_NOTIFY_INFO) | 1078 | if (event == ACPI_BATTERY_NOTIFY_INFO) |
1066 | acpi_battery_refresh(battery); | 1079 | acpi_battery_refresh(battery); |
1067 | acpi_battery_update(battery, false); | 1080 | acpi_battery_update(battery, false); |
@@ -1106,14 +1119,35 @@ static int battery_notify(struct notifier_block *nb, | |||
1106 | return 0; | 1119 | return 0; |
1107 | } | 1120 | } |
1108 | 1121 | ||
1122 | static int battery_bix_broken_package_quirk(const struct dmi_system_id *d) | ||
1123 | { | ||
1124 | battery_bix_broken_package = 1; | ||
1125 | return 0; | ||
1126 | } | ||
1127 | |||
1128 | static int battery_notification_delay_quirk(const struct dmi_system_id *d) | ||
1129 | { | ||
1130 | battery_notification_delay_ms = 1000; | ||
1131 | return 0; | ||
1132 | } | ||
1133 | |||
1109 | static struct dmi_system_id bat_dmi_table[] = { | 1134 | static struct dmi_system_id bat_dmi_table[] = { |
1110 | { | 1135 | { |
1136 | .callback = battery_bix_broken_package_quirk, | ||
1111 | .ident = "NEC LZ750/LS", | 1137 | .ident = "NEC LZ750/LS", |
1112 | .matches = { | 1138 | .matches = { |
1113 | DMI_MATCH(DMI_SYS_VENDOR, "NEC"), | 1139 | DMI_MATCH(DMI_SYS_VENDOR, "NEC"), |
1114 | DMI_MATCH(DMI_PRODUCT_NAME, "PC-LZ750LS"), | 1140 | DMI_MATCH(DMI_PRODUCT_NAME, "PC-LZ750LS"), |
1115 | }, | 1141 | }, |
1116 | }, | 1142 | }, |
1143 | { | ||
1144 | .callback = battery_notification_delay_quirk, | ||
1145 | .ident = "Acer Aspire V5-573G", | ||
1146 | .matches = { | ||
1147 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | ||
1148 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire V5-573G"), | ||
1149 | }, | ||
1150 | }, | ||
1117 | {}, | 1151 | {}, |
1118 | }; | 1152 | }; |
1119 | 1153 | ||
@@ -1227,8 +1261,7 @@ static void __init acpi_battery_init_async(void *unused, async_cookie_t cookie) | |||
1227 | if (acpi_disabled) | 1261 | if (acpi_disabled) |
1228 | return; | 1262 | return; |
1229 | 1263 | ||
1230 | if (dmi_check_system(bat_dmi_table)) | 1264 | dmi_check_system(bat_dmi_table); |
1231 | battery_bix_broken_package = 1; | ||
1232 | 1265 | ||
1233 | #ifdef CONFIG_ACPI_PROCFS_POWER | 1266 | #ifdef CONFIG_ACPI_PROCFS_POWER |
1234 | acpi_battery_dir = acpi_lock_battery_dir(); | 1267 | acpi_battery_dir = acpi_lock_battery_dir(); |
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 3f2bdc812d23..bad25b070fe0 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c | |||
@@ -235,7 +235,8 @@ void acpi_os_vprintf(const char *fmt, va_list args) | |||
235 | static unsigned long acpi_rsdp; | 235 | static unsigned long acpi_rsdp; |
236 | static int __init setup_acpi_rsdp(char *arg) | 236 | static int __init setup_acpi_rsdp(char *arg) |
237 | { | 237 | { |
238 | acpi_rsdp = simple_strtoul(arg, NULL, 16); | 238 | if (kstrtoul(arg, 16, &acpi_rsdp)) |
239 | return -EINVAL; | ||
239 | return 0; | 240 | return 0; |
240 | } | 241 | } |
241 | early_param("acpi_rsdp", setup_acpi_rsdp); | 242 | early_param("acpi_rsdp", setup_acpi_rsdp); |
diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 05550ba44d32..6d5a6cda0734 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c | |||
@@ -360,7 +360,8 @@ static int __init acpi_parse_apic_instance(char *str) | |||
360 | if (!str) | 360 | if (!str) |
361 | return -EINVAL; | 361 | return -EINVAL; |
362 | 362 | ||
363 | acpi_apic_instance = simple_strtoul(str, NULL, 0); | 363 | if (kstrtoint(str, 0, &acpi_apic_instance)) |
364 | return -EINVAL; | ||
364 | 365 | ||
365 | pr_notice("Shall use APIC/MADT table %d\n", acpi_apic_instance); | 366 | pr_notice("Shall use APIC/MADT table %d\n", acpi_apic_instance); |
366 | 367 | ||
diff --git a/drivers/block/null_blk.c b/drivers/block/null_blk.c index 77087a29b127..a3b042c4d448 100644 --- a/drivers/block/null_blk.c +++ b/drivers/block/null_blk.c | |||
@@ -79,7 +79,7 @@ MODULE_PARM_DESC(home_node, "Home node for the device"); | |||
79 | 79 | ||
80 | static int queue_mode = NULL_Q_MQ; | 80 | static int queue_mode = NULL_Q_MQ; |
81 | module_param(queue_mode, int, S_IRUGO); | 81 | module_param(queue_mode, int, S_IRUGO); |
82 | MODULE_PARM_DESC(use_mq, "Use blk-mq interface (0=bio,1=rq,2=multiqueue)"); | 82 | MODULE_PARM_DESC(queue_mode, "Block interface to use (0=bio,1=rq,2=multiqueue)"); |
83 | 83 | ||
84 | static int gb = 250; | 84 | static int gb = 250; |
85 | module_param(gb, int, S_IRUGO); | 85 | module_param(gb, int, S_IRUGO); |
@@ -227,7 +227,10 @@ static void null_cmd_end_timer(struct nullb_cmd *cmd) | |||
227 | 227 | ||
228 | static void null_softirq_done_fn(struct request *rq) | 228 | static void null_softirq_done_fn(struct request *rq) |
229 | { | 229 | { |
230 | end_cmd(blk_mq_rq_to_pdu(rq)); | 230 | if (queue_mode == NULL_Q_MQ) |
231 | end_cmd(blk_mq_rq_to_pdu(rq)); | ||
232 | else | ||
233 | end_cmd(rq->special); | ||
231 | } | 234 | } |
232 | 235 | ||
233 | static inline void null_handle_cmd(struct nullb_cmd *cmd) | 236 | static inline void null_handle_cmd(struct nullb_cmd *cmd) |
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index a118ec1650fa..1f37d9870e7a 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig | |||
@@ -45,7 +45,7 @@ config OMAP_INTERCONNECT | |||
45 | 45 | ||
46 | config ARM_CCI | 46 | config ARM_CCI |
47 | bool "ARM CCI driver support" | 47 | bool "ARM CCI driver support" |
48 | depends on ARM | 48 | depends on ARM && OF && CPU_V7 |
49 | help | 49 | help |
50 | Driver supporting the CCI cache coherent interconnect for ARM | 50 | Driver supporting the CCI cache coherent interconnect for ARM |
51 | platforms. | 51 | platforms. |
diff --git a/drivers/char/random.c b/drivers/char/random.c index 4ad71ef2cd59..0a7ac0a7b252 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c | |||
@@ -980,7 +980,6 @@ static void push_to_pool(struct work_struct *work) | |||
980 | static size_t account(struct entropy_store *r, size_t nbytes, int min, | 980 | static size_t account(struct entropy_store *r, size_t nbytes, int min, |
981 | int reserved) | 981 | int reserved) |
982 | { | 982 | { |
983 | int have_bytes; | ||
984 | int entropy_count, orig; | 983 | int entropy_count, orig; |
985 | size_t ibytes; | 984 | size_t ibytes; |
986 | 985 | ||
@@ -989,17 +988,19 @@ static size_t account(struct entropy_store *r, size_t nbytes, int min, | |||
989 | /* Can we pull enough? */ | 988 | /* Can we pull enough? */ |
990 | retry: | 989 | retry: |
991 | entropy_count = orig = ACCESS_ONCE(r->entropy_count); | 990 | entropy_count = orig = ACCESS_ONCE(r->entropy_count); |
992 | have_bytes = entropy_count >> (ENTROPY_SHIFT + 3); | ||
993 | ibytes = nbytes; | 991 | ibytes = nbytes; |
994 | /* If limited, never pull more than available */ | 992 | /* If limited, never pull more than available */ |
995 | if (r->limit) | 993 | if (r->limit) { |
996 | ibytes = min_t(size_t, ibytes, have_bytes - reserved); | 994 | int have_bytes = entropy_count >> (ENTROPY_SHIFT + 3); |
995 | |||
996 | if ((have_bytes -= reserved) < 0) | ||
997 | have_bytes = 0; | ||
998 | ibytes = min_t(size_t, ibytes, have_bytes); | ||
999 | } | ||
997 | if (ibytes < min) | 1000 | if (ibytes < min) |
998 | ibytes = 0; | 1001 | ibytes = 0; |
999 | if (have_bytes >= ibytes + reserved) | 1002 | if ((entropy_count -= ibytes << (ENTROPY_SHIFT + 3)) < 0) |
1000 | entropy_count -= ibytes << (ENTROPY_SHIFT + 3); | 1003 | entropy_count = 0; |
1001 | else | ||
1002 | entropy_count = reserved << (ENTROPY_SHIFT + 3); | ||
1003 | 1004 | ||
1004 | if (cmpxchg(&r->entropy_count, orig, entropy_count) != orig) | 1005 | if (cmpxchg(&r->entropy_count, orig, entropy_count) != orig) |
1005 | goto retry; | 1006 | goto retry; |
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index e473d6555f96..ffe350f86bca 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig | |||
@@ -186,6 +186,8 @@ config CPU_FREQ_GOV_CONSERVATIVE | |||
186 | config GENERIC_CPUFREQ_CPU0 | 186 | config GENERIC_CPUFREQ_CPU0 |
187 | tristate "Generic CPU0 cpufreq driver" | 187 | tristate "Generic CPU0 cpufreq driver" |
188 | depends on HAVE_CLK && OF | 188 | depends on HAVE_CLK && OF |
189 | # if CPU_THERMAL is on and THERMAL=m, CPU0 cannot be =y: | ||
190 | depends on !CPU_THERMAL || THERMAL | ||
189 | select PM_OPP | 191 | select PM_OPP |
190 | help | 192 | help |
191 | This adds a generic cpufreq driver for CPU0 frequency management. | 193 | This adds a generic cpufreq driver for CPU0 frequency management. |
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index aed2b0cb83dc..62259d27f03e 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c | |||
@@ -2242,10 +2242,8 @@ int cpufreq_update_policy(unsigned int cpu) | |||
2242 | struct cpufreq_policy new_policy; | 2242 | struct cpufreq_policy new_policy; |
2243 | int ret; | 2243 | int ret; |
2244 | 2244 | ||
2245 | if (!policy) { | 2245 | if (!policy) |
2246 | ret = -ENODEV; | 2246 | return -ENODEV; |
2247 | goto no_policy; | ||
2248 | } | ||
2249 | 2247 | ||
2250 | down_write(&policy->rwsem); | 2248 | down_write(&policy->rwsem); |
2251 | 2249 | ||
@@ -2264,7 +2262,7 @@ int cpufreq_update_policy(unsigned int cpu) | |||
2264 | new_policy.cur = cpufreq_driver->get(cpu); | 2262 | new_policy.cur = cpufreq_driver->get(cpu); |
2265 | if (WARN_ON(!new_policy.cur)) { | 2263 | if (WARN_ON(!new_policy.cur)) { |
2266 | ret = -EIO; | 2264 | ret = -EIO; |
2267 | goto no_policy; | 2265 | goto unlock; |
2268 | } | 2266 | } |
2269 | 2267 | ||
2270 | if (!policy->cur) { | 2268 | if (!policy->cur) { |
@@ -2279,10 +2277,10 @@ int cpufreq_update_policy(unsigned int cpu) | |||
2279 | 2277 | ||
2280 | ret = cpufreq_set_policy(policy, &new_policy); | 2278 | ret = cpufreq_set_policy(policy, &new_policy); |
2281 | 2279 | ||
2280 | unlock: | ||
2282 | up_write(&policy->rwsem); | 2281 | up_write(&policy->rwsem); |
2283 | 2282 | ||
2284 | cpufreq_cpu_put(policy); | 2283 | cpufreq_cpu_put(policy); |
2285 | no_policy: | ||
2286 | return ret; | 2284 | return ret; |
2287 | } | 2285 | } |
2288 | EXPORT_SYMBOL(cpufreq_update_policy); | 2286 | EXPORT_SYMBOL(cpufreq_update_policy); |
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 4e7f492ad583..924bb2d42b1c 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c | |||
@@ -196,10 +196,7 @@ static signed int pid_calc(struct _pid *pid, int32_t busy) | |||
196 | pid->last_err = fp_error; | 196 | pid->last_err = fp_error; |
197 | 197 | ||
198 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | 198 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; |
199 | if (result >= 0) | 199 | result = result + (1 << (FRAC_BITS-1)); |
200 | result = result + (1 << (FRAC_BITS-1)); | ||
201 | else | ||
202 | result = result - (1 << (FRAC_BITS-1)); | ||
203 | return (signed int)fp_toint(result); | 200 | return (signed int)fp_toint(result); |
204 | } | 201 | } |
205 | 202 | ||
diff --git a/drivers/cpuidle/cpuidle-armada-370-xp.c b/drivers/cpuidle/cpuidle-armada-370-xp.c index 28587d0f3947..a5fba0287bfb 100644 --- a/drivers/cpuidle/cpuidle-armada-370-xp.c +++ b/drivers/cpuidle/cpuidle-armada-370-xp.c | |||
@@ -55,7 +55,7 @@ static struct cpuidle_driver armada_370_xp_idle_driver = { | |||
55 | .power_usage = 50, | 55 | .power_usage = 50, |
56 | .target_residency = 100, | 56 | .target_residency = 100, |
57 | .flags = CPUIDLE_FLAG_TIME_VALID, | 57 | .flags = CPUIDLE_FLAG_TIME_VALID, |
58 | .name = "MV CPU IDLE", | 58 | .name = "Idle", |
59 | .desc = "CPU power down", | 59 | .desc = "CPU power down", |
60 | }, | 60 | }, |
61 | .states[2] = { | 61 | .states[2] = { |
@@ -65,7 +65,7 @@ static struct cpuidle_driver armada_370_xp_idle_driver = { | |||
65 | .target_residency = 1000, | 65 | .target_residency = 1000, |
66 | .flags = CPUIDLE_FLAG_TIME_VALID | | 66 | .flags = CPUIDLE_FLAG_TIME_VALID | |
67 | ARMADA_370_XP_FLAG_DEEP_IDLE, | 67 | ARMADA_370_XP_FLAG_DEEP_IDLE, |
68 | .name = "MV CPU DEEP IDLE", | 68 | .name = "Deep idle", |
69 | .desc = "CPU and L2 Fabric power down", | 69 | .desc = "CPU and L2 Fabric power down", |
70 | }, | 70 | }, |
71 | .state_count = ARMADA_370_XP_MAX_STATES, | 71 | .state_count = ARMADA_370_XP_MAX_STATES, |
diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c index 7c2497dea1e9..0dc57d5ecd10 100644 --- a/drivers/gpu/drm/drm_modeset_lock.c +++ b/drivers/gpu/drm/drm_modeset_lock.c | |||
@@ -64,6 +64,7 @@ | |||
64 | void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx, | 64 | void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx, |
65 | uint32_t flags) | 65 | uint32_t flags) |
66 | { | 66 | { |
67 | memset(ctx, 0, sizeof(*ctx)); | ||
67 | ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class); | 68 | ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class); |
68 | INIT_LIST_HEAD(&ctx->locked); | 69 | INIT_LIST_HEAD(&ctx->locked); |
69 | } | 70 | } |
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 4c22a5b7f4c5..6c656392d67d 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
@@ -36,6 +36,8 @@ | |||
36 | #include "i915_drv.h" | 36 | #include "i915_drv.h" |
37 | #include "i915_trace.h" | 37 | #include "i915_trace.h" |
38 | #include <linux/pci.h> | 38 | #include <linux/pci.h> |
39 | #include <linux/console.h> | ||
40 | #include <linux/vt.h> | ||
39 | #include <linux/vgaarb.h> | 41 | #include <linux/vgaarb.h> |
40 | #include <linux/acpi.h> | 42 | #include <linux/acpi.h> |
41 | #include <linux/pnp.h> | 43 | #include <linux/pnp.h> |
@@ -1386,7 +1388,6 @@ cleanup_gem: | |||
1386 | i915_gem_context_fini(dev); | 1388 | i915_gem_context_fini(dev); |
1387 | mutex_unlock(&dev->struct_mutex); | 1389 | mutex_unlock(&dev->struct_mutex); |
1388 | WARN_ON(dev_priv->mm.aliasing_ppgtt); | 1390 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
1389 | drm_mm_takedown(&dev_priv->gtt.base.mm); | ||
1390 | cleanup_irq: | 1391 | cleanup_irq: |
1391 | drm_irq_uninstall(dev); | 1392 | drm_irq_uninstall(dev); |
1392 | cleanup_gem_stolen: | 1393 | cleanup_gem_stolen: |
@@ -1450,6 +1451,38 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) | |||
1450 | } | 1451 | } |
1451 | #endif | 1452 | #endif |
1452 | 1453 | ||
1454 | #if !defined(CONFIG_VGA_CONSOLE) | ||
1455 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | ||
1456 | { | ||
1457 | return 0; | ||
1458 | } | ||
1459 | #elif !defined(CONFIG_DUMMY_CONSOLE) | ||
1460 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | ||
1461 | { | ||
1462 | return -ENODEV; | ||
1463 | } | ||
1464 | #else | ||
1465 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | ||
1466 | { | ||
1467 | int ret; | ||
1468 | |||
1469 | DRM_INFO("Replacing VGA console driver\n"); | ||
1470 | |||
1471 | console_lock(); | ||
1472 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | ||
1473 | if (ret == 0) { | ||
1474 | ret = do_unregister_con_driver(&vga_con); | ||
1475 | |||
1476 | /* Ignore "already unregistered". */ | ||
1477 | if (ret == -ENODEV) | ||
1478 | ret = 0; | ||
1479 | } | ||
1480 | console_unlock(); | ||
1481 | |||
1482 | return ret; | ||
1483 | } | ||
1484 | #endif | ||
1485 | |||
1453 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) | 1486 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
1454 | { | 1487 | { |
1455 | const struct intel_device_info *info = &dev_priv->info; | 1488 | const struct intel_device_info *info = &dev_priv->info; |
@@ -1623,8 +1656,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) | |||
1623 | if (ret) | 1656 | if (ret) |
1624 | goto out_regs; | 1657 | goto out_regs; |
1625 | 1658 | ||
1626 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | 1659 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1660 | ret = i915_kick_out_vgacon(dev_priv); | ||
1661 | if (ret) { | ||
1662 | DRM_ERROR("failed to remove conflicting VGA console\n"); | ||
1663 | goto out_gtt; | ||
1664 | } | ||
1665 | |||
1627 | i915_kick_out_firmware_fb(dev_priv); | 1666 | i915_kick_out_firmware_fb(dev_priv); |
1667 | } | ||
1628 | 1668 | ||
1629 | pci_set_master(dev->pdev); | 1669 | pci_set_master(dev->pdev); |
1630 | 1670 | ||
@@ -1756,8 +1796,6 @@ out_mtrrfree: | |||
1756 | arch_phys_wc_del(dev_priv->gtt.mtrr); | 1796 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
1757 | io_mapping_free(dev_priv->gtt.mappable); | 1797 | io_mapping_free(dev_priv->gtt.mappable); |
1758 | out_gtt: | 1798 | out_gtt: |
1759 | list_del(&dev_priv->gtt.base.global_link); | ||
1760 | drm_mm_takedown(&dev_priv->gtt.base.mm); | ||
1761 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); | 1799 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
1762 | out_regs: | 1800 | out_regs: |
1763 | intel_uncore_fini(dev); | 1801 | intel_uncore_fini(dev); |
@@ -1846,7 +1884,6 @@ int i915_driver_unload(struct drm_device *dev) | |||
1846 | i915_free_hws(dev); | 1884 | i915_free_hws(dev); |
1847 | } | 1885 | } |
1848 | 1886 | ||
1849 | list_del(&dev_priv->gtt.base.global_link); | ||
1850 | WARN_ON(!list_empty(&dev_priv->vm_list)); | 1887 | WARN_ON(!list_empty(&dev_priv->vm_list)); |
1851 | 1888 | ||
1852 | drm_vblank_cleanup(dev); | 1889 | drm_vblank_cleanup(dev); |
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index eec820aec022..8b3cde703364 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
@@ -1992,7 +1992,10 @@ static void gen6_gmch_remove(struct i915_address_space *vm) | |||
1992 | 1992 | ||
1993 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | 1993 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); |
1994 | 1994 | ||
1995 | drm_mm_takedown(&vm->mm); | 1995 | if (drm_mm_initialized(&vm->mm)) { |
1996 | drm_mm_takedown(&vm->mm); | ||
1997 | list_del(&vm->global_link); | ||
1998 | } | ||
1996 | iounmap(gtt->gsm); | 1999 | iounmap(gtt->gsm); |
1997 | teardown_scratch_page(vm->dev); | 2000 | teardown_scratch_page(vm->dev); |
1998 | } | 2001 | } |
@@ -2025,6 +2028,10 @@ static int i915_gmch_probe(struct drm_device *dev, | |||
2025 | 2028 | ||
2026 | static void i915_gmch_remove(struct i915_address_space *vm) | 2029 | static void i915_gmch_remove(struct i915_address_space *vm) |
2027 | { | 2030 | { |
2031 | if (drm_mm_initialized(&vm->mm)) { | ||
2032 | drm_mm_takedown(&vm->mm); | ||
2033 | list_del(&vm->global_link); | ||
2034 | } | ||
2028 | intel_gmch_remove(); | 2035 | intel_gmch_remove(); |
2029 | } | 2036 | } |
2030 | 2037 | ||
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 87ec60e181a7..66cf41765bf9 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c | |||
@@ -888,6 +888,8 @@ static void i915_gem_record_rings(struct drm_device *dev, | |||
888 | for (i = 0; i < I915_NUM_RINGS; i++) { | 888 | for (i = 0; i < I915_NUM_RINGS; i++) { |
889 | struct intel_engine_cs *ring = &dev_priv->ring[i]; | 889 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
890 | 890 | ||
891 | error->ring[i].pid = -1; | ||
892 | |||
891 | if (ring->dev == NULL) | 893 | if (ring->dev == NULL) |
892 | continue; | 894 | continue; |
893 | 895 | ||
@@ -895,7 +897,6 @@ static void i915_gem_record_rings(struct drm_device *dev, | |||
895 | 897 | ||
896 | i915_record_ring_state(dev, ring, &error->ring[i]); | 898 | i915_record_ring_state(dev, ring, &error->ring[i]); |
897 | 899 | ||
898 | error->ring[i].pid = -1; | ||
899 | request = i915_gem_find_active_request(ring); | 900 | request = i915_gem_find_active_request(ring); |
900 | if (request) { | 901 | if (request) { |
901 | /* We need to copy these to an anonymous buffer | 902 | /* We need to copy these to an anonymous buffer |
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6f8017a7e937..267f069765ad 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -2847,10 +2847,14 @@ static int semaphore_passed(struct intel_engine_cs *ring) | |||
2847 | struct intel_engine_cs *signaller; | 2847 | struct intel_engine_cs *signaller; |
2848 | u32 seqno, ctl; | 2848 | u32 seqno, ctl; |
2849 | 2849 | ||
2850 | ring->hangcheck.deadlock = true; | 2850 | ring->hangcheck.deadlock++; |
2851 | 2851 | ||
2852 | signaller = semaphore_waits_for(ring, &seqno); | 2852 | signaller = semaphore_waits_for(ring, &seqno); |
2853 | if (signaller == NULL || signaller->hangcheck.deadlock) | 2853 | if (signaller == NULL) |
2854 | return -1; | ||
2855 | |||
2856 | /* Prevent pathological recursion due to driver bugs */ | ||
2857 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | ||
2854 | return -1; | 2858 | return -1; |
2855 | 2859 | ||
2856 | /* cursory check for an unkickable deadlock */ | 2860 | /* cursory check for an unkickable deadlock */ |
@@ -2858,7 +2862,13 @@ static int semaphore_passed(struct intel_engine_cs *ring) | |||
2858 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | 2862 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) |
2859 | return -1; | 2863 | return -1; |
2860 | 2864 | ||
2861 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | 2865 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2866 | return 1; | ||
2867 | |||
2868 | if (signaller->hangcheck.deadlock) | ||
2869 | return -1; | ||
2870 | |||
2871 | return 0; | ||
2862 | } | 2872 | } |
2863 | 2873 | ||
2864 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | 2874 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) |
@@ -2867,7 +2877,7 @@ static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |||
2867 | int i; | 2877 | int i; |
2868 | 2878 | ||
2869 | for_each_ring(ring, dev_priv, i) | 2879 | for_each_ring(ring, dev_priv, i) |
2870 | ring->hangcheck.deadlock = false; | 2880 | ring->hangcheck.deadlock = 0; |
2871 | } | 2881 | } |
2872 | 2882 | ||
2873 | static enum intel_ring_hangcheck_action | 2883 | static enum intel_ring_hangcheck_action |
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 5e6c888b4928..38a98570d10c 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c | |||
@@ -798,9 +798,6 @@ static void i965_enable_backlight(struct intel_connector *connector) | |||
798 | ctl = freq << 16; | 798 | ctl = freq << 16; |
799 | I915_WRITE(BLC_PWM_CTL, ctl); | 799 | I915_WRITE(BLC_PWM_CTL, ctl); |
800 | 800 | ||
801 | /* XXX: combine this into above write? */ | ||
802 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | ||
803 | |||
804 | ctl2 = BLM_PIPE(pipe); | 801 | ctl2 = BLM_PIPE(pipe); |
805 | if (panel->backlight.combination_mode) | 802 | if (panel->backlight.combination_mode) |
806 | ctl2 |= BLM_COMBINATION_MODE; | 803 | ctl2 |= BLM_COMBINATION_MODE; |
@@ -809,6 +806,8 @@ static void i965_enable_backlight(struct intel_connector *connector) | |||
809 | I915_WRITE(BLC_PWM_CTL2, ctl2); | 806 | I915_WRITE(BLC_PWM_CTL2, ctl2); |
810 | POSTING_READ(BLC_PWM_CTL2); | 807 | POSTING_READ(BLC_PWM_CTL2); |
811 | I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); | 808 | I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); |
809 | |||
810 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | ||
812 | } | 811 | } |
813 | 812 | ||
814 | static void vlv_enable_backlight(struct intel_connector *connector) | 813 | static void vlv_enable_backlight(struct intel_connector *connector) |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d1e53abec1b5..54242e4f6f4c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -511,8 +511,7 @@ void intel_update_fbc(struct drm_device *dev) | |||
511 | obj = intel_fb->obj; | 511 | obj = intel_fb->obj; |
512 | adjusted_mode = &intel_crtc->config.adjusted_mode; | 512 | adjusted_mode = &intel_crtc->config.adjusted_mode; |
513 | 513 | ||
514 | if (i915.enable_fbc < 0 && | 514 | if (i915.enable_fbc < 0) { |
515 | INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { | ||
516 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) | 515 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
517 | DRM_DEBUG_KMS("disabled per chip default\n"); | 516 | DRM_DEBUG_KMS("disabled per chip default\n"); |
518 | goto out_disable; | 517 | goto out_disable; |
@@ -3506,15 +3505,11 @@ static void gen8_enable_rps(struct drm_device *dev) | |||
3506 | 3505 | ||
3507 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | 3506 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
3508 | 3507 | ||
3509 | /* WaDisablePwrmtrEvent:chv (pre-production hw) */ | ||
3510 | I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); | ||
3511 | I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); | ||
3512 | |||
3513 | /* 5: Enable RPS */ | 3508 | /* 5: Enable RPS */ |
3514 | I915_WRITE(GEN6_RP_CONTROL, | 3509 | I915_WRITE(GEN6_RP_CONTROL, |
3515 | GEN6_RP_MEDIA_TURBO | | 3510 | GEN6_RP_MEDIA_TURBO | |
3516 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | 3511 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
3517 | GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ | 3512 | GEN6_RP_MEDIA_IS_GFX | |
3518 | GEN6_RP_ENABLE | | 3513 | GEN6_RP_ENABLE | |
3519 | GEN6_RP_UP_BUSY_AVG | | 3514 | GEN6_RP_UP_BUSY_AVG | |
3520 | GEN6_RP_DOWN_IDLE_AVG); | 3515 | GEN6_RP_DOWN_IDLE_AVG); |
@@ -6024,30 +6019,32 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, | |||
6024 | static struct i915_power_domains *hsw_pwr; | 6019 | static struct i915_power_domains *hsw_pwr; |
6025 | 6020 | ||
6026 | /* Display audio driver power well request */ | 6021 | /* Display audio driver power well request */ |
6027 | void i915_request_power_well(void) | 6022 | int i915_request_power_well(void) |
6028 | { | 6023 | { |
6029 | struct drm_i915_private *dev_priv; | 6024 | struct drm_i915_private *dev_priv; |
6030 | 6025 | ||
6031 | if (WARN_ON(!hsw_pwr)) | 6026 | if (!hsw_pwr) |
6032 | return; | 6027 | return -ENODEV; |
6033 | 6028 | ||
6034 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, | 6029 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
6035 | power_domains); | 6030 | power_domains); |
6036 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); | 6031 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
6032 | return 0; | ||
6037 | } | 6033 | } |
6038 | EXPORT_SYMBOL_GPL(i915_request_power_well); | 6034 | EXPORT_SYMBOL_GPL(i915_request_power_well); |
6039 | 6035 | ||
6040 | /* Display audio driver power well release */ | 6036 | /* Display audio driver power well release */ |
6041 | void i915_release_power_well(void) | 6037 | int i915_release_power_well(void) |
6042 | { | 6038 | { |
6043 | struct drm_i915_private *dev_priv; | 6039 | struct drm_i915_private *dev_priv; |
6044 | 6040 | ||
6045 | if (WARN_ON(!hsw_pwr)) | 6041 | if (!hsw_pwr) |
6046 | return; | 6042 | return -ENODEV; |
6047 | 6043 | ||
6048 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, | 6044 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
6049 | power_domains); | 6045 | power_domains); |
6050 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | 6046 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
6047 | return 0; | ||
6051 | } | 6048 | } |
6052 | EXPORT_SYMBOL_GPL(i915_release_power_well); | 6049 | EXPORT_SYMBOL_GPL(i915_release_power_well); |
6053 | 6050 | ||
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 910c83cf7d44..e72017bdcd7f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h | |||
@@ -55,7 +55,7 @@ struct intel_ring_hangcheck { | |||
55 | u32 seqno; | 55 | u32 seqno; |
56 | int score; | 56 | int score; |
57 | enum intel_ring_hangcheck_action action; | 57 | enum intel_ring_hangcheck_action action; |
58 | bool deadlock; | 58 | int deadlock; |
59 | }; | 59 | }; |
60 | 60 | ||
61 | struct intel_ringbuffer { | 61 | struct intel_ringbuffer { |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 6a4d5bc17697..20375cc7f82d 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -1385,7 +1385,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, | |||
1385 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; | 1385 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; |
1386 | } | 1386 | } |
1387 | 1387 | ||
1388 | dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier; | 1388 | dotclock = pipe_config->port_clock; |
1389 | if (pipe_config->pixel_multiplier) | ||
1390 | dotclock /= pipe_config->pixel_multiplier; | ||
1389 | 1391 | ||
1390 | if (HAS_PCH_SPLIT(dev)) | 1392 | if (HAS_PCH_SPLIT(dev)) |
1391 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | 1393 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 79cba593df0d..4f6fef7ac069 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c | |||
@@ -320,7 +320,8 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) | |||
320 | struct drm_i915_private *dev_priv = dev->dev_private; | 320 | struct drm_i915_private *dev_priv = dev->dev_private; |
321 | unsigned long irqflags; | 321 | unsigned long irqflags; |
322 | 322 | ||
323 | del_timer_sync(&dev_priv->uncore.force_wake_timer); | 323 | if (del_timer_sync(&dev_priv->uncore.force_wake_timer)) |
324 | gen6_force_wake_timer((unsigned long)dev_priv); | ||
324 | 325 | ||
325 | /* Hold uncore.lock across reset to prevent any register access | 326 | /* Hold uncore.lock across reset to prevent any register access |
326 | * with forcewake not set correctly | 327 | * with forcewake not set correctly |
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index 2b6156d0e4b5..8b307e143632 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -140,6 +140,7 @@ nouveau-y += core/subdev/i2c/nv4e.o | |||
140 | nouveau-y += core/subdev/i2c/nv50.o | 140 | nouveau-y += core/subdev/i2c/nv50.o |
141 | nouveau-y += core/subdev/i2c/nv94.o | 141 | nouveau-y += core/subdev/i2c/nv94.o |
142 | nouveau-y += core/subdev/i2c/nvd0.o | 142 | nouveau-y += core/subdev/i2c/nvd0.o |
143 | nouveau-y += core/subdev/i2c/gf117.o | ||
143 | nouveau-y += core/subdev/i2c/nve0.o | 144 | nouveau-y += core/subdev/i2c/nve0.o |
144 | nouveau-y += core/subdev/ibus/nvc0.o | 145 | nouveau-y += core/subdev/ibus/nvc0.o |
145 | nouveau-y += core/subdev/ibus/nve0.o | 146 | nouveau-y += core/subdev/ibus/nve0.o |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c index f199957995fa..8d55ed633b19 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c | |||
@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device) | |||
314 | device->cname = "GF117"; | 314 | device->cname = "GF117"; |
315 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 315 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
316 | device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; | 316 | device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; |
317 | device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; | 317 | device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; |
318 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 318 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
319 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 319 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
320 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 320 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/core/engine/disp/base.c index c41f656abe64..9c38c5e40500 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/base.c | |||
@@ -99,8 +99,10 @@ _nouveau_disp_dtor(struct nouveau_object *object) | |||
99 | 99 | ||
100 | nouveau_event_destroy(&disp->vblank); | 100 | nouveau_event_destroy(&disp->vblank); |
101 | 101 | ||
102 | list_for_each_entry_safe(outp, outt, &disp->outp, head) { | 102 | if (disp->outp.next) { |
103 | nouveau_object_ref(NULL, (struct nouveau_object **)&outp); | 103 | list_for_each_entry_safe(outp, outt, &disp->outp, head) { |
104 | nouveau_object_ref(NULL, (struct nouveau_object **)&outp); | ||
105 | } | ||
104 | } | 106 | } |
105 | 107 | ||
106 | nouveau_engine_destroy(&disp->base); | 108 | nouveau_engine_destroy(&disp->base); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c index 39562d48101d..5a5b59b21130 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c | |||
@@ -241,7 +241,9 @@ dp_link_train_eq(struct dp_state *dp) | |||
241 | dp_set_training_pattern(dp, 2); | 241 | dp_set_training_pattern(dp, 2); |
242 | 242 | ||
243 | do { | 243 | do { |
244 | if (dp_link_train_update(dp, dp->pc2, 400)) | 244 | if ((tries && |
245 | dp_link_train_commit(dp, dp->pc2)) || | ||
246 | dp_link_train_update(dp, dp->pc2, 400)) | ||
245 | break; | 247 | break; |
246 | 248 | ||
247 | eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); | 249 | eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); |
@@ -253,9 +255,6 @@ dp_link_train_eq(struct dp_state *dp) | |||
253 | !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) | 255 | !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) |
254 | eq_done = false; | 256 | eq_done = false; |
255 | } | 257 | } |
256 | |||
257 | if (dp_link_train_commit(dp, dp->pc2)) | ||
258 | break; | ||
259 | } while (!eq_done && cr_done && ++tries <= 5); | 258 | } while (!eq_done && cr_done && ++tries <= 5); |
260 | 259 | ||
261 | return eq_done ? 0 : -1; | 260 | return eq_done ? 0 : -1; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 1e85f36c705f..26e962b7e702 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | |||
@@ -1270,7 +1270,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) | |||
1270 | i--; | 1270 | i--; |
1271 | 1271 | ||
1272 | outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); | 1272 | outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); |
1273 | if (!data) | 1273 | if (!outp) |
1274 | return NULL; | 1274 | return NULL; |
1275 | 1275 | ||
1276 | if (outp->info.location == 0) { | 1276 | if (outp->info.location == 0) { |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc index 2f7345f7fe07..7445f12b1d9e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc | |||
@@ -54,7 +54,7 @@ mmio_list_base: | |||
54 | #ifdef INCLUDE_CODE | 54 | #ifdef INCLUDE_CODE |
55 | // reports an exception to the host | 55 | // reports an exception to the host |
56 | // | 56 | // |
57 | // In: $r15 error code (see nvc0.fuc) | 57 | // In: $r15 error code (see os.h) |
58 | // | 58 | // |
59 | error: | 59 | error: |
60 | push $r14 | 60 | push $r14 |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc index c8ddb8d71b91..b4ad18bf5a26 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc | |||
@@ -49,7 +49,7 @@ hub_mmio_list_next: | |||
49 | #ifdef INCLUDE_CODE | 49 | #ifdef INCLUDE_CODE |
50 | // reports an exception to the host | 50 | // reports an exception to the host |
51 | // | 51 | // |
52 | // In: $r15 error code (see nvc0.fuc) | 52 | // In: $r15 error code (see os.h) |
53 | // | 53 | // |
54 | error: | 54 | error: |
55 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) | 55 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) |
@@ -343,13 +343,25 @@ ih: | |||
343 | ih_no_ctxsw: | 343 | ih_no_ctxsw: |
344 | and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD | 344 | and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD |
345 | bra e #ih_no_fwmthd | 345 | bra e #ih_no_fwmthd |
346 | // none we handle, ack, and fall-through to unhandled | 346 | // none we handle; report to host and ack |
347 | nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO) | ||
348 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15) | ||
349 | nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR) | ||
350 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15) | ||
351 | extr $r14 $r15 16:18 | ||
352 | shl b32 $r14 $r14 2 | ||
353 | imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0)) | ||
354 | add b32 $r14 $r15 | ||
355 | call(nv_rd32) | ||
356 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15) | ||
357 | mov $r15 E_BAD_FWMTHD | ||
358 | call(error) | ||
347 | mov $r11 0x100 | 359 | mov $r11 0x100 |
348 | nv_wr32(0x400144, $r11) | 360 | nv_wr32(0x400144, $r11) |
349 | 361 | ||
350 | // anything we didn't handle, bring it to the host's attention | 362 | // anything we didn't handle, bring it to the host's attention |
351 | ih_no_fwmthd: | 363 | ih_no_fwmthd: |
352 | mov $r11 0x104 // FIFO | CHSW | 364 | mov $r11 0x504 // FIFO | CHSW | FWMTHD |
353 | not b32 $r11 | 365 | not b32 $r11 |
354 | and $r11 $r10 $r11 | 366 | and $r11 $r10 $r11 |
355 | bra e #ih_no_other | 367 | bra e #ih_no_other |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h index 214dd16ec566..5f953c5c20b7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h | |||
@@ -478,10 +478,10 @@ uint32_t gm107_grhub_code[] = { | |||
478 | 0x01040080, | 478 | 0x01040080, |
479 | 0xbd0001f6, | 479 | 0xbd0001f6, |
480 | 0x01004104, | 480 | 0x01004104, |
481 | 0x627e020f, | 481 | 0xa87e020f, |
482 | 0x717e0006, | 482 | 0xb77e0006, |
483 | 0x100f0006, | 483 | 0x100f0006, |
484 | 0x0006b37e, | 484 | 0x0006f97e, |
485 | 0x98000e98, | 485 | 0x98000e98, |
486 | 0x207e010f, | 486 | 0x207e010f, |
487 | 0x14950001, | 487 | 0x14950001, |
@@ -523,8 +523,8 @@ uint32_t gm107_grhub_code[] = { | |||
523 | 0x800040b7, | 523 | 0x800040b7, |
524 | 0xf40132b6, | 524 | 0xf40132b6, |
525 | 0x000fb41b, | 525 | 0x000fb41b, |
526 | 0x0006b37e, | 526 | 0x0006f97e, |
527 | 0x627e000f, | 527 | 0xa87e000f, |
528 | 0x00800006, | 528 | 0x00800006, |
529 | 0x01f60201, | 529 | 0x01f60201, |
530 | 0xbd04bd00, | 530 | 0xbd04bd00, |
@@ -554,7 +554,7 @@ uint32_t gm107_grhub_code[] = { | |||
554 | 0x0009f602, | 554 | 0x0009f602, |
555 | 0x32f404bd, | 555 | 0x32f404bd, |
556 | 0x0231f401, | 556 | 0x0231f401, |
557 | 0x0008367e, | 557 | 0x00087c7e, |
558 | 0x99f094bd, | 558 | 0x99f094bd, |
559 | 0x17008007, | 559 | 0x17008007, |
560 | 0x0009f602, | 560 | 0x0009f602, |
@@ -563,7 +563,7 @@ uint32_t gm107_grhub_code[] = { | |||
563 | 0x37008006, | 563 | 0x37008006, |
564 | 0x0009f602, | 564 | 0x0009f602, |
565 | 0x31f404bd, | 565 | 0x31f404bd, |
566 | 0x08367e01, | 566 | 0x087c7e01, |
567 | 0xf094bd00, | 567 | 0xf094bd00, |
568 | 0x00800699, | 568 | 0x00800699, |
569 | 0x09f60217, | 569 | 0x09f60217, |
@@ -572,7 +572,7 @@ uint32_t gm107_grhub_code[] = { | |||
572 | 0x20f92f0e, | 572 | 0x20f92f0e, |
573 | 0x32f412b2, | 573 | 0x32f412b2, |
574 | 0x0232f401, | 574 | 0x0232f401, |
575 | 0x0008367e, | 575 | 0x00087c7e, |
576 | 0x008020fc, | 576 | 0x008020fc, |
577 | 0x02f602c0, | 577 | 0x02f602c0, |
578 | 0xf404bd00, | 578 | 0xf404bd00, |
@@ -580,7 +580,7 @@ uint32_t gm107_grhub_code[] = { | |||
580 | 0x23c8130e, | 580 | 0x23c8130e, |
581 | 0x0d0bf41f, | 581 | 0x0d0bf41f, |
582 | 0xf40131f4, | 582 | 0xf40131f4, |
583 | 0x367e0232, | 583 | 0x7c7e0232, |
584 | /* 0x054e: chsw_done */ | 584 | /* 0x054e: chsw_done */ |
585 | 0x01020008, | 585 | 0x01020008, |
586 | 0x02c30080, | 586 | 0x02c30080, |
@@ -593,7 +593,7 @@ uint32_t gm107_grhub_code[] = { | |||
593 | 0xb0ff2a0e, | 593 | 0xb0ff2a0e, |
594 | 0x1bf401e4, | 594 | 0x1bf401e4, |
595 | 0x7ef2b20c, | 595 | 0x7ef2b20c, |
596 | 0xf40007d6, | 596 | 0xf400081c, |
597 | /* 0x057a: main_not_ctx_chan */ | 597 | /* 0x057a: main_not_ctx_chan */ |
598 | 0xe4b0400e, | 598 | 0xe4b0400e, |
599 | 0x2c1bf402, | 599 | 0x2c1bf402, |
@@ -602,7 +602,7 @@ uint32_t gm107_grhub_code[] = { | |||
602 | 0x0009f602, | 602 | 0x0009f602, |
603 | 0x32f404bd, | 603 | 0x32f404bd, |
604 | 0x0232f401, | 604 | 0x0232f401, |
605 | 0x0008367e, | 605 | 0x00087c7e, |
606 | 0x99f094bd, | 606 | 0x99f094bd, |
607 | 0x17008007, | 607 | 0x17008007, |
608 | 0x0009f602, | 608 | 0x0009f602, |
@@ -642,238 +642,238 @@ uint32_t gm107_grhub_code[] = { | |||
642 | /* 0x061a: ih_no_ctxsw */ | 642 | /* 0x061a: ih_no_ctxsw */ |
643 | 0xabe40000, | 643 | 0xabe40000, |
644 | 0x0bf40400, | 644 | 0x0bf40400, |
645 | 0x01004b10, | 645 | 0x07088e56, |
646 | 0x448ebfb2, | ||
647 | 0x8f7e4001, | ||
648 | /* 0x062e: ih_no_fwmthd */ | ||
649 | 0x044b0000, | ||
650 | 0xffb0bd01, | ||
651 | 0x0bf4b4ab, | ||
652 | 0x0700800c, | ||
653 | 0x000bf603, | ||
654 | /* 0x0642: ih_no_other */ | ||
655 | 0x004004bd, | ||
656 | 0x000af601, | ||
657 | 0xf0fc04bd, | ||
658 | 0xd0fce0fc, | ||
659 | 0xa0fcb0fc, | ||
660 | 0x80fc90fc, | ||
661 | 0xfc0088fe, | ||
662 | 0x0032f480, | ||
663 | /* 0x0662: ctx_4170s */ | ||
664 | 0xf5f001f8, | ||
665 | 0x8effb210, | ||
666 | 0x7e404170, | ||
667 | 0xf800008f, | ||
668 | /* 0x0671: ctx_4170w */ | ||
669 | 0x41708e00, | ||
670 | 0x00657e40, | 646 | 0x00657e40, |
671 | 0xf0ffb200, | 647 | 0x80ffb200, |
672 | 0x1bf410f4, | 648 | 0xf6020400, |
673 | /* 0x0683: ctx_redswitch */ | ||
674 | 0x4e00f8f3, | ||
675 | 0xe5f00200, | ||
676 | 0x20e5f040, | ||
677 | 0x8010e5f0, | ||
678 | 0xf6018500, | ||
679 | 0x04bd000e, | ||
680 | /* 0x069a: ctx_redswitch_delay */ | ||
681 | 0xf2b6080f, | ||
682 | 0xfd1bf401, | ||
683 | 0x0400e5f1, | ||
684 | 0x0100e5f1, | ||
685 | 0x01850080, | ||
686 | 0xbd000ef6, | ||
687 | /* 0x06b3: ctx_86c */ | ||
688 | 0x8000f804, | ||
689 | 0xf6022300, | ||
690 | 0x04bd000f, | 649 | 0x04bd000f, |
691 | 0x148effb2, | 650 | 0x4007048e, |
692 | 0x8f7e408a, | 651 | 0x0000657e, |
693 | 0xffb20000, | 652 | 0x0080ffb2, |
694 | 0x41a88c8e, | 653 | 0x0ff60203, |
654 | 0xc704bd00, | ||
655 | 0xee9450fe, | ||
656 | 0x07008f02, | ||
657 | 0x00efbb40, | ||
658 | 0x0000657e, | ||
659 | 0x02020080, | ||
660 | 0xbd000ff6, | ||
661 | 0x7e030f04, | ||
662 | 0x4b0002f8, | ||
663 | 0xbfb20100, | ||
664 | 0x4001448e, | ||
695 | 0x00008f7e, | 665 | 0x00008f7e, |
696 | /* 0x06d2: ctx_mem */ | 666 | /* 0x0674: ih_no_fwmthd */ |
697 | 0x008000f8, | 667 | 0xbd05044b, |
698 | 0x0ff60284, | 668 | 0xb4abffb0, |
699 | /* 0x06db: ctx_mem_wait */ | 669 | 0x800c0bf4, |
700 | 0x8f04bd00, | 670 | 0xf6030700, |
701 | 0xcf028400, | 671 | 0x04bd000b, |
702 | 0xfffd00ff, | 672 | /* 0x0688: ih_no_other */ |
703 | 0xf61bf405, | 673 | 0xf6010040, |
704 | /* 0x06ea: ctx_load */ | 674 | 0x04bd000a, |
705 | 0x94bd00f8, | 675 | 0xe0fcf0fc, |
706 | 0x800599f0, | 676 | 0xb0fcd0fc, |
707 | 0xf6023700, | 677 | 0x90fca0fc, |
708 | 0x04bd0009, | 678 | 0x88fe80fc, |
709 | 0xb87e0c0a, | 679 | 0xf480fc00, |
710 | 0xf4bd0000, | 680 | 0x01f80032, |
711 | 0x02890080, | 681 | /* 0x06a8: ctx_4170s */ |
682 | 0xb210f5f0, | ||
683 | 0x41708eff, | ||
684 | 0x008f7e40, | ||
685 | /* 0x06b7: ctx_4170w */ | ||
686 | 0x8e00f800, | ||
687 | 0x7e404170, | ||
688 | 0xb2000065, | ||
689 | 0x10f4f0ff, | ||
690 | 0xf8f31bf4, | ||
691 | /* 0x06c9: ctx_redswitch */ | ||
692 | 0x02004e00, | ||
693 | 0xf040e5f0, | ||
694 | 0xe5f020e5, | ||
695 | 0x85008010, | ||
696 | 0x000ef601, | ||
697 | 0x080f04bd, | ||
698 | /* 0x06e0: ctx_redswitch_delay */ | ||
699 | 0xf401f2b6, | ||
700 | 0xe5f1fd1b, | ||
701 | 0xe5f10400, | ||
702 | 0x00800100, | ||
703 | 0x0ef60185, | ||
704 | 0xf804bd00, | ||
705 | /* 0x06f9: ctx_86c */ | ||
706 | 0x23008000, | ||
707 | 0x000ff602, | ||
708 | 0xffb204bd, | ||
709 | 0x408a148e, | ||
710 | 0x00008f7e, | ||
711 | 0x8c8effb2, | ||
712 | 0x8f7e41a8, | ||
713 | 0x00f80000, | ||
714 | /* 0x0718: ctx_mem */ | ||
715 | 0x02840080, | ||
712 | 0xbd000ff6, | 716 | 0xbd000ff6, |
713 | 0xc1008004, | 717 | /* 0x0721: ctx_mem_wait */ |
714 | 0x0002f602, | 718 | 0x84008f04, |
715 | 0x008004bd, | 719 | 0x00ffcf02, |
716 | 0x02f60283, | 720 | 0xf405fffd, |
717 | 0x0f04bd00, | 721 | 0x00f8f61b, |
718 | 0x06d27e07, | 722 | /* 0x0730: ctx_load */ |
719 | 0xc0008000, | 723 | 0x99f094bd, |
720 | 0x0002f602, | 724 | 0x37008005, |
721 | 0x0bfe04bd, | 725 | 0x0009f602, |
722 | 0x1f2af000, | 726 | 0x0c0a04bd, |
723 | 0xb60424b6, | 727 | 0x0000b87e, |
724 | 0x94bd0220, | 728 | 0x0080f4bd, |
725 | 0x800899f0, | 729 | 0x0ff60289, |
726 | 0xf6023700, | 730 | 0x8004bd00, |
727 | 0x04bd0009, | 731 | 0xf602c100, |
728 | 0x02810080, | 732 | 0x04bd0002, |
729 | 0xbd0002f6, | 733 | 0x02830080, |
730 | 0x0000d204, | ||
731 | 0x25f08000, | ||
732 | 0x88008002, | ||
733 | 0x0002f602, | ||
734 | 0x100104bd, | ||
735 | 0xf0020042, | ||
736 | 0x12fa0223, | ||
737 | 0xbd03f805, | ||
738 | 0x0899f094, | ||
739 | 0x02170080, | ||
740 | 0xbd0009f6, | ||
741 | 0x81019804, | ||
742 | 0x981814b6, | ||
743 | 0x25b68002, | ||
744 | 0x0512fd08, | ||
745 | 0xbd1601b5, | ||
746 | 0x0999f094, | ||
747 | 0x02370080, | ||
748 | 0xbd0009f6, | ||
749 | 0x81008004, | ||
750 | 0x0001f602, | ||
751 | 0x010204bd, | ||
752 | 0x02880080, | ||
753 | 0xbd0002f6, | 734 | 0xbd0002f6, |
754 | 0x01004104, | 735 | 0x7e070f04, |
755 | 0xfa0613f0, | 736 | 0x80000718, |
756 | 0x03f80501, | 737 | 0xf602c000, |
738 | 0x04bd0002, | ||
739 | 0xf0000bfe, | ||
740 | 0x24b61f2a, | ||
741 | 0x0220b604, | ||
757 | 0x99f094bd, | 742 | 0x99f094bd, |
758 | 0x17008009, | 743 | 0x37008008, |
759 | 0x0009f602, | 744 | 0x0009f602, |
760 | 0x94bd04bd, | 745 | 0x008004bd, |
761 | 0x800599f0, | 746 | 0x02f60281, |
747 | 0xd204bd00, | ||
748 | 0x80000000, | ||
749 | 0x800225f0, | ||
750 | 0xf6028800, | ||
751 | 0x04bd0002, | ||
752 | 0x00421001, | ||
753 | 0x0223f002, | ||
754 | 0xf80512fa, | ||
755 | 0xf094bd03, | ||
756 | 0x00800899, | ||
757 | 0x09f60217, | ||
758 | 0x9804bd00, | ||
759 | 0x14b68101, | ||
760 | 0x80029818, | ||
761 | 0xfd0825b6, | ||
762 | 0x01b50512, | ||
763 | 0xf094bd16, | ||
764 | 0x00800999, | ||
765 | 0x09f60237, | ||
766 | 0x8004bd00, | ||
767 | 0xf6028100, | ||
768 | 0x04bd0001, | ||
769 | 0x00800102, | ||
770 | 0x02f60288, | ||
771 | 0x4104bd00, | ||
772 | 0x13f00100, | ||
773 | 0x0501fa06, | ||
774 | 0x94bd03f8, | ||
775 | 0x800999f0, | ||
762 | 0xf6021700, | 776 | 0xf6021700, |
763 | 0x04bd0009, | 777 | 0x04bd0009, |
764 | /* 0x07d6: ctx_chan */ | 778 | 0x99f094bd, |
765 | 0xea7e00f8, | 779 | 0x17008005, |
766 | 0x0c0a0006, | 780 | 0x0009f602, |
767 | 0x0000b87e, | 781 | 0x00f804bd, |
768 | 0xd27e050f, | 782 | /* 0x081c: ctx_chan */ |
769 | 0x00f80006, | 783 | 0x0007307e, |
770 | /* 0x07e8: ctx_mmio_exec */ | 784 | 0xb87e0c0a, |
771 | 0x80410398, | 785 | 0x050f0000, |
786 | 0x0007187e, | ||
787 | /* 0x082e: ctx_mmio_exec */ | ||
788 | 0x039800f8, | ||
789 | 0x81008041, | ||
790 | 0x0003f602, | ||
791 | 0x34bd04bd, | ||
792 | /* 0x083c: ctx_mmio_loop */ | ||
793 | 0xf4ff34c4, | ||
794 | 0x00450e1b, | ||
795 | 0x0653f002, | ||
796 | 0xf80535fa, | ||
797 | /* 0x084d: ctx_mmio_pull */ | ||
798 | 0x804e9803, | ||
799 | 0x7e814f98, | ||
800 | 0xb600008f, | ||
801 | 0x12b60830, | ||
802 | 0xdf1bf401, | ||
803 | /* 0x0860: ctx_mmio_done */ | ||
804 | 0x80160398, | ||
772 | 0xf6028100, | 805 | 0xf6028100, |
773 | 0x04bd0003, | 806 | 0x04bd0003, |
774 | /* 0x07f6: ctx_mmio_loop */ | 807 | 0x414000b5, |
775 | 0x34c434bd, | 808 | 0x13f00100, |
776 | 0x0e1bf4ff, | 809 | 0x0601fa06, |
777 | 0xf0020045, | 810 | 0x00f803f8, |
778 | 0x35fa0653, | 811 | /* 0x087c: ctx_xfer */ |
779 | /* 0x0807: ctx_mmio_pull */ | 812 | 0x0080040e, |
780 | 0x9803f805, | 813 | 0x0ef60302, |
781 | 0x4f98804e, | 814 | /* 0x0887: ctx_xfer_idle */ |
782 | 0x008f7e81, | 815 | 0x8e04bd00, |
783 | 0x0830b600, | 816 | 0xcf030000, |
784 | 0xf40112b6, | 817 | 0xe4f100ee, |
785 | /* 0x081a: ctx_mmio_done */ | 818 | 0x1bf42000, |
786 | 0x0398df1b, | 819 | 0x0611f4f5, |
787 | 0x81008016, | 820 | /* 0x089b: ctx_xfer_pre */ |
788 | 0x0003f602, | 821 | 0x0f0c02f4, |
789 | 0x00b504bd, | 822 | 0x06f97e10, |
790 | 0x01004140, | 823 | 0x1b11f400, |
791 | 0xfa0613f0, | 824 | /* 0x08a4: ctx_xfer_pre_load */ |
792 | 0x03f80601, | 825 | 0xa87e020f, |
793 | /* 0x0836: ctx_xfer */ | 826 | 0xb77e0006, |
794 | 0x040e00f8, | 827 | 0xc97e0006, |
795 | 0x03020080, | 828 | 0xf4bd0006, |
796 | 0xbd000ef6, | 829 | 0x0006a87e, |
797 | /* 0x0841: ctx_xfer_idle */ | 830 | 0x0007307e, |
798 | 0x00008e04, | 831 | /* 0x08bc: ctx_xfer_exec */ |
799 | 0x00eecf03, | 832 | 0xbd160198, |
800 | 0x2000e4f1, | 833 | 0x05008024, |
801 | 0xf4f51bf4, | 834 | 0x0002f601, |
802 | 0x02f40611, | 835 | 0x1fb204bd, |
803 | /* 0x0855: ctx_xfer_pre */ | 836 | 0x41a5008e, |
804 | 0x7e100f0c, | ||
805 | 0xf40006b3, | ||
806 | /* 0x085e: ctx_xfer_pre_load */ | ||
807 | 0x020f1b11, | ||
808 | 0x0006627e, | ||
809 | 0x0006717e, | ||
810 | 0x0006837e, | ||
811 | 0x627ef4bd, | ||
812 | 0xea7e0006, | ||
813 | /* 0x0876: ctx_xfer_exec */ | ||
814 | 0x01980006, | ||
815 | 0x8024bd16, | ||
816 | 0xf6010500, | ||
817 | 0x04bd0002, | ||
818 | 0x008e1fb2, | ||
819 | 0x8f7e41a5, | ||
820 | 0xfcf00000, | ||
821 | 0x022cf001, | ||
822 | 0xfd0124b6, | ||
823 | 0xffb205f2, | ||
824 | 0x41a5048e, | ||
825 | 0x00008f7e, | 837 | 0x00008f7e, |
826 | 0x0002167e, | 838 | 0xf001fcf0, |
827 | 0xfc8024bd, | 839 | 0x24b6022c, |
828 | 0x02f60247, | 840 | 0x05f2fd01, |
829 | 0xf004bd00, | 841 | 0x048effb2, |
830 | 0x20b6012c, | 842 | 0x8f7e41a5, |
831 | 0x4afc8003, | 843 | 0x167e0000, |
832 | 0x0002f602, | 844 | 0x24bd0002, |
833 | 0xacf004bd, | 845 | 0x0247fc80, |
834 | 0x06a5f001, | 846 | 0xbd0002f6, |
835 | 0x0c98000b, | 847 | 0x012cf004, |
836 | 0x010d9800, | 848 | 0x800320b6, |
837 | 0x3d7e000e, | 849 | 0xf6024afc, |
838 | 0x080a0001, | 850 | 0x04bd0002, |
839 | 0x0000ec7e, | 851 | 0xf001acf0, |
840 | 0x00020a7e, | 852 | 0x000b06a5, |
841 | 0x0a1201f4, | 853 | 0x98000c98, |
842 | 0x00b87e0c, | 854 | 0x000e010d, |
843 | 0x7e050f00, | 855 | 0x00013d7e, |
844 | 0xf40006d2, | 856 | 0xec7e080a, |
845 | /* 0x08f2: ctx_xfer_post */ | 857 | 0x0a7e0000, |
846 | 0x020f2d02, | 858 | 0x01f40002, |
847 | 0x0006627e, | 859 | 0x7e0c0a12, |
848 | 0xb37ef4bd, | 860 | 0x0f0000b8, |
849 | 0x277e0006, | 861 | 0x07187e05, |
850 | 0x717e0002, | 862 | 0x2d02f400, |
863 | /* 0x0938: ctx_xfer_post */ | ||
864 | 0xa87e020f, | ||
851 | 0xf4bd0006, | 865 | 0xf4bd0006, |
852 | 0x0006627e, | 866 | 0x0006f97e, |
853 | 0x981011f4, | 867 | 0x0002277e, |
854 | 0x11fd4001, | 868 | 0x0006b77e, |
855 | 0x070bf405, | 869 | 0xa87ef4bd, |
856 | 0x0007e87e, | 870 | 0x11f40006, |
857 | /* 0x091c: ctx_xfer_no_post_mmio */ | 871 | 0x40019810, |
858 | /* 0x091c: ctx_xfer_done */ | 872 | 0xf40511fd, |
859 | 0x000000f8, | 873 | 0x2e7e070b, |
860 | 0x00000000, | 874 | /* 0x0962: ctx_xfer_no_post_mmio */ |
861 | 0x00000000, | 875 | /* 0x0962: ctx_xfer_done */ |
862 | 0x00000000, | 876 | 0x00f80008, |
863 | 0x00000000, | ||
864 | 0x00000000, | ||
865 | 0x00000000, | ||
866 | 0x00000000, | ||
867 | 0x00000000, | ||
868 | 0x00000000, | ||
869 | 0x00000000, | ||
870 | 0x00000000, | ||
871 | 0x00000000, | ||
872 | 0x00000000, | ||
873 | 0x00000000, | ||
874 | 0x00000000, | ||
875 | 0x00000000, | ||
876 | 0x00000000, | ||
877 | 0x00000000, | 877 | 0x00000000, |
878 | 0x00000000, | 878 | 0x00000000, |
879 | 0x00000000, | 879 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h index 64dfd75192bf..e49b5a877ae4 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h | |||
@@ -478,10 +478,10 @@ uint32_t nv108_grhub_code[] = { | |||
478 | 0x01040080, | 478 | 0x01040080, |
479 | 0xbd0001f6, | 479 | 0xbd0001f6, |
480 | 0x01004104, | 480 | 0x01004104, |
481 | 0x627e020f, | 481 | 0xa87e020f, |
482 | 0x717e0006, | 482 | 0xb77e0006, |
483 | 0x100f0006, | 483 | 0x100f0006, |
484 | 0x0006b37e, | 484 | 0x0006f97e, |
485 | 0x98000e98, | 485 | 0x98000e98, |
486 | 0x207e010f, | 486 | 0x207e010f, |
487 | 0x14950001, | 487 | 0x14950001, |
@@ -523,8 +523,8 @@ uint32_t nv108_grhub_code[] = { | |||
523 | 0x800040b7, | 523 | 0x800040b7, |
524 | 0xf40132b6, | 524 | 0xf40132b6, |
525 | 0x000fb41b, | 525 | 0x000fb41b, |
526 | 0x0006b37e, | 526 | 0x0006f97e, |
527 | 0x627e000f, | 527 | 0xa87e000f, |
528 | 0x00800006, | 528 | 0x00800006, |
529 | 0x01f60201, | 529 | 0x01f60201, |
530 | 0xbd04bd00, | 530 | 0xbd04bd00, |
@@ -554,7 +554,7 @@ uint32_t nv108_grhub_code[] = { | |||
554 | 0x0009f602, | 554 | 0x0009f602, |
555 | 0x32f404bd, | 555 | 0x32f404bd, |
556 | 0x0231f401, | 556 | 0x0231f401, |
557 | 0x0008367e, | 557 | 0x00087c7e, |
558 | 0x99f094bd, | 558 | 0x99f094bd, |
559 | 0x17008007, | 559 | 0x17008007, |
560 | 0x0009f602, | 560 | 0x0009f602, |
@@ -563,7 +563,7 @@ uint32_t nv108_grhub_code[] = { | |||
563 | 0x37008006, | 563 | 0x37008006, |
564 | 0x0009f602, | 564 | 0x0009f602, |
565 | 0x31f404bd, | 565 | 0x31f404bd, |
566 | 0x08367e01, | 566 | 0x087c7e01, |
567 | 0xf094bd00, | 567 | 0xf094bd00, |
568 | 0x00800699, | 568 | 0x00800699, |
569 | 0x09f60217, | 569 | 0x09f60217, |
@@ -572,7 +572,7 @@ uint32_t nv108_grhub_code[] = { | |||
572 | 0x20f92f0e, | 572 | 0x20f92f0e, |
573 | 0x32f412b2, | 573 | 0x32f412b2, |
574 | 0x0232f401, | 574 | 0x0232f401, |
575 | 0x0008367e, | 575 | 0x00087c7e, |
576 | 0x008020fc, | 576 | 0x008020fc, |
577 | 0x02f602c0, | 577 | 0x02f602c0, |
578 | 0xf404bd00, | 578 | 0xf404bd00, |
@@ -580,7 +580,7 @@ uint32_t nv108_grhub_code[] = { | |||
580 | 0x23c8130e, | 580 | 0x23c8130e, |
581 | 0x0d0bf41f, | 581 | 0x0d0bf41f, |
582 | 0xf40131f4, | 582 | 0xf40131f4, |
583 | 0x367e0232, | 583 | 0x7c7e0232, |
584 | /* 0x054e: chsw_done */ | 584 | /* 0x054e: chsw_done */ |
585 | 0x01020008, | 585 | 0x01020008, |
586 | 0x02c30080, | 586 | 0x02c30080, |
@@ -593,7 +593,7 @@ uint32_t nv108_grhub_code[] = { | |||
593 | 0xb0ff2a0e, | 593 | 0xb0ff2a0e, |
594 | 0x1bf401e4, | 594 | 0x1bf401e4, |
595 | 0x7ef2b20c, | 595 | 0x7ef2b20c, |
596 | 0xf40007d6, | 596 | 0xf400081c, |
597 | /* 0x057a: main_not_ctx_chan */ | 597 | /* 0x057a: main_not_ctx_chan */ |
598 | 0xe4b0400e, | 598 | 0xe4b0400e, |
599 | 0x2c1bf402, | 599 | 0x2c1bf402, |
@@ -602,7 +602,7 @@ uint32_t nv108_grhub_code[] = { | |||
602 | 0x0009f602, | 602 | 0x0009f602, |
603 | 0x32f404bd, | 603 | 0x32f404bd, |
604 | 0x0232f401, | 604 | 0x0232f401, |
605 | 0x0008367e, | 605 | 0x00087c7e, |
606 | 0x99f094bd, | 606 | 0x99f094bd, |
607 | 0x17008007, | 607 | 0x17008007, |
608 | 0x0009f602, | 608 | 0x0009f602, |
@@ -642,238 +642,238 @@ uint32_t nv108_grhub_code[] = { | |||
642 | /* 0x061a: ih_no_ctxsw */ | 642 | /* 0x061a: ih_no_ctxsw */ |
643 | 0xabe40000, | 643 | 0xabe40000, |
644 | 0x0bf40400, | 644 | 0x0bf40400, |
645 | 0x01004b10, | 645 | 0x07088e56, |
646 | 0x448ebfb2, | ||
647 | 0x8f7e4001, | ||
648 | /* 0x062e: ih_no_fwmthd */ | ||
649 | 0x044b0000, | ||
650 | 0xffb0bd01, | ||
651 | 0x0bf4b4ab, | ||
652 | 0x0700800c, | ||
653 | 0x000bf603, | ||
654 | /* 0x0642: ih_no_other */ | ||
655 | 0x004004bd, | ||
656 | 0x000af601, | ||
657 | 0xf0fc04bd, | ||
658 | 0xd0fce0fc, | ||
659 | 0xa0fcb0fc, | ||
660 | 0x80fc90fc, | ||
661 | 0xfc0088fe, | ||
662 | 0x0032f480, | ||
663 | /* 0x0662: ctx_4170s */ | ||
664 | 0xf5f001f8, | ||
665 | 0x8effb210, | ||
666 | 0x7e404170, | ||
667 | 0xf800008f, | ||
668 | /* 0x0671: ctx_4170w */ | ||
669 | 0x41708e00, | ||
670 | 0x00657e40, | 646 | 0x00657e40, |
671 | 0xf0ffb200, | 647 | 0x80ffb200, |
672 | 0x1bf410f4, | 648 | 0xf6020400, |
673 | /* 0x0683: ctx_redswitch */ | ||
674 | 0x4e00f8f3, | ||
675 | 0xe5f00200, | ||
676 | 0x20e5f040, | ||
677 | 0x8010e5f0, | ||
678 | 0xf6018500, | ||
679 | 0x04bd000e, | ||
680 | /* 0x069a: ctx_redswitch_delay */ | ||
681 | 0xf2b6080f, | ||
682 | 0xfd1bf401, | ||
683 | 0x0400e5f1, | ||
684 | 0x0100e5f1, | ||
685 | 0x01850080, | ||
686 | 0xbd000ef6, | ||
687 | /* 0x06b3: ctx_86c */ | ||
688 | 0x8000f804, | ||
689 | 0xf6022300, | ||
690 | 0x04bd000f, | 649 | 0x04bd000f, |
691 | 0x148effb2, | 650 | 0x4007048e, |
692 | 0x8f7e408a, | 651 | 0x0000657e, |
693 | 0xffb20000, | 652 | 0x0080ffb2, |
694 | 0x41a88c8e, | 653 | 0x0ff60203, |
654 | 0xc704bd00, | ||
655 | 0xee9450fe, | ||
656 | 0x07008f02, | ||
657 | 0x00efbb40, | ||
658 | 0x0000657e, | ||
659 | 0x02020080, | ||
660 | 0xbd000ff6, | ||
661 | 0x7e030f04, | ||
662 | 0x4b0002f8, | ||
663 | 0xbfb20100, | ||
664 | 0x4001448e, | ||
695 | 0x00008f7e, | 665 | 0x00008f7e, |
696 | /* 0x06d2: ctx_mem */ | 666 | /* 0x0674: ih_no_fwmthd */ |
697 | 0x008000f8, | 667 | 0xbd05044b, |
698 | 0x0ff60284, | 668 | 0xb4abffb0, |
699 | /* 0x06db: ctx_mem_wait */ | 669 | 0x800c0bf4, |
700 | 0x8f04bd00, | 670 | 0xf6030700, |
701 | 0xcf028400, | 671 | 0x04bd000b, |
702 | 0xfffd00ff, | 672 | /* 0x0688: ih_no_other */ |
703 | 0xf61bf405, | 673 | 0xf6010040, |
704 | /* 0x06ea: ctx_load */ | 674 | 0x04bd000a, |
705 | 0x94bd00f8, | 675 | 0xe0fcf0fc, |
706 | 0x800599f0, | 676 | 0xb0fcd0fc, |
707 | 0xf6023700, | 677 | 0x90fca0fc, |
708 | 0x04bd0009, | 678 | 0x88fe80fc, |
709 | 0xb87e0c0a, | 679 | 0xf480fc00, |
710 | 0xf4bd0000, | 680 | 0x01f80032, |
711 | 0x02890080, | 681 | /* 0x06a8: ctx_4170s */ |
682 | 0xb210f5f0, | ||
683 | 0x41708eff, | ||
684 | 0x008f7e40, | ||
685 | /* 0x06b7: ctx_4170w */ | ||
686 | 0x8e00f800, | ||
687 | 0x7e404170, | ||
688 | 0xb2000065, | ||
689 | 0x10f4f0ff, | ||
690 | 0xf8f31bf4, | ||
691 | /* 0x06c9: ctx_redswitch */ | ||
692 | 0x02004e00, | ||
693 | 0xf040e5f0, | ||
694 | 0xe5f020e5, | ||
695 | 0x85008010, | ||
696 | 0x000ef601, | ||
697 | 0x080f04bd, | ||
698 | /* 0x06e0: ctx_redswitch_delay */ | ||
699 | 0xf401f2b6, | ||
700 | 0xe5f1fd1b, | ||
701 | 0xe5f10400, | ||
702 | 0x00800100, | ||
703 | 0x0ef60185, | ||
704 | 0xf804bd00, | ||
705 | /* 0x06f9: ctx_86c */ | ||
706 | 0x23008000, | ||
707 | 0x000ff602, | ||
708 | 0xffb204bd, | ||
709 | 0x408a148e, | ||
710 | 0x00008f7e, | ||
711 | 0x8c8effb2, | ||
712 | 0x8f7e41a8, | ||
713 | 0x00f80000, | ||
714 | /* 0x0718: ctx_mem */ | ||
715 | 0x02840080, | ||
712 | 0xbd000ff6, | 716 | 0xbd000ff6, |
713 | 0xc1008004, | 717 | /* 0x0721: ctx_mem_wait */ |
714 | 0x0002f602, | 718 | 0x84008f04, |
715 | 0x008004bd, | 719 | 0x00ffcf02, |
716 | 0x02f60283, | 720 | 0xf405fffd, |
717 | 0x0f04bd00, | 721 | 0x00f8f61b, |
718 | 0x06d27e07, | 722 | /* 0x0730: ctx_load */ |
719 | 0xc0008000, | 723 | 0x99f094bd, |
720 | 0x0002f602, | 724 | 0x37008005, |
721 | 0x0bfe04bd, | 725 | 0x0009f602, |
722 | 0x1f2af000, | 726 | 0x0c0a04bd, |
723 | 0xb60424b6, | 727 | 0x0000b87e, |
724 | 0x94bd0220, | 728 | 0x0080f4bd, |
725 | 0x800899f0, | 729 | 0x0ff60289, |
726 | 0xf6023700, | 730 | 0x8004bd00, |
727 | 0x04bd0009, | 731 | 0xf602c100, |
728 | 0x02810080, | 732 | 0x04bd0002, |
729 | 0xbd0002f6, | 733 | 0x02830080, |
730 | 0x0000d204, | ||
731 | 0x25f08000, | ||
732 | 0x88008002, | ||
733 | 0x0002f602, | ||
734 | 0x100104bd, | ||
735 | 0xf0020042, | ||
736 | 0x12fa0223, | ||
737 | 0xbd03f805, | ||
738 | 0x0899f094, | ||
739 | 0x02170080, | ||
740 | 0xbd0009f6, | ||
741 | 0x81019804, | ||
742 | 0x981814b6, | ||
743 | 0x25b68002, | ||
744 | 0x0512fd08, | ||
745 | 0xbd1601b5, | ||
746 | 0x0999f094, | ||
747 | 0x02370080, | ||
748 | 0xbd0009f6, | ||
749 | 0x81008004, | ||
750 | 0x0001f602, | ||
751 | 0x010204bd, | ||
752 | 0x02880080, | ||
753 | 0xbd0002f6, | 734 | 0xbd0002f6, |
754 | 0x01004104, | 735 | 0x7e070f04, |
755 | 0xfa0613f0, | 736 | 0x80000718, |
756 | 0x03f80501, | 737 | 0xf602c000, |
738 | 0x04bd0002, | ||
739 | 0xf0000bfe, | ||
740 | 0x24b61f2a, | ||
741 | 0x0220b604, | ||
757 | 0x99f094bd, | 742 | 0x99f094bd, |
758 | 0x17008009, | 743 | 0x37008008, |
759 | 0x0009f602, | 744 | 0x0009f602, |
760 | 0x94bd04bd, | 745 | 0x008004bd, |
761 | 0x800599f0, | 746 | 0x02f60281, |
747 | 0xd204bd00, | ||
748 | 0x80000000, | ||
749 | 0x800225f0, | ||
750 | 0xf6028800, | ||
751 | 0x04bd0002, | ||
752 | 0x00421001, | ||
753 | 0x0223f002, | ||
754 | 0xf80512fa, | ||
755 | 0xf094bd03, | ||
756 | 0x00800899, | ||
757 | 0x09f60217, | ||
758 | 0x9804bd00, | ||
759 | 0x14b68101, | ||
760 | 0x80029818, | ||
761 | 0xfd0825b6, | ||
762 | 0x01b50512, | ||
763 | 0xf094bd16, | ||
764 | 0x00800999, | ||
765 | 0x09f60237, | ||
766 | 0x8004bd00, | ||
767 | 0xf6028100, | ||
768 | 0x04bd0001, | ||
769 | 0x00800102, | ||
770 | 0x02f60288, | ||
771 | 0x4104bd00, | ||
772 | 0x13f00100, | ||
773 | 0x0501fa06, | ||
774 | 0x94bd03f8, | ||
775 | 0x800999f0, | ||
762 | 0xf6021700, | 776 | 0xf6021700, |
763 | 0x04bd0009, | 777 | 0x04bd0009, |
764 | /* 0x07d6: ctx_chan */ | 778 | 0x99f094bd, |
765 | 0xea7e00f8, | 779 | 0x17008005, |
766 | 0x0c0a0006, | 780 | 0x0009f602, |
767 | 0x0000b87e, | 781 | 0x00f804bd, |
768 | 0xd27e050f, | 782 | /* 0x081c: ctx_chan */ |
769 | 0x00f80006, | 783 | 0x0007307e, |
770 | /* 0x07e8: ctx_mmio_exec */ | 784 | 0xb87e0c0a, |
771 | 0x80410398, | 785 | 0x050f0000, |
786 | 0x0007187e, | ||
787 | /* 0x082e: ctx_mmio_exec */ | ||
788 | 0x039800f8, | ||
789 | 0x81008041, | ||
790 | 0x0003f602, | ||
791 | 0x34bd04bd, | ||
792 | /* 0x083c: ctx_mmio_loop */ | ||
793 | 0xf4ff34c4, | ||
794 | 0x00450e1b, | ||
795 | 0x0653f002, | ||
796 | 0xf80535fa, | ||
797 | /* 0x084d: ctx_mmio_pull */ | ||
798 | 0x804e9803, | ||
799 | 0x7e814f98, | ||
800 | 0xb600008f, | ||
801 | 0x12b60830, | ||
802 | 0xdf1bf401, | ||
803 | /* 0x0860: ctx_mmio_done */ | ||
804 | 0x80160398, | ||
772 | 0xf6028100, | 805 | 0xf6028100, |
773 | 0x04bd0003, | 806 | 0x04bd0003, |
774 | /* 0x07f6: ctx_mmio_loop */ | 807 | 0x414000b5, |
775 | 0x34c434bd, | 808 | 0x13f00100, |
776 | 0x0e1bf4ff, | 809 | 0x0601fa06, |
777 | 0xf0020045, | 810 | 0x00f803f8, |
778 | 0x35fa0653, | 811 | /* 0x087c: ctx_xfer */ |
779 | /* 0x0807: ctx_mmio_pull */ | 812 | 0x0080040e, |
780 | 0x9803f805, | 813 | 0x0ef60302, |
781 | 0x4f98804e, | 814 | /* 0x0887: ctx_xfer_idle */ |
782 | 0x008f7e81, | 815 | 0x8e04bd00, |
783 | 0x0830b600, | 816 | 0xcf030000, |
784 | 0xf40112b6, | 817 | 0xe4f100ee, |
785 | /* 0x081a: ctx_mmio_done */ | 818 | 0x1bf42000, |
786 | 0x0398df1b, | 819 | 0x0611f4f5, |
787 | 0x81008016, | 820 | /* 0x089b: ctx_xfer_pre */ |
788 | 0x0003f602, | 821 | 0x0f0c02f4, |
789 | 0x00b504bd, | 822 | 0x06f97e10, |
790 | 0x01004140, | 823 | 0x1b11f400, |
791 | 0xfa0613f0, | 824 | /* 0x08a4: ctx_xfer_pre_load */ |
792 | 0x03f80601, | 825 | 0xa87e020f, |
793 | /* 0x0836: ctx_xfer */ | 826 | 0xb77e0006, |
794 | 0x040e00f8, | 827 | 0xc97e0006, |
795 | 0x03020080, | 828 | 0xf4bd0006, |
796 | 0xbd000ef6, | 829 | 0x0006a87e, |
797 | /* 0x0841: ctx_xfer_idle */ | 830 | 0x0007307e, |
798 | 0x00008e04, | 831 | /* 0x08bc: ctx_xfer_exec */ |
799 | 0x00eecf03, | 832 | 0xbd160198, |
800 | 0x2000e4f1, | 833 | 0x05008024, |
801 | 0xf4f51bf4, | 834 | 0x0002f601, |
802 | 0x02f40611, | 835 | 0x1fb204bd, |
803 | /* 0x0855: ctx_xfer_pre */ | 836 | 0x41a5008e, |
804 | 0x7e100f0c, | ||
805 | 0xf40006b3, | ||
806 | /* 0x085e: ctx_xfer_pre_load */ | ||
807 | 0x020f1b11, | ||
808 | 0x0006627e, | ||
809 | 0x0006717e, | ||
810 | 0x0006837e, | ||
811 | 0x627ef4bd, | ||
812 | 0xea7e0006, | ||
813 | /* 0x0876: ctx_xfer_exec */ | ||
814 | 0x01980006, | ||
815 | 0x8024bd16, | ||
816 | 0xf6010500, | ||
817 | 0x04bd0002, | ||
818 | 0x008e1fb2, | ||
819 | 0x8f7e41a5, | ||
820 | 0xfcf00000, | ||
821 | 0x022cf001, | ||
822 | 0xfd0124b6, | ||
823 | 0xffb205f2, | ||
824 | 0x41a5048e, | ||
825 | 0x00008f7e, | 837 | 0x00008f7e, |
826 | 0x0002167e, | 838 | 0xf001fcf0, |
827 | 0xfc8024bd, | 839 | 0x24b6022c, |
828 | 0x02f60247, | 840 | 0x05f2fd01, |
829 | 0xf004bd00, | 841 | 0x048effb2, |
830 | 0x20b6012c, | 842 | 0x8f7e41a5, |
831 | 0x4afc8003, | 843 | 0x167e0000, |
832 | 0x0002f602, | 844 | 0x24bd0002, |
833 | 0xacf004bd, | 845 | 0x0247fc80, |
834 | 0x06a5f001, | 846 | 0xbd0002f6, |
835 | 0x0c98000b, | 847 | 0x012cf004, |
836 | 0x010d9800, | 848 | 0x800320b6, |
837 | 0x3d7e000e, | 849 | 0xf6024afc, |
838 | 0x080a0001, | 850 | 0x04bd0002, |
839 | 0x0000ec7e, | 851 | 0xf001acf0, |
840 | 0x00020a7e, | 852 | 0x000b06a5, |
841 | 0x0a1201f4, | 853 | 0x98000c98, |
842 | 0x00b87e0c, | 854 | 0x000e010d, |
843 | 0x7e050f00, | 855 | 0x00013d7e, |
844 | 0xf40006d2, | 856 | 0xec7e080a, |
845 | /* 0x08f2: ctx_xfer_post */ | 857 | 0x0a7e0000, |
846 | 0x020f2d02, | 858 | 0x01f40002, |
847 | 0x0006627e, | 859 | 0x7e0c0a12, |
848 | 0xb37ef4bd, | 860 | 0x0f0000b8, |
849 | 0x277e0006, | 861 | 0x07187e05, |
850 | 0x717e0002, | 862 | 0x2d02f400, |
863 | /* 0x0938: ctx_xfer_post */ | ||
864 | 0xa87e020f, | ||
851 | 0xf4bd0006, | 865 | 0xf4bd0006, |
852 | 0x0006627e, | 866 | 0x0006f97e, |
853 | 0x981011f4, | 867 | 0x0002277e, |
854 | 0x11fd4001, | 868 | 0x0006b77e, |
855 | 0x070bf405, | 869 | 0xa87ef4bd, |
856 | 0x0007e87e, | 870 | 0x11f40006, |
857 | /* 0x091c: ctx_xfer_no_post_mmio */ | 871 | 0x40019810, |
858 | /* 0x091c: ctx_xfer_done */ | 872 | 0xf40511fd, |
859 | 0x000000f8, | 873 | 0x2e7e070b, |
860 | 0x00000000, | 874 | /* 0x0962: ctx_xfer_no_post_mmio */ |
861 | 0x00000000, | 875 | /* 0x0962: ctx_xfer_done */ |
862 | 0x00000000, | 876 | 0x00f80008, |
863 | 0x00000000, | ||
864 | 0x00000000, | ||
865 | 0x00000000, | ||
866 | 0x00000000, | ||
867 | 0x00000000, | ||
868 | 0x00000000, | ||
869 | 0x00000000, | ||
870 | 0x00000000, | ||
871 | 0x00000000, | ||
872 | 0x00000000, | ||
873 | 0x00000000, | ||
874 | 0x00000000, | ||
875 | 0x00000000, | ||
876 | 0x00000000, | ||
877 | 0x00000000, | 877 | 0x00000000, |
878 | 0x00000000, | 878 | 0x00000000, |
879 | 0x00000000, | 879 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h index f8f7b278a13f..92dfe6a4ac87 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h | |||
@@ -528,10 +528,10 @@ uint32_t nvc0_grhub_code[] = { | |||
528 | 0x0001d001, | 528 | 0x0001d001, |
529 | 0x17f104bd, | 529 | 0x17f104bd, |
530 | 0xf7f00100, | 530 | 0xf7f00100, |
531 | 0xb521f502, | 531 | 0x0d21f502, |
532 | 0xc721f507, | 532 | 0x1f21f508, |
533 | 0x10f7f007, | 533 | 0x10f7f008, |
534 | 0x081421f5, | 534 | 0x086c21f5, |
535 | 0x98000e98, | 535 | 0x98000e98, |
536 | 0x21f5010f, | 536 | 0x21f5010f, |
537 | 0x14950150, | 537 | 0x14950150, |
@@ -574,9 +574,9 @@ uint32_t nvc0_grhub_code[] = { | |||
574 | 0xb6800040, | 574 | 0xb6800040, |
575 | 0x1bf40132, | 575 | 0x1bf40132, |
576 | 0x00f7f0be, | 576 | 0x00f7f0be, |
577 | 0x081421f5, | 577 | 0x086c21f5, |
578 | 0xf500f7f0, | 578 | 0xf500f7f0, |
579 | 0xf107b521, | 579 | 0xf1080d21, |
580 | 0xf0010007, | 580 | 0xf0010007, |
581 | 0x01d00203, | 581 | 0x01d00203, |
582 | 0xbd04bd00, | 582 | 0xbd04bd00, |
@@ -610,8 +610,8 @@ uint32_t nvc0_grhub_code[] = { | |||
610 | 0x09d00203, | 610 | 0x09d00203, |
611 | 0xf404bd00, | 611 | 0xf404bd00, |
612 | 0x31f40132, | 612 | 0x31f40132, |
613 | 0xe821f502, | 613 | 0x4021f502, |
614 | 0xf094bd09, | 614 | 0xf094bd0a, |
615 | 0x07f10799, | 615 | 0x07f10799, |
616 | 0x03f01700, | 616 | 0x03f01700, |
617 | 0x0009d002, | 617 | 0x0009d002, |
@@ -621,7 +621,7 @@ uint32_t nvc0_grhub_code[] = { | |||
621 | 0x0203f00f, | 621 | 0x0203f00f, |
622 | 0xbd0009d0, | 622 | 0xbd0009d0, |
623 | 0x0131f404, | 623 | 0x0131f404, |
624 | 0x09e821f5, | 624 | 0x0a4021f5, |
625 | 0x99f094bd, | 625 | 0x99f094bd, |
626 | 0x0007f106, | 626 | 0x0007f106, |
627 | 0x0203f017, | 627 | 0x0203f017, |
@@ -631,7 +631,7 @@ uint32_t nvc0_grhub_code[] = { | |||
631 | 0x12b920f9, | 631 | 0x12b920f9, |
632 | 0x0132f402, | 632 | 0x0132f402, |
633 | 0xf50232f4, | 633 | 0xf50232f4, |
634 | 0xfc09e821, | 634 | 0xfc0a4021, |
635 | 0x0007f120, | 635 | 0x0007f120, |
636 | 0x0203f0c0, | 636 | 0x0203f0c0, |
637 | 0xbd0002d0, | 637 | 0xbd0002d0, |
@@ -640,7 +640,7 @@ uint32_t nvc0_grhub_code[] = { | |||
640 | 0xf41f23c8, | 640 | 0xf41f23c8, |
641 | 0x31f40d0b, | 641 | 0x31f40d0b, |
642 | 0x0232f401, | 642 | 0x0232f401, |
643 | 0x09e821f5, | 643 | 0x0a4021f5, |
644 | /* 0x063c: chsw_done */ | 644 | /* 0x063c: chsw_done */ |
645 | 0xf10127f0, | 645 | 0xf10127f0, |
646 | 0xf0c30007, | 646 | 0xf0c30007, |
@@ -654,7 +654,7 @@ uint32_t nvc0_grhub_code[] = { | |||
654 | /* 0x0660: main_not_ctx_switch */ | 654 | /* 0x0660: main_not_ctx_switch */ |
655 | 0xf401e4b0, | 655 | 0xf401e4b0, |
656 | 0xf2b90d1b, | 656 | 0xf2b90d1b, |
657 | 0x7821f502, | 657 | 0xd021f502, |
658 | 0x460ef409, | 658 | 0x460ef409, |
659 | /* 0x0670: main_not_ctx_chan */ | 659 | /* 0x0670: main_not_ctx_chan */ |
660 | 0xf402e4b0, | 660 | 0xf402e4b0, |
@@ -664,8 +664,8 @@ uint32_t nvc0_grhub_code[] = { | |||
664 | 0x09d00203, | 664 | 0x09d00203, |
665 | 0xf404bd00, | 665 | 0xf404bd00, |
666 | 0x32f40132, | 666 | 0x32f40132, |
667 | 0xe821f502, | 667 | 0x4021f502, |
668 | 0xf094bd09, | 668 | 0xf094bd0a, |
669 | 0x07f10799, | 669 | 0x07f10799, |
670 | 0x03f01700, | 670 | 0x03f01700, |
671 | 0x0009d002, | 671 | 0x0009d002, |
@@ -710,18 +710,40 @@ uint32_t nvc0_grhub_code[] = { | |||
710 | /* 0x072b: ih_no_ctxsw */ | 710 | /* 0x072b: ih_no_ctxsw */ |
711 | 0xe40421f4, | 711 | 0xe40421f4, |
712 | 0xf40400ab, | 712 | 0xf40400ab, |
713 | 0xb7f1140b, | 713 | 0xe7f16c0b, |
714 | 0xe3f00708, | ||
715 | 0x6821f440, | ||
716 | 0xf102ffb9, | ||
717 | 0xf0040007, | ||
718 | 0x0fd00203, | ||
719 | 0xf104bd00, | ||
720 | 0xf00704e7, | ||
721 | 0x21f440e3, | ||
722 | 0x02ffb968, | ||
723 | 0x030007f1, | ||
724 | 0xd00203f0, | ||
725 | 0x04bd000f, | ||
726 | 0x9450fec7, | ||
727 | 0xf7f102ee, | ||
728 | 0xf3f00700, | ||
729 | 0x00efbb40, | ||
730 | 0xf16821f4, | ||
731 | 0xf0020007, | ||
732 | 0x0fd00203, | ||
733 | 0xf004bd00, | ||
734 | 0x21f503f7, | ||
735 | 0xb7f1037e, | ||
714 | 0xbfb90100, | 736 | 0xbfb90100, |
715 | 0x44e7f102, | 737 | 0x44e7f102, |
716 | 0x40e3f001, | 738 | 0x40e3f001, |
717 | /* 0x0743: ih_no_fwmthd */ | 739 | /* 0x079b: ih_no_fwmthd */ |
718 | 0xf19d21f4, | 740 | 0xf19d21f4, |
719 | 0xbd0104b7, | 741 | 0xbd0504b7, |
720 | 0xb4abffb0, | 742 | 0xb4abffb0, |
721 | 0xf10f0bf4, | 743 | 0xf10f0bf4, |
722 | 0xf0070007, | 744 | 0xf0070007, |
723 | 0x0bd00303, | 745 | 0x0bd00303, |
724 | /* 0x075b: ih_no_other */ | 746 | /* 0x07b3: ih_no_other */ |
725 | 0xf104bd00, | 747 | 0xf104bd00, |
726 | 0xf0010007, | 748 | 0xf0010007, |
727 | 0x0ad00003, | 749 | 0x0ad00003, |
@@ -731,36 +753,36 @@ uint32_t nvc0_grhub_code[] = { | |||
731 | 0xfc90fca0, | 753 | 0xfc90fca0, |
732 | 0x0088fe80, | 754 | 0x0088fe80, |
733 | 0x32f480fc, | 755 | 0x32f480fc, |
734 | /* 0x077f: ctx_4160s */ | 756 | /* 0x07d7: ctx_4160s */ |
735 | 0xf001f800, | 757 | 0xf001f800, |
736 | 0xffb901f7, | 758 | 0xffb901f7, |
737 | 0x60e7f102, | 759 | 0x60e7f102, |
738 | 0x40e3f041, | 760 | 0x40e3f041, |
739 | /* 0x078f: ctx_4160s_wait */ | 761 | /* 0x07e7: ctx_4160s_wait */ |
740 | 0xf19d21f4, | 762 | 0xf19d21f4, |
741 | 0xf04160e7, | 763 | 0xf04160e7, |
742 | 0x21f440e3, | 764 | 0x21f440e3, |
743 | 0x02ffb968, | 765 | 0x02ffb968, |
744 | 0xf404ffc8, | 766 | 0xf404ffc8, |
745 | 0x00f8f00b, | 767 | 0x00f8f00b, |
746 | /* 0x07a4: ctx_4160c */ | 768 | /* 0x07fc: ctx_4160c */ |
747 | 0xffb9f4bd, | 769 | 0xffb9f4bd, |
748 | 0x60e7f102, | 770 | 0x60e7f102, |
749 | 0x40e3f041, | 771 | 0x40e3f041, |
750 | 0xf89d21f4, | 772 | 0xf89d21f4, |
751 | /* 0x07b5: ctx_4170s */ | 773 | /* 0x080d: ctx_4170s */ |
752 | 0x10f5f000, | 774 | 0x10f5f000, |
753 | 0xf102ffb9, | 775 | 0xf102ffb9, |
754 | 0xf04170e7, | 776 | 0xf04170e7, |
755 | 0x21f440e3, | 777 | 0x21f440e3, |
756 | /* 0x07c7: ctx_4170w */ | 778 | /* 0x081f: ctx_4170w */ |
757 | 0xf100f89d, | 779 | 0xf100f89d, |
758 | 0xf04170e7, | 780 | 0xf04170e7, |
759 | 0x21f440e3, | 781 | 0x21f440e3, |
760 | 0x02ffb968, | 782 | 0x02ffb968, |
761 | 0xf410f4f0, | 783 | 0xf410f4f0, |
762 | 0x00f8f01b, | 784 | 0x00f8f01b, |
763 | /* 0x07dc: ctx_redswitch */ | 785 | /* 0x0834: ctx_redswitch */ |
764 | 0x0200e7f1, | 786 | 0x0200e7f1, |
765 | 0xf040e5f0, | 787 | 0xf040e5f0, |
766 | 0xe5f020e5, | 788 | 0xe5f020e5, |
@@ -768,7 +790,7 @@ uint32_t nvc0_grhub_code[] = { | |||
768 | 0x0103f085, | 790 | 0x0103f085, |
769 | 0xbd000ed0, | 791 | 0xbd000ed0, |
770 | 0x08f7f004, | 792 | 0x08f7f004, |
771 | /* 0x07f8: ctx_redswitch_delay */ | 793 | /* 0x0850: ctx_redswitch_delay */ |
772 | 0xf401f2b6, | 794 | 0xf401f2b6, |
773 | 0xe5f1fd1b, | 795 | 0xe5f1fd1b, |
774 | 0xe5f10400, | 796 | 0xe5f10400, |
@@ -776,7 +798,7 @@ uint32_t nvc0_grhub_code[] = { | |||
776 | 0x03f08500, | 798 | 0x03f08500, |
777 | 0x000ed001, | 799 | 0x000ed001, |
778 | 0x00f804bd, | 800 | 0x00f804bd, |
779 | /* 0x0814: ctx_86c */ | 801 | /* 0x086c: ctx_86c */ |
780 | 0x1b0007f1, | 802 | 0x1b0007f1, |
781 | 0xd00203f0, | 803 | 0xd00203f0, |
782 | 0x04bd000f, | 804 | 0x04bd000f, |
@@ -787,16 +809,16 @@ uint32_t nvc0_grhub_code[] = { | |||
787 | 0xa86ce7f1, | 809 | 0xa86ce7f1, |
788 | 0xf441e3f0, | 810 | 0xf441e3f0, |
789 | 0x00f89d21, | 811 | 0x00f89d21, |
790 | /* 0x083c: ctx_mem */ | 812 | /* 0x0894: ctx_mem */ |
791 | 0x840007f1, | 813 | 0x840007f1, |
792 | 0xd00203f0, | 814 | 0xd00203f0, |
793 | 0x04bd000f, | 815 | 0x04bd000f, |
794 | /* 0x0848: ctx_mem_wait */ | 816 | /* 0x08a0: ctx_mem_wait */ |
795 | 0x8400f7f1, | 817 | 0x8400f7f1, |
796 | 0xcf02f3f0, | 818 | 0xcf02f3f0, |
797 | 0xfffd00ff, | 819 | 0xfffd00ff, |
798 | 0xf31bf405, | 820 | 0xf31bf405, |
799 | /* 0x085a: ctx_load */ | 821 | /* 0x08b2: ctx_load */ |
800 | 0x94bd00f8, | 822 | 0x94bd00f8, |
801 | 0xf10599f0, | 823 | 0xf10599f0, |
802 | 0xf00f0007, | 824 | 0xf00f0007, |
@@ -814,7 +836,7 @@ uint32_t nvc0_grhub_code[] = { | |||
814 | 0x02d00203, | 836 | 0x02d00203, |
815 | 0xf004bd00, | 837 | 0xf004bd00, |
816 | 0x21f507f7, | 838 | 0x21f507f7, |
817 | 0x07f1083c, | 839 | 0x07f10894, |
818 | 0x03f0c000, | 840 | 0x03f0c000, |
819 | 0x0002d002, | 841 | 0x0002d002, |
820 | 0x0bfe04bd, | 842 | 0x0bfe04bd, |
@@ -869,31 +891,31 @@ uint32_t nvc0_grhub_code[] = { | |||
869 | 0x03f01700, | 891 | 0x03f01700, |
870 | 0x0009d002, | 892 | 0x0009d002, |
871 | 0x00f804bd, | 893 | 0x00f804bd, |
872 | /* 0x0978: ctx_chan */ | 894 | /* 0x09d0: ctx_chan */ |
873 | 0x077f21f5, | 895 | 0x07d721f5, |
874 | 0x085a21f5, | 896 | 0x08b221f5, |
875 | 0xf40ca7f0, | 897 | 0xf40ca7f0, |
876 | 0xf7f0d021, | 898 | 0xf7f0d021, |
877 | 0x3c21f505, | 899 | 0x9421f505, |
878 | 0xa421f508, | 900 | 0xfc21f508, |
879 | /* 0x0993: ctx_mmio_exec */ | 901 | /* 0x09eb: ctx_mmio_exec */ |
880 | 0x9800f807, | 902 | 0x9800f807, |
881 | 0x07f14103, | 903 | 0x07f14103, |
882 | 0x03f08100, | 904 | 0x03f08100, |
883 | 0x0003d002, | 905 | 0x0003d002, |
884 | 0x34bd04bd, | 906 | 0x34bd04bd, |
885 | /* 0x09a4: ctx_mmio_loop */ | 907 | /* 0x09fc: ctx_mmio_loop */ |
886 | 0xf4ff34c4, | 908 | 0xf4ff34c4, |
887 | 0x57f10f1b, | 909 | 0x57f10f1b, |
888 | 0x53f00200, | 910 | 0x53f00200, |
889 | 0x0535fa06, | 911 | 0x0535fa06, |
890 | /* 0x09b6: ctx_mmio_pull */ | 912 | /* 0x0a0e: ctx_mmio_pull */ |
891 | 0x4e9803f8, | 913 | 0x4e9803f8, |
892 | 0x814f9880, | 914 | 0x814f9880, |
893 | 0xb69d21f4, | 915 | 0xb69d21f4, |
894 | 0x12b60830, | 916 | 0x12b60830, |
895 | 0xdf1bf401, | 917 | 0xdf1bf401, |
896 | /* 0x09c8: ctx_mmio_done */ | 918 | /* 0x0a20: ctx_mmio_done */ |
897 | 0xf1160398, | 919 | 0xf1160398, |
898 | 0xf0810007, | 920 | 0xf0810007, |
899 | 0x03d00203, | 921 | 0x03d00203, |
@@ -902,30 +924,30 @@ uint32_t nvc0_grhub_code[] = { | |||
902 | 0x13f00100, | 924 | 0x13f00100, |
903 | 0x0601fa06, | 925 | 0x0601fa06, |
904 | 0x00f803f8, | 926 | 0x00f803f8, |
905 | /* 0x09e8: ctx_xfer */ | 927 | /* 0x0a40: ctx_xfer */ |
906 | 0xf104e7f0, | 928 | 0xf104e7f0, |
907 | 0xf0020007, | 929 | 0xf0020007, |
908 | 0x0ed00303, | 930 | 0x0ed00303, |
909 | /* 0x09f7: ctx_xfer_idle */ | 931 | /* 0x0a4f: ctx_xfer_idle */ |
910 | 0xf104bd00, | 932 | 0xf104bd00, |
911 | 0xf00000e7, | 933 | 0xf00000e7, |
912 | 0xeecf03e3, | 934 | 0xeecf03e3, |
913 | 0x00e4f100, | 935 | 0x00e4f100, |
914 | 0xf21bf420, | 936 | 0xf21bf420, |
915 | 0xf40611f4, | 937 | 0xf40611f4, |
916 | /* 0x0a0e: ctx_xfer_pre */ | 938 | /* 0x0a66: ctx_xfer_pre */ |
917 | 0xf7f01102, | 939 | 0xf7f01102, |
918 | 0x1421f510, | 940 | 0x6c21f510, |
919 | 0x7f21f508, | 941 | 0xd721f508, |
920 | 0x1c11f407, | 942 | 0x1c11f407, |
921 | /* 0x0a1c: ctx_xfer_pre_load */ | 943 | /* 0x0a74: ctx_xfer_pre_load */ |
922 | 0xf502f7f0, | 944 | 0xf502f7f0, |
923 | 0xf507b521, | 945 | 0xf5080d21, |
924 | 0xf507c721, | 946 | 0xf5081f21, |
925 | 0xbd07dc21, | 947 | 0xbd083421, |
926 | 0xb521f5f4, | 948 | 0x0d21f5f4, |
927 | 0x5a21f507, | 949 | 0xb221f508, |
928 | /* 0x0a35: ctx_xfer_exec */ | 950 | /* 0x0a8d: ctx_xfer_exec */ |
929 | 0x16019808, | 951 | 0x16019808, |
930 | 0x07f124bd, | 952 | 0x07f124bd, |
931 | 0x03f00500, | 953 | 0x03f00500, |
@@ -960,23 +982,65 @@ uint32_t nvc0_grhub_code[] = { | |||
960 | 0x1301f402, | 982 | 0x1301f402, |
961 | 0xf40ca7f0, | 983 | 0xf40ca7f0, |
962 | 0xf7f0d021, | 984 | 0xf7f0d021, |
963 | 0x3c21f505, | 985 | 0x9421f505, |
964 | 0x3202f408, | 986 | 0x3202f408, |
965 | /* 0x0ac4: ctx_xfer_post */ | 987 | /* 0x0b1c: ctx_xfer_post */ |
966 | 0xf502f7f0, | 988 | 0xf502f7f0, |
967 | 0xbd07b521, | 989 | 0xbd080d21, |
968 | 0x1421f5f4, | 990 | 0x6c21f5f4, |
969 | 0x7f21f508, | 991 | 0x7f21f508, |
970 | 0xc721f502, | 992 | 0x1f21f502, |
971 | 0xf5f4bd07, | 993 | 0xf5f4bd08, |
972 | 0xf407b521, | 994 | 0xf4080d21, |
973 | 0x01981011, | 995 | 0x01981011, |
974 | 0x0511fd40, | 996 | 0x0511fd40, |
975 | 0xf5070bf4, | 997 | 0xf5070bf4, |
976 | /* 0x0aef: ctx_xfer_no_post_mmio */ | 998 | /* 0x0b47: ctx_xfer_no_post_mmio */ |
977 | 0xf5099321, | 999 | 0xf509eb21, |
978 | /* 0x0af3: ctx_xfer_done */ | 1000 | /* 0x0b4b: ctx_xfer_done */ |
979 | 0xf807a421, | 1001 | 0xf807fc21, |
1002 | 0x00000000, | ||
1003 | 0x00000000, | ||
1004 | 0x00000000, | ||
1005 | 0x00000000, | ||
1006 | 0x00000000, | ||
1007 | 0x00000000, | ||
1008 | 0x00000000, | ||
1009 | 0x00000000, | ||
1010 | 0x00000000, | ||
1011 | 0x00000000, | ||
1012 | 0x00000000, | ||
1013 | 0x00000000, | ||
1014 | 0x00000000, | ||
1015 | 0x00000000, | ||
1016 | 0x00000000, | ||
1017 | 0x00000000, | ||
1018 | 0x00000000, | ||
1019 | 0x00000000, | ||
1020 | 0x00000000, | ||
1021 | 0x00000000, | ||
1022 | 0x00000000, | ||
1023 | 0x00000000, | ||
1024 | 0x00000000, | ||
1025 | 0x00000000, | ||
1026 | 0x00000000, | ||
1027 | 0x00000000, | ||
1028 | 0x00000000, | ||
1029 | 0x00000000, | ||
1030 | 0x00000000, | ||
1031 | 0x00000000, | ||
1032 | 0x00000000, | ||
1033 | 0x00000000, | ||
1034 | 0x00000000, | ||
1035 | 0x00000000, | ||
1036 | 0x00000000, | ||
1037 | 0x00000000, | ||
1038 | 0x00000000, | ||
1039 | 0x00000000, | ||
1040 | 0x00000000, | ||
1041 | 0x00000000, | ||
1042 | 0x00000000, | ||
1043 | 0x00000000, | ||
980 | 0x00000000, | 1044 | 0x00000000, |
981 | 0x00000000, | 1045 | 0x00000000, |
982 | 0x00000000, | 1046 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h index 624215a005b0..62b0c7601d8b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h | |||
@@ -528,10 +528,10 @@ uint32_t nvd7_grhub_code[] = { | |||
528 | 0x0001d001, | 528 | 0x0001d001, |
529 | 0x17f104bd, | 529 | 0x17f104bd, |
530 | 0xf7f00100, | 530 | 0xf7f00100, |
531 | 0xb521f502, | 531 | 0x0d21f502, |
532 | 0xc721f507, | 532 | 0x1f21f508, |
533 | 0x10f7f007, | 533 | 0x10f7f008, |
534 | 0x081421f5, | 534 | 0x086c21f5, |
535 | 0x98000e98, | 535 | 0x98000e98, |
536 | 0x21f5010f, | 536 | 0x21f5010f, |
537 | 0x14950150, | 537 | 0x14950150, |
@@ -574,9 +574,9 @@ uint32_t nvd7_grhub_code[] = { | |||
574 | 0xb6800040, | 574 | 0xb6800040, |
575 | 0x1bf40132, | 575 | 0x1bf40132, |
576 | 0x00f7f0be, | 576 | 0x00f7f0be, |
577 | 0x081421f5, | 577 | 0x086c21f5, |
578 | 0xf500f7f0, | 578 | 0xf500f7f0, |
579 | 0xf107b521, | 579 | 0xf1080d21, |
580 | 0xf0010007, | 580 | 0xf0010007, |
581 | 0x01d00203, | 581 | 0x01d00203, |
582 | 0xbd04bd00, | 582 | 0xbd04bd00, |
@@ -610,8 +610,8 @@ uint32_t nvd7_grhub_code[] = { | |||
610 | 0x09d00203, | 610 | 0x09d00203, |
611 | 0xf404bd00, | 611 | 0xf404bd00, |
612 | 0x31f40132, | 612 | 0x31f40132, |
613 | 0xe821f502, | 613 | 0x4021f502, |
614 | 0xf094bd09, | 614 | 0xf094bd0a, |
615 | 0x07f10799, | 615 | 0x07f10799, |
616 | 0x03f01700, | 616 | 0x03f01700, |
617 | 0x0009d002, | 617 | 0x0009d002, |
@@ -621,7 +621,7 @@ uint32_t nvd7_grhub_code[] = { | |||
621 | 0x0203f00f, | 621 | 0x0203f00f, |
622 | 0xbd0009d0, | 622 | 0xbd0009d0, |
623 | 0x0131f404, | 623 | 0x0131f404, |
624 | 0x09e821f5, | 624 | 0x0a4021f5, |
625 | 0x99f094bd, | 625 | 0x99f094bd, |
626 | 0x0007f106, | 626 | 0x0007f106, |
627 | 0x0203f017, | 627 | 0x0203f017, |
@@ -631,7 +631,7 @@ uint32_t nvd7_grhub_code[] = { | |||
631 | 0x12b920f9, | 631 | 0x12b920f9, |
632 | 0x0132f402, | 632 | 0x0132f402, |
633 | 0xf50232f4, | 633 | 0xf50232f4, |
634 | 0xfc09e821, | 634 | 0xfc0a4021, |
635 | 0x0007f120, | 635 | 0x0007f120, |
636 | 0x0203f0c0, | 636 | 0x0203f0c0, |
637 | 0xbd0002d0, | 637 | 0xbd0002d0, |
@@ -640,7 +640,7 @@ uint32_t nvd7_grhub_code[] = { | |||
640 | 0xf41f23c8, | 640 | 0xf41f23c8, |
641 | 0x31f40d0b, | 641 | 0x31f40d0b, |
642 | 0x0232f401, | 642 | 0x0232f401, |
643 | 0x09e821f5, | 643 | 0x0a4021f5, |
644 | /* 0x063c: chsw_done */ | 644 | /* 0x063c: chsw_done */ |
645 | 0xf10127f0, | 645 | 0xf10127f0, |
646 | 0xf0c30007, | 646 | 0xf0c30007, |
@@ -654,7 +654,7 @@ uint32_t nvd7_grhub_code[] = { | |||
654 | /* 0x0660: main_not_ctx_switch */ | 654 | /* 0x0660: main_not_ctx_switch */ |
655 | 0xf401e4b0, | 655 | 0xf401e4b0, |
656 | 0xf2b90d1b, | 656 | 0xf2b90d1b, |
657 | 0x7821f502, | 657 | 0xd021f502, |
658 | 0x460ef409, | 658 | 0x460ef409, |
659 | /* 0x0670: main_not_ctx_chan */ | 659 | /* 0x0670: main_not_ctx_chan */ |
660 | 0xf402e4b0, | 660 | 0xf402e4b0, |
@@ -664,8 +664,8 @@ uint32_t nvd7_grhub_code[] = { | |||
664 | 0x09d00203, | 664 | 0x09d00203, |
665 | 0xf404bd00, | 665 | 0xf404bd00, |
666 | 0x32f40132, | 666 | 0x32f40132, |
667 | 0xe821f502, | 667 | 0x4021f502, |
668 | 0xf094bd09, | 668 | 0xf094bd0a, |
669 | 0x07f10799, | 669 | 0x07f10799, |
670 | 0x03f01700, | 670 | 0x03f01700, |
671 | 0x0009d002, | 671 | 0x0009d002, |
@@ -710,18 +710,40 @@ uint32_t nvd7_grhub_code[] = { | |||
710 | /* 0x072b: ih_no_ctxsw */ | 710 | /* 0x072b: ih_no_ctxsw */ |
711 | 0xe40421f4, | 711 | 0xe40421f4, |
712 | 0xf40400ab, | 712 | 0xf40400ab, |
713 | 0xb7f1140b, | 713 | 0xe7f16c0b, |
714 | 0xe3f00708, | ||
715 | 0x6821f440, | ||
716 | 0xf102ffb9, | ||
717 | 0xf0040007, | ||
718 | 0x0fd00203, | ||
719 | 0xf104bd00, | ||
720 | 0xf00704e7, | ||
721 | 0x21f440e3, | ||
722 | 0x02ffb968, | ||
723 | 0x030007f1, | ||
724 | 0xd00203f0, | ||
725 | 0x04bd000f, | ||
726 | 0x9450fec7, | ||
727 | 0xf7f102ee, | ||
728 | 0xf3f00700, | ||
729 | 0x00efbb40, | ||
730 | 0xf16821f4, | ||
731 | 0xf0020007, | ||
732 | 0x0fd00203, | ||
733 | 0xf004bd00, | ||
734 | 0x21f503f7, | ||
735 | 0xb7f1037e, | ||
714 | 0xbfb90100, | 736 | 0xbfb90100, |
715 | 0x44e7f102, | 737 | 0x44e7f102, |
716 | 0x40e3f001, | 738 | 0x40e3f001, |
717 | /* 0x0743: ih_no_fwmthd */ | 739 | /* 0x079b: ih_no_fwmthd */ |
718 | 0xf19d21f4, | 740 | 0xf19d21f4, |
719 | 0xbd0104b7, | 741 | 0xbd0504b7, |
720 | 0xb4abffb0, | 742 | 0xb4abffb0, |
721 | 0xf10f0bf4, | 743 | 0xf10f0bf4, |
722 | 0xf0070007, | 744 | 0xf0070007, |
723 | 0x0bd00303, | 745 | 0x0bd00303, |
724 | /* 0x075b: ih_no_other */ | 746 | /* 0x07b3: ih_no_other */ |
725 | 0xf104bd00, | 747 | 0xf104bd00, |
726 | 0xf0010007, | 748 | 0xf0010007, |
727 | 0x0ad00003, | 749 | 0x0ad00003, |
@@ -731,36 +753,36 @@ uint32_t nvd7_grhub_code[] = { | |||
731 | 0xfc90fca0, | 753 | 0xfc90fca0, |
732 | 0x0088fe80, | 754 | 0x0088fe80, |
733 | 0x32f480fc, | 755 | 0x32f480fc, |
734 | /* 0x077f: ctx_4160s */ | 756 | /* 0x07d7: ctx_4160s */ |
735 | 0xf001f800, | 757 | 0xf001f800, |
736 | 0xffb901f7, | 758 | 0xffb901f7, |
737 | 0x60e7f102, | 759 | 0x60e7f102, |
738 | 0x40e3f041, | 760 | 0x40e3f041, |
739 | /* 0x078f: ctx_4160s_wait */ | 761 | /* 0x07e7: ctx_4160s_wait */ |
740 | 0xf19d21f4, | 762 | 0xf19d21f4, |
741 | 0xf04160e7, | 763 | 0xf04160e7, |
742 | 0x21f440e3, | 764 | 0x21f440e3, |
743 | 0x02ffb968, | 765 | 0x02ffb968, |
744 | 0xf404ffc8, | 766 | 0xf404ffc8, |
745 | 0x00f8f00b, | 767 | 0x00f8f00b, |
746 | /* 0x07a4: ctx_4160c */ | 768 | /* 0x07fc: ctx_4160c */ |
747 | 0xffb9f4bd, | 769 | 0xffb9f4bd, |
748 | 0x60e7f102, | 770 | 0x60e7f102, |
749 | 0x40e3f041, | 771 | 0x40e3f041, |
750 | 0xf89d21f4, | 772 | 0xf89d21f4, |
751 | /* 0x07b5: ctx_4170s */ | 773 | /* 0x080d: ctx_4170s */ |
752 | 0x10f5f000, | 774 | 0x10f5f000, |
753 | 0xf102ffb9, | 775 | 0xf102ffb9, |
754 | 0xf04170e7, | 776 | 0xf04170e7, |
755 | 0x21f440e3, | 777 | 0x21f440e3, |
756 | /* 0x07c7: ctx_4170w */ | 778 | /* 0x081f: ctx_4170w */ |
757 | 0xf100f89d, | 779 | 0xf100f89d, |
758 | 0xf04170e7, | 780 | 0xf04170e7, |
759 | 0x21f440e3, | 781 | 0x21f440e3, |
760 | 0x02ffb968, | 782 | 0x02ffb968, |
761 | 0xf410f4f0, | 783 | 0xf410f4f0, |
762 | 0x00f8f01b, | 784 | 0x00f8f01b, |
763 | /* 0x07dc: ctx_redswitch */ | 785 | /* 0x0834: ctx_redswitch */ |
764 | 0x0200e7f1, | 786 | 0x0200e7f1, |
765 | 0xf040e5f0, | 787 | 0xf040e5f0, |
766 | 0xe5f020e5, | 788 | 0xe5f020e5, |
@@ -768,7 +790,7 @@ uint32_t nvd7_grhub_code[] = { | |||
768 | 0x0103f085, | 790 | 0x0103f085, |
769 | 0xbd000ed0, | 791 | 0xbd000ed0, |
770 | 0x08f7f004, | 792 | 0x08f7f004, |
771 | /* 0x07f8: ctx_redswitch_delay */ | 793 | /* 0x0850: ctx_redswitch_delay */ |
772 | 0xf401f2b6, | 794 | 0xf401f2b6, |
773 | 0xe5f1fd1b, | 795 | 0xe5f1fd1b, |
774 | 0xe5f10400, | 796 | 0xe5f10400, |
@@ -776,7 +798,7 @@ uint32_t nvd7_grhub_code[] = { | |||
776 | 0x03f08500, | 798 | 0x03f08500, |
777 | 0x000ed001, | 799 | 0x000ed001, |
778 | 0x00f804bd, | 800 | 0x00f804bd, |
779 | /* 0x0814: ctx_86c */ | 801 | /* 0x086c: ctx_86c */ |
780 | 0x1b0007f1, | 802 | 0x1b0007f1, |
781 | 0xd00203f0, | 803 | 0xd00203f0, |
782 | 0x04bd000f, | 804 | 0x04bd000f, |
@@ -787,16 +809,16 @@ uint32_t nvd7_grhub_code[] = { | |||
787 | 0xa86ce7f1, | 809 | 0xa86ce7f1, |
788 | 0xf441e3f0, | 810 | 0xf441e3f0, |
789 | 0x00f89d21, | 811 | 0x00f89d21, |
790 | /* 0x083c: ctx_mem */ | 812 | /* 0x0894: ctx_mem */ |
791 | 0x840007f1, | 813 | 0x840007f1, |
792 | 0xd00203f0, | 814 | 0xd00203f0, |
793 | 0x04bd000f, | 815 | 0x04bd000f, |
794 | /* 0x0848: ctx_mem_wait */ | 816 | /* 0x08a0: ctx_mem_wait */ |
795 | 0x8400f7f1, | 817 | 0x8400f7f1, |
796 | 0xcf02f3f0, | 818 | 0xcf02f3f0, |
797 | 0xfffd00ff, | 819 | 0xfffd00ff, |
798 | 0xf31bf405, | 820 | 0xf31bf405, |
799 | /* 0x085a: ctx_load */ | 821 | /* 0x08b2: ctx_load */ |
800 | 0x94bd00f8, | 822 | 0x94bd00f8, |
801 | 0xf10599f0, | 823 | 0xf10599f0, |
802 | 0xf00f0007, | 824 | 0xf00f0007, |
@@ -814,7 +836,7 @@ uint32_t nvd7_grhub_code[] = { | |||
814 | 0x02d00203, | 836 | 0x02d00203, |
815 | 0xf004bd00, | 837 | 0xf004bd00, |
816 | 0x21f507f7, | 838 | 0x21f507f7, |
817 | 0x07f1083c, | 839 | 0x07f10894, |
818 | 0x03f0c000, | 840 | 0x03f0c000, |
819 | 0x0002d002, | 841 | 0x0002d002, |
820 | 0x0bfe04bd, | 842 | 0x0bfe04bd, |
@@ -869,31 +891,31 @@ uint32_t nvd7_grhub_code[] = { | |||
869 | 0x03f01700, | 891 | 0x03f01700, |
870 | 0x0009d002, | 892 | 0x0009d002, |
871 | 0x00f804bd, | 893 | 0x00f804bd, |
872 | /* 0x0978: ctx_chan */ | 894 | /* 0x09d0: ctx_chan */ |
873 | 0x077f21f5, | 895 | 0x07d721f5, |
874 | 0x085a21f5, | 896 | 0x08b221f5, |
875 | 0xf40ca7f0, | 897 | 0xf40ca7f0, |
876 | 0xf7f0d021, | 898 | 0xf7f0d021, |
877 | 0x3c21f505, | 899 | 0x9421f505, |
878 | 0xa421f508, | 900 | 0xfc21f508, |
879 | /* 0x0993: ctx_mmio_exec */ | 901 | /* 0x09eb: ctx_mmio_exec */ |
880 | 0x9800f807, | 902 | 0x9800f807, |
881 | 0x07f14103, | 903 | 0x07f14103, |
882 | 0x03f08100, | 904 | 0x03f08100, |
883 | 0x0003d002, | 905 | 0x0003d002, |
884 | 0x34bd04bd, | 906 | 0x34bd04bd, |
885 | /* 0x09a4: ctx_mmio_loop */ | 907 | /* 0x09fc: ctx_mmio_loop */ |
886 | 0xf4ff34c4, | 908 | 0xf4ff34c4, |
887 | 0x57f10f1b, | 909 | 0x57f10f1b, |
888 | 0x53f00200, | 910 | 0x53f00200, |
889 | 0x0535fa06, | 911 | 0x0535fa06, |
890 | /* 0x09b6: ctx_mmio_pull */ | 912 | /* 0x0a0e: ctx_mmio_pull */ |
891 | 0x4e9803f8, | 913 | 0x4e9803f8, |
892 | 0x814f9880, | 914 | 0x814f9880, |
893 | 0xb69d21f4, | 915 | 0xb69d21f4, |
894 | 0x12b60830, | 916 | 0x12b60830, |
895 | 0xdf1bf401, | 917 | 0xdf1bf401, |
896 | /* 0x09c8: ctx_mmio_done */ | 918 | /* 0x0a20: ctx_mmio_done */ |
897 | 0xf1160398, | 919 | 0xf1160398, |
898 | 0xf0810007, | 920 | 0xf0810007, |
899 | 0x03d00203, | 921 | 0x03d00203, |
@@ -902,30 +924,30 @@ uint32_t nvd7_grhub_code[] = { | |||
902 | 0x13f00100, | 924 | 0x13f00100, |
903 | 0x0601fa06, | 925 | 0x0601fa06, |
904 | 0x00f803f8, | 926 | 0x00f803f8, |
905 | /* 0x09e8: ctx_xfer */ | 927 | /* 0x0a40: ctx_xfer */ |
906 | 0xf104e7f0, | 928 | 0xf104e7f0, |
907 | 0xf0020007, | 929 | 0xf0020007, |
908 | 0x0ed00303, | 930 | 0x0ed00303, |
909 | /* 0x09f7: ctx_xfer_idle */ | 931 | /* 0x0a4f: ctx_xfer_idle */ |
910 | 0xf104bd00, | 932 | 0xf104bd00, |
911 | 0xf00000e7, | 933 | 0xf00000e7, |
912 | 0xeecf03e3, | 934 | 0xeecf03e3, |
913 | 0x00e4f100, | 935 | 0x00e4f100, |
914 | 0xf21bf420, | 936 | 0xf21bf420, |
915 | 0xf40611f4, | 937 | 0xf40611f4, |
916 | /* 0x0a0e: ctx_xfer_pre */ | 938 | /* 0x0a66: ctx_xfer_pre */ |
917 | 0xf7f01102, | 939 | 0xf7f01102, |
918 | 0x1421f510, | 940 | 0x6c21f510, |
919 | 0x7f21f508, | 941 | 0xd721f508, |
920 | 0x1c11f407, | 942 | 0x1c11f407, |
921 | /* 0x0a1c: ctx_xfer_pre_load */ | 943 | /* 0x0a74: ctx_xfer_pre_load */ |
922 | 0xf502f7f0, | 944 | 0xf502f7f0, |
923 | 0xf507b521, | 945 | 0xf5080d21, |
924 | 0xf507c721, | 946 | 0xf5081f21, |
925 | 0xbd07dc21, | 947 | 0xbd083421, |
926 | 0xb521f5f4, | 948 | 0x0d21f5f4, |
927 | 0x5a21f507, | 949 | 0xb221f508, |
928 | /* 0x0a35: ctx_xfer_exec */ | 950 | /* 0x0a8d: ctx_xfer_exec */ |
929 | 0x16019808, | 951 | 0x16019808, |
930 | 0x07f124bd, | 952 | 0x07f124bd, |
931 | 0x03f00500, | 953 | 0x03f00500, |
@@ -960,23 +982,65 @@ uint32_t nvd7_grhub_code[] = { | |||
960 | 0x1301f402, | 982 | 0x1301f402, |
961 | 0xf40ca7f0, | 983 | 0xf40ca7f0, |
962 | 0xf7f0d021, | 984 | 0xf7f0d021, |
963 | 0x3c21f505, | 985 | 0x9421f505, |
964 | 0x3202f408, | 986 | 0x3202f408, |
965 | /* 0x0ac4: ctx_xfer_post */ | 987 | /* 0x0b1c: ctx_xfer_post */ |
966 | 0xf502f7f0, | 988 | 0xf502f7f0, |
967 | 0xbd07b521, | 989 | 0xbd080d21, |
968 | 0x1421f5f4, | 990 | 0x6c21f5f4, |
969 | 0x7f21f508, | 991 | 0x7f21f508, |
970 | 0xc721f502, | 992 | 0x1f21f502, |
971 | 0xf5f4bd07, | 993 | 0xf5f4bd08, |
972 | 0xf407b521, | 994 | 0xf4080d21, |
973 | 0x01981011, | 995 | 0x01981011, |
974 | 0x0511fd40, | 996 | 0x0511fd40, |
975 | 0xf5070bf4, | 997 | 0xf5070bf4, |
976 | /* 0x0aef: ctx_xfer_no_post_mmio */ | 998 | /* 0x0b47: ctx_xfer_no_post_mmio */ |
977 | 0xf5099321, | 999 | 0xf509eb21, |
978 | /* 0x0af3: ctx_xfer_done */ | 1000 | /* 0x0b4b: ctx_xfer_done */ |
979 | 0xf807a421, | 1001 | 0xf807fc21, |
1002 | 0x00000000, | ||
1003 | 0x00000000, | ||
1004 | 0x00000000, | ||
1005 | 0x00000000, | ||
1006 | 0x00000000, | ||
1007 | 0x00000000, | ||
1008 | 0x00000000, | ||
1009 | 0x00000000, | ||
1010 | 0x00000000, | ||
1011 | 0x00000000, | ||
1012 | 0x00000000, | ||
1013 | 0x00000000, | ||
1014 | 0x00000000, | ||
1015 | 0x00000000, | ||
1016 | 0x00000000, | ||
1017 | 0x00000000, | ||
1018 | 0x00000000, | ||
1019 | 0x00000000, | ||
1020 | 0x00000000, | ||
1021 | 0x00000000, | ||
1022 | 0x00000000, | ||
1023 | 0x00000000, | ||
1024 | 0x00000000, | ||
1025 | 0x00000000, | ||
1026 | 0x00000000, | ||
1027 | 0x00000000, | ||
1028 | 0x00000000, | ||
1029 | 0x00000000, | ||
1030 | 0x00000000, | ||
1031 | 0x00000000, | ||
1032 | 0x00000000, | ||
1033 | 0x00000000, | ||
1034 | 0x00000000, | ||
1035 | 0x00000000, | ||
1036 | 0x00000000, | ||
1037 | 0x00000000, | ||
1038 | 0x00000000, | ||
1039 | 0x00000000, | ||
1040 | 0x00000000, | ||
1041 | 0x00000000, | ||
1042 | 0x00000000, | ||
1043 | 0x00000000, | ||
980 | 0x00000000, | 1044 | 0x00000000, |
981 | 0x00000000, | 1045 | 0x00000000, |
982 | 0x00000000, | 1046 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h index 6547b3dfc7ed..51c3797d8537 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h | |||
@@ -528,10 +528,10 @@ uint32_t nve0_grhub_code[] = { | |||
528 | 0x0001d001, | 528 | 0x0001d001, |
529 | 0x17f104bd, | 529 | 0x17f104bd, |
530 | 0xf7f00100, | 530 | 0xf7f00100, |
531 | 0x7f21f502, | 531 | 0xd721f502, |
532 | 0x9121f507, | 532 | 0xe921f507, |
533 | 0x10f7f007, | 533 | 0x10f7f007, |
534 | 0x07de21f5, | 534 | 0x083621f5, |
535 | 0x98000e98, | 535 | 0x98000e98, |
536 | 0x21f5010f, | 536 | 0x21f5010f, |
537 | 0x14950150, | 537 | 0x14950150, |
@@ -574,9 +574,9 @@ uint32_t nve0_grhub_code[] = { | |||
574 | 0xb6800040, | 574 | 0xb6800040, |
575 | 0x1bf40132, | 575 | 0x1bf40132, |
576 | 0x00f7f0be, | 576 | 0x00f7f0be, |
577 | 0x07de21f5, | 577 | 0x083621f5, |
578 | 0xf500f7f0, | 578 | 0xf500f7f0, |
579 | 0xf1077f21, | 579 | 0xf107d721, |
580 | 0xf0010007, | 580 | 0xf0010007, |
581 | 0x01d00203, | 581 | 0x01d00203, |
582 | 0xbd04bd00, | 582 | 0xbd04bd00, |
@@ -610,8 +610,8 @@ uint32_t nve0_grhub_code[] = { | |||
610 | 0x09d00203, | 610 | 0x09d00203, |
611 | 0xf404bd00, | 611 | 0xf404bd00, |
612 | 0x31f40132, | 612 | 0x31f40132, |
613 | 0xaa21f502, | 613 | 0x0221f502, |
614 | 0xf094bd09, | 614 | 0xf094bd0a, |
615 | 0x07f10799, | 615 | 0x07f10799, |
616 | 0x03f01700, | 616 | 0x03f01700, |
617 | 0x0009d002, | 617 | 0x0009d002, |
@@ -621,7 +621,7 @@ uint32_t nve0_grhub_code[] = { | |||
621 | 0x0203f00f, | 621 | 0x0203f00f, |
622 | 0xbd0009d0, | 622 | 0xbd0009d0, |
623 | 0x0131f404, | 623 | 0x0131f404, |
624 | 0x09aa21f5, | 624 | 0x0a0221f5, |
625 | 0x99f094bd, | 625 | 0x99f094bd, |
626 | 0x0007f106, | 626 | 0x0007f106, |
627 | 0x0203f017, | 627 | 0x0203f017, |
@@ -631,7 +631,7 @@ uint32_t nve0_grhub_code[] = { | |||
631 | 0x12b920f9, | 631 | 0x12b920f9, |
632 | 0x0132f402, | 632 | 0x0132f402, |
633 | 0xf50232f4, | 633 | 0xf50232f4, |
634 | 0xfc09aa21, | 634 | 0xfc0a0221, |
635 | 0x0007f120, | 635 | 0x0007f120, |
636 | 0x0203f0c0, | 636 | 0x0203f0c0, |
637 | 0xbd0002d0, | 637 | 0xbd0002d0, |
@@ -640,7 +640,7 @@ uint32_t nve0_grhub_code[] = { | |||
640 | 0xf41f23c8, | 640 | 0xf41f23c8, |
641 | 0x31f40d0b, | 641 | 0x31f40d0b, |
642 | 0x0232f401, | 642 | 0x0232f401, |
643 | 0x09aa21f5, | 643 | 0x0a0221f5, |
644 | /* 0x063c: chsw_done */ | 644 | /* 0x063c: chsw_done */ |
645 | 0xf10127f0, | 645 | 0xf10127f0, |
646 | 0xf0c30007, | 646 | 0xf0c30007, |
@@ -654,7 +654,7 @@ uint32_t nve0_grhub_code[] = { | |||
654 | /* 0x0660: main_not_ctx_switch */ | 654 | /* 0x0660: main_not_ctx_switch */ |
655 | 0xf401e4b0, | 655 | 0xf401e4b0, |
656 | 0xf2b90d1b, | 656 | 0xf2b90d1b, |
657 | 0x4221f502, | 657 | 0x9a21f502, |
658 | 0x460ef409, | 658 | 0x460ef409, |
659 | /* 0x0670: main_not_ctx_chan */ | 659 | /* 0x0670: main_not_ctx_chan */ |
660 | 0xf402e4b0, | 660 | 0xf402e4b0, |
@@ -664,8 +664,8 @@ uint32_t nve0_grhub_code[] = { | |||
664 | 0x09d00203, | 664 | 0x09d00203, |
665 | 0xf404bd00, | 665 | 0xf404bd00, |
666 | 0x32f40132, | 666 | 0x32f40132, |
667 | 0xaa21f502, | 667 | 0x0221f502, |
668 | 0xf094bd09, | 668 | 0xf094bd0a, |
669 | 0x07f10799, | 669 | 0x07f10799, |
670 | 0x03f01700, | 670 | 0x03f01700, |
671 | 0x0009d002, | 671 | 0x0009d002, |
@@ -710,18 +710,40 @@ uint32_t nve0_grhub_code[] = { | |||
710 | /* 0x072b: ih_no_ctxsw */ | 710 | /* 0x072b: ih_no_ctxsw */ |
711 | 0xe40421f4, | 711 | 0xe40421f4, |
712 | 0xf40400ab, | 712 | 0xf40400ab, |
713 | 0xb7f1140b, | 713 | 0xe7f16c0b, |
714 | 0xe3f00708, | ||
715 | 0x6821f440, | ||
716 | 0xf102ffb9, | ||
717 | 0xf0040007, | ||
718 | 0x0fd00203, | ||
719 | 0xf104bd00, | ||
720 | 0xf00704e7, | ||
721 | 0x21f440e3, | ||
722 | 0x02ffb968, | ||
723 | 0x030007f1, | ||
724 | 0xd00203f0, | ||
725 | 0x04bd000f, | ||
726 | 0x9450fec7, | ||
727 | 0xf7f102ee, | ||
728 | 0xf3f00700, | ||
729 | 0x00efbb40, | ||
730 | 0xf16821f4, | ||
731 | 0xf0020007, | ||
732 | 0x0fd00203, | ||
733 | 0xf004bd00, | ||
734 | 0x21f503f7, | ||
735 | 0xb7f1037e, | ||
714 | 0xbfb90100, | 736 | 0xbfb90100, |
715 | 0x44e7f102, | 737 | 0x44e7f102, |
716 | 0x40e3f001, | 738 | 0x40e3f001, |
717 | /* 0x0743: ih_no_fwmthd */ | 739 | /* 0x079b: ih_no_fwmthd */ |
718 | 0xf19d21f4, | 740 | 0xf19d21f4, |
719 | 0xbd0104b7, | 741 | 0xbd0504b7, |
720 | 0xb4abffb0, | 742 | 0xb4abffb0, |
721 | 0xf10f0bf4, | 743 | 0xf10f0bf4, |
722 | 0xf0070007, | 744 | 0xf0070007, |
723 | 0x0bd00303, | 745 | 0x0bd00303, |
724 | /* 0x075b: ih_no_other */ | 746 | /* 0x07b3: ih_no_other */ |
725 | 0xf104bd00, | 747 | 0xf104bd00, |
726 | 0xf0010007, | 748 | 0xf0010007, |
727 | 0x0ad00003, | 749 | 0x0ad00003, |
@@ -731,19 +753,19 @@ uint32_t nve0_grhub_code[] = { | |||
731 | 0xfc90fca0, | 753 | 0xfc90fca0, |
732 | 0x0088fe80, | 754 | 0x0088fe80, |
733 | 0x32f480fc, | 755 | 0x32f480fc, |
734 | /* 0x077f: ctx_4170s */ | 756 | /* 0x07d7: ctx_4170s */ |
735 | 0xf001f800, | 757 | 0xf001f800, |
736 | 0xffb910f5, | 758 | 0xffb910f5, |
737 | 0x70e7f102, | 759 | 0x70e7f102, |
738 | 0x40e3f041, | 760 | 0x40e3f041, |
739 | 0xf89d21f4, | 761 | 0xf89d21f4, |
740 | /* 0x0791: ctx_4170w */ | 762 | /* 0x07e9: ctx_4170w */ |
741 | 0x70e7f100, | 763 | 0x70e7f100, |
742 | 0x40e3f041, | 764 | 0x40e3f041, |
743 | 0xb96821f4, | 765 | 0xb96821f4, |
744 | 0xf4f002ff, | 766 | 0xf4f002ff, |
745 | 0xf01bf410, | 767 | 0xf01bf410, |
746 | /* 0x07a6: ctx_redswitch */ | 768 | /* 0x07fe: ctx_redswitch */ |
747 | 0xe7f100f8, | 769 | 0xe7f100f8, |
748 | 0xe5f00200, | 770 | 0xe5f00200, |
749 | 0x20e5f040, | 771 | 0x20e5f040, |
@@ -751,7 +773,7 @@ uint32_t nve0_grhub_code[] = { | |||
751 | 0xf0850007, | 773 | 0xf0850007, |
752 | 0x0ed00103, | 774 | 0x0ed00103, |
753 | 0xf004bd00, | 775 | 0xf004bd00, |
754 | /* 0x07c2: ctx_redswitch_delay */ | 776 | /* 0x081a: ctx_redswitch_delay */ |
755 | 0xf2b608f7, | 777 | 0xf2b608f7, |
756 | 0xfd1bf401, | 778 | 0xfd1bf401, |
757 | 0x0400e5f1, | 779 | 0x0400e5f1, |
@@ -759,7 +781,7 @@ uint32_t nve0_grhub_code[] = { | |||
759 | 0x850007f1, | 781 | 0x850007f1, |
760 | 0xd00103f0, | 782 | 0xd00103f0, |
761 | 0x04bd000e, | 783 | 0x04bd000e, |
762 | /* 0x07de: ctx_86c */ | 784 | /* 0x0836: ctx_86c */ |
763 | 0x07f100f8, | 785 | 0x07f100f8, |
764 | 0x03f01b00, | 786 | 0x03f01b00, |
765 | 0x000fd002, | 787 | 0x000fd002, |
@@ -770,17 +792,17 @@ uint32_t nve0_grhub_code[] = { | |||
770 | 0xe7f102ff, | 792 | 0xe7f102ff, |
771 | 0xe3f0a86c, | 793 | 0xe3f0a86c, |
772 | 0x9d21f441, | 794 | 0x9d21f441, |
773 | /* 0x0806: ctx_mem */ | 795 | /* 0x085e: ctx_mem */ |
774 | 0x07f100f8, | 796 | 0x07f100f8, |
775 | 0x03f08400, | 797 | 0x03f08400, |
776 | 0x000fd002, | 798 | 0x000fd002, |
777 | /* 0x0812: ctx_mem_wait */ | 799 | /* 0x086a: ctx_mem_wait */ |
778 | 0xf7f104bd, | 800 | 0xf7f104bd, |
779 | 0xf3f08400, | 801 | 0xf3f08400, |
780 | 0x00ffcf02, | 802 | 0x00ffcf02, |
781 | 0xf405fffd, | 803 | 0xf405fffd, |
782 | 0x00f8f31b, | 804 | 0x00f8f31b, |
783 | /* 0x0824: ctx_load */ | 805 | /* 0x087c: ctx_load */ |
784 | 0x99f094bd, | 806 | 0x99f094bd, |
785 | 0x0007f105, | 807 | 0x0007f105, |
786 | 0x0203f00f, | 808 | 0x0203f00f, |
@@ -797,7 +819,7 @@ uint32_t nve0_grhub_code[] = { | |||
797 | 0x0203f083, | 819 | 0x0203f083, |
798 | 0xbd0002d0, | 820 | 0xbd0002d0, |
799 | 0x07f7f004, | 821 | 0x07f7f004, |
800 | 0x080621f5, | 822 | 0x085e21f5, |
801 | 0xc00007f1, | 823 | 0xc00007f1, |
802 | 0xd00203f0, | 824 | 0xd00203f0, |
803 | 0x04bd0002, | 825 | 0x04bd0002, |
@@ -852,29 +874,29 @@ uint32_t nve0_grhub_code[] = { | |||
852 | 0x170007f1, | 874 | 0x170007f1, |
853 | 0xd00203f0, | 875 | 0xd00203f0, |
854 | 0x04bd0009, | 876 | 0x04bd0009, |
855 | /* 0x0942: ctx_chan */ | 877 | /* 0x099a: ctx_chan */ |
856 | 0x21f500f8, | 878 | 0x21f500f8, |
857 | 0xa7f00824, | 879 | 0xa7f0087c, |
858 | 0xd021f40c, | 880 | 0xd021f40c, |
859 | 0xf505f7f0, | 881 | 0xf505f7f0, |
860 | 0xf8080621, | 882 | 0xf8085e21, |
861 | /* 0x0955: ctx_mmio_exec */ | 883 | /* 0x09ad: ctx_mmio_exec */ |
862 | 0x41039800, | 884 | 0x41039800, |
863 | 0x810007f1, | 885 | 0x810007f1, |
864 | 0xd00203f0, | 886 | 0xd00203f0, |
865 | 0x04bd0003, | 887 | 0x04bd0003, |
866 | /* 0x0966: ctx_mmio_loop */ | 888 | /* 0x09be: ctx_mmio_loop */ |
867 | 0x34c434bd, | 889 | 0x34c434bd, |
868 | 0x0f1bf4ff, | 890 | 0x0f1bf4ff, |
869 | 0x020057f1, | 891 | 0x020057f1, |
870 | 0xfa0653f0, | 892 | 0xfa0653f0, |
871 | 0x03f80535, | 893 | 0x03f80535, |
872 | /* 0x0978: ctx_mmio_pull */ | 894 | /* 0x09d0: ctx_mmio_pull */ |
873 | 0x98804e98, | 895 | 0x98804e98, |
874 | 0x21f4814f, | 896 | 0x21f4814f, |
875 | 0x0830b69d, | 897 | 0x0830b69d, |
876 | 0xf40112b6, | 898 | 0xf40112b6, |
877 | /* 0x098a: ctx_mmio_done */ | 899 | /* 0x09e2: ctx_mmio_done */ |
878 | 0x0398df1b, | 900 | 0x0398df1b, |
879 | 0x0007f116, | 901 | 0x0007f116, |
880 | 0x0203f081, | 902 | 0x0203f081, |
@@ -883,30 +905,30 @@ uint32_t nve0_grhub_code[] = { | |||
883 | 0x010017f1, | 905 | 0x010017f1, |
884 | 0xfa0613f0, | 906 | 0xfa0613f0, |
885 | 0x03f80601, | 907 | 0x03f80601, |
886 | /* 0x09aa: ctx_xfer */ | 908 | /* 0x0a02: ctx_xfer */ |
887 | 0xe7f000f8, | 909 | 0xe7f000f8, |
888 | 0x0007f104, | 910 | 0x0007f104, |
889 | 0x0303f002, | 911 | 0x0303f002, |
890 | 0xbd000ed0, | 912 | 0xbd000ed0, |
891 | /* 0x09b9: ctx_xfer_idle */ | 913 | /* 0x0a11: ctx_xfer_idle */ |
892 | 0x00e7f104, | 914 | 0x00e7f104, |
893 | 0x03e3f000, | 915 | 0x03e3f000, |
894 | 0xf100eecf, | 916 | 0xf100eecf, |
895 | 0xf42000e4, | 917 | 0xf42000e4, |
896 | 0x11f4f21b, | 918 | 0x11f4f21b, |
897 | 0x0d02f406, | 919 | 0x0d02f406, |
898 | /* 0x09d0: ctx_xfer_pre */ | 920 | /* 0x0a28: ctx_xfer_pre */ |
899 | 0xf510f7f0, | 921 | 0xf510f7f0, |
900 | 0xf407de21, | 922 | 0xf4083621, |
901 | /* 0x09da: ctx_xfer_pre_load */ | 923 | /* 0x0a32: ctx_xfer_pre_load */ |
902 | 0xf7f01c11, | 924 | 0xf7f01c11, |
903 | 0x7f21f502, | 925 | 0xd721f502, |
904 | 0x9121f507, | 926 | 0xe921f507, |
905 | 0xa621f507, | 927 | 0xfe21f507, |
906 | 0xf5f4bd07, | 928 | 0xf5f4bd07, |
907 | 0xf5077f21, | 929 | 0xf507d721, |
908 | /* 0x09f3: ctx_xfer_exec */ | 930 | /* 0x0a4b: ctx_xfer_exec */ |
909 | 0x98082421, | 931 | 0x98087c21, |
910 | 0x24bd1601, | 932 | 0x24bd1601, |
911 | 0x050007f1, | 933 | 0x050007f1, |
912 | 0xd00103f0, | 934 | 0xd00103f0, |
@@ -941,21 +963,21 @@ uint32_t nve0_grhub_code[] = { | |||
941 | 0xa7f01301, | 963 | 0xa7f01301, |
942 | 0xd021f40c, | 964 | 0xd021f40c, |
943 | 0xf505f7f0, | 965 | 0xf505f7f0, |
944 | 0xf4080621, | 966 | 0xf4085e21, |
945 | /* 0x0a82: ctx_xfer_post */ | 967 | /* 0x0ada: ctx_xfer_post */ |
946 | 0xf7f02e02, | 968 | 0xf7f02e02, |
947 | 0x7f21f502, | 969 | 0xd721f502, |
948 | 0xf5f4bd07, | 970 | 0xf5f4bd07, |
949 | 0xf507de21, | 971 | 0xf5083621, |
950 | 0xf5027f21, | 972 | 0xf5027f21, |
951 | 0xbd079121, | 973 | 0xbd07e921, |
952 | 0x7f21f5f4, | 974 | 0xd721f5f4, |
953 | 0x1011f407, | 975 | 0x1011f407, |
954 | 0xfd400198, | 976 | 0xfd400198, |
955 | 0x0bf40511, | 977 | 0x0bf40511, |
956 | 0x5521f507, | 978 | 0xad21f507, |
957 | /* 0x0aad: ctx_xfer_no_post_mmio */ | 979 | /* 0x0b05: ctx_xfer_no_post_mmio */ |
958 | /* 0x0aad: ctx_xfer_done */ | 980 | /* 0x0b05: ctx_xfer_done */ |
959 | 0x0000f809, | 981 | 0x0000f809, |
960 | 0x00000000, | 982 | 0x00000000, |
961 | 0x00000000, | 983 | 0x00000000, |
@@ -977,4 +999,46 @@ uint32_t nve0_grhub_code[] = { | |||
977 | 0x00000000, | 999 | 0x00000000, |
978 | 0x00000000, | 1000 | 0x00000000, |
979 | 0x00000000, | 1001 | 0x00000000, |
1002 | 0x00000000, | ||
1003 | 0x00000000, | ||
1004 | 0x00000000, | ||
1005 | 0x00000000, | ||
1006 | 0x00000000, | ||
1007 | 0x00000000, | ||
1008 | 0x00000000, | ||
1009 | 0x00000000, | ||
1010 | 0x00000000, | ||
1011 | 0x00000000, | ||
1012 | 0x00000000, | ||
1013 | 0x00000000, | ||
1014 | 0x00000000, | ||
1015 | 0x00000000, | ||
1016 | 0x00000000, | ||
1017 | 0x00000000, | ||
1018 | 0x00000000, | ||
1019 | 0x00000000, | ||
1020 | 0x00000000, | ||
1021 | 0x00000000, | ||
1022 | 0x00000000, | ||
1023 | 0x00000000, | ||
1024 | 0x00000000, | ||
1025 | 0x00000000, | ||
1026 | 0x00000000, | ||
1027 | 0x00000000, | ||
1028 | 0x00000000, | ||
1029 | 0x00000000, | ||
1030 | 0x00000000, | ||
1031 | 0x00000000, | ||
1032 | 0x00000000, | ||
1033 | 0x00000000, | ||
1034 | 0x00000000, | ||
1035 | 0x00000000, | ||
1036 | 0x00000000, | ||
1037 | 0x00000000, | ||
1038 | 0x00000000, | ||
1039 | 0x00000000, | ||
1040 | 0x00000000, | ||
1041 | 0x00000000, | ||
1042 | 0x00000000, | ||
1043 | 0x00000000, | ||
980 | }; | 1044 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h index a5aee5a4302f..a0af4b703a8e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h | |||
@@ -528,10 +528,10 @@ uint32_t nvf0_grhub_code[] = { | |||
528 | 0x0001d001, | 528 | 0x0001d001, |
529 | 0x17f104bd, | 529 | 0x17f104bd, |
530 | 0xf7f00100, | 530 | 0xf7f00100, |
531 | 0x7f21f502, | 531 | 0xd721f502, |
532 | 0x9121f507, | 532 | 0xe921f507, |
533 | 0x10f7f007, | 533 | 0x10f7f007, |
534 | 0x07de21f5, | 534 | 0x083621f5, |
535 | 0x98000e98, | 535 | 0x98000e98, |
536 | 0x21f5010f, | 536 | 0x21f5010f, |
537 | 0x14950150, | 537 | 0x14950150, |
@@ -574,9 +574,9 @@ uint32_t nvf0_grhub_code[] = { | |||
574 | 0xb6800040, | 574 | 0xb6800040, |
575 | 0x1bf40132, | 575 | 0x1bf40132, |
576 | 0x00f7f0be, | 576 | 0x00f7f0be, |
577 | 0x07de21f5, | 577 | 0x083621f5, |
578 | 0xf500f7f0, | 578 | 0xf500f7f0, |
579 | 0xf1077f21, | 579 | 0xf107d721, |
580 | 0xf0010007, | 580 | 0xf0010007, |
581 | 0x01d00203, | 581 | 0x01d00203, |
582 | 0xbd04bd00, | 582 | 0xbd04bd00, |
@@ -610,8 +610,8 @@ uint32_t nvf0_grhub_code[] = { | |||
610 | 0x09d00203, | 610 | 0x09d00203, |
611 | 0xf404bd00, | 611 | 0xf404bd00, |
612 | 0x31f40132, | 612 | 0x31f40132, |
613 | 0xaa21f502, | 613 | 0x0221f502, |
614 | 0xf094bd09, | 614 | 0xf094bd0a, |
615 | 0x07f10799, | 615 | 0x07f10799, |
616 | 0x03f01700, | 616 | 0x03f01700, |
617 | 0x0009d002, | 617 | 0x0009d002, |
@@ -621,7 +621,7 @@ uint32_t nvf0_grhub_code[] = { | |||
621 | 0x0203f037, | 621 | 0x0203f037, |
622 | 0xbd0009d0, | 622 | 0xbd0009d0, |
623 | 0x0131f404, | 623 | 0x0131f404, |
624 | 0x09aa21f5, | 624 | 0x0a0221f5, |
625 | 0x99f094bd, | 625 | 0x99f094bd, |
626 | 0x0007f106, | 626 | 0x0007f106, |
627 | 0x0203f017, | 627 | 0x0203f017, |
@@ -631,7 +631,7 @@ uint32_t nvf0_grhub_code[] = { | |||
631 | 0x12b920f9, | 631 | 0x12b920f9, |
632 | 0x0132f402, | 632 | 0x0132f402, |
633 | 0xf50232f4, | 633 | 0xf50232f4, |
634 | 0xfc09aa21, | 634 | 0xfc0a0221, |
635 | 0x0007f120, | 635 | 0x0007f120, |
636 | 0x0203f0c0, | 636 | 0x0203f0c0, |
637 | 0xbd0002d0, | 637 | 0xbd0002d0, |
@@ -640,7 +640,7 @@ uint32_t nvf0_grhub_code[] = { | |||
640 | 0xf41f23c8, | 640 | 0xf41f23c8, |
641 | 0x31f40d0b, | 641 | 0x31f40d0b, |
642 | 0x0232f401, | 642 | 0x0232f401, |
643 | 0x09aa21f5, | 643 | 0x0a0221f5, |
644 | /* 0x063c: chsw_done */ | 644 | /* 0x063c: chsw_done */ |
645 | 0xf10127f0, | 645 | 0xf10127f0, |
646 | 0xf0c30007, | 646 | 0xf0c30007, |
@@ -654,7 +654,7 @@ uint32_t nvf0_grhub_code[] = { | |||
654 | /* 0x0660: main_not_ctx_switch */ | 654 | /* 0x0660: main_not_ctx_switch */ |
655 | 0xf401e4b0, | 655 | 0xf401e4b0, |
656 | 0xf2b90d1b, | 656 | 0xf2b90d1b, |
657 | 0x4221f502, | 657 | 0x9a21f502, |
658 | 0x460ef409, | 658 | 0x460ef409, |
659 | /* 0x0670: main_not_ctx_chan */ | 659 | /* 0x0670: main_not_ctx_chan */ |
660 | 0xf402e4b0, | 660 | 0xf402e4b0, |
@@ -664,8 +664,8 @@ uint32_t nvf0_grhub_code[] = { | |||
664 | 0x09d00203, | 664 | 0x09d00203, |
665 | 0xf404bd00, | 665 | 0xf404bd00, |
666 | 0x32f40132, | 666 | 0x32f40132, |
667 | 0xaa21f502, | 667 | 0x0221f502, |
668 | 0xf094bd09, | 668 | 0xf094bd0a, |
669 | 0x07f10799, | 669 | 0x07f10799, |
670 | 0x03f01700, | 670 | 0x03f01700, |
671 | 0x0009d002, | 671 | 0x0009d002, |
@@ -710,18 +710,40 @@ uint32_t nvf0_grhub_code[] = { | |||
710 | /* 0x072b: ih_no_ctxsw */ | 710 | /* 0x072b: ih_no_ctxsw */ |
711 | 0xe40421f4, | 711 | 0xe40421f4, |
712 | 0xf40400ab, | 712 | 0xf40400ab, |
713 | 0xb7f1140b, | 713 | 0xe7f16c0b, |
714 | 0xe3f00708, | ||
715 | 0x6821f440, | ||
716 | 0xf102ffb9, | ||
717 | 0xf0040007, | ||
718 | 0x0fd00203, | ||
719 | 0xf104bd00, | ||
720 | 0xf00704e7, | ||
721 | 0x21f440e3, | ||
722 | 0x02ffb968, | ||
723 | 0x030007f1, | ||
724 | 0xd00203f0, | ||
725 | 0x04bd000f, | ||
726 | 0x9450fec7, | ||
727 | 0xf7f102ee, | ||
728 | 0xf3f00700, | ||
729 | 0x00efbb40, | ||
730 | 0xf16821f4, | ||
731 | 0xf0020007, | ||
732 | 0x0fd00203, | ||
733 | 0xf004bd00, | ||
734 | 0x21f503f7, | ||
735 | 0xb7f1037e, | ||
714 | 0xbfb90100, | 736 | 0xbfb90100, |
715 | 0x44e7f102, | 737 | 0x44e7f102, |
716 | 0x40e3f001, | 738 | 0x40e3f001, |
717 | /* 0x0743: ih_no_fwmthd */ | 739 | /* 0x079b: ih_no_fwmthd */ |
718 | 0xf19d21f4, | 740 | 0xf19d21f4, |
719 | 0xbd0104b7, | 741 | 0xbd0504b7, |
720 | 0xb4abffb0, | 742 | 0xb4abffb0, |
721 | 0xf10f0bf4, | 743 | 0xf10f0bf4, |
722 | 0xf0070007, | 744 | 0xf0070007, |
723 | 0x0bd00303, | 745 | 0x0bd00303, |
724 | /* 0x075b: ih_no_other */ | 746 | /* 0x07b3: ih_no_other */ |
725 | 0xf104bd00, | 747 | 0xf104bd00, |
726 | 0xf0010007, | 748 | 0xf0010007, |
727 | 0x0ad00003, | 749 | 0x0ad00003, |
@@ -731,19 +753,19 @@ uint32_t nvf0_grhub_code[] = { | |||
731 | 0xfc90fca0, | 753 | 0xfc90fca0, |
732 | 0x0088fe80, | 754 | 0x0088fe80, |
733 | 0x32f480fc, | 755 | 0x32f480fc, |
734 | /* 0x077f: ctx_4170s */ | 756 | /* 0x07d7: ctx_4170s */ |
735 | 0xf001f800, | 757 | 0xf001f800, |
736 | 0xffb910f5, | 758 | 0xffb910f5, |
737 | 0x70e7f102, | 759 | 0x70e7f102, |
738 | 0x40e3f041, | 760 | 0x40e3f041, |
739 | 0xf89d21f4, | 761 | 0xf89d21f4, |
740 | /* 0x0791: ctx_4170w */ | 762 | /* 0x07e9: ctx_4170w */ |
741 | 0x70e7f100, | 763 | 0x70e7f100, |
742 | 0x40e3f041, | 764 | 0x40e3f041, |
743 | 0xb96821f4, | 765 | 0xb96821f4, |
744 | 0xf4f002ff, | 766 | 0xf4f002ff, |
745 | 0xf01bf410, | 767 | 0xf01bf410, |
746 | /* 0x07a6: ctx_redswitch */ | 768 | /* 0x07fe: ctx_redswitch */ |
747 | 0xe7f100f8, | 769 | 0xe7f100f8, |
748 | 0xe5f00200, | 770 | 0xe5f00200, |
749 | 0x20e5f040, | 771 | 0x20e5f040, |
@@ -751,7 +773,7 @@ uint32_t nvf0_grhub_code[] = { | |||
751 | 0xf0850007, | 773 | 0xf0850007, |
752 | 0x0ed00103, | 774 | 0x0ed00103, |
753 | 0xf004bd00, | 775 | 0xf004bd00, |
754 | /* 0x07c2: ctx_redswitch_delay */ | 776 | /* 0x081a: ctx_redswitch_delay */ |
755 | 0xf2b608f7, | 777 | 0xf2b608f7, |
756 | 0xfd1bf401, | 778 | 0xfd1bf401, |
757 | 0x0400e5f1, | 779 | 0x0400e5f1, |
@@ -759,7 +781,7 @@ uint32_t nvf0_grhub_code[] = { | |||
759 | 0x850007f1, | 781 | 0x850007f1, |
760 | 0xd00103f0, | 782 | 0xd00103f0, |
761 | 0x04bd000e, | 783 | 0x04bd000e, |
762 | /* 0x07de: ctx_86c */ | 784 | /* 0x0836: ctx_86c */ |
763 | 0x07f100f8, | 785 | 0x07f100f8, |
764 | 0x03f02300, | 786 | 0x03f02300, |
765 | 0x000fd002, | 787 | 0x000fd002, |
@@ -770,17 +792,17 @@ uint32_t nvf0_grhub_code[] = { | |||
770 | 0xe7f102ff, | 792 | 0xe7f102ff, |
771 | 0xe3f0a88c, | 793 | 0xe3f0a88c, |
772 | 0x9d21f441, | 794 | 0x9d21f441, |
773 | /* 0x0806: ctx_mem */ | 795 | /* 0x085e: ctx_mem */ |
774 | 0x07f100f8, | 796 | 0x07f100f8, |
775 | 0x03f08400, | 797 | 0x03f08400, |
776 | 0x000fd002, | 798 | 0x000fd002, |
777 | /* 0x0812: ctx_mem_wait */ | 799 | /* 0x086a: ctx_mem_wait */ |
778 | 0xf7f104bd, | 800 | 0xf7f104bd, |
779 | 0xf3f08400, | 801 | 0xf3f08400, |
780 | 0x00ffcf02, | 802 | 0x00ffcf02, |
781 | 0xf405fffd, | 803 | 0xf405fffd, |
782 | 0x00f8f31b, | 804 | 0x00f8f31b, |
783 | /* 0x0824: ctx_load */ | 805 | /* 0x087c: ctx_load */ |
784 | 0x99f094bd, | 806 | 0x99f094bd, |
785 | 0x0007f105, | 807 | 0x0007f105, |
786 | 0x0203f037, | 808 | 0x0203f037, |
@@ -797,7 +819,7 @@ uint32_t nvf0_grhub_code[] = { | |||
797 | 0x0203f083, | 819 | 0x0203f083, |
798 | 0xbd0002d0, | 820 | 0xbd0002d0, |
799 | 0x07f7f004, | 821 | 0x07f7f004, |
800 | 0x080621f5, | 822 | 0x085e21f5, |
801 | 0xc00007f1, | 823 | 0xc00007f1, |
802 | 0xd00203f0, | 824 | 0xd00203f0, |
803 | 0x04bd0002, | 825 | 0x04bd0002, |
@@ -852,29 +874,29 @@ uint32_t nvf0_grhub_code[] = { | |||
852 | 0x170007f1, | 874 | 0x170007f1, |
853 | 0xd00203f0, | 875 | 0xd00203f0, |
854 | 0x04bd0009, | 876 | 0x04bd0009, |
855 | /* 0x0942: ctx_chan */ | 877 | /* 0x099a: ctx_chan */ |
856 | 0x21f500f8, | 878 | 0x21f500f8, |
857 | 0xa7f00824, | 879 | 0xa7f0087c, |
858 | 0xd021f40c, | 880 | 0xd021f40c, |
859 | 0xf505f7f0, | 881 | 0xf505f7f0, |
860 | 0xf8080621, | 882 | 0xf8085e21, |
861 | /* 0x0955: ctx_mmio_exec */ | 883 | /* 0x09ad: ctx_mmio_exec */ |
862 | 0x41039800, | 884 | 0x41039800, |
863 | 0x810007f1, | 885 | 0x810007f1, |
864 | 0xd00203f0, | 886 | 0xd00203f0, |
865 | 0x04bd0003, | 887 | 0x04bd0003, |
866 | /* 0x0966: ctx_mmio_loop */ | 888 | /* 0x09be: ctx_mmio_loop */ |
867 | 0x34c434bd, | 889 | 0x34c434bd, |
868 | 0x0f1bf4ff, | 890 | 0x0f1bf4ff, |
869 | 0x020057f1, | 891 | 0x020057f1, |
870 | 0xfa0653f0, | 892 | 0xfa0653f0, |
871 | 0x03f80535, | 893 | 0x03f80535, |
872 | /* 0x0978: ctx_mmio_pull */ | 894 | /* 0x09d0: ctx_mmio_pull */ |
873 | 0x98804e98, | 895 | 0x98804e98, |
874 | 0x21f4814f, | 896 | 0x21f4814f, |
875 | 0x0830b69d, | 897 | 0x0830b69d, |
876 | 0xf40112b6, | 898 | 0xf40112b6, |
877 | /* 0x098a: ctx_mmio_done */ | 899 | /* 0x09e2: ctx_mmio_done */ |
878 | 0x0398df1b, | 900 | 0x0398df1b, |
879 | 0x0007f116, | 901 | 0x0007f116, |
880 | 0x0203f081, | 902 | 0x0203f081, |
@@ -883,30 +905,30 @@ uint32_t nvf0_grhub_code[] = { | |||
883 | 0x010017f1, | 905 | 0x010017f1, |
884 | 0xfa0613f0, | 906 | 0xfa0613f0, |
885 | 0x03f80601, | 907 | 0x03f80601, |
886 | /* 0x09aa: ctx_xfer */ | 908 | /* 0x0a02: ctx_xfer */ |
887 | 0xe7f000f8, | 909 | 0xe7f000f8, |
888 | 0x0007f104, | 910 | 0x0007f104, |
889 | 0x0303f002, | 911 | 0x0303f002, |
890 | 0xbd000ed0, | 912 | 0xbd000ed0, |
891 | /* 0x09b9: ctx_xfer_idle */ | 913 | /* 0x0a11: ctx_xfer_idle */ |
892 | 0x00e7f104, | 914 | 0x00e7f104, |
893 | 0x03e3f000, | 915 | 0x03e3f000, |
894 | 0xf100eecf, | 916 | 0xf100eecf, |
895 | 0xf42000e4, | 917 | 0xf42000e4, |
896 | 0x11f4f21b, | 918 | 0x11f4f21b, |
897 | 0x0d02f406, | 919 | 0x0d02f406, |
898 | /* 0x09d0: ctx_xfer_pre */ | 920 | /* 0x0a28: ctx_xfer_pre */ |
899 | 0xf510f7f0, | 921 | 0xf510f7f0, |
900 | 0xf407de21, | 922 | 0xf4083621, |
901 | /* 0x09da: ctx_xfer_pre_load */ | 923 | /* 0x0a32: ctx_xfer_pre_load */ |
902 | 0xf7f01c11, | 924 | 0xf7f01c11, |
903 | 0x7f21f502, | 925 | 0xd721f502, |
904 | 0x9121f507, | 926 | 0xe921f507, |
905 | 0xa621f507, | 927 | 0xfe21f507, |
906 | 0xf5f4bd07, | 928 | 0xf5f4bd07, |
907 | 0xf5077f21, | 929 | 0xf507d721, |
908 | /* 0x09f3: ctx_xfer_exec */ | 930 | /* 0x0a4b: ctx_xfer_exec */ |
909 | 0x98082421, | 931 | 0x98087c21, |
910 | 0x24bd1601, | 932 | 0x24bd1601, |
911 | 0x050007f1, | 933 | 0x050007f1, |
912 | 0xd00103f0, | 934 | 0xd00103f0, |
@@ -941,21 +963,21 @@ uint32_t nvf0_grhub_code[] = { | |||
941 | 0xa7f01301, | 963 | 0xa7f01301, |
942 | 0xd021f40c, | 964 | 0xd021f40c, |
943 | 0xf505f7f0, | 965 | 0xf505f7f0, |
944 | 0xf4080621, | 966 | 0xf4085e21, |
945 | /* 0x0a82: ctx_xfer_post */ | 967 | /* 0x0ada: ctx_xfer_post */ |
946 | 0xf7f02e02, | 968 | 0xf7f02e02, |
947 | 0x7f21f502, | 969 | 0xd721f502, |
948 | 0xf5f4bd07, | 970 | 0xf5f4bd07, |
949 | 0xf507de21, | 971 | 0xf5083621, |
950 | 0xf5027f21, | 972 | 0xf5027f21, |
951 | 0xbd079121, | 973 | 0xbd07e921, |
952 | 0x7f21f5f4, | 974 | 0xd721f5f4, |
953 | 0x1011f407, | 975 | 0x1011f407, |
954 | 0xfd400198, | 976 | 0xfd400198, |
955 | 0x0bf40511, | 977 | 0x0bf40511, |
956 | 0x5521f507, | 978 | 0xad21f507, |
957 | /* 0x0aad: ctx_xfer_no_post_mmio */ | 979 | /* 0x0b05: ctx_xfer_no_post_mmio */ |
958 | /* 0x0aad: ctx_xfer_done */ | 980 | /* 0x0b05: ctx_xfer_done */ |
959 | 0x0000f809, | 981 | 0x0000f809, |
960 | 0x00000000, | 982 | 0x00000000, |
961 | 0x00000000, | 983 | 0x00000000, |
@@ -977,4 +999,46 @@ uint32_t nvf0_grhub_code[] = { | |||
977 | 0x00000000, | 999 | 0x00000000, |
978 | 0x00000000, | 1000 | 0x00000000, |
979 | 0x00000000, | 1001 | 0x00000000, |
1002 | 0x00000000, | ||
1003 | 0x00000000, | ||
1004 | 0x00000000, | ||
1005 | 0x00000000, | ||
1006 | 0x00000000, | ||
1007 | 0x00000000, | ||
1008 | 0x00000000, | ||
1009 | 0x00000000, | ||
1010 | 0x00000000, | ||
1011 | 0x00000000, | ||
1012 | 0x00000000, | ||
1013 | 0x00000000, | ||
1014 | 0x00000000, | ||
1015 | 0x00000000, | ||
1016 | 0x00000000, | ||
1017 | 0x00000000, | ||
1018 | 0x00000000, | ||
1019 | 0x00000000, | ||
1020 | 0x00000000, | ||
1021 | 0x00000000, | ||
1022 | 0x00000000, | ||
1023 | 0x00000000, | ||
1024 | 0x00000000, | ||
1025 | 0x00000000, | ||
1026 | 0x00000000, | ||
1027 | 0x00000000, | ||
1028 | 0x00000000, | ||
1029 | 0x00000000, | ||
1030 | 0x00000000, | ||
1031 | 0x00000000, | ||
1032 | 0x00000000, | ||
1033 | 0x00000000, | ||
1034 | 0x00000000, | ||
1035 | 0x00000000, | ||
1036 | 0x00000000, | ||
1037 | 0x00000000, | ||
1038 | 0x00000000, | ||
1039 | 0x00000000, | ||
1040 | 0x00000000, | ||
1041 | 0x00000000, | ||
1042 | 0x00000000, | ||
1043 | 0x00000000, | ||
980 | }; | 1044 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc index a47d49db5232..2a0b0f844299 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc | |||
@@ -30,6 +30,12 @@ | |||
30 | #define GK110 0xf0 | 30 | #define GK110 0xf0 |
31 | #define GK208 0x108 | 31 | #define GK208 0x108 |
32 | 32 | ||
33 | #define NV_PGRAPH_TRAPPED_ADDR 0x400704 | ||
34 | #define NV_PGRAPH_TRAPPED_DATA_LO 0x400708 | ||
35 | #define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c | ||
36 | |||
37 | #define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700) | ||
38 | |||
33 | #define NV_PGRAPH_FECS_INTR_ACK 0x409004 | 39 | #define NV_PGRAPH_FECS_INTR_ACK 0x409004 |
34 | #define NV_PGRAPH_FECS_INTR 0x409008 | 40 | #define NV_PGRAPH_FECS_INTR 0x409008 |
35 | #define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 | 41 | #define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h index fd1d380de094..1718ae4e8224 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h | |||
@@ -3,5 +3,6 @@ | |||
3 | 3 | ||
4 | #define E_BAD_COMMAND 0x00000001 | 4 | #define E_BAD_COMMAND 0x00000001 |
5 | #define E_CMD_OVERFLOW 0x00000002 | 5 | #define E_CMD_OVERFLOW 0x00000002 |
6 | #define E_BAD_FWMTHD 0x00000003 | ||
6 | 7 | ||
7 | #endif | 8 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c index 1a2d56493cf6..20665c21d80e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | |||
@@ -976,7 +976,6 @@ nv50_graph_init(struct nouveau_object *object) | |||
976 | break; | 976 | break; |
977 | case 0xa0: | 977 | case 0xa0: |
978 | default: | 978 | default: |
979 | nv_wr32(priv, 0x402cc0, 0x00000000); | ||
980 | if (nv_device(priv)->chipset == 0xa0 || | 979 | if (nv_device(priv)->chipset == 0xa0 || |
981 | nv_device(priv)->chipset == 0xaa || | 980 | nv_device(priv)->chipset == 0xaa || |
982 | nv_device(priv)->chipset == 0xac) { | 981 | nv_device(priv)->chipset == 0xac) { |
@@ -991,10 +990,10 @@ nv50_graph_init(struct nouveau_object *object) | |||
991 | 990 | ||
992 | /* zero out zcull regions */ | 991 | /* zero out zcull regions */ |
993 | for (i = 0; i < 8; i++) { | 992 | for (i = 0; i < 8; i++) { |
994 | nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000); | 993 | nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); |
995 | nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000); | 994 | nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); |
996 | nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000); | 995 | nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000); |
997 | nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000); | 996 | nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000); |
998 | } | 997 | } |
999 | return 0; | 998 | return 0; |
1000 | } | 999 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index bf7bdb1f291e..aa0838916354 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | |||
@@ -789,17 +789,40 @@ nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv) | |||
789 | static void | 789 | static void |
790 | nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) | 790 | nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) |
791 | { | 791 | { |
792 | u32 ustat = nv_rd32(priv, 0x409c18); | 792 | u32 stat = nv_rd32(priv, 0x409c18); |
793 | 793 | ||
794 | if (ustat & 0x00000001) | 794 | if (stat & 0x00000001) { |
795 | nv_error(priv, "CTXCTL ucode error\n"); | 795 | u32 code = nv_rd32(priv, 0x409814); |
796 | if (ustat & 0x00080000) | 796 | if (code == E_BAD_FWMTHD) { |
797 | nv_error(priv, "CTXCTL watchdog timeout\n"); | 797 | u32 class = nv_rd32(priv, 0x409808); |
798 | if (ustat & ~0x00080001) | 798 | u32 addr = nv_rd32(priv, 0x40980c); |
799 | nv_error(priv, "CTXCTL 0x%08x\n", ustat); | 799 | u32 subc = (addr & 0x00070000) >> 16; |
800 | u32 mthd = (addr & 0x00003ffc); | ||
801 | u32 data = nv_rd32(priv, 0x409810); | ||
802 | |||
803 | nv_error(priv, "FECS MTHD subc %d class 0x%04x " | ||
804 | "mthd 0x%04x data 0x%08x\n", | ||
805 | subc, class, mthd, data); | ||
800 | 806 | ||
801 | nvc0_graph_ctxctl_debug(priv); | 807 | nv_wr32(priv, 0x409c20, 0x00000001); |
802 | nv_wr32(priv, 0x409c20, ustat); | 808 | stat &= ~0x00000001; |
809 | } else { | ||
810 | nv_error(priv, "FECS ucode error %d\n", code); | ||
811 | } | ||
812 | } | ||
813 | |||
814 | if (stat & 0x00080000) { | ||
815 | nv_error(priv, "FECS watchdog timeout\n"); | ||
816 | nvc0_graph_ctxctl_debug(priv); | ||
817 | nv_wr32(priv, 0x409c20, 0x00080000); | ||
818 | stat &= ~0x00080000; | ||
819 | } | ||
820 | |||
821 | if (stat) { | ||
822 | nv_error(priv, "FECS 0x%08x\n", stat); | ||
823 | nvc0_graph_ctxctl_debug(priv); | ||
824 | nv_wr32(priv, 0x409c20, stat); | ||
825 | } | ||
803 | } | 826 | } |
804 | 827 | ||
805 | static void | 828 | static void |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h index 75203a99d902..ffc289198dd8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | |||
@@ -38,6 +38,8 @@ | |||
38 | #include <engine/fifo.h> | 38 | #include <engine/fifo.h> |
39 | #include <engine/graph.h> | 39 | #include <engine/graph.h> |
40 | 40 | ||
41 | #include "fuc/os.h" | ||
42 | |||
41 | #define GPC_MAX 32 | 43 | #define GPC_MAX 32 |
42 | #define TPC_MAX (GPC_MAX * 8) | 44 | #define TPC_MAX (GPC_MAX * 8) |
43 | 45 | ||
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h index db1b39d08013..825f7bb46b67 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h | |||
@@ -84,6 +84,7 @@ extern struct nouveau_oclass *nv4e_i2c_oclass; | |||
84 | extern struct nouveau_oclass *nv50_i2c_oclass; | 84 | extern struct nouveau_oclass *nv50_i2c_oclass; |
85 | extern struct nouveau_oclass *nv94_i2c_oclass; | 85 | extern struct nouveau_oclass *nv94_i2c_oclass; |
86 | extern struct nouveau_oclass *nvd0_i2c_oclass; | 86 | extern struct nouveau_oclass *nvd0_i2c_oclass; |
87 | extern struct nouveau_oclass *gf117_i2c_oclass; | ||
87 | extern struct nouveau_oclass *nve0_i2c_oclass; | 88 | extern struct nouveau_oclass *nve0_i2c_oclass; |
88 | 89 | ||
89 | static inline int | 90 | static inline int |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c index 4ac1aa30ea11..0e62a3240144 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c | |||
@@ -307,7 +307,6 @@ calc_clk(struct nve0_clock_priv *priv, | |||
307 | info->dsrc = src0; | 307 | info->dsrc = src0; |
308 | if (div0) { | 308 | if (div0) { |
309 | info->ddiv |= 0x80000000; | 309 | info->ddiv |= 0x80000000; |
310 | info->ddiv |= div0 << 8; | ||
311 | info->ddiv |= div0; | 310 | info->ddiv |= div0; |
312 | } | 311 | } |
313 | if (div1D) { | 312 | if (div1D) { |
@@ -352,7 +351,7 @@ nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk) | |||
352 | { | 351 | { |
353 | struct nve0_clock_info *info = &priv->eng[clk]; | 352 | struct nve0_clock_info *info = &priv->eng[clk]; |
354 | if (!info->ssel) { | 353 | if (!info->ssel) { |
355 | nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); | 354 | nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); |
356 | nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); | 355 | nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); |
357 | } | 356 | } |
358 | } | 357 | } |
@@ -389,7 +388,10 @@ static void | |||
389 | nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) | 388 | nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) |
390 | { | 389 | { |
391 | struct nve0_clock_info *info = &priv->eng[clk]; | 390 | struct nve0_clock_info *info = &priv->eng[clk]; |
392 | nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); | 391 | if (info->ssel) |
392 | nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); | ||
393 | else | ||
394 | nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); | ||
393 | } | 395 | } |
394 | 396 | ||
395 | static void | 397 | static void |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index 84c7efbc4f38..1ad3ea503133 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | |||
@@ -262,8 +262,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
262 | struct nve0_ram *ram = (void *)pfb->ram; | 262 | struct nve0_ram *ram = (void *)pfb->ram; |
263 | struct nve0_ramfuc *fuc = &ram->fuc; | 263 | struct nve0_ramfuc *fuc = &ram->fuc; |
264 | struct nouveau_ram_data *next = ram->base.next; | 264 | struct nouveau_ram_data *next = ram->base.next; |
265 | int vc = !(next->bios.ramcfg_11_02_08); | 265 | int vc = !next->bios.ramcfg_11_02_08; |
266 | int mv = !(next->bios.ramcfg_11_02_04); | 266 | int mv = !next->bios.ramcfg_11_02_04; |
267 | u32 mask, data; | 267 | u32 mask, data; |
268 | 268 | ||
269 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); | 269 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); |
@@ -370,8 +370,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
370 | } | 370 | } |
371 | } | 371 | } |
372 | 372 | ||
373 | if ( (next->bios.ramcfg_11_02_40) || | 373 | if (next->bios.ramcfg_11_02_40 || |
374 | (next->bios.ramcfg_11_07_10)) { | 374 | next->bios.ramcfg_11_07_10) { |
375 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); | 375 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); |
376 | ram_nsec(fuc, 20000); | 376 | ram_nsec(fuc, 20000); |
377 | } | 377 | } |
@@ -417,7 +417,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
417 | ram_mask(fuc, 0x10f694, 0xff00ff00, data); | 417 | ram_mask(fuc, 0x10f694, 0xff00ff00, data); |
418 | } | 418 | } |
419 | 419 | ||
420 | if (ram->mode == 2 && (next->bios.ramcfg_11_08_10)) | 420 | if (ram->mode == 2 && next->bios.ramcfg_11_08_10) |
421 | data = 0x00000080; | 421 | data = 0x00000080; |
422 | else | 422 | else |
423 | data = 0x00000000; | 423 | data = 0x00000000; |
@@ -425,13 +425,13 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
425 | 425 | ||
426 | mask = 0x00070000; | 426 | mask = 0x00070000; |
427 | data = 0x00000000; | 427 | data = 0x00000000; |
428 | if (!(next->bios.ramcfg_11_02_80)) | 428 | if (!next->bios.ramcfg_11_02_80) |
429 | data |= 0x03000000; | 429 | data |= 0x03000000; |
430 | if (!(next->bios.ramcfg_11_02_40)) | 430 | if (!next->bios.ramcfg_11_02_40) |
431 | data |= 0x00002000; | 431 | data |= 0x00002000; |
432 | if (!(next->bios.ramcfg_11_07_10)) | 432 | if (!next->bios.ramcfg_11_07_10) |
433 | data |= 0x00004000; | 433 | data |= 0x00004000; |
434 | if (!(next->bios.ramcfg_11_07_08)) | 434 | if (!next->bios.ramcfg_11_07_08) |
435 | data |= 0x00000003; | 435 | data |= 0x00000003; |
436 | else | 436 | else |
437 | data |= 0x74000000; | 437 | data |= 0x74000000; |
@@ -486,7 +486,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
486 | 486 | ||
487 | data = mask = 0x00000000; | 487 | data = mask = 0x00000000; |
488 | if (NOTE00(ramcfg_02_03 != 0)) { | 488 | if (NOTE00(ramcfg_02_03 != 0)) { |
489 | data |= (next->bios.ramcfg_11_02_03) << 8; | 489 | data |= next->bios.ramcfg_11_02_03 << 8; |
490 | mask |= 0x00000300; | 490 | mask |= 0x00000300; |
491 | } | 491 | } |
492 | if (NOTE00(ramcfg_01_10)) { | 492 | if (NOTE00(ramcfg_01_10)) { |
@@ -498,7 +498,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
498 | 498 | ||
499 | data = mask = 0x00000000; | 499 | data = mask = 0x00000000; |
500 | if (NOTE00(timing_30_07 != 0)) { | 500 | if (NOTE00(timing_30_07 != 0)) { |
501 | data |= (next->bios.timing_20_30_07) << 28; | 501 | data |= next->bios.timing_20_30_07 << 28; |
502 | mask |= 0x70000000; | 502 | mask |= 0x70000000; |
503 | } | 503 | } |
504 | if (NOTE00(ramcfg_01_01)) { | 504 | if (NOTE00(ramcfg_01_01)) { |
@@ -510,7 +510,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
510 | 510 | ||
511 | data = mask = 0x00000000; | 511 | data = mask = 0x00000000; |
512 | if (NOTE00(timing_30_07 != 0)) { | 512 | if (NOTE00(timing_30_07 != 0)) { |
513 | data |= (next->bios.timing_20_30_07) << 28; | 513 | data |= next->bios.timing_20_30_07 << 28; |
514 | mask |= 0x70000000; | 514 | mask |= 0x70000000; |
515 | } | 515 | } |
516 | if (NOTE00(ramcfg_01_02)) { | 516 | if (NOTE00(ramcfg_01_02)) { |
@@ -522,16 +522,16 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
522 | 522 | ||
523 | mask = 0x33f00000; | 523 | mask = 0x33f00000; |
524 | data = 0x00000000; | 524 | data = 0x00000000; |
525 | if (!(next->bios.ramcfg_11_01_04)) | 525 | if (!next->bios.ramcfg_11_01_04) |
526 | data |= 0x20200000; | 526 | data |= 0x20200000; |
527 | if (!(next->bios.ramcfg_11_07_80)) | 527 | if (!next->bios.ramcfg_11_07_80) |
528 | data |= 0x12800000; | 528 | data |= 0x12800000; |
529 | /*XXX: see note above about there probably being some condition | 529 | /*XXX: see note above about there probably being some condition |
530 | * for the 10f824 stuff that uses ramcfg 3... | 530 | * for the 10f824 stuff that uses ramcfg 3... |
531 | */ | 531 | */ |
532 | if ( (next->bios.ramcfg_11_03_f0)) { | 532 | if (next->bios.ramcfg_11_03_f0) { |
533 | if (next->bios.rammap_11_08_0c) { | 533 | if (next->bios.rammap_11_08_0c) { |
534 | if (!(next->bios.ramcfg_11_07_80)) | 534 | if (!next->bios.ramcfg_11_07_80) |
535 | mask |= 0x00000020; | 535 | mask |= 0x00000020; |
536 | else | 536 | else |
537 | data |= 0x00000020; | 537 | data |= 0x00000020; |
@@ -563,7 +563,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
563 | ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); | 563 | ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); |
564 | } | 564 | } |
565 | 565 | ||
566 | data = (next->bios.timing_20_30_07) << 8; | 566 | data = next->bios.timing_20_30_07 << 8; |
567 | if (next->bios.ramcfg_11_01_01) | 567 | if (next->bios.ramcfg_11_01_01) |
568 | data |= 0x80000000; | 568 | data |= 0x80000000; |
569 | ram_mask(fuc, 0x100778, 0x00000700, data); | 569 | ram_mask(fuc, 0x100778, 0x00000700, data); |
@@ -588,7 +588,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
588 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ | 588 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ |
589 | ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ | 589 | ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ |
590 | 590 | ||
591 | if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) { | 591 | if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { |
592 | u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); | 592 | u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); |
593 | nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ | 593 | nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ |
594 | ram_nsec(fuc, 1000); | 594 | ram_nsec(fuc, 1000); |
@@ -621,8 +621,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
621 | data = ram_rd32(fuc, 0x10f978); | 621 | data = ram_rd32(fuc, 0x10f978); |
622 | data &= ~0x00046144; | 622 | data &= ~0x00046144; |
623 | data |= 0x0000000b; | 623 | data |= 0x0000000b; |
624 | if (!(next->bios.ramcfg_11_07_08)) { | 624 | if (!next->bios.ramcfg_11_07_08) { |
625 | if (!(next->bios.ramcfg_11_07_04)) | 625 | if (!next->bios.ramcfg_11_07_04) |
626 | data |= 0x0000200c; | 626 | data |= 0x0000200c; |
627 | else | 627 | else |
628 | data |= 0x00000000; | 628 | data |= 0x00000000; |
@@ -636,11 +636,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
636 | ram_wr32(fuc, 0x10f830, data); | 636 | ram_wr32(fuc, 0x10f830, data); |
637 | } | 637 | } |
638 | 638 | ||
639 | if (!(next->bios.ramcfg_11_07_08)) { | 639 | if (!next->bios.ramcfg_11_07_08) { |
640 | data = 0x88020000; | 640 | data = 0x88020000; |
641 | if ( (next->bios.ramcfg_11_07_04)) | 641 | if ( next->bios.ramcfg_11_07_04) |
642 | data |= 0x10000000; | 642 | data |= 0x10000000; |
643 | if (!(next->bios.rammap_11_08_10)) | 643 | if (!next->bios.rammap_11_08_10) |
644 | data |= 0x00080000; | 644 | data |= 0x00080000; |
645 | } else { | 645 | } else { |
646 | data = 0xa40e0000; | 646 | data = 0xa40e0000; |
@@ -689,8 +689,8 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
689 | const u32 runk0 = ram->fN1 << 16; | 689 | const u32 runk0 = ram->fN1 << 16; |
690 | const u32 runk1 = ram->fN1; | 690 | const u32 runk1 = ram->fN1; |
691 | struct nouveau_ram_data *next = ram->base.next; | 691 | struct nouveau_ram_data *next = ram->base.next; |
692 | int vc = !(next->bios.ramcfg_11_02_08); | 692 | int vc = !next->bios.ramcfg_11_02_08; |
693 | int mv = !(next->bios.ramcfg_11_02_04); | 693 | int mv = !next->bios.ramcfg_11_02_04; |
694 | u32 mask, data; | 694 | u32 mask, data; |
695 | 695 | ||
696 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); | 696 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); |
@@ -705,7 +705,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
705 | } | 705 | } |
706 | 706 | ||
707 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); | 707 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); |
708 | if ((next->bios.ramcfg_11_03_f0)) | 708 | if (next->bios.ramcfg_11_03_f0) |
709 | ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); | 709 | ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); |
710 | 710 | ||
711 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ | 711 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ |
@@ -761,7 +761,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
761 | 761 | ||
762 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); | 762 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); |
763 | data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; | 763 | data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; |
764 | data |= (next->bios.ramcfg_11_03_30) << 12; | 764 | data |= next->bios.ramcfg_11_03_30 << 16; |
765 | ram_wr32(fuc, 0x1373ec, data); | 765 | ram_wr32(fuc, 0x1373ec, data); |
766 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); | 766 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); |
767 | ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); | 767 | ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); |
@@ -793,8 +793,8 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
793 | } | 793 | } |
794 | } | 794 | } |
795 | 795 | ||
796 | if ( (next->bios.ramcfg_11_02_40) || | 796 | if (next->bios.ramcfg_11_02_40 || |
797 | (next->bios.ramcfg_11_07_10)) { | 797 | next->bios.ramcfg_11_07_10) { |
798 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); | 798 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); |
799 | ram_nsec(fuc, 20000); | 799 | ram_nsec(fuc, 20000); |
800 | } | 800 | } |
@@ -810,13 +810,13 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
810 | 810 | ||
811 | mask = 0x00010000; | 811 | mask = 0x00010000; |
812 | data = 0x00000000; | 812 | data = 0x00000000; |
813 | if (!(next->bios.ramcfg_11_02_80)) | 813 | if (!next->bios.ramcfg_11_02_80) |
814 | data |= 0x03000000; | 814 | data |= 0x03000000; |
815 | if (!(next->bios.ramcfg_11_02_40)) | 815 | if (!next->bios.ramcfg_11_02_40) |
816 | data |= 0x00002000; | 816 | data |= 0x00002000; |
817 | if (!(next->bios.ramcfg_11_07_10)) | 817 | if (!next->bios.ramcfg_11_07_10) |
818 | data |= 0x00004000; | 818 | data |= 0x00004000; |
819 | if (!(next->bios.ramcfg_11_07_08)) | 819 | if (!next->bios.ramcfg_11_07_08) |
820 | data |= 0x00000003; | 820 | data |= 0x00000003; |
821 | else | 821 | else |
822 | data |= 0x14000000; | 822 | data |= 0x14000000; |
@@ -844,16 +844,16 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
844 | 844 | ||
845 | mask = 0x33f00000; | 845 | mask = 0x33f00000; |
846 | data = 0x00000000; | 846 | data = 0x00000000; |
847 | if (!(next->bios.ramcfg_11_01_04)) | 847 | if (!next->bios.ramcfg_11_01_04) |
848 | data |= 0x20200000; | 848 | data |= 0x20200000; |
849 | if (!(next->bios.ramcfg_11_07_80)) | 849 | if (!next->bios.ramcfg_11_07_80) |
850 | data |= 0x12800000; | 850 | data |= 0x12800000; |
851 | /*XXX: see note above about there probably being some condition | 851 | /*XXX: see note above about there probably being some condition |
852 | * for the 10f824 stuff that uses ramcfg 3... | 852 | * for the 10f824 stuff that uses ramcfg 3... |
853 | */ | 853 | */ |
854 | if ( (next->bios.ramcfg_11_03_f0)) { | 854 | if (next->bios.ramcfg_11_03_f0) { |
855 | if (next->bios.rammap_11_08_0c) { | 855 | if (next->bios.rammap_11_08_0c) { |
856 | if (!(next->bios.ramcfg_11_07_80)) | 856 | if (!next->bios.ramcfg_11_07_80) |
857 | mask |= 0x00000020; | 857 | mask |= 0x00000020; |
858 | else | 858 | else |
859 | data |= 0x00000020; | 859 | data |= 0x00000020; |
@@ -876,7 +876,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
876 | data = next->bios.timing_20_2c_1fc0; | 876 | data = next->bios.timing_20_2c_1fc0; |
877 | ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); | 877 | ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); |
878 | 878 | ||
879 | ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8); | 879 | ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); |
880 | 880 | ||
881 | ram_wr32(fuc, 0x10f090, 0x4000007f); | 881 | ram_wr32(fuc, 0x10f090, 0x4000007f); |
882 | ram_nsec(fuc, 1000); | 882 | ram_nsec(fuc, 1000); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c new file mode 100644 index 000000000000..fa891c39866b --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include "nv50.h" | ||
26 | |||
27 | struct nouveau_oclass * | ||
28 | gf117_i2c_oclass = &(struct nouveau_i2c_impl) { | ||
29 | .base.handle = NV_SUBDEV(I2C, 0xd7), | ||
30 | .base.ofuncs = &(struct nouveau_ofuncs) { | ||
31 | .ctor = _nouveau_i2c_ctor, | ||
32 | .dtor = _nouveau_i2c_dtor, | ||
33 | .init = _nouveau_i2c_init, | ||
34 | .fini = _nouveau_i2c_fini, | ||
35 | }, | ||
36 | .sclass = nvd0_i2c_sclass, | ||
37 | .pad_x = &nv04_i2c_pad_oclass, | ||
38 | .pad_s = &nv04_i2c_pad_oclass, | ||
39 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c index 7120124dceac..ebef970a0645 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c | |||
@@ -95,6 +95,23 @@ nve0_ibus_intr(struct nouveau_subdev *subdev) | |||
95 | } | 95 | } |
96 | 96 | ||
97 | static int | 97 | static int |
98 | nve0_ibus_init(struct nouveau_object *object) | ||
99 | { | ||
100 | struct nve0_ibus_priv *priv = (void *)object; | ||
101 | int ret = nouveau_ibus_init(&priv->base); | ||
102 | if (ret == 0) { | ||
103 | nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000); | ||
104 | nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200); | ||
105 | nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800); | ||
106 | nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100); | ||
107 | nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff); | ||
108 | nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200); | ||
109 | nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880); | ||
110 | } | ||
111 | return ret; | ||
112 | } | ||
113 | |||
114 | static int | ||
98 | nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 115 | nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
99 | struct nouveau_oclass *oclass, void *data, u32 size, | 116 | struct nouveau_oclass *oclass, void *data, u32 size, |
100 | struct nouveau_object **pobject) | 117 | struct nouveau_object **pobject) |
@@ -117,7 +134,7 @@ nve0_ibus_oclass = { | |||
117 | .ofuncs = &(struct nouveau_ofuncs) { | 134 | .ofuncs = &(struct nouveau_ofuncs) { |
118 | .ctor = nve0_ibus_ctor, | 135 | .ctor = nve0_ibus_ctor, |
119 | .dtor = _nouveau_ibus_dtor, | 136 | .dtor = _nouveau_ibus_dtor, |
120 | .init = _nouveau_ibus_init, | 137 | .init = nve0_ibus_init, |
121 | .fini = _nouveau_ibus_fini, | 138 | .fini = _nouveau_ibus_fini, |
122 | }, | 139 | }, |
123 | }; | 140 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc index 2284ecb1c9b8..c2bb616a8da5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc | |||
@@ -83,7 +83,7 @@ host_send: | |||
83 | // increment GET | 83 | // increment GET |
84 | add b32 $r1 0x1 | 84 | add b32 $r1 0x1 |
85 | and $r14 $r1 #fifo_qmaskf | 85 | and $r14 $r1 #fifo_qmaskf |
86 | nv_iowr(NV_PPWR_FIFO_GET(0), $r1) | 86 | nv_iowr(NV_PPWR_FIFO_GET(0), $r14) |
87 | bra #host_send | 87 | bra #host_send |
88 | host_send_done: | 88 | host_send_done: |
89 | ret | 89 | ret |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h index 4bd43a99fdcc..39a5dc150a05 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h | |||
@@ -1018,7 +1018,7 @@ uint32_t nv108_pwr_code[] = { | |||
1018 | 0xb600023f, | 1018 | 0xb600023f, |
1019 | 0x1ec40110, | 1019 | 0x1ec40110, |
1020 | 0x04b0400f, | 1020 | 0x04b0400f, |
1021 | 0xbd0001f6, | 1021 | 0xbd000ef6, |
1022 | 0xc70ef404, | 1022 | 0xc70ef404, |
1023 | /* 0x0328: host_send_done */ | 1023 | /* 0x0328: host_send_done */ |
1024 | /* 0x032a: host_recv */ | 1024 | /* 0x032a: host_recv */ |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h index 5a73fa620978..254205cd5166 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h | |||
@@ -1124,7 +1124,7 @@ uint32_t nva3_pwr_code[] = { | |||
1124 | 0x0f1ec401, | 1124 | 0x0f1ec401, |
1125 | 0x04b007f1, | 1125 | 0x04b007f1, |
1126 | 0xd00604b6, | 1126 | 0xd00604b6, |
1127 | 0x04bd0001, | 1127 | 0x04bd000e, |
1128 | /* 0x03cb: host_send_done */ | 1128 | /* 0x03cb: host_send_done */ |
1129 | 0xf8ba0ef4, | 1129 | 0xf8ba0ef4, |
1130 | /* 0x03cd: host_recv */ | 1130 | /* 0x03cd: host_recv */ |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h index 4dba00d2dd1a..7ac87405d01b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h | |||
@@ -1124,7 +1124,7 @@ uint32_t nvc0_pwr_code[] = { | |||
1124 | 0x0f1ec401, | 1124 | 0x0f1ec401, |
1125 | 0x04b007f1, | 1125 | 0x04b007f1, |
1126 | 0xd00604b6, | 1126 | 0xd00604b6, |
1127 | 0x04bd0001, | 1127 | 0x04bd000e, |
1128 | /* 0x03cb: host_send_done */ | 1128 | /* 0x03cb: host_send_done */ |
1129 | 0xf8ba0ef4, | 1129 | 0xf8ba0ef4, |
1130 | /* 0x03cd: host_recv */ | 1130 | /* 0x03cd: host_recv */ |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h index 5e24c6bc041d..cd9ff1a73284 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h | |||
@@ -1033,7 +1033,7 @@ uint32_t nvd0_pwr_code[] = { | |||
1033 | 0xb6026b21, | 1033 | 0xb6026b21, |
1034 | 0x1ec40110, | 1034 | 0x1ec40110, |
1035 | 0xb007f10f, | 1035 | 0xb007f10f, |
1036 | 0x0001d004, | 1036 | 0x000ed004, |
1037 | 0x0ef404bd, | 1037 | 0x0ef404bd, |
1038 | /* 0x0365: host_send_done */ | 1038 | /* 0x0365: host_send_done */ |
1039 | /* 0x0367: host_recv */ | 1039 | /* 0x0367: host_recv */ |
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 26b5647188ef..47ad74255bf1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c | |||
@@ -736,6 +736,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
736 | fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y, | 736 | fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y, |
737 | new_bo->bo.offset }; | 737 | new_bo->bo.offset }; |
738 | 738 | ||
739 | /* Keep vblanks on during flip, for the target crtc of this flip */ | ||
740 | drm_vblank_get(dev, nouveau_crtc(crtc)->index); | ||
741 | |||
739 | /* Emit a page flip */ | 742 | /* Emit a page flip */ |
740 | if (nv_device(drm->device)->card_type >= NV_50) { | 743 | if (nv_device(drm->device)->card_type >= NV_50) { |
741 | ret = nv50_display_flip_next(crtc, fb, chan, swap_interval); | 744 | ret = nv50_display_flip_next(crtc, fb, chan, swap_interval); |
@@ -779,6 +782,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
779 | return 0; | 782 | return 0; |
780 | 783 | ||
781 | fail_unreserve: | 784 | fail_unreserve: |
785 | drm_vblank_put(dev, nouveau_crtc(crtc)->index); | ||
782 | ttm_bo_unreserve(&old_bo->bo); | 786 | ttm_bo_unreserve(&old_bo->bo); |
783 | fail_unpin: | 787 | fail_unpin: |
784 | mutex_unlock(&chan->cli->mutex); | 788 | mutex_unlock(&chan->cli->mutex); |
@@ -817,6 +821,9 @@ nouveau_finish_page_flip(struct nouveau_channel *chan, | |||
817 | drm_send_vblank_event(dev, crtcid, s->event); | 821 | drm_send_vblank_event(dev, crtcid, s->event); |
818 | } | 822 | } |
819 | 823 | ||
824 | /* Give up ownership of vblank for page-flipped crtc */ | ||
825 | drm_vblank_put(dev, s->crtc); | ||
826 | |||
820 | list_del(&s->head); | 827 | list_del(&s->head); |
821 | if (ps) | 828 | if (ps) |
822 | *ps = *s; | 829 | *ps = *s; |
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 26c12a3fe430..a03c73411a56 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -1052,7 +1052,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode | |||
1052 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); | 1052 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
1053 | 1053 | ||
1054 | /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ | 1054 | /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ |
1055 | if (ASIC_IS_DCE5(rdev) && !ASIC_IS_DCE8(rdev) && | 1055 | if (ASIC_IS_DCE5(rdev) && |
1056 | (encoder_mode == ATOM_ENCODER_MODE_HDMI) && | 1056 | (encoder_mode == ATOM_ENCODER_MODE_HDMI) && |
1057 | (radeon_crtc->bpc > 8)) | 1057 | (radeon_crtc->bpc > 8)) |
1058 | clock = radeon_crtc->adjusted_clock; | 1058 | clock = radeon_crtc->adjusted_clock; |
@@ -1136,6 +1136,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1136 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); | 1136 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
1137 | u32 tmp, viewport_w, viewport_h; | 1137 | u32 tmp, viewport_w, viewport_h; |
1138 | int r; | 1138 | int r; |
1139 | bool bypass_lut = false; | ||
1139 | 1140 | ||
1140 | /* no fb bound */ | 1141 | /* no fb bound */ |
1141 | if (!atomic && !crtc->primary->fb) { | 1142 | if (!atomic && !crtc->primary->fb) { |
@@ -1174,33 +1175,73 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1174 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); | 1175 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1175 | radeon_bo_unreserve(rbo); | 1176 | radeon_bo_unreserve(rbo); |
1176 | 1177 | ||
1177 | switch (target_fb->bits_per_pixel) { | 1178 | switch (target_fb->pixel_format) { |
1178 | case 8: | 1179 | case DRM_FORMAT_C8: |
1179 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | | 1180 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
1180 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); | 1181 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
1181 | break; | 1182 | break; |
1182 | case 15: | 1183 | case DRM_FORMAT_XRGB4444: |
1184 | case DRM_FORMAT_ARGB4444: | ||
1185 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | ||
1186 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); | ||
1187 | #ifdef __BIG_ENDIAN | ||
1188 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); | ||
1189 | #endif | ||
1190 | break; | ||
1191 | case DRM_FORMAT_XRGB1555: | ||
1192 | case DRM_FORMAT_ARGB1555: | ||
1183 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | 1193 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1184 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); | 1194 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
1195 | #ifdef __BIG_ENDIAN | ||
1196 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); | ||
1197 | #endif | ||
1198 | break; | ||
1199 | case DRM_FORMAT_BGRX5551: | ||
1200 | case DRM_FORMAT_BGRA5551: | ||
1201 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | ||
1202 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); | ||
1203 | #ifdef __BIG_ENDIAN | ||
1204 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); | ||
1205 | #endif | ||
1185 | break; | 1206 | break; |
1186 | case 16: | 1207 | case DRM_FORMAT_RGB565: |
1187 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | 1208 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1188 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); | 1209 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
1189 | #ifdef __BIG_ENDIAN | 1210 | #ifdef __BIG_ENDIAN |
1190 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); | 1211 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1191 | #endif | 1212 | #endif |
1192 | break; | 1213 | break; |
1193 | case 24: | 1214 | case DRM_FORMAT_XRGB8888: |
1194 | case 32: | 1215 | case DRM_FORMAT_ARGB8888: |
1195 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | | 1216 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1196 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); | 1217 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
1197 | #ifdef __BIG_ENDIAN | 1218 | #ifdef __BIG_ENDIAN |
1198 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); | 1219 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1199 | #endif | 1220 | #endif |
1200 | break; | 1221 | break; |
1222 | case DRM_FORMAT_XRGB2101010: | ||
1223 | case DRM_FORMAT_ARGB2101010: | ||
1224 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | | ||
1225 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); | ||
1226 | #ifdef __BIG_ENDIAN | ||
1227 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); | ||
1228 | #endif | ||
1229 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ | ||
1230 | bypass_lut = true; | ||
1231 | break; | ||
1232 | case DRM_FORMAT_BGRX1010102: | ||
1233 | case DRM_FORMAT_BGRA1010102: | ||
1234 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | | ||
1235 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); | ||
1236 | #ifdef __BIG_ENDIAN | ||
1237 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); | ||
1238 | #endif | ||
1239 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ | ||
1240 | bypass_lut = true; | ||
1241 | break; | ||
1201 | default: | 1242 | default: |
1202 | DRM_ERROR("Unsupported screen depth %d\n", | 1243 | DRM_ERROR("Unsupported screen format %s\n", |
1203 | target_fb->bits_per_pixel); | 1244 | drm_get_format_name(target_fb->pixel_format)); |
1204 | return -EINVAL; | 1245 | return -EINVAL; |
1205 | } | 1246 | } |
1206 | 1247 | ||
@@ -1329,6 +1370,18 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1329 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); | 1370 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1330 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); | 1371 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1331 | 1372 | ||
1373 | /* | ||
1374 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT | ||
1375 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to | ||
1376 | * retain the full precision throughout the pipeline. | ||
1377 | */ | ||
1378 | WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, | ||
1379 | (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), | ||
1380 | ~EVERGREEN_LUT_10BIT_BYPASS_EN); | ||
1381 | |||
1382 | if (bypass_lut) | ||
1383 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); | ||
1384 | |||
1332 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | 1385 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1333 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | 1386 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1334 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); | 1387 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
@@ -1396,6 +1449,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, | |||
1396 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; | 1449 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
1397 | u32 tmp, viewport_w, viewport_h; | 1450 | u32 tmp, viewport_w, viewport_h; |
1398 | int r; | 1451 | int r; |
1452 | bool bypass_lut = false; | ||
1399 | 1453 | ||
1400 | /* no fb bound */ | 1454 | /* no fb bound */ |
1401 | if (!atomic && !crtc->primary->fb) { | 1455 | if (!atomic && !crtc->primary->fb) { |
@@ -1433,18 +1487,30 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, | |||
1433 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); | 1487 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1434 | radeon_bo_unreserve(rbo); | 1488 | radeon_bo_unreserve(rbo); |
1435 | 1489 | ||
1436 | switch (target_fb->bits_per_pixel) { | 1490 | switch (target_fb->pixel_format) { |
1437 | case 8: | 1491 | case DRM_FORMAT_C8: |
1438 | fb_format = | 1492 | fb_format = |
1439 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | | 1493 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
1440 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; | 1494 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
1441 | break; | 1495 | break; |
1442 | case 15: | 1496 | case DRM_FORMAT_XRGB4444: |
1497 | case DRM_FORMAT_ARGB4444: | ||
1498 | fb_format = | ||
1499 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | ||
1500 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; | ||
1501 | #ifdef __BIG_ENDIAN | ||
1502 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; | ||
1503 | #endif | ||
1504 | break; | ||
1505 | case DRM_FORMAT_XRGB1555: | ||
1443 | fb_format = | 1506 | fb_format = |
1444 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | 1507 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1445 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; | 1508 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
1509 | #ifdef __BIG_ENDIAN | ||
1510 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; | ||
1511 | #endif | ||
1446 | break; | 1512 | break; |
1447 | case 16: | 1513 | case DRM_FORMAT_RGB565: |
1448 | fb_format = | 1514 | fb_format = |
1449 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | 1515 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1450 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; | 1516 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
@@ -1452,8 +1518,8 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, | |||
1452 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; | 1518 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1453 | #endif | 1519 | #endif |
1454 | break; | 1520 | break; |
1455 | case 24: | 1521 | case DRM_FORMAT_XRGB8888: |
1456 | case 32: | 1522 | case DRM_FORMAT_ARGB8888: |
1457 | fb_format = | 1523 | fb_format = |
1458 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | | 1524 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1459 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; | 1525 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
@@ -1461,9 +1527,20 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, | |||
1461 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; | 1527 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1462 | #endif | 1528 | #endif |
1463 | break; | 1529 | break; |
1530 | case DRM_FORMAT_XRGB2101010: | ||
1531 | case DRM_FORMAT_ARGB2101010: | ||
1532 | fb_format = | ||
1533 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | | ||
1534 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; | ||
1535 | #ifdef __BIG_ENDIAN | ||
1536 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; | ||
1537 | #endif | ||
1538 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ | ||
1539 | bypass_lut = true; | ||
1540 | break; | ||
1464 | default: | 1541 | default: |
1465 | DRM_ERROR("Unsupported screen depth %d\n", | 1542 | DRM_ERROR("Unsupported screen format %s\n", |
1466 | target_fb->bits_per_pixel); | 1543 | drm_get_format_name(target_fb->pixel_format)); |
1467 | return -EINVAL; | 1544 | return -EINVAL; |
1468 | } | 1545 | } |
1469 | 1546 | ||
@@ -1502,6 +1579,13 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, | |||
1502 | if (rdev->family >= CHIP_R600) | 1579 | if (rdev->family >= CHIP_R600) |
1503 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); | 1580 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1504 | 1581 | ||
1582 | /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ | ||
1583 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, | ||
1584 | (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); | ||
1585 | |||
1586 | if (bypass_lut) | ||
1587 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); | ||
1588 | |||
1505 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | 1589 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1506 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | 1590 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1507 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); | 1591 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h index a0f63ff5a5e9..333d143fca2c 100644 --- a/drivers/gpu/drm/radeon/evergreen_reg.h +++ b/drivers/gpu/drm/radeon/evergreen_reg.h | |||
@@ -116,6 +116,8 @@ | |||
116 | # define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 | 116 | # define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 |
117 | # define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 | 117 | # define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 |
118 | # define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 | 118 | # define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 |
119 | #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x6808 | ||
120 | # define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8) | ||
119 | #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c | 121 | #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c |
120 | # define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) | 122 | # define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) |
121 | # define EVERGREEN_GRPH_ENDIAN_NONE 0 | 123 | # define EVERGREEN_GRPH_ENDIAN_NONE 0 |
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h index 1dd0d32993d5..136b7bc7cd20 100644 --- a/drivers/gpu/drm/radeon/r500_reg.h +++ b/drivers/gpu/drm/radeon/r500_reg.h | |||
@@ -402,6 +402,7 @@ | |||
402 | * block and vice versa. This applies to GRPH, CUR, etc. | 402 | * block and vice versa. This applies to GRPH, CUR, etc. |
403 | */ | 403 | */ |
404 | #define AVIVO_D1GRPH_LUT_SEL 0x6108 | 404 | #define AVIVO_D1GRPH_LUT_SEL 0x6108 |
405 | # define AVIVO_LUT_10BIT_BYPASS_EN (1 << 8) | ||
405 | #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 | 406 | #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
406 | #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 | 407 | #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 |
407 | #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 | 408 | #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 |
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 933c5c39654d..1b9177ed181f 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c | |||
@@ -1288,17 +1288,15 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector, | |||
1288 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || | 1288 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || |
1289 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) | 1289 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) |
1290 | return MODE_OK; | 1290 | return MODE_OK; |
1291 | else if (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_A) { | 1291 | else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) { |
1292 | if (ASIC_IS_DCE6(rdev)) { | 1292 | /* HDMI 1.3+ supports max clock of 340 Mhz */ |
1293 | /* HDMI 1.3+ supports max clock of 340 Mhz */ | 1293 | if (mode->clock > 340000) |
1294 | if (mode->clock > 340000) | ||
1295 | return MODE_CLOCK_HIGH; | ||
1296 | else | ||
1297 | return MODE_OK; | ||
1298 | } else | ||
1299 | return MODE_CLOCK_HIGH; | 1294 | return MODE_CLOCK_HIGH; |
1300 | } else | 1295 | else |
1296 | return MODE_OK; | ||
1297 | } else { | ||
1301 | return MODE_CLOCK_HIGH; | 1298 | return MODE_CLOCK_HIGH; |
1299 | } | ||
1302 | } | 1300 | } |
1303 | 1301 | ||
1304 | /* check against the max pixel clock */ | 1302 | /* check against the max pixel clock */ |
@@ -1549,6 +1547,8 @@ out: | |||
1549 | static int radeon_dp_mode_valid(struct drm_connector *connector, | 1547 | static int radeon_dp_mode_valid(struct drm_connector *connector, |
1550 | struct drm_display_mode *mode) | 1548 | struct drm_display_mode *mode) |
1551 | { | 1549 | { |
1550 | struct drm_device *dev = connector->dev; | ||
1551 | struct radeon_device *rdev = dev->dev_private; | ||
1552 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 1552 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1553 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; | 1553 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
1554 | 1554 | ||
@@ -1579,14 +1579,23 @@ static int radeon_dp_mode_valid(struct drm_connector *connector, | |||
1579 | return MODE_PANEL; | 1579 | return MODE_PANEL; |
1580 | } | 1580 | } |
1581 | } | 1581 | } |
1582 | return MODE_OK; | ||
1583 | } else { | 1582 | } else { |
1584 | if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | 1583 | if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
1585 | (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) | 1584 | (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
1586 | return radeon_dp_mode_valid_helper(connector, mode); | 1585 | return radeon_dp_mode_valid_helper(connector, mode); |
1587 | else | 1586 | } else { |
1588 | return MODE_OK; | 1587 | if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) { |
1588 | /* HDMI 1.3+ supports max clock of 340 Mhz */ | ||
1589 | if (mode->clock > 340000) | ||
1590 | return MODE_CLOCK_HIGH; | ||
1591 | } else { | ||
1592 | if (mode->clock > 165000) | ||
1593 | return MODE_CLOCK_HIGH; | ||
1594 | } | ||
1595 | } | ||
1589 | } | 1596 | } |
1597 | |||
1598 | return MODE_OK; | ||
1590 | } | 1599 | } |
1591 | 1600 | ||
1592 | static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = { | 1601 | static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = { |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 5ed617056b9c..8fc362aa6a1a 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c | |||
@@ -66,7 +66,8 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc) | |||
66 | (radeon_crtc->lut_b[i] << 0)); | 66 | (radeon_crtc->lut_b[i] << 0)); |
67 | } | 67 | } |
68 | 68 | ||
69 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); | 69 | /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ |
70 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); | ||
70 | } | 71 | } |
71 | 72 | ||
72 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) | 73 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
@@ -357,8 +358,9 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) | |||
357 | 358 | ||
358 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); | 359 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
359 | 360 | ||
361 | drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); | ||
360 | radeon_fence_unref(&work->fence); | 362 | radeon_fence_unref(&work->fence); |
361 | radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id); | 363 | radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); |
362 | queue_work(radeon_crtc->flip_queue, &work->unpin_work); | 364 | queue_work(radeon_crtc->flip_queue, &work->unpin_work); |
363 | } | 365 | } |
364 | 366 | ||
@@ -459,6 +461,12 @@ static void radeon_flip_work_func(struct work_struct *__work) | |||
459 | base &= ~7; | 461 | base &= ~7; |
460 | } | 462 | } |
461 | 463 | ||
464 | r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); | ||
465 | if (r) { | ||
466 | DRM_ERROR("failed to get vblank before flip\n"); | ||
467 | goto pflip_cleanup; | ||
468 | } | ||
469 | |||
462 | /* We borrow the event spin lock for protecting flip_work */ | 470 | /* We borrow the event spin lock for protecting flip_work */ |
463 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | 471 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
464 | 472 | ||
@@ -473,6 +481,16 @@ static void radeon_flip_work_func(struct work_struct *__work) | |||
473 | 481 | ||
474 | return; | 482 | return; |
475 | 483 | ||
484 | pflip_cleanup: | ||
485 | if (unlikely(radeon_bo_reserve(work->new_rbo, false) != 0)) { | ||
486 | DRM_ERROR("failed to reserve new rbo in error path\n"); | ||
487 | goto cleanup; | ||
488 | } | ||
489 | if (unlikely(radeon_bo_unpin(work->new_rbo) != 0)) { | ||
490 | DRM_ERROR("failed to unpin new rbo in error path\n"); | ||
491 | } | ||
492 | radeon_bo_unreserve(work->new_rbo); | ||
493 | |||
476 | cleanup: | 494 | cleanup: |
477 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); | 495 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); |
478 | radeon_fence_unref(&work->fence); | 496 | radeon_fence_unref(&work->fence); |
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 620d1004a1e7..9f7d5859cf65 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig | |||
@@ -676,6 +676,16 @@ config I2C_RIIC | |||
676 | This driver can also be built as a module. If so, the module | 676 | This driver can also be built as a module. If so, the module |
677 | will be called i2c-riic. | 677 | will be called i2c-riic. |
678 | 678 | ||
679 | config I2C_RK3X | ||
680 | tristate "Rockchip RK3xxx I2C adapter" | ||
681 | depends on OF | ||
682 | help | ||
683 | Say Y here to include support for the I2C adapter in Rockchip RK3xxx | ||
684 | SoCs. | ||
685 | |||
686 | This driver can also be built as a module. If so, the module will | ||
687 | be called i2c-rk3x. | ||
688 | |||
679 | config HAVE_S3C2410_I2C | 689 | config HAVE_S3C2410_I2C |
680 | bool | 690 | bool |
681 | help | 691 | help |
@@ -764,6 +774,19 @@ config I2C_STU300 | |||
764 | This driver can also be built as a module. If so, the module | 774 | This driver can also be built as a module. If so, the module |
765 | will be called i2c-stu300. | 775 | will be called i2c-stu300. |
766 | 776 | ||
777 | config I2C_SUN6I_P2WI | ||
778 | tristate "Allwinner sun6i internal P2WI controller" | ||
779 | depends on RESET_CONTROLLER | ||
780 | depends on MACH_SUN6I || COMPILE_TEST | ||
781 | help | ||
782 | If you say yes to this option, support will be included for the | ||
783 | P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi | ||
784 | SOCs. | ||
785 | The P2WI looks like an SMBus controller (which supports only byte | ||
786 | accesses), except that it only supports one slave device. | ||
787 | This interface is used to connect to specific PMIC devices (like the | ||
788 | AXP221). | ||
789 | |||
767 | config I2C_TEGRA | 790 | config I2C_TEGRA |
768 | tristate "NVIDIA Tegra internal I2C controller" | 791 | tristate "NVIDIA Tegra internal I2C controller" |
769 | depends on ARCH_TEGRA | 792 | depends on ARCH_TEGRA |
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 298692cc6000..dd9a7f8e873f 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile | |||
@@ -66,6 +66,7 @@ obj-$(CONFIG_I2C_PXA) += i2c-pxa.o | |||
66 | obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o | 66 | obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o |
67 | obj-$(CONFIG_I2C_QUP) += i2c-qup.o | 67 | obj-$(CONFIG_I2C_QUP) += i2c-qup.o |
68 | obj-$(CONFIG_I2C_RIIC) += i2c-riic.o | 68 | obj-$(CONFIG_I2C_RIIC) += i2c-riic.o |
69 | obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o | ||
69 | obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o | 70 | obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o |
70 | obj-$(CONFIG_I2C_S6000) += i2c-s6000.o | 71 | obj-$(CONFIG_I2C_S6000) += i2c-s6000.o |
71 | obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o | 72 | obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o |
@@ -74,6 +75,7 @@ obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o | |||
74 | obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o | 75 | obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o |
75 | obj-$(CONFIG_I2C_ST) += i2c-st.o | 76 | obj-$(CONFIG_I2C_ST) += i2c-st.o |
76 | obj-$(CONFIG_I2C_STU300) += i2c-stu300.o | 77 | obj-$(CONFIG_I2C_STU300) += i2c-stu300.o |
78 | obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o | ||
77 | obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o | 79 | obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o |
78 | obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o | 80 | obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o |
79 | obj-$(CONFIG_I2C_WMT) += i2c-wmt.o | 81 | obj-$(CONFIG_I2C_WMT) += i2c-wmt.o |
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c new file mode 100644 index 000000000000..a9791509966a --- /dev/null +++ b/drivers/i2c/busses/i2c-rk3x.c | |||
@@ -0,0 +1,763 @@ | |||
1 | /* | ||
2 | * Driver for I2C adapter in Rockchip RK3xxx SoC | ||
3 | * | ||
4 | * Max Schwarz <max.schwarz@online.de> | ||
5 | * based on the patches by Rockchip Inc. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/module.h> | ||
14 | #include <linux/i2c.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/errno.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <linux/of_address.h> | ||
21 | #include <linux/of_irq.h> | ||
22 | #include <linux/spinlock.h> | ||
23 | #include <linux/clk.h> | ||
24 | #include <linux/wait.h> | ||
25 | #include <linux/mfd/syscon.h> | ||
26 | #include <linux/regmap.h> | ||
27 | |||
28 | |||
29 | /* Register Map */ | ||
30 | #define REG_CON 0x00 /* control register */ | ||
31 | #define REG_CLKDIV 0x04 /* clock divisor register */ | ||
32 | #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */ | ||
33 | #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */ | ||
34 | #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */ | ||
35 | #define REG_MRXCNT 0x14 /* number of bytes to be received */ | ||
36 | #define REG_IEN 0x18 /* interrupt enable */ | ||
37 | #define REG_IPD 0x1c /* interrupt pending */ | ||
38 | #define REG_FCNT 0x20 /* finished count */ | ||
39 | |||
40 | /* Data buffer offsets */ | ||
41 | #define TXBUFFER_BASE 0x100 | ||
42 | #define RXBUFFER_BASE 0x200 | ||
43 | |||
44 | /* REG_CON bits */ | ||
45 | #define REG_CON_EN BIT(0) | ||
46 | enum { | ||
47 | REG_CON_MOD_TX = 0, /* transmit data */ | ||
48 | REG_CON_MOD_REGISTER_TX, /* select register and restart */ | ||
49 | REG_CON_MOD_RX, /* receive data */ | ||
50 | REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes | ||
51 | * register addr */ | ||
52 | }; | ||
53 | #define REG_CON_MOD(mod) ((mod) << 1) | ||
54 | #define REG_CON_MOD_MASK (BIT(1) | BIT(2)) | ||
55 | #define REG_CON_START BIT(3) | ||
56 | #define REG_CON_STOP BIT(4) | ||
57 | #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ | ||
58 | #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ | ||
59 | |||
60 | /* REG_MRXADDR bits */ | ||
61 | #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ | ||
62 | |||
63 | /* REG_IEN/REG_IPD bits */ | ||
64 | #define REG_INT_BTF BIT(0) /* a byte was transmitted */ | ||
65 | #define REG_INT_BRF BIT(1) /* a byte was received */ | ||
66 | #define REG_INT_MBTF BIT(2) /* master data transmit finished */ | ||
67 | #define REG_INT_MBRF BIT(3) /* master data receive finished */ | ||
68 | #define REG_INT_START BIT(4) /* START condition generated */ | ||
69 | #define REG_INT_STOP BIT(5) /* STOP condition generated */ | ||
70 | #define REG_INT_NAKRCV BIT(6) /* NACK received */ | ||
71 | #define REG_INT_ALL 0x7f | ||
72 | |||
73 | /* Constants */ | ||
74 | #define WAIT_TIMEOUT 200 /* ms */ | ||
75 | #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ | ||
76 | |||
77 | enum rk3x_i2c_state { | ||
78 | STATE_IDLE, | ||
79 | STATE_START, | ||
80 | STATE_READ, | ||
81 | STATE_WRITE, | ||
82 | STATE_STOP | ||
83 | }; | ||
84 | |||
85 | /** | ||
86 | * @grf_offset: offset inside the grf regmap for setting the i2c type | ||
87 | */ | ||
88 | struct rk3x_i2c_soc_data { | ||
89 | int grf_offset; | ||
90 | }; | ||
91 | |||
92 | struct rk3x_i2c { | ||
93 | struct i2c_adapter adap; | ||
94 | struct device *dev; | ||
95 | struct rk3x_i2c_soc_data *soc_data; | ||
96 | |||
97 | /* Hardware resources */ | ||
98 | void __iomem *regs; | ||
99 | struct clk *clk; | ||
100 | |||
101 | /* Settings */ | ||
102 | unsigned int scl_frequency; | ||
103 | |||
104 | /* Synchronization & notification */ | ||
105 | spinlock_t lock; | ||
106 | wait_queue_head_t wait; | ||
107 | bool busy; | ||
108 | |||
109 | /* Current message */ | ||
110 | struct i2c_msg *msg; | ||
111 | u8 addr; | ||
112 | unsigned int mode; | ||
113 | bool is_last_msg; | ||
114 | |||
115 | /* I2C state machine */ | ||
116 | enum rk3x_i2c_state state; | ||
117 | unsigned int processed; /* sent/received bytes */ | ||
118 | int error; | ||
119 | }; | ||
120 | |||
121 | static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, | ||
122 | unsigned int offset) | ||
123 | { | ||
124 | writel(value, i2c->regs + offset); | ||
125 | } | ||
126 | |||
127 | static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset) | ||
128 | { | ||
129 | return readl(i2c->regs + offset); | ||
130 | } | ||
131 | |||
132 | /* Reset all interrupt pending bits */ | ||
133 | static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c) | ||
134 | { | ||
135 | i2c_writel(i2c, REG_INT_ALL, REG_IPD); | ||
136 | } | ||
137 | |||
138 | /** | ||
139 | * Generate a START condition, which triggers a REG_INT_START interrupt. | ||
140 | */ | ||
141 | static void rk3x_i2c_start(struct rk3x_i2c *i2c) | ||
142 | { | ||
143 | u32 val; | ||
144 | |||
145 | rk3x_i2c_clean_ipd(i2c); | ||
146 | i2c_writel(i2c, REG_INT_START, REG_IEN); | ||
147 | |||
148 | /* enable adapter with correct mode, send START condition */ | ||
149 | val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; | ||
150 | |||
151 | /* if we want to react to NACK, set ACTACK bit */ | ||
152 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) | ||
153 | val |= REG_CON_ACTACK; | ||
154 | |||
155 | i2c_writel(i2c, val, REG_CON); | ||
156 | } | ||
157 | |||
158 | /** | ||
159 | * Generate a STOP condition, which triggers a REG_INT_STOP interrupt. | ||
160 | * | ||
161 | * @error: Error code to return in rk3x_i2c_xfer | ||
162 | */ | ||
163 | static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) | ||
164 | { | ||
165 | unsigned int ctrl; | ||
166 | |||
167 | i2c->processed = 0; | ||
168 | i2c->msg = NULL; | ||
169 | i2c->error = error; | ||
170 | |||
171 | if (i2c->is_last_msg) { | ||
172 | /* Enable stop interrupt */ | ||
173 | i2c_writel(i2c, REG_INT_STOP, REG_IEN); | ||
174 | |||
175 | i2c->state = STATE_STOP; | ||
176 | |||
177 | ctrl = i2c_readl(i2c, REG_CON); | ||
178 | ctrl |= REG_CON_STOP; | ||
179 | i2c_writel(i2c, ctrl, REG_CON); | ||
180 | } else { | ||
181 | /* Signal rk3x_i2c_xfer to start the next message. */ | ||
182 | i2c->busy = false; | ||
183 | i2c->state = STATE_IDLE; | ||
184 | |||
185 | /* | ||
186 | * The HW is actually not capable of REPEATED START. But we can | ||
187 | * get the intended effect by resetting its internal state | ||
188 | * and issuing an ordinary START. | ||
189 | */ | ||
190 | i2c_writel(i2c, 0, REG_CON); | ||
191 | |||
192 | /* signal that we are finished with the current msg */ | ||
193 | wake_up(&i2c->wait); | ||
194 | } | ||
195 | } | ||
196 | |||
197 | /** | ||
198 | * Setup a read according to i2c->msg | ||
199 | */ | ||
200 | static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) | ||
201 | { | ||
202 | unsigned int len = i2c->msg->len - i2c->processed; | ||
203 | u32 con; | ||
204 | |||
205 | con = i2c_readl(i2c, REG_CON); | ||
206 | |||
207 | /* | ||
208 | * The hw can read up to 32 bytes at a time. If we need more than one | ||
209 | * chunk, send an ACK after the last byte of the current chunk. | ||
210 | */ | ||
211 | if (unlikely(len > 32)) { | ||
212 | len = 32; | ||
213 | con &= ~REG_CON_LASTACK; | ||
214 | } else { | ||
215 | con |= REG_CON_LASTACK; | ||
216 | } | ||
217 | |||
218 | /* make sure we are in plain RX mode if we read a second chunk */ | ||
219 | if (i2c->processed != 0) { | ||
220 | con &= ~REG_CON_MOD_MASK; | ||
221 | con |= REG_CON_MOD(REG_CON_MOD_RX); | ||
222 | } | ||
223 | |||
224 | i2c_writel(i2c, con, REG_CON); | ||
225 | i2c_writel(i2c, len, REG_MRXCNT); | ||
226 | } | ||
227 | |||
228 | /** | ||
229 | * Fill the transmit buffer with data from i2c->msg | ||
230 | */ | ||
231 | static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) | ||
232 | { | ||
233 | unsigned int i, j; | ||
234 | u32 cnt = 0; | ||
235 | u32 val; | ||
236 | u8 byte; | ||
237 | |||
238 | for (i = 0; i < 8; ++i) { | ||
239 | val = 0; | ||
240 | for (j = 0; j < 4; ++j) { | ||
241 | if (i2c->processed == i2c->msg->len) | ||
242 | break; | ||
243 | |||
244 | if (i2c->processed == 0 && cnt == 0) | ||
245 | byte = (i2c->addr & 0x7f) << 1; | ||
246 | else | ||
247 | byte = i2c->msg->buf[i2c->processed++]; | ||
248 | |||
249 | val |= byte << (j * 8); | ||
250 | cnt++; | ||
251 | } | ||
252 | |||
253 | i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); | ||
254 | |||
255 | if (i2c->processed == i2c->msg->len) | ||
256 | break; | ||
257 | } | ||
258 | |||
259 | i2c_writel(i2c, cnt, REG_MTXCNT); | ||
260 | } | ||
261 | |||
262 | |||
263 | /* IRQ handlers for individual states */ | ||
264 | |||
265 | static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd) | ||
266 | { | ||
267 | if (!(ipd & REG_INT_START)) { | ||
268 | rk3x_i2c_stop(i2c, -EIO); | ||
269 | dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd); | ||
270 | rk3x_i2c_clean_ipd(i2c); | ||
271 | return; | ||
272 | } | ||
273 | |||
274 | /* ack interrupt */ | ||
275 | i2c_writel(i2c, REG_INT_START, REG_IPD); | ||
276 | |||
277 | /* disable start bit */ | ||
278 | i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON); | ||
279 | |||
280 | /* enable appropriate interrupts and transition */ | ||
281 | if (i2c->mode == REG_CON_MOD_TX) { | ||
282 | i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN); | ||
283 | i2c->state = STATE_WRITE; | ||
284 | rk3x_i2c_fill_transmit_buf(i2c); | ||
285 | } else { | ||
286 | /* in any other case, we are going to be reading. */ | ||
287 | i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN); | ||
288 | i2c->state = STATE_READ; | ||
289 | rk3x_i2c_prepare_read(i2c); | ||
290 | } | ||
291 | } | ||
292 | |||
293 | static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd) | ||
294 | { | ||
295 | if (!(ipd & REG_INT_MBTF)) { | ||
296 | rk3x_i2c_stop(i2c, -EIO); | ||
297 | dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd); | ||
298 | rk3x_i2c_clean_ipd(i2c); | ||
299 | return; | ||
300 | } | ||
301 | |||
302 | /* ack interrupt */ | ||
303 | i2c_writel(i2c, REG_INT_MBTF, REG_IPD); | ||
304 | |||
305 | /* are we finished? */ | ||
306 | if (i2c->processed == i2c->msg->len) | ||
307 | rk3x_i2c_stop(i2c, i2c->error); | ||
308 | else | ||
309 | rk3x_i2c_fill_transmit_buf(i2c); | ||
310 | } | ||
311 | |||
312 | static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) | ||
313 | { | ||
314 | unsigned int i; | ||
315 | unsigned int len = i2c->msg->len - i2c->processed; | ||
316 | u32 uninitialized_var(val); | ||
317 | u8 byte; | ||
318 | |||
319 | /* we only care for MBRF here. */ | ||
320 | if (!(ipd & REG_INT_MBRF)) | ||
321 | return; | ||
322 | |||
323 | /* ack interrupt */ | ||
324 | i2c_writel(i2c, REG_INT_MBRF, REG_IPD); | ||
325 | |||
326 | /* read the data from receive buffer */ | ||
327 | for (i = 0; i < len; ++i) { | ||
328 | if (i % 4 == 0) | ||
329 | val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); | ||
330 | |||
331 | byte = (val >> ((i % 4) * 8)) & 0xff; | ||
332 | i2c->msg->buf[i2c->processed++] = byte; | ||
333 | } | ||
334 | |||
335 | /* are we finished? */ | ||
336 | if (i2c->processed == i2c->msg->len) | ||
337 | rk3x_i2c_stop(i2c, i2c->error); | ||
338 | else | ||
339 | rk3x_i2c_prepare_read(i2c); | ||
340 | } | ||
341 | |||
342 | static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd) | ||
343 | { | ||
344 | unsigned int con; | ||
345 | |||
346 | if (!(ipd & REG_INT_STOP)) { | ||
347 | rk3x_i2c_stop(i2c, -EIO); | ||
348 | dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd); | ||
349 | rk3x_i2c_clean_ipd(i2c); | ||
350 | return; | ||
351 | } | ||
352 | |||
353 | /* ack interrupt */ | ||
354 | i2c_writel(i2c, REG_INT_STOP, REG_IPD); | ||
355 | |||
356 | /* disable STOP bit */ | ||
357 | con = i2c_readl(i2c, REG_CON); | ||
358 | con &= ~REG_CON_STOP; | ||
359 | i2c_writel(i2c, con, REG_CON); | ||
360 | |||
361 | i2c->busy = false; | ||
362 | i2c->state = STATE_IDLE; | ||
363 | |||
364 | /* signal rk3x_i2c_xfer that we are finished */ | ||
365 | wake_up(&i2c->wait); | ||
366 | } | ||
367 | |||
368 | static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id) | ||
369 | { | ||
370 | struct rk3x_i2c *i2c = dev_id; | ||
371 | unsigned int ipd; | ||
372 | |||
373 | spin_lock(&i2c->lock); | ||
374 | |||
375 | ipd = i2c_readl(i2c, REG_IPD); | ||
376 | if (i2c->state == STATE_IDLE) { | ||
377 | dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd); | ||
378 | rk3x_i2c_clean_ipd(i2c); | ||
379 | goto out; | ||
380 | } | ||
381 | |||
382 | dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd); | ||
383 | |||
384 | /* Clean interrupt bits we don't care about */ | ||
385 | ipd &= ~(REG_INT_BRF | REG_INT_BTF); | ||
386 | |||
387 | if (ipd & REG_INT_NAKRCV) { | ||
388 | /* | ||
389 | * We got a NACK in the last operation. Depending on whether | ||
390 | * IGNORE_NAK is set, we have to stop the operation and report | ||
391 | * an error. | ||
392 | */ | ||
393 | i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD); | ||
394 | |||
395 | ipd &= ~REG_INT_NAKRCV; | ||
396 | |||
397 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) | ||
398 | rk3x_i2c_stop(i2c, -ENXIO); | ||
399 | } | ||
400 | |||
401 | /* is there anything left to handle? */ | ||
402 | if (unlikely(ipd == 0)) | ||
403 | goto out; | ||
404 | |||
405 | switch (i2c->state) { | ||
406 | case STATE_START: | ||
407 | rk3x_i2c_handle_start(i2c, ipd); | ||
408 | break; | ||
409 | case STATE_WRITE: | ||
410 | rk3x_i2c_handle_write(i2c, ipd); | ||
411 | break; | ||
412 | case STATE_READ: | ||
413 | rk3x_i2c_handle_read(i2c, ipd); | ||
414 | break; | ||
415 | case STATE_STOP: | ||
416 | rk3x_i2c_handle_stop(i2c, ipd); | ||
417 | break; | ||
418 | case STATE_IDLE: | ||
419 | break; | ||
420 | } | ||
421 | |||
422 | out: | ||
423 | spin_unlock(&i2c->lock); | ||
424 | return IRQ_HANDLED; | ||
425 | } | ||
426 | |||
427 | static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate) | ||
428 | { | ||
429 | unsigned long i2c_rate = clk_get_rate(i2c->clk); | ||
430 | unsigned int div; | ||
431 | |||
432 | /* SCL rate = (clk rate) / (8 * DIV) */ | ||
433 | div = DIV_ROUND_UP(i2c_rate, scl_rate * 8); | ||
434 | |||
435 | /* The lower and upper half of the CLKDIV reg describe the length of | ||
436 | * SCL low & high periods. */ | ||
437 | div = DIV_ROUND_UP(div, 2); | ||
438 | |||
439 | i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV); | ||
440 | } | ||
441 | |||
442 | /** | ||
443 | * Setup I2C registers for an I2C operation specified by msgs, num. | ||
444 | * | ||
445 | * Must be called with i2c->lock held. | ||
446 | * | ||
447 | * @msgs: I2C msgs to process | ||
448 | * @num: Number of msgs | ||
449 | * | ||
450 | * returns: Number of I2C msgs processed or negative in case of error | ||
451 | */ | ||
452 | static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) | ||
453 | { | ||
454 | u32 addr = (msgs[0].addr & 0x7f) << 1; | ||
455 | int ret = 0; | ||
456 | |||
457 | /* | ||
458 | * The I2C adapter can issue a small (len < 4) write packet before | ||
459 | * reading. This speeds up SMBus-style register reads. | ||
460 | * The MRXADDR/MRXRADDR hold the slave address and the slave register | ||
461 | * address in this case. | ||
462 | */ | ||
463 | |||
464 | if (num >= 2 && msgs[0].len < 4 && | ||
465 | !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) { | ||
466 | u32 reg_addr = 0; | ||
467 | int i; | ||
468 | |||
469 | dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", | ||
470 | addr >> 1); | ||
471 | |||
472 | /* Fill MRXRADDR with the register address(es) */ | ||
473 | for (i = 0; i < msgs[0].len; ++i) { | ||
474 | reg_addr |= msgs[0].buf[i] << (i * 8); | ||
475 | reg_addr |= REG_MRXADDR_VALID(i); | ||
476 | } | ||
477 | |||
478 | /* msgs[0] is handled by hw. */ | ||
479 | i2c->msg = &msgs[1]; | ||
480 | |||
481 | i2c->mode = REG_CON_MOD_REGISTER_TX; | ||
482 | |||
483 | i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR); | ||
484 | i2c_writel(i2c, reg_addr, REG_MRXRADDR); | ||
485 | |||
486 | ret = 2; | ||
487 | } else { | ||
488 | /* | ||
489 | * We'll have to do it the boring way and process the msgs | ||
490 | * one-by-one. | ||
491 | */ | ||
492 | |||
493 | if (msgs[0].flags & I2C_M_RD) { | ||
494 | addr |= 1; /* set read bit */ | ||
495 | |||
496 | /* | ||
497 | * We have to transmit the slave addr first. Use | ||
498 | * MOD_REGISTER_TX for that purpose. | ||
499 | */ | ||
500 | i2c->mode = REG_CON_MOD_REGISTER_TX; | ||
501 | i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), | ||
502 | REG_MRXADDR); | ||
503 | i2c_writel(i2c, 0, REG_MRXRADDR); | ||
504 | } else { | ||
505 | i2c->mode = REG_CON_MOD_TX; | ||
506 | } | ||
507 | |||
508 | i2c->msg = &msgs[0]; | ||
509 | |||
510 | ret = 1; | ||
511 | } | ||
512 | |||
513 | i2c->addr = msgs[0].addr; | ||
514 | i2c->busy = true; | ||
515 | i2c->state = STATE_START; | ||
516 | i2c->processed = 0; | ||
517 | i2c->error = 0; | ||
518 | |||
519 | rk3x_i2c_clean_ipd(i2c); | ||
520 | |||
521 | return ret; | ||
522 | } | ||
523 | |||
524 | static int rk3x_i2c_xfer(struct i2c_adapter *adap, | ||
525 | struct i2c_msg *msgs, int num) | ||
526 | { | ||
527 | struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data; | ||
528 | unsigned long timeout, flags; | ||
529 | int ret = 0; | ||
530 | int i; | ||
531 | |||
532 | spin_lock_irqsave(&i2c->lock, flags); | ||
533 | |||
534 | clk_enable(i2c->clk); | ||
535 | |||
536 | /* The clock rate might have changed, so setup the divider again */ | ||
537 | rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency); | ||
538 | |||
539 | i2c->is_last_msg = false; | ||
540 | |||
541 | /* | ||
542 | * Process msgs. We can handle more than one message at once (see | ||
543 | * rk3x_i2c_setup()). | ||
544 | */ | ||
545 | for (i = 0; i < num; i += ret) { | ||
546 | ret = rk3x_i2c_setup(i2c, msgs + i, num - i); | ||
547 | |||
548 | if (ret < 0) { | ||
549 | dev_err(i2c->dev, "rk3x_i2c_setup() failed\n"); | ||
550 | break; | ||
551 | } | ||
552 | |||
553 | if (i + ret >= num) | ||
554 | i2c->is_last_msg = true; | ||
555 | |||
556 | spin_unlock_irqrestore(&i2c->lock, flags); | ||
557 | |||
558 | rk3x_i2c_start(i2c); | ||
559 | |||
560 | timeout = wait_event_timeout(i2c->wait, !i2c->busy, | ||
561 | msecs_to_jiffies(WAIT_TIMEOUT)); | ||
562 | |||
563 | spin_lock_irqsave(&i2c->lock, flags); | ||
564 | |||
565 | if (timeout == 0) { | ||
566 | dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", | ||
567 | i2c_readl(i2c, REG_IPD), i2c->state); | ||
568 | |||
569 | /* Force a STOP condition without interrupt */ | ||
570 | i2c_writel(i2c, 0, REG_IEN); | ||
571 | i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON); | ||
572 | |||
573 | i2c->state = STATE_IDLE; | ||
574 | |||
575 | ret = -ETIMEDOUT; | ||
576 | break; | ||
577 | } | ||
578 | |||
579 | if (i2c->error) { | ||
580 | ret = i2c->error; | ||
581 | break; | ||
582 | } | ||
583 | } | ||
584 | |||
585 | clk_disable(i2c->clk); | ||
586 | spin_unlock_irqrestore(&i2c->lock, flags); | ||
587 | |||
588 | return ret; | ||
589 | } | ||
590 | |||
591 | static u32 rk3x_i2c_func(struct i2c_adapter *adap) | ||
592 | { | ||
593 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | ||
594 | } | ||
595 | |||
596 | static const struct i2c_algorithm rk3x_i2c_algorithm = { | ||
597 | .master_xfer = rk3x_i2c_xfer, | ||
598 | .functionality = rk3x_i2c_func, | ||
599 | }; | ||
600 | |||
601 | static struct rk3x_i2c_soc_data soc_data[3] = { | ||
602 | { .grf_offset = 0x154 }, /* rk3066 */ | ||
603 | { .grf_offset = 0x0a4 }, /* rk3188 */ | ||
604 | { .grf_offset = -1 }, /* no I2C switching needed */ | ||
605 | }; | ||
606 | |||
607 | static const struct of_device_id rk3x_i2c_match[] = { | ||
608 | { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] }, | ||
609 | { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] }, | ||
610 | { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] }, | ||
611 | {}, | ||
612 | }; | ||
613 | |||
614 | static int rk3x_i2c_probe(struct platform_device *pdev) | ||
615 | { | ||
616 | struct device_node *np = pdev->dev.of_node; | ||
617 | const struct of_device_id *match; | ||
618 | struct rk3x_i2c *i2c; | ||
619 | struct resource *mem; | ||
620 | int ret = 0; | ||
621 | int bus_nr; | ||
622 | u32 value; | ||
623 | int irq; | ||
624 | |||
625 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); | ||
626 | if (!i2c) | ||
627 | return -ENOMEM; | ||
628 | |||
629 | match = of_match_node(rk3x_i2c_match, np); | ||
630 | i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data; | ||
631 | |||
632 | if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", | ||
633 | &i2c->scl_frequency)) { | ||
634 | dev_info(&pdev->dev, "using default SCL frequency: %d\n", | ||
635 | DEFAULT_SCL_RATE); | ||
636 | i2c->scl_frequency = DEFAULT_SCL_RATE; | ||
637 | } | ||
638 | |||
639 | if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) { | ||
640 | dev_warn(&pdev->dev, "invalid SCL frequency specified.\n"); | ||
641 | dev_warn(&pdev->dev, "using default SCL frequency: %d\n", | ||
642 | DEFAULT_SCL_RATE); | ||
643 | i2c->scl_frequency = DEFAULT_SCL_RATE; | ||
644 | } | ||
645 | |||
646 | strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); | ||
647 | i2c->adap.owner = THIS_MODULE; | ||
648 | i2c->adap.algo = &rk3x_i2c_algorithm; | ||
649 | i2c->adap.retries = 3; | ||
650 | i2c->adap.dev.of_node = np; | ||
651 | i2c->adap.algo_data = i2c; | ||
652 | i2c->adap.dev.parent = &pdev->dev; | ||
653 | |||
654 | i2c->dev = &pdev->dev; | ||
655 | |||
656 | spin_lock_init(&i2c->lock); | ||
657 | init_waitqueue_head(&i2c->wait); | ||
658 | |||
659 | i2c->clk = devm_clk_get(&pdev->dev, NULL); | ||
660 | if (IS_ERR(i2c->clk)) { | ||
661 | dev_err(&pdev->dev, "cannot get clock\n"); | ||
662 | return PTR_ERR(i2c->clk); | ||
663 | } | ||
664 | |||
665 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
666 | i2c->regs = devm_ioremap_resource(&pdev->dev, mem); | ||
667 | if (IS_ERR(i2c->regs)) | ||
668 | return PTR_ERR(i2c->regs); | ||
669 | |||
670 | /* Try to set the I2C adapter number from dt */ | ||
671 | bus_nr = of_alias_get_id(np, "i2c"); | ||
672 | |||
673 | /* | ||
674 | * Switch to new interface if the SoC also offers the old one. | ||
675 | * The control bit is located in the GRF register space. | ||
676 | */ | ||
677 | if (i2c->soc_data->grf_offset >= 0) { | ||
678 | struct regmap *grf; | ||
679 | |||
680 | grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); | ||
681 | if (IS_ERR(grf)) { | ||
682 | dev_err(&pdev->dev, | ||
683 | "rk3x-i2c needs 'rockchip,grf' property\n"); | ||
684 | return PTR_ERR(grf); | ||
685 | } | ||
686 | |||
687 | if (bus_nr < 0) { | ||
688 | dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias"); | ||
689 | return -EINVAL; | ||
690 | } | ||
691 | |||
692 | /* 27+i: write mask, 11+i: value */ | ||
693 | value = BIT(27 + bus_nr) | BIT(11 + bus_nr); | ||
694 | |||
695 | ret = regmap_write(grf, i2c->soc_data->grf_offset, value); | ||
696 | if (ret != 0) { | ||
697 | dev_err(i2c->dev, "Could not write to GRF: %d\n", ret); | ||
698 | return ret; | ||
699 | } | ||
700 | } | ||
701 | |||
702 | /* IRQ setup */ | ||
703 | irq = platform_get_irq(pdev, 0); | ||
704 | if (irq < 0) { | ||
705 | dev_err(&pdev->dev, "cannot find rk3x IRQ\n"); | ||
706 | return irq; | ||
707 | } | ||
708 | |||
709 | ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, | ||
710 | 0, dev_name(&pdev->dev), i2c); | ||
711 | if (ret < 0) { | ||
712 | dev_err(&pdev->dev, "cannot request IRQ\n"); | ||
713 | return ret; | ||
714 | } | ||
715 | |||
716 | platform_set_drvdata(pdev, i2c); | ||
717 | |||
718 | ret = clk_prepare(i2c->clk); | ||
719 | if (ret < 0) { | ||
720 | dev_err(&pdev->dev, "Could not prepare clock\n"); | ||
721 | return ret; | ||
722 | } | ||
723 | |||
724 | ret = i2c_add_adapter(&i2c->adap); | ||
725 | if (ret < 0) { | ||
726 | dev_err(&pdev->dev, "Could not register adapter\n"); | ||
727 | goto err_clk; | ||
728 | } | ||
729 | |||
730 | dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs); | ||
731 | |||
732 | return 0; | ||
733 | |||
734 | err_clk: | ||
735 | clk_unprepare(i2c->clk); | ||
736 | return ret; | ||
737 | } | ||
738 | |||
739 | static int rk3x_i2c_remove(struct platform_device *pdev) | ||
740 | { | ||
741 | struct rk3x_i2c *i2c = platform_get_drvdata(pdev); | ||
742 | |||
743 | i2c_del_adapter(&i2c->adap); | ||
744 | clk_unprepare(i2c->clk); | ||
745 | |||
746 | return 0; | ||
747 | } | ||
748 | |||
749 | static struct platform_driver rk3x_i2c_driver = { | ||
750 | .probe = rk3x_i2c_probe, | ||
751 | .remove = rk3x_i2c_remove, | ||
752 | .driver = { | ||
753 | .owner = THIS_MODULE, | ||
754 | .name = "rk3x-i2c", | ||
755 | .of_match_table = rk3x_i2c_match, | ||
756 | }, | ||
757 | }; | ||
758 | |||
759 | module_platform_driver(rk3x_i2c_driver); | ||
760 | |||
761 | MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver"); | ||
762 | MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>"); | ||
763 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/i2c/busses/i2c-sun6i-p2wi.c b/drivers/i2c/busses/i2c-sun6i-p2wi.c new file mode 100644 index 000000000000..09de4fd12d57 --- /dev/null +++ b/drivers/i2c/busses/i2c-sun6i-p2wi.c | |||
@@ -0,0 +1,345 @@ | |||
1 | /* | ||
2 | * P2WI (Push-Pull Two Wire Interface) bus driver. | ||
3 | * | ||
4 | * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | * | ||
10 | * The P2WI controller looks like an SMBus controller which only supports byte | ||
11 | * data transfers. But, it differs from standard SMBus protocol on several | ||
12 | * aspects: | ||
13 | * - it supports only one slave device, and thus drop the address field | ||
14 | * - it adds a parity bit every 8bits of data | ||
15 | * - only one read access is required to read a byte (instead of a write | ||
16 | * followed by a read access in standard SMBus protocol) | ||
17 | * - there's no Ack bit after each byte transfer | ||
18 | * | ||
19 | * This means this bus cannot be used to interface with standard SMBus | ||
20 | * devices (the only known device to support this interface is the AXP221 | ||
21 | * PMIC). | ||
22 | * | ||
23 | */ | ||
24 | #include <linux/clk.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/i2c.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/interrupt.h> | ||
29 | #include <linux/module.h> | ||
30 | #include <linux/of.h> | ||
31 | #include <linux/platform_device.h> | ||
32 | #include <linux/reset.h> | ||
33 | |||
34 | |||
35 | /* P2WI registers */ | ||
36 | #define P2WI_CTRL 0x0 | ||
37 | #define P2WI_CCR 0x4 | ||
38 | #define P2WI_INTE 0x8 | ||
39 | #define P2WI_INTS 0xc | ||
40 | #define P2WI_DADDR0 0x10 | ||
41 | #define P2WI_DADDR1 0x14 | ||
42 | #define P2WI_DLEN 0x18 | ||
43 | #define P2WI_DATA0 0x1c | ||
44 | #define P2WI_DATA1 0x20 | ||
45 | #define P2WI_LCR 0x24 | ||
46 | #define P2WI_PMCR 0x28 | ||
47 | |||
48 | /* CTRL fields */ | ||
49 | #define P2WI_CTRL_START_TRANS BIT(7) | ||
50 | #define P2WI_CTRL_ABORT_TRANS BIT(6) | ||
51 | #define P2WI_CTRL_GLOBAL_INT_ENB BIT(1) | ||
52 | #define P2WI_CTRL_SOFT_RST BIT(0) | ||
53 | |||
54 | /* CLK CTRL fields */ | ||
55 | #define P2WI_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8) | ||
56 | #define P2WI_CCR_MAX_CLK_DIV 0xff | ||
57 | #define P2WI_CCR_CLK_DIV(v) ((v) & P2WI_CCR_MAX_CLK_DIV) | ||
58 | |||
59 | /* STATUS fields */ | ||
60 | #define P2WI_INTS_TRANS_ERR_ID(v) (((v) >> 8) & 0xff) | ||
61 | #define P2WI_INTS_LOAD_BSY BIT(2) | ||
62 | #define P2WI_INTS_TRANS_ERR BIT(1) | ||
63 | #define P2WI_INTS_TRANS_OVER BIT(0) | ||
64 | |||
65 | /* DATA LENGTH fields*/ | ||
66 | #define P2WI_DLEN_READ BIT(4) | ||
67 | #define P2WI_DLEN_DATA_LENGTH(v) ((v - 1) & 0x7) | ||
68 | |||
69 | /* LINE CTRL fields*/ | ||
70 | #define P2WI_LCR_SCL_STATE BIT(5) | ||
71 | #define P2WI_LCR_SDA_STATE BIT(4) | ||
72 | #define P2WI_LCR_SCL_CTL BIT(3) | ||
73 | #define P2WI_LCR_SCL_CTL_EN BIT(2) | ||
74 | #define P2WI_LCR_SDA_CTL BIT(1) | ||
75 | #define P2WI_LCR_SDA_CTL_EN BIT(0) | ||
76 | |||
77 | /* PMU MODE CTRL fields */ | ||
78 | #define P2WI_PMCR_PMU_INIT_SEND BIT(31) | ||
79 | #define P2WI_PMCR_PMU_INIT_DATA(v) (((v) & 0xff) << 16) | ||
80 | #define P2WI_PMCR_PMU_MODE_REG(v) (((v) & 0xff) << 8) | ||
81 | #define P2WI_PMCR_PMU_DEV_ADDR(v) ((v) & 0xff) | ||
82 | |||
83 | #define P2WI_MAX_FREQ 6000000 | ||
84 | |||
85 | struct p2wi { | ||
86 | struct i2c_adapter adapter; | ||
87 | struct completion complete; | ||
88 | unsigned int status; | ||
89 | void __iomem *regs; | ||
90 | struct clk *clk; | ||
91 | struct reset_control *rstc; | ||
92 | int slave_addr; | ||
93 | }; | ||
94 | |||
95 | static irqreturn_t p2wi_interrupt(int irq, void *dev_id) | ||
96 | { | ||
97 | struct p2wi *p2wi = dev_id; | ||
98 | unsigned long status; | ||
99 | |||
100 | status = readl(p2wi->regs + P2WI_INTS); | ||
101 | p2wi->status = status; | ||
102 | |||
103 | /* Clear interrupts */ | ||
104 | status &= (P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR | | ||
105 | P2WI_INTS_TRANS_OVER); | ||
106 | writel(status, p2wi->regs + P2WI_INTS); | ||
107 | |||
108 | complete(&p2wi->complete); | ||
109 | |||
110 | return IRQ_HANDLED; | ||
111 | } | ||
112 | |||
113 | static u32 p2wi_functionality(struct i2c_adapter *adap) | ||
114 | { | ||
115 | return I2C_FUNC_SMBUS_BYTE_DATA; | ||
116 | } | ||
117 | |||
118 | static int p2wi_smbus_xfer(struct i2c_adapter *adap, u16 addr, | ||
119 | unsigned short flags, char read_write, | ||
120 | u8 command, int size, union i2c_smbus_data *data) | ||
121 | { | ||
122 | struct p2wi *p2wi = i2c_get_adapdata(adap); | ||
123 | unsigned long dlen = P2WI_DLEN_DATA_LENGTH(1); | ||
124 | |||
125 | if (p2wi->slave_addr >= 0 && addr != p2wi->slave_addr) { | ||
126 | dev_err(&adap->dev, "invalid P2WI address\n"); | ||
127 | return -EINVAL; | ||
128 | } | ||
129 | |||
130 | if (!data) | ||
131 | return -EINVAL; | ||
132 | |||
133 | writel(command, p2wi->regs + P2WI_DADDR0); | ||
134 | |||
135 | if (read_write == I2C_SMBUS_READ) | ||
136 | dlen |= P2WI_DLEN_READ; | ||
137 | else | ||
138 | writel(data->byte, p2wi->regs + P2WI_DATA0); | ||
139 | |||
140 | writel(dlen, p2wi->regs + P2WI_DLEN); | ||
141 | |||
142 | if (readl(p2wi->regs + P2WI_CTRL) & P2WI_CTRL_START_TRANS) { | ||
143 | dev_err(&adap->dev, "P2WI bus busy\n"); | ||
144 | return -EBUSY; | ||
145 | } | ||
146 | |||
147 | reinit_completion(&p2wi->complete); | ||
148 | |||
149 | writel(P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR | P2WI_INTS_TRANS_OVER, | ||
150 | p2wi->regs + P2WI_INTE); | ||
151 | |||
152 | writel(P2WI_CTRL_START_TRANS | P2WI_CTRL_GLOBAL_INT_ENB, | ||
153 | p2wi->regs + P2WI_CTRL); | ||
154 | |||
155 | wait_for_completion(&p2wi->complete); | ||
156 | |||
157 | if (p2wi->status & P2WI_INTS_LOAD_BSY) { | ||
158 | dev_err(&adap->dev, "P2WI bus busy\n"); | ||
159 | return -EBUSY; | ||
160 | } | ||
161 | |||
162 | if (p2wi->status & P2WI_INTS_TRANS_ERR) { | ||
163 | dev_err(&adap->dev, "P2WI bus xfer error\n"); | ||
164 | return -ENXIO; | ||
165 | } | ||
166 | |||
167 | if (read_write == I2C_SMBUS_READ) | ||
168 | data->byte = readl(p2wi->regs + P2WI_DATA0); | ||
169 | |||
170 | return 0; | ||
171 | } | ||
172 | |||
173 | static const struct i2c_algorithm p2wi_algo = { | ||
174 | .smbus_xfer = p2wi_smbus_xfer, | ||
175 | .functionality = p2wi_functionality, | ||
176 | }; | ||
177 | |||
178 | static const struct of_device_id p2wi_of_match_table[] = { | ||
179 | { .compatible = "allwinner,sun6i-a31-p2wi" }, | ||
180 | {} | ||
181 | }; | ||
182 | MODULE_DEVICE_TABLE(of, p2wi_of_match_table); | ||
183 | |||
184 | static int p2wi_probe(struct platform_device *pdev) | ||
185 | { | ||
186 | struct device *dev = &pdev->dev; | ||
187 | struct device_node *np = dev->of_node; | ||
188 | struct device_node *childnp; | ||
189 | unsigned long parent_clk_freq; | ||
190 | u32 clk_freq = 100000; | ||
191 | struct resource *r; | ||
192 | struct p2wi *p2wi; | ||
193 | u32 slave_addr; | ||
194 | int clk_div; | ||
195 | int irq; | ||
196 | int ret; | ||
197 | |||
198 | of_property_read_u32(np, "clock-frequency", &clk_freq); | ||
199 | if (clk_freq > P2WI_MAX_FREQ) { | ||
200 | dev_err(dev, | ||
201 | "required clock-frequency (%u Hz) is too high (max = 6MHz)", | ||
202 | clk_freq); | ||
203 | return -EINVAL; | ||
204 | } | ||
205 | |||
206 | if (of_get_child_count(np) > 1) { | ||
207 | dev_err(dev, "P2WI only supports one slave device\n"); | ||
208 | return -EINVAL; | ||
209 | } | ||
210 | |||
211 | p2wi = devm_kzalloc(dev, sizeof(struct p2wi), GFP_KERNEL); | ||
212 | if (!p2wi) | ||
213 | return -ENOMEM; | ||
214 | |||
215 | p2wi->slave_addr = -1; | ||
216 | |||
217 | /* | ||
218 | * Authorize a p2wi node without any children to be able to use an | ||
219 | * i2c-dev from userpace. | ||
220 | * In this case the slave_addr is set to -1 and won't be checked when | ||
221 | * launching a P2WI transfer. | ||
222 | */ | ||
223 | childnp = of_get_next_available_child(np, NULL); | ||
224 | if (childnp) { | ||
225 | ret = of_property_read_u32(childnp, "reg", &slave_addr); | ||
226 | if (ret) { | ||
227 | dev_err(dev, "invalid slave address on node %s\n", | ||
228 | childnp->full_name); | ||
229 | return -EINVAL; | ||
230 | } | ||
231 | |||
232 | p2wi->slave_addr = slave_addr; | ||
233 | } | ||
234 | |||
235 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
236 | p2wi->regs = devm_ioremap_resource(dev, r); | ||
237 | if (IS_ERR(p2wi->regs)) | ||
238 | return PTR_ERR(p2wi->regs); | ||
239 | |||
240 | strlcpy(p2wi->adapter.name, pdev->name, sizeof(p2wi->adapter.name)); | ||
241 | irq = platform_get_irq(pdev, 0); | ||
242 | if (irq < 0) { | ||
243 | dev_err(dev, "failed to retrieve irq: %d\n", irq); | ||
244 | return irq; | ||
245 | } | ||
246 | |||
247 | p2wi->clk = devm_clk_get(dev, NULL); | ||
248 | if (IS_ERR(p2wi->clk)) { | ||
249 | ret = PTR_ERR(p2wi->clk); | ||
250 | dev_err(dev, "failed to retrieve clk: %d\n", ret); | ||
251 | return ret; | ||
252 | } | ||
253 | |||
254 | ret = clk_prepare_enable(p2wi->clk); | ||
255 | if (ret) { | ||
256 | dev_err(dev, "failed to enable clk: %d\n", ret); | ||
257 | return ret; | ||
258 | } | ||
259 | |||
260 | parent_clk_freq = clk_get_rate(p2wi->clk); | ||
261 | |||
262 | p2wi->rstc = devm_reset_control_get(dev, NULL); | ||
263 | if (IS_ERR(p2wi->rstc)) { | ||
264 | ret = PTR_ERR(p2wi->rstc); | ||
265 | dev_err(dev, "failed to retrieve reset controller: %d\n", ret); | ||
266 | goto err_clk_disable; | ||
267 | } | ||
268 | |||
269 | ret = reset_control_deassert(p2wi->rstc); | ||
270 | if (ret) { | ||
271 | dev_err(dev, "failed to deassert reset line: %d\n", ret); | ||
272 | goto err_clk_disable; | ||
273 | } | ||
274 | |||
275 | init_completion(&p2wi->complete); | ||
276 | p2wi->adapter.dev.parent = dev; | ||
277 | p2wi->adapter.algo = &p2wi_algo; | ||
278 | p2wi->adapter.owner = THIS_MODULE; | ||
279 | p2wi->adapter.dev.of_node = pdev->dev.of_node; | ||
280 | platform_set_drvdata(pdev, p2wi); | ||
281 | i2c_set_adapdata(&p2wi->adapter, p2wi); | ||
282 | |||
283 | ret = devm_request_irq(dev, irq, p2wi_interrupt, 0, pdev->name, p2wi); | ||
284 | if (ret) { | ||
285 | dev_err(dev, "can't register interrupt handler irq%d: %d\n", | ||
286 | irq, ret); | ||
287 | goto err_reset_assert; | ||
288 | } | ||
289 | |||
290 | writel(P2WI_CTRL_SOFT_RST, p2wi->regs + P2WI_CTRL); | ||
291 | |||
292 | clk_div = parent_clk_freq / clk_freq; | ||
293 | if (!clk_div) { | ||
294 | dev_warn(dev, | ||
295 | "clock-frequency is too high, setting it to %lu Hz\n", | ||
296 | parent_clk_freq); | ||
297 | clk_div = 1; | ||
298 | } else if (clk_div > P2WI_CCR_MAX_CLK_DIV) { | ||
299 | dev_warn(dev, | ||
300 | "clock-frequency is too low, setting it to %lu Hz\n", | ||
301 | parent_clk_freq / P2WI_CCR_MAX_CLK_DIV); | ||
302 | clk_div = P2WI_CCR_MAX_CLK_DIV; | ||
303 | } | ||
304 | |||
305 | writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div), | ||
306 | p2wi->regs + P2WI_CCR); | ||
307 | |||
308 | ret = i2c_add_adapter(&p2wi->adapter); | ||
309 | if (!ret) | ||
310 | return 0; | ||
311 | |||
312 | err_reset_assert: | ||
313 | reset_control_assert(p2wi->rstc); | ||
314 | |||
315 | err_clk_disable: | ||
316 | clk_disable_unprepare(p2wi->clk); | ||
317 | |||
318 | return ret; | ||
319 | } | ||
320 | |||
321 | static int p2wi_remove(struct platform_device *dev) | ||
322 | { | ||
323 | struct p2wi *p2wi = platform_get_drvdata(dev); | ||
324 | |||
325 | reset_control_assert(p2wi->rstc); | ||
326 | clk_disable_unprepare(p2wi->clk); | ||
327 | i2c_del_adapter(&p2wi->adapter); | ||
328 | |||
329 | return 0; | ||
330 | } | ||
331 | |||
332 | static struct platform_driver p2wi_driver = { | ||
333 | .probe = p2wi_probe, | ||
334 | .remove = p2wi_remove, | ||
335 | .driver = { | ||
336 | .owner = THIS_MODULE, | ||
337 | .name = "i2c-sunxi-p2wi", | ||
338 | .of_match_table = p2wi_of_match_table, | ||
339 | }, | ||
340 | }; | ||
341 | module_platform_driver(p2wi_driver); | ||
342 | |||
343 | MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>"); | ||
344 | MODULE_DESCRIPTION("Allwinner P2WI driver"); | ||
345 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c index 8a5e67c4ced1..772e869c280e 100644 --- a/drivers/iio/adc/at91_adc.c +++ b/drivers/iio/adc/at91_adc.c | |||
@@ -510,12 +510,11 @@ static int at91_adc_channel_init(struct iio_dev *idev) | |||
510 | return idev->num_channels; | 510 | return idev->num_channels; |
511 | } | 511 | } |
512 | 512 | ||
513 | static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev, | 513 | static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, |
514 | struct at91_adc_trigger *triggers, | 514 | struct at91_adc_trigger *triggers, |
515 | const char *trigger_name) | 515 | const char *trigger_name) |
516 | { | 516 | { |
517 | struct at91_adc_state *st = iio_priv(idev); | 517 | struct at91_adc_state *st = iio_priv(idev); |
518 | u8 value = 0; | ||
519 | int i; | 518 | int i; |
520 | 519 | ||
521 | for (i = 0; i < st->trigger_number; i++) { | 520 | for (i = 0; i < st->trigger_number; i++) { |
@@ -528,15 +527,16 @@ static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev, | |||
528 | return -ENOMEM; | 527 | return -ENOMEM; |
529 | 528 | ||
530 | if (strcmp(trigger_name, name) == 0) { | 529 | if (strcmp(trigger_name, name) == 0) { |
531 | value = triggers[i].value; | ||
532 | kfree(name); | 530 | kfree(name); |
533 | break; | 531 | if (triggers[i].value == 0) |
532 | return -EINVAL; | ||
533 | return triggers[i].value; | ||
534 | } | 534 | } |
535 | 535 | ||
536 | kfree(name); | 536 | kfree(name); |
537 | } | 537 | } |
538 | 538 | ||
539 | return value; | 539 | return -EINVAL; |
540 | } | 540 | } |
541 | 541 | ||
542 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) | 542 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) |
@@ -546,14 +546,14 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) | |||
546 | struct iio_buffer *buffer = idev->buffer; | 546 | struct iio_buffer *buffer = idev->buffer; |
547 | struct at91_adc_reg_desc *reg = st->registers; | 547 | struct at91_adc_reg_desc *reg = st->registers; |
548 | u32 status = at91_adc_readl(st, reg->trigger_register); | 548 | u32 status = at91_adc_readl(st, reg->trigger_register); |
549 | u8 value; | 549 | int value; |
550 | u8 bit; | 550 | u8 bit; |
551 | 551 | ||
552 | value = at91_adc_get_trigger_value_by_name(idev, | 552 | value = at91_adc_get_trigger_value_by_name(idev, |
553 | st->trigger_list, | 553 | st->trigger_list, |
554 | idev->trig->name); | 554 | idev->trig->name); |
555 | if (value == 0) | 555 | if (value < 0) |
556 | return -EINVAL; | 556 | return value; |
557 | 557 | ||
558 | if (state) { | 558 | if (state) { |
559 | st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); | 559 | st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); |
diff --git a/drivers/iio/adc/men_z188_adc.c b/drivers/iio/adc/men_z188_adc.c index 6989c16aec2b..b58d6302521f 100644 --- a/drivers/iio/adc/men_z188_adc.c +++ b/drivers/iio/adc/men_z188_adc.c | |||
@@ -121,8 +121,8 @@ static int men_z188_probe(struct mcb_device *dev, | |||
121 | indio_dev->num_channels = ARRAY_SIZE(z188_adc_iio_channels); | 121 | indio_dev->num_channels = ARRAY_SIZE(z188_adc_iio_channels); |
122 | 122 | ||
123 | mem = mcb_request_mem(dev, "z188-adc"); | 123 | mem = mcb_request_mem(dev, "z188-adc"); |
124 | if (!mem) | 124 | if (IS_ERR(mem)) |
125 | return -ENOMEM; | 125 | return PTR_ERR(mem); |
126 | 126 | ||
127 | adc->base = ioremap(mem->start, resource_size(mem)); | 127 | adc->base = ioremap(mem->start, resource_size(mem)); |
128 | if (adc->base == NULL) | 128 | if (adc->base == NULL) |
diff --git a/drivers/iio/adc/twl4030-madc.c b/drivers/iio/adc/twl4030-madc.c index 7de1c4c87942..eb86786e698e 100644 --- a/drivers/iio/adc/twl4030-madc.c +++ b/drivers/iio/adc/twl4030-madc.c | |||
@@ -645,6 +645,7 @@ int twl4030_get_madc_conversion(int channel_no) | |||
645 | req.channels = (1 << channel_no); | 645 | req.channels = (1 << channel_no); |
646 | req.method = TWL4030_MADC_SW2; | 646 | req.method = TWL4030_MADC_SW2; |
647 | req.active = 0; | 647 | req.active = 0; |
648 | req.raw = 0; | ||
648 | req.func_cb = NULL; | 649 | req.func_cb = NULL; |
649 | ret = twl4030_madc_conversion(&req); | 650 | ret = twl4030_madc_conversion(&req); |
650 | if (ret < 0) | 651 | if (ret < 0) |
diff --git a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c index 73282cee0c81..a3109a6f4d86 100644 --- a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c +++ b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c | |||
@@ -75,6 +75,9 @@ int hid_sensor_power_state(struct hid_sensor_common *st, bool state) | |||
75 | (s32)report_val); | 75 | (s32)report_val); |
76 | } | 76 | } |
77 | 77 | ||
78 | sensor_hub_get_feature(st->hsdev, st->power_state.report_id, | ||
79 | st->power_state.index, | ||
80 | &state_val); | ||
78 | return 0; | 81 | return 0; |
79 | } | 82 | } |
80 | EXPORT_SYMBOL(hid_sensor_power_state); | 83 | EXPORT_SYMBOL(hid_sensor_power_state); |
diff --git a/drivers/iio/magnetometer/ak8975.c b/drivers/iio/magnetometer/ak8975.c index 09ea5c481f4c..ea08313af0d2 100644 --- a/drivers/iio/magnetometer/ak8975.c +++ b/drivers/iio/magnetometer/ak8975.c | |||
@@ -373,8 +373,6 @@ static int ak8975_read_axis(struct iio_dev *indio_dev, int index, int *val) | |||
373 | { | 373 | { |
374 | struct ak8975_data *data = iio_priv(indio_dev); | 374 | struct ak8975_data *data = iio_priv(indio_dev); |
375 | struct i2c_client *client = data->client; | 375 | struct i2c_client *client = data->client; |
376 | u16 meas_reg; | ||
377 | s16 raw; | ||
378 | int ret; | 376 | int ret; |
379 | 377 | ||
380 | mutex_lock(&data->lock); | 378 | mutex_lock(&data->lock); |
@@ -422,16 +420,11 @@ static int ak8975_read_axis(struct iio_dev *indio_dev, int index, int *val) | |||
422 | dev_err(&client->dev, "Read axis data fails\n"); | 420 | dev_err(&client->dev, "Read axis data fails\n"); |
423 | goto exit; | 421 | goto exit; |
424 | } | 422 | } |
425 | meas_reg = ret; | ||
426 | 423 | ||
427 | mutex_unlock(&data->lock); | 424 | mutex_unlock(&data->lock); |
428 | 425 | ||
429 | /* Endian conversion of the measured values. */ | ||
430 | raw = (s16) (le16_to_cpu(meas_reg)); | ||
431 | |||
432 | /* Clamp to valid range. */ | 426 | /* Clamp to valid range. */ |
433 | raw = clamp_t(s16, raw, -4096, 4095); | 427 | *val = clamp_t(s16, ret, -4096, 4095); |
434 | *val = raw; | ||
435 | return IIO_VAL_INT; | 428 | return IIO_VAL_INT; |
436 | 429 | ||
437 | exit: | 430 | exit: |
diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index ba6d0c520e63..01b2e0b18878 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c | |||
@@ -98,7 +98,7 @@ static int mpl3115_read_raw(struct iio_dev *indio_dev, | |||
98 | mutex_unlock(&data->lock); | 98 | mutex_unlock(&data->lock); |
99 | if (ret < 0) | 99 | if (ret < 0) |
100 | return ret; | 100 | return ret; |
101 | *val = sign_extend32(be32_to_cpu(tmp) >> 12, 23); | 101 | *val = be32_to_cpu(tmp) >> 12; |
102 | return IIO_VAL_INT; | 102 | return IIO_VAL_INT; |
103 | case IIO_TEMP: /* in 0.0625 celsius / LSB */ | 103 | case IIO_TEMP: /* in 0.0625 celsius / LSB */ |
104 | mutex_lock(&data->lock); | 104 | mutex_lock(&data->lock); |
@@ -112,7 +112,7 @@ static int mpl3115_read_raw(struct iio_dev *indio_dev, | |||
112 | mutex_unlock(&data->lock); | 112 | mutex_unlock(&data->lock); |
113 | if (ret < 0) | 113 | if (ret < 0) |
114 | return ret; | 114 | return ret; |
115 | *val = sign_extend32(be32_to_cpu(tmp) >> 20, 15); | 115 | *val = sign_extend32(be32_to_cpu(tmp) >> 20, 11); |
116 | return IIO_VAL_INT; | 116 | return IIO_VAL_INT; |
117 | default: | 117 | default: |
118 | return -EINVAL; | 118 | return -EINVAL; |
@@ -185,7 +185,7 @@ static const struct iio_chan_spec mpl3115_channels[] = { | |||
185 | BIT(IIO_CHAN_INFO_SCALE), | 185 | BIT(IIO_CHAN_INFO_SCALE), |
186 | .scan_index = 0, | 186 | .scan_index = 0, |
187 | .scan_type = { | 187 | .scan_type = { |
188 | .sign = 's', | 188 | .sign = 'u', |
189 | .realbits = 20, | 189 | .realbits = 20, |
190 | .storagebits = 32, | 190 | .storagebits = 32, |
191 | .shift = 12, | 191 | .shift = 12, |
diff --git a/drivers/misc/vexpress-syscfg.c b/drivers/misc/vexpress-syscfg.c index 73068e50e56d..3250fc1df0aa 100644 --- a/drivers/misc/vexpress-syscfg.c +++ b/drivers/misc/vexpress-syscfg.c | |||
@@ -199,7 +199,7 @@ static struct regmap *vexpress_syscfg_regmap_init(struct device *dev, | |||
199 | func = kzalloc(sizeof(*func) + sizeof(*func->template) * num, | 199 | func = kzalloc(sizeof(*func) + sizeof(*func->template) * num, |
200 | GFP_KERNEL); | 200 | GFP_KERNEL); |
201 | if (!func) | 201 | if (!func) |
202 | return NULL; | 202 | return ERR_PTR(-ENOMEM); |
203 | 203 | ||
204 | func->syscfg = syscfg; | 204 | func->syscfg = syscfg; |
205 | func->num_templates = num; | 205 | func->num_templates = num; |
@@ -231,10 +231,14 @@ static struct regmap *vexpress_syscfg_regmap_init(struct device *dev, | |||
231 | func->regmap = regmap_init(dev, NULL, func, | 231 | func->regmap = regmap_init(dev, NULL, func, |
232 | &vexpress_syscfg_regmap_config); | 232 | &vexpress_syscfg_regmap_config); |
233 | 233 | ||
234 | if (IS_ERR(func->regmap)) | 234 | if (IS_ERR(func->regmap)) { |
235 | void *err = func->regmap; | ||
236 | |||
235 | kfree(func); | 237 | kfree(func); |
236 | else | 238 | return err; |
237 | list_add(&func->list, &syscfg->funcs); | 239 | } |
240 | |||
241 | list_add(&func->list, &syscfg->funcs); | ||
238 | 242 | ||
239 | return func->regmap; | 243 | return func->regmap; |
240 | } | 244 | } |
diff --git a/drivers/misc/vmw_balloon.c b/drivers/misc/vmw_balloon.c index 2421835d5daf..191617492181 100644 --- a/drivers/misc/vmw_balloon.c +++ b/drivers/misc/vmw_balloon.c | |||
@@ -17,7 +17,8 @@ | |||
17 | * along with this program; if not, write to the Free Software | 17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
19 | * | 19 | * |
20 | * Maintained by: Dmitry Torokhov <dtor@vmware.com> | 20 | * Maintained by: Xavier Deguillard <xdeguillard@vmware.com> |
21 | * Philip Moltmann <moltmann@vmware.com> | ||
21 | */ | 22 | */ |
22 | 23 | ||
23 | /* | 24 | /* |
diff --git a/drivers/of/base.c b/drivers/of/base.c index 8368d96ae7b4..b9864806e9b8 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c | |||
@@ -227,7 +227,8 @@ static int __of_node_add(struct device_node *np) | |||
227 | np->kobj.kset = of_kset; | 227 | np->kobj.kset = of_kset; |
228 | if (!np->parent) { | 228 | if (!np->parent) { |
229 | /* Nodes without parents are new top level trees */ | 229 | /* Nodes without parents are new top level trees */ |
230 | rc = kobject_add(&np->kobj, NULL, safe_name(&of_kset->kobj, "base")); | 230 | rc = kobject_add(&np->kobj, NULL, "%s", |
231 | safe_name(&of_kset->kobj, "base")); | ||
231 | } else { | 232 | } else { |
232 | name = safe_name(&np->parent->kobj, kbasename(np->full_name)); | 233 | name = safe_name(&np->parent->kobj, kbasename(np->full_name)); |
233 | if (!name || !name[0]) | 234 | if (!name || !name[0]) |
@@ -1960,9 +1961,9 @@ int of_attach_node(struct device_node *np) | |||
1960 | 1961 | ||
1961 | raw_spin_lock_irqsave(&devtree_lock, flags); | 1962 | raw_spin_lock_irqsave(&devtree_lock, flags); |
1962 | np->sibling = np->parent->child; | 1963 | np->sibling = np->parent->child; |
1963 | np->allnext = of_allnodes; | 1964 | np->allnext = np->parent->allnext; |
1965 | np->parent->allnext = np; | ||
1964 | np->parent->child = np; | 1966 | np->parent->child = np; |
1965 | of_allnodes = np; | ||
1966 | of_node_clear_flag(np, OF_DETACHED); | 1967 | of_node_clear_flag(np, OF_DETACHED); |
1967 | raw_spin_unlock_irqrestore(&devtree_lock, flags); | 1968 | raw_spin_unlock_irqrestore(&devtree_lock, flags); |
1968 | 1969 | ||
diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 6c48d73a7fd7..500436f9be7f 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c | |||
@@ -166,10 +166,6 @@ static void of_dma_configure(struct platform_device *pdev) | |||
166 | int ret; | 166 | int ret; |
167 | struct device *dev = &pdev->dev; | 167 | struct device *dev = &pdev->dev; |
168 | 168 | ||
169 | #if defined(CONFIG_MICROBLAZE) | ||
170 | pdev->archdata.dma_mask = 0xffffffffUL; | ||
171 | #endif | ||
172 | |||
173 | /* | 169 | /* |
174 | * Set default dma-mask to 32 bit. Drivers are expected to setup | 170 | * Set default dma-mask to 32 bit. Drivers are expected to setup |
175 | * the correct supported dma_mask. | 171 | * the correct supported dma_mask. |
diff --git a/drivers/regulator/as3722-regulator.c b/drivers/regulator/as3722-regulator.c index 85585219ce82..ad9e0c9b7daf 100644 --- a/drivers/regulator/as3722-regulator.c +++ b/drivers/regulator/as3722-regulator.c | |||
@@ -433,6 +433,7 @@ static struct regulator_ops as3722_ldo3_extcntrl_ops = { | |||
433 | }; | 433 | }; |
434 | 434 | ||
435 | static const struct regulator_linear_range as3722_ldo_ranges[] = { | 435 | static const struct regulator_linear_range as3722_ldo_ranges[] = { |
436 | REGULATOR_LINEAR_RANGE(0, 0x00, 0x00, 0), | ||
436 | REGULATOR_LINEAR_RANGE(825000, 0x01, 0x24, 25000), | 437 | REGULATOR_LINEAR_RANGE(825000, 0x01, 0x24, 25000), |
437 | REGULATOR_LINEAR_RANGE(1725000, 0x40, 0x7F, 25000), | 438 | REGULATOR_LINEAR_RANGE(1725000, 0x40, 0x7F, 25000), |
438 | }; | 439 | }; |
@@ -609,6 +610,7 @@ static bool as3722_sd0_is_low_voltage(struct as3722_regulators *as3722_regs) | |||
609 | } | 610 | } |
610 | 611 | ||
611 | static const struct regulator_linear_range as3722_sd2345_ranges[] = { | 612 | static const struct regulator_linear_range as3722_sd2345_ranges[] = { |
613 | REGULATOR_LINEAR_RANGE(0, 0x00, 0x00, 0), | ||
612 | REGULATOR_LINEAR_RANGE(612500, 0x01, 0x40, 12500), | 614 | REGULATOR_LINEAR_RANGE(612500, 0x01, 0x40, 12500), |
613 | REGULATOR_LINEAR_RANGE(1425000, 0x41, 0x70, 25000), | 615 | REGULATOR_LINEAR_RANGE(1425000, 0x41, 0x70, 25000), |
614 | REGULATOR_LINEAR_RANGE(2650000, 0x71, 0x7F, 50000), | 616 | REGULATOR_LINEAR_RANGE(2650000, 0x71, 0x7F, 50000), |
diff --git a/drivers/regulator/ltc3589.c b/drivers/regulator/ltc3589.c index 110a99ee1162..c8105182b8b8 100644 --- a/drivers/regulator/ltc3589.c +++ b/drivers/regulator/ltc3589.c | |||
@@ -255,7 +255,7 @@ static int ltc3589_parse_regulators_dt(struct ltc3589 *ltc3589) | |||
255 | struct device_node *node; | 255 | struct device_node *node; |
256 | int i, ret; | 256 | int i, ret; |
257 | 257 | ||
258 | node = of_find_node_by_name(dev->of_node, "regulators"); | 258 | node = of_get_child_by_name(dev->of_node, "regulators"); |
259 | if (!node) { | 259 | if (!node) { |
260 | dev_err(dev, "regulators node not found\n"); | 260 | dev_err(dev, "regulators node not found\n"); |
261 | return -EINVAL; | 261 | return -EINVAL; |
diff --git a/drivers/regulator/palmas-regulator.c b/drivers/regulator/palmas-regulator.c index 864ed02ce4b7..b982f0ff4e01 100644 --- a/drivers/regulator/palmas-regulator.c +++ b/drivers/regulator/palmas-regulator.c | |||
@@ -37,12 +37,14 @@ struct regs_info { | |||
37 | }; | 37 | }; |
38 | 38 | ||
39 | static const struct regulator_linear_range smps_low_ranges[] = { | 39 | static const struct regulator_linear_range smps_low_ranges[] = { |
40 | REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), | ||
40 | REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0), | 41 | REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0), |
41 | REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000), | 42 | REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000), |
42 | REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0), | 43 | REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0), |
43 | }; | 44 | }; |
44 | 45 | ||
45 | static const struct regulator_linear_range smps_high_ranges[] = { | 46 | static const struct regulator_linear_range smps_high_ranges[] = { |
47 | REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), | ||
46 | REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0), | 48 | REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0), |
47 | REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000), | 49 | REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000), |
48 | REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0), | 50 | REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0), |
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index ce1743d0b679..5e343bab9458 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig | |||
@@ -44,7 +44,7 @@ config STE_MODEM_RPROC | |||
44 | config DA8XX_REMOTEPROC | 44 | config DA8XX_REMOTEPROC |
45 | tristate "DA8xx/OMAP-L13x remoteproc support" | 45 | tristate "DA8xx/OMAP-L13x remoteproc support" |
46 | depends on ARCH_DAVINCI_DA8XX | 46 | depends on ARCH_DAVINCI_DA8XX |
47 | select CMA | 47 | select CMA if MMU |
48 | select REMOTEPROC | 48 | select REMOTEPROC |
49 | select RPMSG | 49 | select RPMSG |
50 | help | 50 | help |
diff --git a/drivers/rtc/rtc-puv3.c b/drivers/rtc/rtc-puv3.c index 1ecfe3bd92ac..1cff2a21db67 100644 --- a/drivers/rtc/rtc-puv3.c +++ b/drivers/rtc/rtc-puv3.c | |||
@@ -71,7 +71,7 @@ static int puv3_rtc_setpie(struct device *dev, int enabled) | |||
71 | { | 71 | { |
72 | unsigned int tmp; | 72 | unsigned int tmp; |
73 | 73 | ||
74 | dev_debug(dev, "%s: pie=%d\n", __func__, enabled); | 74 | dev_dbg(dev, "%s: pie=%d\n", __func__, enabled); |
75 | 75 | ||
76 | spin_lock_irq(&puv3_rtc_pie_lock); | 76 | spin_lock_irq(&puv3_rtc_pie_lock); |
77 | tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE; | 77 | tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE; |
@@ -140,7 +140,7 @@ static int puv3_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |||
140 | rtc_tm_to_time(tm, &rtcalarm_count); | 140 | rtc_tm_to_time(tm, &rtcalarm_count); |
141 | writel(rtcalarm_count, RTC_RTAR); | 141 | writel(rtcalarm_count, RTC_RTAR); |
142 | 142 | ||
143 | puv3_rtc_setaie(&dev->dev, alrm->enabled); | 143 | puv3_rtc_setaie(dev, alrm->enabled); |
144 | 144 | ||
145 | if (alrm->enabled) | 145 | if (alrm->enabled) |
146 | enable_irq_wake(puv3_rtc_alarmno); | 146 | enable_irq_wake(puv3_rtc_alarmno); |
diff --git a/drivers/s390/block/dcssblk.c b/drivers/s390/block/dcssblk.c index ee0e85abe1fd..0f471750327e 100644 --- a/drivers/s390/block/dcssblk.c +++ b/drivers/s390/block/dcssblk.c | |||
@@ -593,7 +593,7 @@ dcssblk_add_store(struct device *dev, struct device_attribute *attr, const char | |||
593 | dev_info->start = dcssblk_find_lowest_addr(dev_info); | 593 | dev_info->start = dcssblk_find_lowest_addr(dev_info); |
594 | dev_info->end = dcssblk_find_highest_addr(dev_info); | 594 | dev_info->end = dcssblk_find_highest_addr(dev_info); |
595 | 595 | ||
596 | dev_set_name(&dev_info->dev, dev_info->segment_name); | 596 | dev_set_name(&dev_info->dev, "%s", dev_info->segment_name); |
597 | dev_info->dev.release = dcssblk_release_segment; | 597 | dev_info->dev.release = dcssblk_release_segment; |
598 | dev_info->dev.groups = dcssblk_dev_attr_groups; | 598 | dev_info->dev.groups = dcssblk_dev_attr_groups; |
599 | INIT_LIST_HEAD(&dev_info->lh); | 599 | INIT_LIST_HEAD(&dev_info->lh); |
diff --git a/drivers/s390/char/Makefile b/drivers/s390/char/Makefile index 629fcc275e92..78b6ace7edcb 100644 --- a/drivers/s390/char/Makefile +++ b/drivers/s390/char/Makefile | |||
@@ -19,7 +19,6 @@ obj-$(CONFIG_SCLP_VT220_TTY) += sclp_vt220.o | |||
19 | obj-$(CONFIG_SCLP_CPI) += sclp_cpi.o | 19 | obj-$(CONFIG_SCLP_CPI) += sclp_cpi.o |
20 | obj-$(CONFIG_SCLP_ASYNC) += sclp_async.o | 20 | obj-$(CONFIG_SCLP_ASYNC) += sclp_async.o |
21 | 21 | ||
22 | obj-$(CONFIG_ZVM_WATCHDOG) += vmwatchdog.o | ||
23 | obj-$(CONFIG_VMLOGRDR) += vmlogrdr.o | 22 | obj-$(CONFIG_VMLOGRDR) += vmlogrdr.o |
24 | obj-$(CONFIG_VMCP) += vmcp.o | 23 | obj-$(CONFIG_VMCP) += vmcp.o |
25 | 24 | ||
diff --git a/drivers/s390/char/sclp_vt220.c b/drivers/s390/char/sclp_vt220.c index cd9c91909596..b9a9f721716d 100644 --- a/drivers/s390/char/sclp_vt220.c +++ b/drivers/s390/char/sclp_vt220.c | |||
@@ -838,8 +838,6 @@ sclp_vt220_con_init(void) | |||
838 | { | 838 | { |
839 | int rc; | 839 | int rc; |
840 | 840 | ||
841 | if (!CONSOLE_IS_SCLP) | ||
842 | return 0; | ||
843 | rc = __sclp_vt220_init(sclp_console_pages); | 841 | rc = __sclp_vt220_init(sclp_console_pages); |
844 | if (rc) | 842 | if (rc) |
845 | return rc; | 843 | return rc; |
diff --git a/drivers/s390/char/vmlogrdr.c b/drivers/s390/char/vmlogrdr.c index cf31d3321dab..a8848db7b09d 100644 --- a/drivers/s390/char/vmlogrdr.c +++ b/drivers/s390/char/vmlogrdr.c | |||
@@ -761,7 +761,7 @@ static int vmlogrdr_register_device(struct vmlogrdr_priv_t *priv) | |||
761 | 761 | ||
762 | dev = kzalloc(sizeof(struct device), GFP_KERNEL); | 762 | dev = kzalloc(sizeof(struct device), GFP_KERNEL); |
763 | if (dev) { | 763 | if (dev) { |
764 | dev_set_name(dev, priv->internal_name); | 764 | dev_set_name(dev, "%s", priv->internal_name); |
765 | dev->bus = &iucv_bus; | 765 | dev->bus = &iucv_bus; |
766 | dev->parent = iucv_root; | 766 | dev->parent = iucv_root; |
767 | dev->driver = &vmlogrdr_driver; | 767 | dev->driver = &vmlogrdr_driver; |
diff --git a/drivers/s390/char/vmwatchdog.c b/drivers/s390/char/vmwatchdog.c deleted file mode 100644 index d5eac985976b..000000000000 --- a/drivers/s390/char/vmwatchdog.c +++ /dev/null | |||
@@ -1,338 +0,0 @@ | |||
1 | /* | ||
2 | * Watchdog implementation based on z/VM Watchdog Timer API | ||
3 | * | ||
4 | * Copyright IBM Corp. 2004, 2009 | ||
5 | * | ||
6 | * The user space watchdog daemon can use this driver as | ||
7 | * /dev/vmwatchdog to have z/VM execute the specified CP | ||
8 | * command when the timeout expires. The default command is | ||
9 | * "IPL", which which cause an immediate reboot. | ||
10 | */ | ||
11 | #define KMSG_COMPONENT "vmwatchdog" | ||
12 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/fs.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/miscdevice.h> | ||
18 | #include <linux/module.h> | ||
19 | #include <linux/moduleparam.h> | ||
20 | #include <linux/slab.h> | ||
21 | #include <linux/suspend.h> | ||
22 | #include <linux/watchdog.h> | ||
23 | |||
24 | #include <asm/ebcdic.h> | ||
25 | #include <asm/io.h> | ||
26 | #include <asm/uaccess.h> | ||
27 | |||
28 | #define MAX_CMDLEN 240 | ||
29 | #define MIN_INTERVAL 15 | ||
30 | static char vmwdt_cmd[MAX_CMDLEN] = "IPL"; | ||
31 | static bool vmwdt_conceal; | ||
32 | |||
33 | static bool vmwdt_nowayout = WATCHDOG_NOWAYOUT; | ||
34 | |||
35 | MODULE_LICENSE("GPL"); | ||
36 | MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>"); | ||
37 | MODULE_DESCRIPTION("z/VM Watchdog Timer"); | ||
38 | module_param_string(cmd, vmwdt_cmd, MAX_CMDLEN, 0644); | ||
39 | MODULE_PARM_DESC(cmd, "CP command that is run when the watchdog triggers"); | ||
40 | module_param_named(conceal, vmwdt_conceal, bool, 0644); | ||
41 | MODULE_PARM_DESC(conceal, "Enable the CONCEAL CP option while the watchdog " | ||
42 | " is active"); | ||
43 | module_param_named(nowayout, vmwdt_nowayout, bool, 0); | ||
44 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started" | ||
45 | " (default=CONFIG_WATCHDOG_NOWAYOUT)"); | ||
46 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | ||
47 | |||
48 | static unsigned int vmwdt_interval = 60; | ||
49 | static unsigned long vmwdt_is_open; | ||
50 | static int vmwdt_expect_close; | ||
51 | |||
52 | static DEFINE_MUTEX(vmwdt_mutex); | ||
53 | |||
54 | #define VMWDT_OPEN 0 /* devnode is open or suspend in progress */ | ||
55 | #define VMWDT_RUNNING 1 /* The watchdog is armed */ | ||
56 | |||
57 | enum vmwdt_func { | ||
58 | /* function codes */ | ||
59 | wdt_init = 0, | ||
60 | wdt_change = 1, | ||
61 | wdt_cancel = 2, | ||
62 | /* flags */ | ||
63 | wdt_conceal = 0x80000000, | ||
64 | }; | ||
65 | |||
66 | static int __diag288(enum vmwdt_func func, unsigned int timeout, | ||
67 | char *cmd, size_t len) | ||
68 | { | ||
69 | register unsigned long __func asm("2") = func; | ||
70 | register unsigned long __timeout asm("3") = timeout; | ||
71 | register unsigned long __cmdp asm("4") = virt_to_phys(cmd); | ||
72 | register unsigned long __cmdl asm("5") = len; | ||
73 | int err; | ||
74 | |||
75 | err = -EINVAL; | ||
76 | asm volatile( | ||
77 | " diag %1,%3,0x288\n" | ||
78 | "0: la %0,0\n" | ||
79 | "1:\n" | ||
80 | EX_TABLE(0b,1b) | ||
81 | : "+d" (err) : "d"(__func), "d"(__timeout), | ||
82 | "d"(__cmdp), "d"(__cmdl) : "1", "cc"); | ||
83 | return err; | ||
84 | } | ||
85 | |||
86 | static int vmwdt_keepalive(void) | ||
87 | { | ||
88 | /* we allocate new memory every time to avoid having | ||
89 | * to track the state. static allocation is not an | ||
90 | * option since that might not be contiguous in real | ||
91 | * storage in case of a modular build */ | ||
92 | static char *ebc_cmd; | ||
93 | size_t len; | ||
94 | int ret; | ||
95 | unsigned int func; | ||
96 | |||
97 | ebc_cmd = kmalloc(MAX_CMDLEN, GFP_KERNEL); | ||
98 | if (!ebc_cmd) | ||
99 | return -ENOMEM; | ||
100 | |||
101 | len = strlcpy(ebc_cmd, vmwdt_cmd, MAX_CMDLEN); | ||
102 | ASCEBC(ebc_cmd, MAX_CMDLEN); | ||
103 | EBC_TOUPPER(ebc_cmd, MAX_CMDLEN); | ||
104 | |||
105 | func = vmwdt_conceal ? (wdt_init | wdt_conceal) : wdt_init; | ||
106 | set_bit(VMWDT_RUNNING, &vmwdt_is_open); | ||
107 | ret = __diag288(func, vmwdt_interval, ebc_cmd, len); | ||
108 | WARN_ON(ret != 0); | ||
109 | kfree(ebc_cmd); | ||
110 | return ret; | ||
111 | } | ||
112 | |||
113 | static int vmwdt_disable(void) | ||
114 | { | ||
115 | char cmd[] = {'\0'}; | ||
116 | int ret = __diag288(wdt_cancel, 0, cmd, 0); | ||
117 | WARN_ON(ret != 0); | ||
118 | clear_bit(VMWDT_RUNNING, &vmwdt_is_open); | ||
119 | return ret; | ||
120 | } | ||
121 | |||
122 | static int __init vmwdt_probe(void) | ||
123 | { | ||
124 | /* there is no real way to see if the watchdog is supported, | ||
125 | * so we try initializing it with a NOP command ("BEGIN") | ||
126 | * that won't cause any harm even if the following disable | ||
127 | * fails for some reason */ | ||
128 | char ebc_begin[] = { | ||
129 | 194, 197, 199, 201, 213 | ||
130 | }; | ||
131 | if (__diag288(wdt_init, 15, ebc_begin, sizeof(ebc_begin)) != 0) | ||
132 | return -EINVAL; | ||
133 | return vmwdt_disable(); | ||
134 | } | ||
135 | |||
136 | static int vmwdt_open(struct inode *i, struct file *f) | ||
137 | { | ||
138 | int ret; | ||
139 | if (test_and_set_bit(VMWDT_OPEN, &vmwdt_is_open)) | ||
140 | return -EBUSY; | ||
141 | ret = vmwdt_keepalive(); | ||
142 | if (ret) | ||
143 | clear_bit(VMWDT_OPEN, &vmwdt_is_open); | ||
144 | return ret ? ret : nonseekable_open(i, f); | ||
145 | } | ||
146 | |||
147 | static int vmwdt_close(struct inode *i, struct file *f) | ||
148 | { | ||
149 | if (vmwdt_expect_close == 42) | ||
150 | vmwdt_disable(); | ||
151 | vmwdt_expect_close = 0; | ||
152 | clear_bit(VMWDT_OPEN, &vmwdt_is_open); | ||
153 | return 0; | ||
154 | } | ||
155 | |||
156 | static struct watchdog_info vmwdt_info = { | ||
157 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | ||
158 | .firmware_version = 0, | ||
159 | .identity = "z/VM Watchdog Timer", | ||
160 | }; | ||
161 | |||
162 | static int __vmwdt_ioctl(unsigned int cmd, unsigned long arg) | ||
163 | { | ||
164 | switch (cmd) { | ||
165 | case WDIOC_GETSUPPORT: | ||
166 | if (copy_to_user((void __user *)arg, &vmwdt_info, | ||
167 | sizeof(vmwdt_info))) | ||
168 | return -EFAULT; | ||
169 | return 0; | ||
170 | case WDIOC_GETSTATUS: | ||
171 | case WDIOC_GETBOOTSTATUS: | ||
172 | return put_user(0, (int __user *)arg); | ||
173 | case WDIOC_GETTEMP: | ||
174 | return -EINVAL; | ||
175 | case WDIOC_SETOPTIONS: | ||
176 | { | ||
177 | int options, ret; | ||
178 | if (get_user(options, (int __user *)arg)) | ||
179 | return -EFAULT; | ||
180 | ret = -EINVAL; | ||
181 | if (options & WDIOS_DISABLECARD) { | ||
182 | ret = vmwdt_disable(); | ||
183 | if (ret) | ||
184 | return ret; | ||
185 | } | ||
186 | if (options & WDIOS_ENABLECARD) { | ||
187 | ret = vmwdt_keepalive(); | ||
188 | } | ||
189 | return ret; | ||
190 | } | ||
191 | case WDIOC_GETTIMEOUT: | ||
192 | return put_user(vmwdt_interval, (int __user *)arg); | ||
193 | case WDIOC_SETTIMEOUT: | ||
194 | { | ||
195 | int interval; | ||
196 | if (get_user(interval, (int __user *)arg)) | ||
197 | return -EFAULT; | ||
198 | if (interval < MIN_INTERVAL) | ||
199 | return -EINVAL; | ||
200 | vmwdt_interval = interval; | ||
201 | } | ||
202 | return vmwdt_keepalive(); | ||
203 | case WDIOC_KEEPALIVE: | ||
204 | return vmwdt_keepalive(); | ||
205 | } | ||
206 | return -EINVAL; | ||
207 | } | ||
208 | |||
209 | static long vmwdt_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | ||
210 | { | ||
211 | int rc; | ||
212 | |||
213 | mutex_lock(&vmwdt_mutex); | ||
214 | rc = __vmwdt_ioctl(cmd, arg); | ||
215 | mutex_unlock(&vmwdt_mutex); | ||
216 | return (long) rc; | ||
217 | } | ||
218 | |||
219 | static ssize_t vmwdt_write(struct file *f, const char __user *buf, | ||
220 | size_t count, loff_t *ppos) | ||
221 | { | ||
222 | if(count) { | ||
223 | if (!vmwdt_nowayout) { | ||
224 | size_t i; | ||
225 | |||
226 | /* note: just in case someone wrote the magic character | ||
227 | * five months ago... */ | ||
228 | vmwdt_expect_close = 0; | ||
229 | |||
230 | for (i = 0; i != count; i++) { | ||
231 | char c; | ||
232 | if (get_user(c, buf+i)) | ||
233 | return -EFAULT; | ||
234 | if (c == 'V') | ||
235 | vmwdt_expect_close = 42; | ||
236 | } | ||
237 | } | ||
238 | /* someone wrote to us, we should restart timer */ | ||
239 | vmwdt_keepalive(); | ||
240 | } | ||
241 | return count; | ||
242 | } | ||
243 | |||
244 | static int vmwdt_resume(void) | ||
245 | { | ||
246 | clear_bit(VMWDT_OPEN, &vmwdt_is_open); | ||
247 | return NOTIFY_DONE; | ||
248 | } | ||
249 | |||
250 | /* | ||
251 | * It makes no sense to go into suspend while the watchdog is running. | ||
252 | * Depending on the memory size, the watchdog might trigger, while we | ||
253 | * are still saving the memory. | ||
254 | * We reuse the open flag to ensure that suspend and watchdog open are | ||
255 | * exclusive operations | ||
256 | */ | ||
257 | static int vmwdt_suspend(void) | ||
258 | { | ||
259 | if (test_and_set_bit(VMWDT_OPEN, &vmwdt_is_open)) { | ||
260 | pr_err("The system cannot be suspended while the watchdog" | ||
261 | " is in use\n"); | ||
262 | return notifier_from_errno(-EBUSY); | ||
263 | } | ||
264 | if (test_bit(VMWDT_RUNNING, &vmwdt_is_open)) { | ||
265 | clear_bit(VMWDT_OPEN, &vmwdt_is_open); | ||
266 | pr_err("The system cannot be suspended while the watchdog" | ||
267 | " is running\n"); | ||
268 | return notifier_from_errno(-EBUSY); | ||
269 | } | ||
270 | return NOTIFY_DONE; | ||
271 | } | ||
272 | |||
273 | /* | ||
274 | * This function is called for suspend and resume. | ||
275 | */ | ||
276 | static int vmwdt_power_event(struct notifier_block *this, unsigned long event, | ||
277 | void *ptr) | ||
278 | { | ||
279 | switch (event) { | ||
280 | case PM_POST_HIBERNATION: | ||
281 | case PM_POST_SUSPEND: | ||
282 | return vmwdt_resume(); | ||
283 | case PM_HIBERNATION_PREPARE: | ||
284 | case PM_SUSPEND_PREPARE: | ||
285 | return vmwdt_suspend(); | ||
286 | default: | ||
287 | return NOTIFY_DONE; | ||
288 | } | ||
289 | } | ||
290 | |||
291 | static struct notifier_block vmwdt_power_notifier = { | ||
292 | .notifier_call = vmwdt_power_event, | ||
293 | }; | ||
294 | |||
295 | static const struct file_operations vmwdt_fops = { | ||
296 | .open = &vmwdt_open, | ||
297 | .release = &vmwdt_close, | ||
298 | .unlocked_ioctl = &vmwdt_ioctl, | ||
299 | .write = &vmwdt_write, | ||
300 | .owner = THIS_MODULE, | ||
301 | .llseek = noop_llseek, | ||
302 | }; | ||
303 | |||
304 | static struct miscdevice vmwdt_dev = { | ||
305 | .minor = WATCHDOG_MINOR, | ||
306 | .name = "watchdog", | ||
307 | .fops = &vmwdt_fops, | ||
308 | }; | ||
309 | |||
310 | static int __init vmwdt_init(void) | ||
311 | { | ||
312 | int ret; | ||
313 | |||
314 | ret = vmwdt_probe(); | ||
315 | if (ret) | ||
316 | return ret; | ||
317 | ret = register_pm_notifier(&vmwdt_power_notifier); | ||
318 | if (ret) | ||
319 | return ret; | ||
320 | /* | ||
321 | * misc_register() has to be the last action in module_init(), because | ||
322 | * file operations will be available right after this. | ||
323 | */ | ||
324 | ret = misc_register(&vmwdt_dev); | ||
325 | if (ret) { | ||
326 | unregister_pm_notifier(&vmwdt_power_notifier); | ||
327 | return ret; | ||
328 | } | ||
329 | return 0; | ||
330 | } | ||
331 | module_init(vmwdt_init); | ||
332 | |||
333 | static void __exit vmwdt_exit(void) | ||
334 | { | ||
335 | unregister_pm_notifier(&vmwdt_power_notifier); | ||
336 | misc_deregister(&vmwdt_dev); | ||
337 | } | ||
338 | module_exit(vmwdt_exit); | ||
diff --git a/drivers/s390/cio/airq.c b/drivers/s390/cio/airq.c index 445564c790f6..00bfbee0af9e 100644 --- a/drivers/s390/cio/airq.c +++ b/drivers/s390/cio/airq.c | |||
@@ -196,11 +196,11 @@ EXPORT_SYMBOL(airq_iv_release); | |||
196 | */ | 196 | */ |
197 | unsigned long airq_iv_alloc(struct airq_iv *iv, unsigned long num) | 197 | unsigned long airq_iv_alloc(struct airq_iv *iv, unsigned long num) |
198 | { | 198 | { |
199 | unsigned long bit, i; | 199 | unsigned long bit, i, flags; |
200 | 200 | ||
201 | if (!iv->avail || num == 0) | 201 | if (!iv->avail || num == 0) |
202 | return -1UL; | 202 | return -1UL; |
203 | spin_lock(&iv->lock); | 203 | spin_lock_irqsave(&iv->lock, flags); |
204 | bit = find_first_bit_inv(iv->avail, iv->bits); | 204 | bit = find_first_bit_inv(iv->avail, iv->bits); |
205 | while (bit + num <= iv->bits) { | 205 | while (bit + num <= iv->bits) { |
206 | for (i = 1; i < num; i++) | 206 | for (i = 1; i < num; i++) |
@@ -218,9 +218,8 @@ unsigned long airq_iv_alloc(struct airq_iv *iv, unsigned long num) | |||
218 | } | 218 | } |
219 | if (bit + num > iv->bits) | 219 | if (bit + num > iv->bits) |
220 | bit = -1UL; | 220 | bit = -1UL; |
221 | spin_unlock(&iv->lock); | 221 | spin_unlock_irqrestore(&iv->lock, flags); |
222 | return bit; | 222 | return bit; |
223 | |||
224 | } | 223 | } |
225 | EXPORT_SYMBOL(airq_iv_alloc); | 224 | EXPORT_SYMBOL(airq_iv_alloc); |
226 | 225 | ||
@@ -232,11 +231,11 @@ EXPORT_SYMBOL(airq_iv_alloc); | |||
232 | */ | 231 | */ |
233 | void airq_iv_free(struct airq_iv *iv, unsigned long bit, unsigned long num) | 232 | void airq_iv_free(struct airq_iv *iv, unsigned long bit, unsigned long num) |
234 | { | 233 | { |
235 | unsigned long i; | 234 | unsigned long i, flags; |
236 | 235 | ||
237 | if (!iv->avail || num == 0) | 236 | if (!iv->avail || num == 0) |
238 | return; | 237 | return; |
239 | spin_lock(&iv->lock); | 238 | spin_lock_irqsave(&iv->lock, flags); |
240 | for (i = 0; i < num; i++) { | 239 | for (i = 0; i < num; i++) { |
241 | /* Clear (possibly left over) interrupt bit */ | 240 | /* Clear (possibly left over) interrupt bit */ |
242 | clear_bit_inv(bit + i, iv->vector); | 241 | clear_bit_inv(bit + i, iv->vector); |
@@ -248,7 +247,7 @@ void airq_iv_free(struct airq_iv *iv, unsigned long bit, unsigned long num) | |||
248 | while (iv->end > 0 && !test_bit_inv(iv->end - 1, iv->avail)) | 247 | while (iv->end > 0 && !test_bit_inv(iv->end - 1, iv->avail)) |
249 | iv->end--; | 248 | iv->end--; |
250 | } | 249 | } |
251 | spin_unlock(&iv->lock); | 250 | spin_unlock_irqrestore(&iv->lock, flags); |
252 | } | 251 | } |
253 | EXPORT_SYMBOL(airq_iv_free); | 252 | EXPORT_SYMBOL(airq_iv_free); |
254 | 253 | ||
diff --git a/drivers/s390/cio/ccwgroup.c b/drivers/s390/cio/ccwgroup.c index dfd7bc681c25..e443b0d0b236 100644 --- a/drivers/s390/cio/ccwgroup.c +++ b/drivers/s390/cio/ccwgroup.c | |||
@@ -184,7 +184,7 @@ static ssize_t ccwgroup_ungroup_store(struct device *dev, | |||
184 | const char *buf, size_t count) | 184 | const char *buf, size_t count) |
185 | { | 185 | { |
186 | struct ccwgroup_device *gdev = to_ccwgroupdev(dev); | 186 | struct ccwgroup_device *gdev = to_ccwgroupdev(dev); |
187 | int rc; | 187 | int rc = 0; |
188 | 188 | ||
189 | /* Prevent concurrent online/offline processing and ungrouping. */ | 189 | /* Prevent concurrent online/offline processing and ungrouping. */ |
190 | if (atomic_cmpxchg(&gdev->onoff, 0, 1) != 0) | 190 | if (atomic_cmpxchg(&gdev->onoff, 0, 1) != 0) |
@@ -196,11 +196,12 @@ static ssize_t ccwgroup_ungroup_store(struct device *dev, | |||
196 | 196 | ||
197 | if (device_remove_file_self(dev, attr)) | 197 | if (device_remove_file_self(dev, attr)) |
198 | ccwgroup_ungroup(gdev); | 198 | ccwgroup_ungroup(gdev); |
199 | else | ||
200 | rc = -ENODEV; | ||
199 | out: | 201 | out: |
200 | if (rc) { | 202 | if (rc) { |
201 | if (rc != -EAGAIN) | 203 | /* Release onoff "lock" when ungrouping failed. */ |
202 | /* Release onoff "lock" when ungrouping failed. */ | 204 | atomic_set(&gdev->onoff, 0); |
203 | atomic_set(&gdev->onoff, 0); | ||
204 | return rc; | 205 | return rc; |
205 | } | 206 | } |
206 | return count; | 207 | return count; |
@@ -227,6 +228,7 @@ static void ccwgroup_ungroup_workfn(struct work_struct *work) | |||
227 | container_of(work, struct ccwgroup_device, ungroup_work); | 228 | container_of(work, struct ccwgroup_device, ungroup_work); |
228 | 229 | ||
229 | ccwgroup_ungroup(gdev); | 230 | ccwgroup_ungroup(gdev); |
231 | put_device(&gdev->dev); | ||
230 | } | 232 | } |
231 | 233 | ||
232 | static void ccwgroup_release(struct device *dev) | 234 | static void ccwgroup_release(struct device *dev) |
@@ -412,8 +414,10 @@ static int ccwgroup_notifier(struct notifier_block *nb, unsigned long action, | |||
412 | { | 414 | { |
413 | struct ccwgroup_device *gdev = to_ccwgroupdev(data); | 415 | struct ccwgroup_device *gdev = to_ccwgroupdev(data); |
414 | 416 | ||
415 | if (action == BUS_NOTIFY_UNBIND_DRIVER) | 417 | if (action == BUS_NOTIFY_UNBIND_DRIVER) { |
418 | get_device(&gdev->dev); | ||
416 | schedule_work(&gdev->ungroup_work); | 419 | schedule_work(&gdev->ungroup_work); |
420 | } | ||
417 | 421 | ||
418 | return NOTIFY_OK; | 422 | return NOTIFY_OK; |
419 | } | 423 | } |
@@ -582,11 +586,7 @@ void ccwgroup_driver_unregister(struct ccwgroup_driver *cdriver) | |||
582 | __ccwgroup_match_all))) { | 586 | __ccwgroup_match_all))) { |
583 | struct ccwgroup_device *gdev = to_ccwgroupdev(dev); | 587 | struct ccwgroup_device *gdev = to_ccwgroupdev(dev); |
584 | 588 | ||
585 | mutex_lock(&gdev->reg_mutex); | 589 | ccwgroup_ungroup(gdev); |
586 | __ccwgroup_remove_symlinks(gdev); | ||
587 | device_unregister(dev); | ||
588 | __ccwgroup_remove_cdev_refs(gdev); | ||
589 | mutex_unlock(&gdev->reg_mutex); | ||
590 | put_device(dev); | 590 | put_device(dev); |
591 | } | 591 | } |
592 | driver_unregister(&cdriver->driver); | 592 | driver_unregister(&cdriver->driver); |
@@ -633,13 +633,7 @@ void ccwgroup_remove_ccwdev(struct ccw_device *cdev) | |||
633 | get_device(&gdev->dev); | 633 | get_device(&gdev->dev); |
634 | spin_unlock_irq(cdev->ccwlock); | 634 | spin_unlock_irq(cdev->ccwlock); |
635 | /* Unregister group device. */ | 635 | /* Unregister group device. */ |
636 | mutex_lock(&gdev->reg_mutex); | 636 | ccwgroup_ungroup(gdev); |
637 | if (device_is_registered(&gdev->dev)) { | ||
638 | __ccwgroup_remove_symlinks(gdev); | ||
639 | device_unregister(&gdev->dev); | ||
640 | __ccwgroup_remove_cdev_refs(gdev); | ||
641 | } | ||
642 | mutex_unlock(&gdev->reg_mutex); | ||
643 | /* Release ccwgroup device reference for local processing. */ | 637 | /* Release ccwgroup device reference for local processing. */ |
644 | put_device(&gdev->dev); | 638 | put_device(&gdev->dev); |
645 | } | 639 | } |
diff --git a/drivers/s390/cio/cio.c b/drivers/s390/cio/cio.c index 77f9c92df4b9..2905d8b0ec95 100644 --- a/drivers/s390/cio/cio.c +++ b/drivers/s390/cio/cio.c | |||
@@ -602,6 +602,7 @@ void __init init_cio_interrupts(void) | |||
602 | 602 | ||
603 | #ifdef CONFIG_CCW_CONSOLE | 603 | #ifdef CONFIG_CCW_CONSOLE |
604 | static struct subchannel *console_sch; | 604 | static struct subchannel *console_sch; |
605 | static struct lock_class_key console_sch_key; | ||
605 | 606 | ||
606 | /* | 607 | /* |
607 | * Use cio_tsch to update the subchannel status and call the interrupt handler | 608 | * Use cio_tsch to update the subchannel status and call the interrupt handler |
@@ -686,6 +687,7 @@ struct subchannel *cio_probe_console(void) | |||
686 | if (IS_ERR(sch)) | 687 | if (IS_ERR(sch)) |
687 | return sch; | 688 | return sch; |
688 | 689 | ||
690 | lockdep_set_class(sch->lock, &console_sch_key); | ||
689 | isc_register(CONSOLE_ISC); | 691 | isc_register(CONSOLE_ISC); |
690 | sch->config.isc = CONSOLE_ISC; | 692 | sch->config.isc = CONSOLE_ISC; |
691 | sch->config.intparm = (u32)(addr_t)sch; | 693 | sch->config.intparm = (u32)(addr_t)sch; |
diff --git a/drivers/s390/cio/device.c b/drivers/s390/cio/device.c index d8d9b5b5cc56..dfef5e63cb7b 100644 --- a/drivers/s390/cio/device.c +++ b/drivers/s390/cio/device.c | |||
@@ -678,18 +678,11 @@ static const struct attribute_group *ccwdev_attr_groups[] = { | |||
678 | NULL, | 678 | NULL, |
679 | }; | 679 | }; |
680 | 680 | ||
681 | /* this is a simple abstraction for device_register that sets the | 681 | static int ccw_device_add(struct ccw_device *cdev) |
682 | * correct bus type and adds the bus specific files */ | ||
683 | static int ccw_device_register(struct ccw_device *cdev) | ||
684 | { | 682 | { |
685 | struct device *dev = &cdev->dev; | 683 | struct device *dev = &cdev->dev; |
686 | int ret; | ||
687 | 684 | ||
688 | dev->bus = &ccw_bus_type; | 685 | dev->bus = &ccw_bus_type; |
689 | ret = dev_set_name(&cdev->dev, "0.%x.%04x", cdev->private->dev_id.ssid, | ||
690 | cdev->private->dev_id.devno); | ||
691 | if (ret) | ||
692 | return ret; | ||
693 | return device_add(dev); | 686 | return device_add(dev); |
694 | } | 687 | } |
695 | 688 | ||
@@ -764,22 +757,46 @@ static void ccw_device_todo(struct work_struct *work); | |||
764 | static int io_subchannel_initialize_dev(struct subchannel *sch, | 757 | static int io_subchannel_initialize_dev(struct subchannel *sch, |
765 | struct ccw_device *cdev) | 758 | struct ccw_device *cdev) |
766 | { | 759 | { |
767 | cdev->private->cdev = cdev; | 760 | struct ccw_device_private *priv = cdev->private; |
768 | cdev->private->int_class = IRQIO_CIO; | 761 | int ret; |
769 | atomic_set(&cdev->private->onoff, 0); | 762 | |
763 | priv->cdev = cdev; | ||
764 | priv->int_class = IRQIO_CIO; | ||
765 | priv->state = DEV_STATE_NOT_OPER; | ||
766 | priv->dev_id.devno = sch->schib.pmcw.dev; | ||
767 | priv->dev_id.ssid = sch->schid.ssid; | ||
768 | priv->schid = sch->schid; | ||
769 | |||
770 | INIT_WORK(&priv->todo_work, ccw_device_todo); | ||
771 | INIT_LIST_HEAD(&priv->cmb_list); | ||
772 | init_waitqueue_head(&priv->wait_q); | ||
773 | init_timer(&priv->timer); | ||
774 | |||
775 | atomic_set(&priv->onoff, 0); | ||
776 | cdev->ccwlock = sch->lock; | ||
770 | cdev->dev.parent = &sch->dev; | 777 | cdev->dev.parent = &sch->dev; |
771 | cdev->dev.release = ccw_device_release; | 778 | cdev->dev.release = ccw_device_release; |
772 | INIT_WORK(&cdev->private->todo_work, ccw_device_todo); | ||
773 | cdev->dev.groups = ccwdev_attr_groups; | 779 | cdev->dev.groups = ccwdev_attr_groups; |
774 | /* Do first half of device_register. */ | 780 | /* Do first half of device_register. */ |
775 | device_initialize(&cdev->dev); | 781 | device_initialize(&cdev->dev); |
782 | ret = dev_set_name(&cdev->dev, "0.%x.%04x", cdev->private->dev_id.ssid, | ||
783 | cdev->private->dev_id.devno); | ||
784 | if (ret) | ||
785 | goto out_put; | ||
776 | if (!get_device(&sch->dev)) { | 786 | if (!get_device(&sch->dev)) { |
777 | /* Release reference from device_initialize(). */ | 787 | ret = -ENODEV; |
778 | put_device(&cdev->dev); | 788 | goto out_put; |
779 | return -ENODEV; | ||
780 | } | 789 | } |
781 | cdev->private->flags.initialized = 1; | 790 | priv->flags.initialized = 1; |
791 | spin_lock_irq(sch->lock); | ||
792 | sch_set_cdev(sch, cdev); | ||
793 | spin_unlock_irq(sch->lock); | ||
782 | return 0; | 794 | return 0; |
795 | |||
796 | out_put: | ||
797 | /* Release reference from device_initialize(). */ | ||
798 | put_device(&cdev->dev); | ||
799 | return ret; | ||
783 | } | 800 | } |
784 | 801 | ||
785 | static struct ccw_device * io_subchannel_create_ccwdev(struct subchannel *sch) | 802 | static struct ccw_device * io_subchannel_create_ccwdev(struct subchannel *sch) |
@@ -858,7 +875,7 @@ static void io_subchannel_register(struct ccw_device *cdev) | |||
858 | dev_set_uevent_suppress(&sch->dev, 0); | 875 | dev_set_uevent_suppress(&sch->dev, 0); |
859 | kobject_uevent(&sch->dev.kobj, KOBJ_ADD); | 876 | kobject_uevent(&sch->dev.kobj, KOBJ_ADD); |
860 | /* make it known to the system */ | 877 | /* make it known to the system */ |
861 | ret = ccw_device_register(cdev); | 878 | ret = ccw_device_add(cdev); |
862 | if (ret) { | 879 | if (ret) { |
863 | CIO_MSG_EVENT(0, "Could not register ccw dev 0.%x.%04x: %d\n", | 880 | CIO_MSG_EVENT(0, "Could not register ccw dev 0.%x.%04x: %d\n", |
864 | cdev->private->dev_id.ssid, | 881 | cdev->private->dev_id.ssid, |
@@ -923,26 +940,11 @@ io_subchannel_recog_done(struct ccw_device *cdev) | |||
923 | 940 | ||
924 | static void io_subchannel_recog(struct ccw_device *cdev, struct subchannel *sch) | 941 | static void io_subchannel_recog(struct ccw_device *cdev, struct subchannel *sch) |
925 | { | 942 | { |
926 | struct ccw_device_private *priv; | ||
927 | |||
928 | cdev->ccwlock = sch->lock; | ||
929 | |||
930 | /* Init private data. */ | ||
931 | priv = cdev->private; | ||
932 | priv->dev_id.devno = sch->schib.pmcw.dev; | ||
933 | priv->dev_id.ssid = sch->schid.ssid; | ||
934 | priv->schid = sch->schid; | ||
935 | priv->state = DEV_STATE_NOT_OPER; | ||
936 | INIT_LIST_HEAD(&priv->cmb_list); | ||
937 | init_waitqueue_head(&priv->wait_q); | ||
938 | init_timer(&priv->timer); | ||
939 | |||
940 | /* Increase counter of devices currently in recognition. */ | 943 | /* Increase counter of devices currently in recognition. */ |
941 | atomic_inc(&ccw_device_init_count); | 944 | atomic_inc(&ccw_device_init_count); |
942 | 945 | ||
943 | /* Start async. device sensing. */ | 946 | /* Start async. device sensing. */ |
944 | spin_lock_irq(sch->lock); | 947 | spin_lock_irq(sch->lock); |
945 | sch_set_cdev(sch, cdev); | ||
946 | ccw_device_recognition(cdev); | 948 | ccw_device_recognition(cdev); |
947 | spin_unlock_irq(sch->lock); | 949 | spin_unlock_irq(sch->lock); |
948 | } | 950 | } |
@@ -1083,7 +1085,7 @@ static int io_subchannel_probe(struct subchannel *sch) | |||
1083 | dev_set_uevent_suppress(&sch->dev, 0); | 1085 | dev_set_uevent_suppress(&sch->dev, 0); |
1084 | kobject_uevent(&sch->dev.kobj, KOBJ_ADD); | 1086 | kobject_uevent(&sch->dev.kobj, KOBJ_ADD); |
1085 | cdev = sch_get_cdev(sch); | 1087 | cdev = sch_get_cdev(sch); |
1086 | rc = ccw_device_register(cdev); | 1088 | rc = ccw_device_add(cdev); |
1087 | if (rc) { | 1089 | if (rc) { |
1088 | /* Release online reference. */ | 1090 | /* Release online reference. */ |
1089 | put_device(&cdev->dev); | 1091 | put_device(&cdev->dev); |
@@ -1597,7 +1599,6 @@ int __init ccw_device_enable_console(struct ccw_device *cdev) | |||
1597 | if (rc) | 1599 | if (rc) |
1598 | return rc; | 1600 | return rc; |
1599 | sch->driver = &io_subchannel_driver; | 1601 | sch->driver = &io_subchannel_driver; |
1600 | sch_set_cdev(sch, cdev); | ||
1601 | io_subchannel_recog(cdev, sch); | 1602 | io_subchannel_recog(cdev, sch); |
1602 | /* Now wait for the async. recognition to come to an end. */ | 1603 | /* Now wait for the async. recognition to come to an end. */ |
1603 | spin_lock_irq(cdev->ccwlock); | 1604 | spin_lock_irq(cdev->ccwlock); |
@@ -1639,6 +1640,7 @@ struct ccw_device * __init ccw_device_create_console(struct ccw_driver *drv) | |||
1639 | put_device(&sch->dev); | 1640 | put_device(&sch->dev); |
1640 | return ERR_PTR(-ENOMEM); | 1641 | return ERR_PTR(-ENOMEM); |
1641 | } | 1642 | } |
1643 | set_io_private(sch, io_priv); | ||
1642 | cdev = io_subchannel_create_ccwdev(sch); | 1644 | cdev = io_subchannel_create_ccwdev(sch); |
1643 | if (IS_ERR(cdev)) { | 1645 | if (IS_ERR(cdev)) { |
1644 | put_device(&sch->dev); | 1646 | put_device(&sch->dev); |
@@ -1646,7 +1648,6 @@ struct ccw_device * __init ccw_device_create_console(struct ccw_driver *drv) | |||
1646 | return cdev; | 1648 | return cdev; |
1647 | } | 1649 | } |
1648 | cdev->drv = drv; | 1650 | cdev->drv = drv; |
1649 | set_io_private(sch, io_priv); | ||
1650 | ccw_device_set_int_class(cdev); | 1651 | ccw_device_set_int_class(cdev); |
1651 | return cdev; | 1652 | return cdev; |
1652 | } | 1653 | } |
diff --git a/drivers/s390/cio/qdio_debug.c b/drivers/s390/cio/qdio_debug.c index 4221b02085ad..f1f3baa8e6e4 100644 --- a/drivers/s390/cio/qdio_debug.c +++ b/drivers/s390/cio/qdio_debug.c | |||
@@ -7,6 +7,7 @@ | |||
7 | #include <linux/debugfs.h> | 7 | #include <linux/debugfs.h> |
8 | #include <linux/uaccess.h> | 8 | #include <linux/uaccess.h> |
9 | #include <linux/export.h> | 9 | #include <linux/export.h> |
10 | #include <linux/slab.h> | ||
10 | #include <asm/debug.h> | 11 | #include <asm/debug.h> |
11 | #include "qdio_debug.h" | 12 | #include "qdio_debug.h" |
12 | #include "qdio.h" | 13 | #include "qdio.h" |
@@ -16,11 +17,51 @@ debug_info_t *qdio_dbf_error; | |||
16 | 17 | ||
17 | static struct dentry *debugfs_root; | 18 | static struct dentry *debugfs_root; |
18 | #define QDIO_DEBUGFS_NAME_LEN 10 | 19 | #define QDIO_DEBUGFS_NAME_LEN 10 |
20 | #define QDIO_DBF_NAME_LEN 20 | ||
19 | 21 | ||
20 | void qdio_allocate_dbf(struct qdio_initialize *init_data, | 22 | struct qdio_dbf_entry { |
23 | char dbf_name[QDIO_DBF_NAME_LEN]; | ||
24 | debug_info_t *dbf_info; | ||
25 | struct list_head dbf_list; | ||
26 | }; | ||
27 | |||
28 | static LIST_HEAD(qdio_dbf_list); | ||
29 | static DEFINE_MUTEX(qdio_dbf_list_mutex); | ||
30 | |||
31 | static debug_info_t *qdio_get_dbf_entry(char *name) | ||
32 | { | ||
33 | struct qdio_dbf_entry *entry; | ||
34 | debug_info_t *rc = NULL; | ||
35 | |||
36 | mutex_lock(&qdio_dbf_list_mutex); | ||
37 | list_for_each_entry(entry, &qdio_dbf_list, dbf_list) { | ||
38 | if (strcmp(entry->dbf_name, name) == 0) { | ||
39 | rc = entry->dbf_info; | ||
40 | break; | ||
41 | } | ||
42 | } | ||
43 | mutex_unlock(&qdio_dbf_list_mutex); | ||
44 | return rc; | ||
45 | } | ||
46 | |||
47 | static void qdio_clear_dbf_list(void) | ||
48 | { | ||
49 | struct qdio_dbf_entry *entry, *tmp; | ||
50 | |||
51 | mutex_lock(&qdio_dbf_list_mutex); | ||
52 | list_for_each_entry_safe(entry, tmp, &qdio_dbf_list, dbf_list) { | ||
53 | list_del(&entry->dbf_list); | ||
54 | debug_unregister(entry->dbf_info); | ||
55 | kfree(entry); | ||
56 | } | ||
57 | mutex_unlock(&qdio_dbf_list_mutex); | ||
58 | } | ||
59 | |||
60 | int qdio_allocate_dbf(struct qdio_initialize *init_data, | ||
21 | struct qdio_irq *irq_ptr) | 61 | struct qdio_irq *irq_ptr) |
22 | { | 62 | { |
23 | char text[20]; | 63 | char text[QDIO_DBF_NAME_LEN]; |
64 | struct qdio_dbf_entry *new_entry; | ||
24 | 65 | ||
25 | DBF_EVENT("qfmt:%1d", init_data->q_format); | 66 | DBF_EVENT("qfmt:%1d", init_data->q_format); |
26 | DBF_HEX(init_data->adapter_name, 8); | 67 | DBF_HEX(init_data->adapter_name, 8); |
@@ -38,11 +79,34 @@ void qdio_allocate_dbf(struct qdio_initialize *init_data, | |||
38 | DBF_EVENT("irq:%8lx", (unsigned long)irq_ptr); | 79 | DBF_EVENT("irq:%8lx", (unsigned long)irq_ptr); |
39 | 80 | ||
40 | /* allocate trace view for the interface */ | 81 | /* allocate trace view for the interface */ |
41 | snprintf(text, 20, "qdio_%s", dev_name(&init_data->cdev->dev)); | 82 | snprintf(text, QDIO_DBF_NAME_LEN, "qdio_%s", |
42 | irq_ptr->debug_area = debug_register(text, 2, 1, 16); | 83 | dev_name(&init_data->cdev->dev)); |
43 | debug_register_view(irq_ptr->debug_area, &debug_hex_ascii_view); | 84 | irq_ptr->debug_area = qdio_get_dbf_entry(text); |
44 | debug_set_level(irq_ptr->debug_area, DBF_WARN); | 85 | if (irq_ptr->debug_area) |
45 | DBF_DEV_EVENT(DBF_ERR, irq_ptr, "dbf created"); | 86 | DBF_DEV_EVENT(DBF_ERR, irq_ptr, "dbf reused"); |
87 | else { | ||
88 | irq_ptr->debug_area = debug_register(text, 2, 1, 16); | ||
89 | if (!irq_ptr->debug_area) | ||
90 | return -ENOMEM; | ||
91 | if (debug_register_view(irq_ptr->debug_area, | ||
92 | &debug_hex_ascii_view)) { | ||
93 | debug_unregister(irq_ptr->debug_area); | ||
94 | return -ENOMEM; | ||
95 | } | ||
96 | debug_set_level(irq_ptr->debug_area, DBF_WARN); | ||
97 | DBF_DEV_EVENT(DBF_ERR, irq_ptr, "dbf created"); | ||
98 | new_entry = kzalloc(sizeof(struct qdio_dbf_entry), GFP_KERNEL); | ||
99 | if (!new_entry) { | ||
100 | debug_unregister(irq_ptr->debug_area); | ||
101 | return -ENOMEM; | ||
102 | } | ||
103 | strlcpy(new_entry->dbf_name, text, QDIO_DBF_NAME_LEN); | ||
104 | new_entry->dbf_info = irq_ptr->debug_area; | ||
105 | mutex_lock(&qdio_dbf_list_mutex); | ||
106 | list_add(&new_entry->dbf_list, &qdio_dbf_list); | ||
107 | mutex_unlock(&qdio_dbf_list_mutex); | ||
108 | } | ||
109 | return 0; | ||
46 | } | 110 | } |
47 | 111 | ||
48 | static int qstat_show(struct seq_file *m, void *v) | 112 | static int qstat_show(struct seq_file *m, void *v) |
@@ -300,6 +364,7 @@ int __init qdio_debug_init(void) | |||
300 | 364 | ||
301 | void qdio_debug_exit(void) | 365 | void qdio_debug_exit(void) |
302 | { | 366 | { |
367 | qdio_clear_dbf_list(); | ||
303 | debugfs_remove(debugfs_root); | 368 | debugfs_remove(debugfs_root); |
304 | if (qdio_dbf_setup) | 369 | if (qdio_dbf_setup) |
305 | debug_unregister(qdio_dbf_setup); | 370 | debug_unregister(qdio_dbf_setup); |
diff --git a/drivers/s390/cio/qdio_debug.h b/drivers/s390/cio/qdio_debug.h index dfac9bfefea3..f33ce8577619 100644 --- a/drivers/s390/cio/qdio_debug.h +++ b/drivers/s390/cio/qdio_debug.h | |||
@@ -75,7 +75,7 @@ static inline void DBF_DEV_HEX(struct qdio_irq *dev, void *addr, | |||
75 | } | 75 | } |
76 | } | 76 | } |
77 | 77 | ||
78 | void qdio_allocate_dbf(struct qdio_initialize *init_data, | 78 | int qdio_allocate_dbf(struct qdio_initialize *init_data, |
79 | struct qdio_irq *irq_ptr); | 79 | struct qdio_irq *irq_ptr); |
80 | void qdio_setup_debug_entries(struct qdio_irq *irq_ptr, | 80 | void qdio_setup_debug_entries(struct qdio_irq *irq_ptr, |
81 | struct ccw_device *cdev); | 81 | struct ccw_device *cdev); |
diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 77466c4faabb..848e3b64ea6e 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c | |||
@@ -409,17 +409,16 @@ static inline void qdio_stop_polling(struct qdio_q *q) | |||
409 | set_buf_state(q, q->u.in.ack_start, SLSB_P_INPUT_NOT_INIT); | 409 | set_buf_state(q, q->u.in.ack_start, SLSB_P_INPUT_NOT_INIT); |
410 | } | 410 | } |
411 | 411 | ||
412 | static inline void account_sbals(struct qdio_q *q, int count) | 412 | static inline void account_sbals(struct qdio_q *q, unsigned int count) |
413 | { | 413 | { |
414 | int pos = 0; | 414 | int pos; |
415 | 415 | ||
416 | q->q_stats.nr_sbal_total += count; | 416 | q->q_stats.nr_sbal_total += count; |
417 | if (count == QDIO_MAX_BUFFERS_MASK) { | 417 | if (count == QDIO_MAX_BUFFERS_MASK) { |
418 | q->q_stats.nr_sbals[7]++; | 418 | q->q_stats.nr_sbals[7]++; |
419 | return; | 419 | return; |
420 | } | 420 | } |
421 | while (count >>= 1) | 421 | pos = ilog2(count); |
422 | pos++; | ||
423 | q->q_stats.nr_sbals[pos]++; | 422 | q->q_stats.nr_sbals[pos]++; |
424 | } | 423 | } |
425 | 424 | ||
@@ -1234,12 +1233,10 @@ int qdio_free(struct ccw_device *cdev) | |||
1234 | return -ENODEV; | 1233 | return -ENODEV; |
1235 | 1234 | ||
1236 | DBF_EVENT("qfree:%4x", cdev->private->schid.sch_no); | 1235 | DBF_EVENT("qfree:%4x", cdev->private->schid.sch_no); |
1236 | DBF_DEV_EVENT(DBF_ERR, irq_ptr, "dbf abandoned"); | ||
1237 | mutex_lock(&irq_ptr->setup_mutex); | 1237 | mutex_lock(&irq_ptr->setup_mutex); |
1238 | 1238 | ||
1239 | if (irq_ptr->debug_area != NULL) { | 1239 | irq_ptr->debug_area = NULL; |
1240 | debug_unregister(irq_ptr->debug_area); | ||
1241 | irq_ptr->debug_area = NULL; | ||
1242 | } | ||
1243 | cdev->private->qdio_data = NULL; | 1240 | cdev->private->qdio_data = NULL; |
1244 | mutex_unlock(&irq_ptr->setup_mutex); | 1241 | mutex_unlock(&irq_ptr->setup_mutex); |
1245 | 1242 | ||
@@ -1276,7 +1273,8 @@ int qdio_allocate(struct qdio_initialize *init_data) | |||
1276 | goto out_err; | 1273 | goto out_err; |
1277 | 1274 | ||
1278 | mutex_init(&irq_ptr->setup_mutex); | 1275 | mutex_init(&irq_ptr->setup_mutex); |
1279 | qdio_allocate_dbf(init_data, irq_ptr); | 1276 | if (qdio_allocate_dbf(init_data, irq_ptr)) |
1277 | goto out_rel; | ||
1280 | 1278 | ||
1281 | /* | 1279 | /* |
1282 | * Allocate a page for the chsc calls in qdio_establish. | 1280 | * Allocate a page for the chsc calls in qdio_establish. |
diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index 8eec1653c9cc..69ef4f8cfac8 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c | |||
@@ -77,12 +77,12 @@ MODULE_ALIAS("z90crypt"); | |||
77 | * Module parameter | 77 | * Module parameter |
78 | */ | 78 | */ |
79 | int ap_domain_index = -1; /* Adjunct Processor Domain Index */ | 79 | int ap_domain_index = -1; /* Adjunct Processor Domain Index */ |
80 | module_param_named(domain, ap_domain_index, int, 0000); | 80 | module_param_named(domain, ap_domain_index, int, S_IRUSR|S_IRGRP); |
81 | MODULE_PARM_DESC(domain, "domain index for ap devices"); | 81 | MODULE_PARM_DESC(domain, "domain index for ap devices"); |
82 | EXPORT_SYMBOL(ap_domain_index); | 82 | EXPORT_SYMBOL(ap_domain_index); |
83 | 83 | ||
84 | static int ap_thread_flag = 0; | 84 | static int ap_thread_flag = 0; |
85 | module_param_named(poll_thread, ap_thread_flag, int, 0000); | 85 | module_param_named(poll_thread, ap_thread_flag, int, S_IRUSR|S_IRGRP); |
86 | MODULE_PARM_DESC(poll_thread, "Turn on/off poll thread, default is 0 (off)."); | 86 | MODULE_PARM_DESC(poll_thread, "Turn on/off poll thread, default is 0 (off)."); |
87 | 87 | ||
88 | static struct device *ap_root_device = NULL; | 88 | static struct device *ap_root_device = NULL; |
diff --git a/drivers/s390/crypto/zcrypt_api.c b/drivers/s390/crypto/zcrypt_api.c index 5222ebe15705..0e18c5dcd91f 100644 --- a/drivers/s390/crypto/zcrypt_api.c +++ b/drivers/s390/crypto/zcrypt_api.c | |||
@@ -356,7 +356,7 @@ struct zcrypt_ops *zcrypt_msgtype_request(unsigned char *name, int variant) | |||
356 | 356 | ||
357 | zops = __ops_lookup(name, variant); | 357 | zops = __ops_lookup(name, variant); |
358 | if (!zops) { | 358 | if (!zops) { |
359 | request_module(name); | 359 | request_module("%s", name); |
360 | zops = __ops_lookup(name, variant); | 360 | zops = __ops_lookup(name, variant); |
361 | } | 361 | } |
362 | if ((!zops) || (!try_module_get(zops->owner))) | 362 | if ((!zops) || (!try_module_get(zops->owner))) |
diff --git a/drivers/scsi/mvsas/mv_94xx.c b/drivers/scsi/mvsas/mv_94xx.c index 1e4479f3331a..9270d15ff1a4 100644 --- a/drivers/scsi/mvsas/mv_94xx.c +++ b/drivers/scsi/mvsas/mv_94xx.c | |||
@@ -564,7 +564,7 @@ static void mvs_94xx_interrupt_enable(struct mvs_info *mvi) | |||
564 | u32 tmp; | 564 | u32 tmp; |
565 | 565 | ||
566 | tmp = mr32(MVS_GBL_CTL); | 566 | tmp = mr32(MVS_GBL_CTL); |
567 | tmp |= (IRQ_SAS_A | IRQ_SAS_B); | 567 | tmp |= (MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); |
568 | mw32(MVS_GBL_INT_STAT, tmp); | 568 | mw32(MVS_GBL_INT_STAT, tmp); |
569 | writel(tmp, regs + 0x0C); | 569 | writel(tmp, regs + 0x0C); |
570 | writel(tmp, regs + 0x10); | 570 | writel(tmp, regs + 0x10); |
@@ -580,7 +580,7 @@ static void mvs_94xx_interrupt_disable(struct mvs_info *mvi) | |||
580 | 580 | ||
581 | tmp = mr32(MVS_GBL_CTL); | 581 | tmp = mr32(MVS_GBL_CTL); |
582 | 582 | ||
583 | tmp &= ~(IRQ_SAS_A | IRQ_SAS_B); | 583 | tmp &= ~(MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); |
584 | mw32(MVS_GBL_INT_STAT, tmp); | 584 | mw32(MVS_GBL_INT_STAT, tmp); |
585 | writel(tmp, regs + 0x0C); | 585 | writel(tmp, regs + 0x0C); |
586 | writel(tmp, regs + 0x10); | 586 | writel(tmp, regs + 0x10); |
@@ -596,7 +596,7 @@ static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq) | |||
596 | if (!(mvi->flags & MVF_FLAG_SOC)) { | 596 | if (!(mvi->flags & MVF_FLAG_SOC)) { |
597 | stat = mr32(MVS_GBL_INT_STAT); | 597 | stat = mr32(MVS_GBL_INT_STAT); |
598 | 598 | ||
599 | if (!(stat & (IRQ_SAS_A | IRQ_SAS_B))) | 599 | if (!(stat & (MVS_IRQ_SAS_A | MVS_IRQ_SAS_B))) |
600 | return 0; | 600 | return 0; |
601 | } | 601 | } |
602 | return stat; | 602 | return stat; |
@@ -606,8 +606,8 @@ static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat) | |||
606 | { | 606 | { |
607 | void __iomem *regs = mvi->regs; | 607 | void __iomem *regs = mvi->regs; |
608 | 608 | ||
609 | if (((stat & IRQ_SAS_A) && mvi->id == 0) || | 609 | if (((stat & MVS_IRQ_SAS_A) && mvi->id == 0) || |
610 | ((stat & IRQ_SAS_B) && mvi->id == 1)) { | 610 | ((stat & MVS_IRQ_SAS_B) && mvi->id == 1)) { |
611 | mw32_f(MVS_INT_STAT, CINT_DONE); | 611 | mw32_f(MVS_INT_STAT, CINT_DONE); |
612 | 612 | ||
613 | spin_lock(&mvi->lock); | 613 | spin_lock(&mvi->lock); |
diff --git a/drivers/scsi/mvsas/mv_94xx.h b/drivers/scsi/mvsas/mv_94xx.h index 487aa6f97412..14e197497b46 100644 --- a/drivers/scsi/mvsas/mv_94xx.h +++ b/drivers/scsi/mvsas/mv_94xx.h | |||
@@ -150,35 +150,35 @@ enum chip_register_bits { | |||
150 | 150 | ||
151 | enum pci_interrupt_cause { | 151 | enum pci_interrupt_cause { |
152 | /* MAIN_IRQ_CAUSE (R10200) Bits*/ | 152 | /* MAIN_IRQ_CAUSE (R10200) Bits*/ |
153 | IRQ_COM_IN_I2O_IOP0 = (1 << 0), | 153 | MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0), |
154 | IRQ_COM_IN_I2O_IOP1 = (1 << 1), | 154 | MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1), |
155 | IRQ_COM_IN_I2O_IOP2 = (1 << 2), | 155 | MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2), |
156 | IRQ_COM_IN_I2O_IOP3 = (1 << 3), | 156 | MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3), |
157 | IRQ_COM_OUT_I2O_HOS0 = (1 << 4), | 157 | MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4), |
158 | IRQ_COM_OUT_I2O_HOS1 = (1 << 5), | 158 | MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5), |
159 | IRQ_COM_OUT_I2O_HOS2 = (1 << 6), | 159 | MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6), |
160 | IRQ_COM_OUT_I2O_HOS3 = (1 << 7), | 160 | MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7), |
161 | IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8), | 161 | MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8), |
162 | IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9), | 162 | MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9), |
163 | IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10), | 163 | MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10), |
164 | IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11), | 164 | MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11), |
165 | IRQ_PCIF_DRBL0 = (1 << 12), | 165 | MVS_IRQ_PCIF_DRBL0 = (1 << 12), |
166 | IRQ_PCIF_DRBL1 = (1 << 13), | 166 | MVS_IRQ_PCIF_DRBL1 = (1 << 13), |
167 | IRQ_PCIF_DRBL2 = (1 << 14), | 167 | MVS_IRQ_PCIF_DRBL2 = (1 << 14), |
168 | IRQ_PCIF_DRBL3 = (1 << 15), | 168 | MVS_IRQ_PCIF_DRBL3 = (1 << 15), |
169 | IRQ_XOR_A = (1 << 16), | 169 | MVS_IRQ_XOR_A = (1 << 16), |
170 | IRQ_XOR_B = (1 << 17), | 170 | MVS_IRQ_XOR_B = (1 << 17), |
171 | IRQ_SAS_A = (1 << 18), | 171 | MVS_IRQ_SAS_A = (1 << 18), |
172 | IRQ_SAS_B = (1 << 19), | 172 | MVS_IRQ_SAS_B = (1 << 19), |
173 | IRQ_CPU_CNTRL = (1 << 20), | 173 | MVS_IRQ_CPU_CNTRL = (1 << 20), |
174 | IRQ_GPIO = (1 << 21), | 174 | MVS_IRQ_GPIO = (1 << 21), |
175 | IRQ_UART = (1 << 22), | 175 | MVS_IRQ_UART = (1 << 22), |
176 | IRQ_SPI = (1 << 23), | 176 | MVS_IRQ_SPI = (1 << 23), |
177 | IRQ_I2C = (1 << 24), | 177 | MVS_IRQ_I2C = (1 << 24), |
178 | IRQ_SGPIO = (1 << 25), | 178 | MVS_IRQ_SGPIO = (1 << 25), |
179 | IRQ_COM_ERR = (1 << 29), | 179 | MVS_IRQ_COM_ERR = (1 << 29), |
180 | IRQ_I2O_ERR = (1 << 30), | 180 | MVS_IRQ_I2O_ERR = (1 << 30), |
181 | IRQ_PCIE_ERR = (1 << 31), | 181 | MVS_IRQ_PCIE_ERR = (1 << 31), |
182 | }; | 182 | }; |
183 | 183 | ||
184 | union reg_phy_cfg { | 184 | union reg_phy_cfg { |
diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c index f6759dc0153b..c41ff148a2b4 100644 --- a/drivers/spi/spi-pxa2xx-dma.c +++ b/drivers/spi/spi-pxa2xx-dma.c | |||
@@ -368,7 +368,7 @@ int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, | |||
368 | * otherwise we use the default. Also we use the default FIFO | 368 | * otherwise we use the default. Also we use the default FIFO |
369 | * thresholds for now. | 369 | * thresholds for now. |
370 | */ | 370 | */ |
371 | *burst_code = chip_info ? chip_info->dma_burst_size : 16; | 371 | *burst_code = chip_info ? chip_info->dma_burst_size : 1; |
372 | *threshold = SSCR1_RxTresh(RX_THRESH_DFLT) | 372 | *threshold = SSCR1_RxTresh(RX_THRESH_DFLT) |
373 | | SSCR1_TxTresh(TX_THRESH_DFLT); | 373 | | SSCR1_TxTresh(TX_THRESH_DFLT); |
374 | 374 | ||
diff --git a/drivers/staging/android/timed_output.c b/drivers/staging/android/timed_output.c index 2c617834dc46..c341ac11c5a3 100644 --- a/drivers/staging/android/timed_output.c +++ b/drivers/staging/android/timed_output.c | |||
@@ -97,7 +97,6 @@ void timed_output_dev_unregister(struct timed_output_dev *tdev) | |||
97 | { | 97 | { |
98 | tdev->enable(tdev, 0); | 98 | tdev->enable(tdev, 0); |
99 | device_destroy(timed_output_class, MKDEV(0, tdev->index)); | 99 | device_destroy(timed_output_class, MKDEV(0, tdev->index)); |
100 | dev_set_drvdata(tdev->dev, NULL); | ||
101 | } | 100 | } |
102 | EXPORT_SYMBOL_GPL(timed_output_dev_unregister); | 101 | EXPORT_SYMBOL_GPL(timed_output_dev_unregister); |
103 | 102 | ||
diff --git a/drivers/staging/comedi/Kconfig b/drivers/staging/comedi/Kconfig index 3a07f0b9afd5..8d992a87d3c4 100644 --- a/drivers/staging/comedi/Kconfig +++ b/drivers/staging/comedi/Kconfig | |||
@@ -653,6 +653,7 @@ config COMEDI_ADDI_APCI_1516 | |||
653 | 653 | ||
654 | config COMEDI_ADDI_APCI_1564 | 654 | config COMEDI_ADDI_APCI_1564 |
655 | tristate "ADDI-DATA APCI_1564 support" | 655 | tristate "ADDI-DATA APCI_1564 support" |
656 | select COMEDI_ADDI_WATCHDOG | ||
656 | ---help--- | 657 | ---help--- |
657 | Enable support for ADDI-DATA APCI_1564 cards | 658 | Enable support for ADDI-DATA APCI_1564 cards |
658 | 659 | ||
diff --git a/drivers/staging/iio/Kconfig b/drivers/staging/iio/Kconfig index b36feb080cba..fa38be0982f9 100644 --- a/drivers/staging/iio/Kconfig +++ b/drivers/staging/iio/Kconfig | |||
@@ -36,10 +36,11 @@ config IIO_SIMPLE_DUMMY_EVENTS | |||
36 | Add some dummy events to the simple dummy driver. | 36 | Add some dummy events to the simple dummy driver. |
37 | 37 | ||
38 | config IIO_SIMPLE_DUMMY_BUFFER | 38 | config IIO_SIMPLE_DUMMY_BUFFER |
39 | boolean "Buffered capture support" | 39 | boolean "Buffered capture support" |
40 | select IIO_KFIFO_BUF | 40 | select IIO_BUFFER |
41 | help | 41 | select IIO_KFIFO_BUF |
42 | Add buffered data capture to the simple dummy driver. | 42 | help |
43 | Add buffered data capture to the simple dummy driver. | ||
43 | 44 | ||
44 | endif # IIO_SIMPLE_DUMMY | 45 | endif # IIO_SIMPLE_DUMMY |
45 | 46 | ||
diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c index d8619993c6ff..468327f4a753 100644 --- a/drivers/staging/iio/adc/mxs-lradc.c +++ b/drivers/staging/iio/adc/mxs-lradc.c | |||
@@ -846,6 +846,14 @@ static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val) | |||
846 | LRADC_CTRL1); | 846 | LRADC_CTRL1); |
847 | mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0); | 847 | mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0); |
848 | 848 | ||
849 | /* Enable / disable the divider per requirement */ | ||
850 | if (test_bit(chan, &lradc->is_divided)) | ||
851 | mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, | ||
852 | LRADC_CTRL2); | ||
853 | else | ||
854 | mxs_lradc_reg_clear(lradc, | ||
855 | 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2); | ||
856 | |||
849 | /* Clean the slot's previous content, then set new one. */ | 857 | /* Clean the slot's previous content, then set new one. */ |
850 | mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0), | 858 | mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0), |
851 | LRADC_CTRL4); | 859 | LRADC_CTRL4); |
@@ -961,15 +969,11 @@ static int mxs_lradc_write_raw(struct iio_dev *iio_dev, | |||
961 | if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer && | 969 | if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer && |
962 | val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) { | 970 | val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) { |
963 | /* divider by two disabled */ | 971 | /* divider by two disabled */ |
964 | writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, | ||
965 | lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); | ||
966 | clear_bit(chan->channel, &lradc->is_divided); | 972 | clear_bit(chan->channel, &lradc->is_divided); |
967 | ret = 0; | 973 | ret = 0; |
968 | } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer && | 974 | } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer && |
969 | val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) { | 975 | val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) { |
970 | /* divider by two enabled */ | 976 | /* divider by two enabled */ |
971 | writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, | ||
972 | lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); | ||
973 | set_bit(chan->channel, &lradc->is_divided); | 977 | set_bit(chan->channel, &lradc->is_divided); |
974 | ret = 0; | 978 | ret = 0; |
975 | } | 979 | } |
diff --git a/drivers/staging/iio/light/tsl2x7x_core.c b/drivers/staging/iio/light/tsl2x7x_core.c index 9e0f2a9c73ae..ab338e3ddd05 100644 --- a/drivers/staging/iio/light/tsl2x7x_core.c +++ b/drivers/staging/iio/light/tsl2x7x_core.c | |||
@@ -667,9 +667,13 @@ static int tsl2x7x_chip_on(struct iio_dev *indio_dev) | |||
667 | chip->tsl2x7x_config[TSL2X7X_PRX_COUNT] = | 667 | chip->tsl2x7x_config[TSL2X7X_PRX_COUNT] = |
668 | chip->tsl2x7x_settings.prox_pulse_count; | 668 | chip->tsl2x7x_settings.prox_pulse_count; |
669 | chip->tsl2x7x_config[TSL2X7X_PRX_MINTHRESHLO] = | 669 | chip->tsl2x7x_config[TSL2X7X_PRX_MINTHRESHLO] = |
670 | chip->tsl2x7x_settings.prox_thres_low; | 670 | (chip->tsl2x7x_settings.prox_thres_low) & 0xFF; |
671 | chip->tsl2x7x_config[TSL2X7X_PRX_MINTHRESHHI] = | ||
672 | (chip->tsl2x7x_settings.prox_thres_low >> 8) & 0xFF; | ||
671 | chip->tsl2x7x_config[TSL2X7X_PRX_MAXTHRESHLO] = | 673 | chip->tsl2x7x_config[TSL2X7X_PRX_MAXTHRESHLO] = |
672 | chip->tsl2x7x_settings.prox_thres_high; | 674 | (chip->tsl2x7x_settings.prox_thres_high) & 0xFF; |
675 | chip->tsl2x7x_config[TSL2X7X_PRX_MAXTHRESHHI] = | ||
676 | (chip->tsl2x7x_settings.prox_thres_high >> 8) & 0xFF; | ||
673 | 677 | ||
674 | /* and make sure we're not already on */ | 678 | /* and make sure we're not already on */ |
675 | if (chip->tsl2x7x_chip_status == TSL2X7X_CHIP_WORKING) { | 679 | if (chip->tsl2x7x_chip_status == TSL2X7X_CHIP_WORKING) { |
diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c index b5678328fc40..4ca61afdf622 100644 --- a/drivers/staging/imx-drm/parallel-display.c +++ b/drivers/staging/imx-drm/parallel-display.c | |||
@@ -173,6 +173,13 @@ static int imx_pd_register(struct drm_device *drm, | |||
173 | if (ret) | 173 | if (ret) |
174 | return ret; | 174 | return ret; |
175 | 175 | ||
176 | /* set the connector's dpms to OFF so that | ||
177 | * drm_helper_connector_dpms() won't return | ||
178 | * immediately since the current state is ON | ||
179 | * at this point. | ||
180 | */ | ||
181 | imxpd->connector.dpms = DRM_MODE_DPMS_OFF; | ||
182 | |||
176 | drm_encoder_helper_add(&imxpd->encoder, &imx_pd_encoder_helper_funcs); | 183 | drm_encoder_helper_add(&imxpd->encoder, &imx_pd_encoder_helper_funcs); |
177 | drm_encoder_init(drm, &imxpd->encoder, &imx_pd_encoder_funcs, | 184 | drm_encoder_init(drm, &imxpd->encoder, &imx_pd_encoder_funcs, |
178 | DRM_MODE_ENCODER_NONE); | 185 | DRM_MODE_ENCODER_NONE); |
diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c index f95569dedc88..f44f1ba762c3 100644 --- a/drivers/tty/n_tty.c +++ b/drivers/tty/n_tty.c | |||
@@ -1214,15 +1214,16 @@ static void n_tty_receive_parity_error(struct tty_struct *tty, unsigned char c) | |||
1214 | { | 1214 | { |
1215 | struct n_tty_data *ldata = tty->disc_data; | 1215 | struct n_tty_data *ldata = tty->disc_data; |
1216 | 1216 | ||
1217 | if (I_IGNPAR(tty)) | 1217 | if (I_INPCK(tty)) { |
1218 | return; | 1218 | if (I_IGNPAR(tty)) |
1219 | if (I_PARMRK(tty)) { | 1219 | return; |
1220 | put_tty_queue('\377', ldata); | 1220 | if (I_PARMRK(tty)) { |
1221 | put_tty_queue('\0', ldata); | 1221 | put_tty_queue('\377', ldata); |
1222 | put_tty_queue(c, ldata); | 1222 | put_tty_queue('\0', ldata); |
1223 | } else if (I_INPCK(tty)) | 1223 | put_tty_queue(c, ldata); |
1224 | put_tty_queue('\0', ldata); | 1224 | } else |
1225 | else | 1225 | put_tty_queue('\0', ldata); |
1226 | } else | ||
1226 | put_tty_queue(c, ldata); | 1227 | put_tty_queue(c, ldata); |
1227 | if (waitqueue_active(&tty->read_wait)) | 1228 | if (waitqueue_active(&tty->read_wait)) |
1228 | wake_up_interruptible(&tty->read_wait); | 1229 | wake_up_interruptible(&tty->read_wait); |
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index 27f7ad6b74c1..7a91c6d1eb7d 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c | |||
@@ -2357,7 +2357,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, | |||
2357 | port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | 2357 | port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
2358 | if (termios->c_iflag & INPCK) | 2358 | if (termios->c_iflag & INPCK) |
2359 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; | 2359 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
2360 | if (termios->c_iflag & (BRKINT | PARMRK)) | 2360 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
2361 | port->read_status_mask |= UART_LSR_BI; | 2361 | port->read_status_mask |= UART_LSR_BI; |
2362 | 2362 | ||
2363 | /* | 2363 | /* |
diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index cfef801a49d4..4858b8a99d3b 100644 --- a/drivers/tty/serial/8250/8250_early.c +++ b/drivers/tty/serial/8250/8250_early.c | |||
@@ -144,8 +144,11 @@ static int __init early_serial8250_setup(struct earlycon_device *device, | |||
144 | if (!(device->port.membase || device->port.iobase)) | 144 | if (!(device->port.membase || device->port.iobase)) |
145 | return 0; | 145 | return 0; |
146 | 146 | ||
147 | if (!device->baud) | 147 | if (!device->baud) { |
148 | device->baud = probe_baud(&device->port); | 148 | device->baud = probe_baud(&device->port); |
149 | snprintf(device->options, sizeof(device->options), "%u", | ||
150 | device->baud); | ||
151 | } | ||
149 | 152 | ||
150 | init_port(device); | 153 | init_port(device); |
151 | 154 | ||
diff --git a/drivers/tty/serial/altera_uart.c b/drivers/tty/serial/altera_uart.c index 501667e3e3f5..323376668b72 100644 --- a/drivers/tty/serial/altera_uart.c +++ b/drivers/tty/serial/altera_uart.c | |||
@@ -185,6 +185,12 @@ static void altera_uart_set_termios(struct uart_port *port, | |||
185 | uart_update_timeout(port, termios->c_cflag, baud); | 185 | uart_update_timeout(port, termios->c_cflag, baud); |
186 | altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG); | 186 | altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG); |
187 | spin_unlock_irqrestore(&port->lock, flags); | 187 | spin_unlock_irqrestore(&port->lock, flags); |
188 | |||
189 | /* | ||
190 | * FIXME: port->read_status_mask and port->ignore_status_mask | ||
191 | * need to be initialized based on termios settings for | ||
192 | * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT | ||
193 | */ | ||
188 | } | 194 | } |
189 | 195 | ||
190 | static void altera_uart_rx_chars(struct altera_uart *pp) | 196 | static void altera_uart_rx_chars(struct altera_uart *pp) |
diff --git a/drivers/tty/serial/amba-pl010.c b/drivers/tty/serial/amba-pl010.c index 01c9e72433e1..971af1e22d0f 100644 --- a/drivers/tty/serial/amba-pl010.c +++ b/drivers/tty/serial/amba-pl010.c | |||
@@ -420,7 +420,7 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios, | |||
420 | uap->port.read_status_mask = UART01x_RSR_OE; | 420 | uap->port.read_status_mask = UART01x_RSR_OE; |
421 | if (termios->c_iflag & INPCK) | 421 | if (termios->c_iflag & INPCK) |
422 | uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; | 422 | uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
423 | if (termios->c_iflag & (BRKINT | PARMRK)) | 423 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
424 | uap->port.read_status_mask |= UART01x_RSR_BE; | 424 | uap->port.read_status_mask |= UART01x_RSR_BE; |
425 | 425 | ||
426 | /* | 426 | /* |
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 908a6e3142a2..0e26dcbd5ea4 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c | |||
@@ -1744,7 +1744,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1744 | port->read_status_mask = UART011_DR_OE | 255; | 1744 | port->read_status_mask = UART011_DR_OE | 255; |
1745 | if (termios->c_iflag & INPCK) | 1745 | if (termios->c_iflag & INPCK) |
1746 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; | 1746 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1747 | if (termios->c_iflag & (BRKINT | PARMRK)) | 1747 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1748 | port->read_status_mask |= UART011_DR_BE; | 1748 | port->read_status_mask |= UART011_DR_BE; |
1749 | 1749 | ||
1750 | /* | 1750 | /* |
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 3fceae099c44..c4f750314100 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c | |||
@@ -1932,7 +1932,7 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1932 | port->read_status_mask = ATMEL_US_OVRE; | 1932 | port->read_status_mask = ATMEL_US_OVRE; |
1933 | if (termios->c_iflag & INPCK) | 1933 | if (termios->c_iflag & INPCK) |
1934 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); | 1934 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1935 | if (termios->c_iflag & (BRKINT | PARMRK)) | 1935 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1936 | port->read_status_mask |= ATMEL_US_RXBRK; | 1936 | port->read_status_mask |= ATMEL_US_RXBRK; |
1937 | 1937 | ||
1938 | if (atmel_use_pdc_rx(port)) | 1938 | if (atmel_use_pdc_rx(port)) |
diff --git a/drivers/tty/serial/bcm63xx_uart.c b/drivers/tty/serial/bcm63xx_uart.c index a47421e4627c..231519022b73 100644 --- a/drivers/tty/serial/bcm63xx_uart.c +++ b/drivers/tty/serial/bcm63xx_uart.c | |||
@@ -567,7 +567,7 @@ static void bcm_uart_set_termios(struct uart_port *port, | |||
567 | port->read_status_mask |= UART_FIFO_FRAMEERR_MASK; | 567 | port->read_status_mask |= UART_FIFO_FRAMEERR_MASK; |
568 | port->read_status_mask |= UART_FIFO_PARERR_MASK; | 568 | port->read_status_mask |= UART_FIFO_PARERR_MASK; |
569 | } | 569 | } |
570 | if (new->c_iflag & (BRKINT)) | 570 | if (new->c_iflag & (IGNBRK | BRKINT)) |
571 | port->read_status_mask |= UART_FIFO_BRKDET_MASK; | 571 | port->read_status_mask |= UART_FIFO_BRKDET_MASK; |
572 | 572 | ||
573 | port->ignore_status_mask = 0; | 573 | port->ignore_status_mask = 0; |
diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c index 869ceba2ec57..ac86a20992e9 100644 --- a/drivers/tty/serial/bfin_uart.c +++ b/drivers/tty/serial/bfin_uart.c | |||
@@ -833,7 +833,7 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |||
833 | port->read_status_mask = OE; | 833 | port->read_status_mask = OE; |
834 | if (termios->c_iflag & INPCK) | 834 | if (termios->c_iflag & INPCK) |
835 | port->read_status_mask |= (FE | PE); | 835 | port->read_status_mask |= (FE | PE); |
836 | if (termios->c_iflag & (BRKINT | PARMRK)) | 836 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
837 | port->read_status_mask |= BI; | 837 | port->read_status_mask |= BI; |
838 | 838 | ||
839 | /* | 839 | /* |
diff --git a/drivers/tty/serial/dz.c b/drivers/tty/serial/dz.c index 2f2b2e538a54..cdbbc788230a 100644 --- a/drivers/tty/serial/dz.c +++ b/drivers/tty/serial/dz.c | |||
@@ -625,7 +625,7 @@ static void dz_set_termios(struct uart_port *uport, struct ktermios *termios, | |||
625 | dport->port.read_status_mask = DZ_OERR; | 625 | dport->port.read_status_mask = DZ_OERR; |
626 | if (termios->c_iflag & INPCK) | 626 | if (termios->c_iflag & INPCK) |
627 | dport->port.read_status_mask |= DZ_FERR | DZ_PERR; | 627 | dport->port.read_status_mask |= DZ_FERR | DZ_PERR; |
628 | if (termios->c_iflag & (BRKINT | PARMRK)) | 628 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
629 | dport->port.read_status_mask |= DZ_BREAK; | 629 | dport->port.read_status_mask |= DZ_BREAK; |
630 | 630 | ||
631 | /* characters to ignore */ | 631 | /* characters to ignore */ |
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c index 5131b5ee6164..a514ee6f5406 100644 --- a/drivers/tty/serial/earlycon.c +++ b/drivers/tty/serial/earlycon.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include <asm/serial.h> | 25 | #include <asm/serial.h> |
26 | 26 | ||
27 | static struct console early_con = { | 27 | static struct console early_con = { |
28 | .name = "earlycon", | 28 | .name = "uart", /* 8250 console switch requires this name */ |
29 | .flags = CON_PRINTBUFFER | CON_BOOT, | 29 | .flags = CON_PRINTBUFFER | CON_BOOT, |
30 | .index = -1, | 30 | .index = -1, |
31 | }; | 31 | }; |
diff --git a/drivers/tty/serial/efm32-uart.c b/drivers/tty/serial/efm32-uart.c index b373f6416e8c..3b0ee9afd76f 100644 --- a/drivers/tty/serial/efm32-uart.c +++ b/drivers/tty/serial/efm32-uart.c | |||
@@ -407,7 +407,7 @@ static void efm32_uart_set_termios(struct uart_port *port, | |||
407 | if (new->c_iflag & INPCK) | 407 | if (new->c_iflag & INPCK) |
408 | port->read_status_mask |= | 408 | port->read_status_mask |= |
409 | UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR; | 409 | UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR; |
410 | if (new->c_iflag & (BRKINT | PARMRK)) | 410 | if (new->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
411 | port->read_status_mask |= SW_UARTn_RXDATAX_BERR; | 411 | port->read_status_mask |= SW_UARTn_RXDATAX_BERR; |
412 | 412 | ||
413 | port->ignore_status_mask = 0; | 413 | port->ignore_status_mask = 0; |
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index c5eb897de9de..49385c86cfba 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c | |||
@@ -902,7 +902,7 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios, | |||
902 | sport->port.read_status_mask = 0; | 902 | sport->port.read_status_mask = 0; |
903 | if (termios->c_iflag & INPCK) | 903 | if (termios->c_iflag & INPCK) |
904 | sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); | 904 | sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); |
905 | if (termios->c_iflag & (BRKINT | PARMRK)) | 905 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
906 | sport->port.read_status_mask |= UARTSR1_FE; | 906 | sport->port.read_status_mask |= UARTSR1_FE; |
907 | 907 | ||
908 | /* characters to ignore */ | 908 | /* characters to ignore */ |
diff --git a/drivers/tty/serial/ip22zilog.c b/drivers/tty/serial/ip22zilog.c index 1d9420548e16..1efd4c36ba0c 100644 --- a/drivers/tty/serial/ip22zilog.c +++ b/drivers/tty/serial/ip22zilog.c | |||
@@ -850,7 +850,7 @@ ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, | |||
850 | up->port.read_status_mask = Rx_OVR; | 850 | up->port.read_status_mask = Rx_OVR; |
851 | if (iflag & INPCK) | 851 | if (iflag & INPCK) |
852 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; | 852 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; |
853 | if (iflag & (BRKINT | PARMRK)) | 853 | if (iflag & (IGNBRK | BRKINT | PARMRK)) |
854 | up->port.read_status_mask |= BRK_ABRT; | 854 | up->port.read_status_mask |= BRK_ABRT; |
855 | 855 | ||
856 | up->port.ignore_status_mask = 0; | 856 | up->port.ignore_status_mask = 0; |
diff --git a/drivers/tty/serial/m32r_sio.c b/drivers/tty/serial/m32r_sio.c index 9cd9b4eba9fc..68f2c53e0b54 100644 --- a/drivers/tty/serial/m32r_sio.c +++ b/drivers/tty/serial/m32r_sio.c | |||
@@ -737,7 +737,7 @@ static void m32r_sio_set_termios(struct uart_port *port, | |||
737 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | 737 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
738 | if (termios->c_iflag & INPCK) | 738 | if (termios->c_iflag & INPCK) |
739 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | 739 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
740 | if (termios->c_iflag & (BRKINT | PARMRK)) | 740 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
741 | up->port.read_status_mask |= UART_LSR_BI; | 741 | up->port.read_status_mask |= UART_LSR_BI; |
742 | 742 | ||
743 | /* | 743 | /* |
diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c index 2a99d0c61b9e..ba285cd45b59 100644 --- a/drivers/tty/serial/max310x.c +++ b/drivers/tty/serial/max310x.c | |||
@@ -835,7 +835,7 @@ static void max310x_set_termios(struct uart_port *port, | |||
835 | if (termios->c_iflag & INPCK) | 835 | if (termios->c_iflag & INPCK) |
836 | port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | | 836 | port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | |
837 | MAX310X_LSR_FRERR_BIT; | 837 | MAX310X_LSR_FRERR_BIT; |
838 | if (termios->c_iflag & (BRKINT | PARMRK)) | 838 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
839 | port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; | 839 | port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; |
840 | 840 | ||
841 | /* Set status ignore mask */ | 841 | /* Set status ignore mask */ |
diff --git a/drivers/tty/serial/mcf.c b/drivers/tty/serial/mcf.c index 0edfaf8cd269..a6f085717f94 100644 --- a/drivers/tty/serial/mcf.c +++ b/drivers/tty/serial/mcf.c | |||
@@ -248,6 +248,12 @@ static void mcf_set_termios(struct uart_port *port, struct ktermios *termios, | |||
248 | mr1 |= MCFUART_MR1_PARITYNONE; | 248 | mr1 |= MCFUART_MR1_PARITYNONE; |
249 | } | 249 | } |
250 | 250 | ||
251 | /* | ||
252 | * FIXME: port->read_status_mask and port->ignore_status_mask | ||
253 | * need to be initialized based on termios settings for | ||
254 | * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT | ||
255 | */ | ||
256 | |||
251 | if (termios->c_cflag & CSTOPB) | 257 | if (termios->c_cflag & CSTOPB) |
252 | mr2 |= MCFUART_MR2_STOP2; | 258 | mr2 |= MCFUART_MR2_STOP2; |
253 | else | 259 | else |
diff --git a/drivers/tty/serial/mfd.c b/drivers/tty/serial/mfd.c index 52c930fac210..445799dc9846 100644 --- a/drivers/tty/serial/mfd.c +++ b/drivers/tty/serial/mfd.c | |||
@@ -977,7 +977,7 @@ serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios, | |||
977 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | 977 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
978 | if (termios->c_iflag & INPCK) | 978 | if (termios->c_iflag & INPCK) |
979 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | 979 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
980 | if (termios->c_iflag & (BRKINT | PARMRK)) | 980 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
981 | up->port.read_status_mask |= UART_LSR_BI; | 981 | up->port.read_status_mask |= UART_LSR_BI; |
982 | 982 | ||
983 | /* Characters to ignore */ | 983 | /* Characters to ignore */ |
diff --git a/drivers/tty/serial/mpsc.c b/drivers/tty/serial/mpsc.c index e30a3ca3cea3..759c6a6fa74a 100644 --- a/drivers/tty/serial/mpsc.c +++ b/drivers/tty/serial/mpsc.c | |||
@@ -1458,7 +1458,7 @@ static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1458 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE | 1458 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
1459 | | SDMA_DESC_CMDSTAT_FR; | 1459 | | SDMA_DESC_CMDSTAT_FR; |
1460 | 1460 | ||
1461 | if (termios->c_iflag & (BRKINT | PARMRK)) | 1461 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1462 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; | 1462 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; |
1463 | 1463 | ||
1464 | /* Characters/events to ignore */ | 1464 | /* Characters/events to ignore */ |
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c index 778e376f197e..c41aca4dfc43 100644 --- a/drivers/tty/serial/msm_serial.c +++ b/drivers/tty/serial/msm_serial.c | |||
@@ -582,7 +582,7 @@ static void msm_set_termios(struct uart_port *port, struct ktermios *termios, | |||
582 | port->read_status_mask = 0; | 582 | port->read_status_mask = 0; |
583 | if (termios->c_iflag & INPCK) | 583 | if (termios->c_iflag & INPCK) |
584 | port->read_status_mask |= UART_SR_PAR_FRAME_ERR; | 584 | port->read_status_mask |= UART_SR_PAR_FRAME_ERR; |
585 | if (termios->c_iflag & (BRKINT | PARMRK)) | 585 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
586 | port->read_status_mask |= UART_SR_RX_BREAK; | 586 | port->read_status_mask |= UART_SR_RX_BREAK; |
587 | 587 | ||
588 | uart_update_timeout(port, termios->c_cflag, baud); | 588 | uart_update_timeout(port, termios->c_cflag, baud); |
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c index 4b5b3c2fe328..86de4477d98a 100644 --- a/drivers/tty/serial/mxs-auart.c +++ b/drivers/tty/serial/mxs-auart.c | |||
@@ -604,7 +604,7 @@ static void mxs_auart_settermios(struct uart_port *u, | |||
604 | 604 | ||
605 | if (termios->c_iflag & INPCK) | 605 | if (termios->c_iflag & INPCK) |
606 | u->read_status_mask |= AUART_STAT_PERR; | 606 | u->read_status_mask |= AUART_STAT_PERR; |
607 | if (termios->c_iflag & (BRKINT | PARMRK)) | 607 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
608 | u->read_status_mask |= AUART_STAT_BERR; | 608 | u->read_status_mask |= AUART_STAT_BERR; |
609 | 609 | ||
610 | /* | 610 | /* |
diff --git a/drivers/tty/serial/netx-serial.c b/drivers/tty/serial/netx-serial.c index 0a4dd70d29eb..7a6745601d4e 100644 --- a/drivers/tty/serial/netx-serial.c +++ b/drivers/tty/serial/netx-serial.c | |||
@@ -419,7 +419,7 @@ netx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
419 | } | 419 | } |
420 | 420 | ||
421 | port->read_status_mask = 0; | 421 | port->read_status_mask = 0; |
422 | if (termios->c_iflag & (BRKINT | PARMRK)) | 422 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
423 | port->read_status_mask |= SR_BE; | 423 | port->read_status_mask |= SR_BE; |
424 | if (termios->c_iflag & INPCK) | 424 | if (termios->c_iflag & INPCK) |
425 | port->read_status_mask |= SR_PE | SR_FE; | 425 | port->read_status_mask |= SR_PE | SR_FE; |
diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c index e9d420ff3931..8193635103ee 100644 --- a/drivers/tty/serial/pmac_zilog.c +++ b/drivers/tty/serial/pmac_zilog.c | |||
@@ -1092,7 +1092,7 @@ static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, | |||
1092 | uap->port.read_status_mask = Rx_OVR; | 1092 | uap->port.read_status_mask = Rx_OVR; |
1093 | if (iflag & INPCK) | 1093 | if (iflag & INPCK) |
1094 | uap->port.read_status_mask |= CRC_ERR | PAR_ERR; | 1094 | uap->port.read_status_mask |= CRC_ERR | PAR_ERR; |
1095 | if (iflag & (BRKINT | PARMRK)) | 1095 | if (iflag & (IGNBRK | BRKINT | PARMRK)) |
1096 | uap->port.read_status_mask |= BRK_ABRT; | 1096 | uap->port.read_status_mask |= BRK_ABRT; |
1097 | 1097 | ||
1098 | uap->port.ignore_status_mask = 0; | 1098 | uap->port.ignore_status_mask = 0; |
diff --git a/drivers/tty/serial/pnx8xxx_uart.c b/drivers/tty/serial/pnx8xxx_uart.c index de6c05c63683..2ba24a45c97f 100644 --- a/drivers/tty/serial/pnx8xxx_uart.c +++ b/drivers/tty/serial/pnx8xxx_uart.c | |||
@@ -477,7 +477,7 @@ pnx8xxx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
477 | sport->port.read_status_mask |= | 477 | sport->port.read_status_mask |= |
478 | FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) | | 478 | FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) | |
479 | FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR); | 479 | FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR); |
480 | if (termios->c_iflag & (BRKINT | PARMRK)) | 480 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
481 | sport->port.read_status_mask |= | 481 | sport->port.read_status_mask |= |
482 | ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK); | 482 | ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK); |
483 | 483 | ||
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c index 9e7ee39f8b2a..c638c53cd2b6 100644 --- a/drivers/tty/serial/pxa.c +++ b/drivers/tty/serial/pxa.c | |||
@@ -492,7 +492,7 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, | |||
492 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | 492 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
493 | if (termios->c_iflag & INPCK) | 493 | if (termios->c_iflag & INPCK) |
494 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | 494 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
495 | if (termios->c_iflag & (BRKINT | PARMRK)) | 495 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
496 | up->port.read_status_mask |= UART_LSR_BI; | 496 | up->port.read_status_mask |= UART_LSR_BI; |
497 | 497 | ||
498 | /* | 498 | /* |
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 329337711bb0..c1d3ebdf3b97 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c | |||
@@ -66,7 +66,7 @@ static void dbg(const char *fmt, ...) | |||
66 | char buff[256]; | 66 | char buff[256]; |
67 | 67 | ||
68 | va_start(va, fmt); | 68 | va_start(va, fmt); |
69 | vscnprintf(buff, sizeof(buf), fmt, va); | 69 | vscnprintf(buff, sizeof(buff), fmt, va); |
70 | va_end(va); | 70 | va_end(va); |
71 | 71 | ||
72 | printascii(buff); | 72 | printascii(buff); |
diff --git a/drivers/tty/serial/sb1250-duart.c b/drivers/tty/serial/sb1250-duart.c index a7cdec2962dd..771f361c47ea 100644 --- a/drivers/tty/serial/sb1250-duart.c +++ b/drivers/tty/serial/sb1250-duart.c | |||
@@ -596,7 +596,7 @@ static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios, | |||
596 | if (termios->c_iflag & INPCK) | 596 | if (termios->c_iflag & INPCK) |
597 | uport->read_status_mask |= M_DUART_FRM_ERR | | 597 | uport->read_status_mask |= M_DUART_FRM_ERR | |
598 | M_DUART_PARITY_ERR; | 598 | M_DUART_PARITY_ERR; |
599 | if (termios->c_iflag & (BRKINT | PARMRK)) | 599 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
600 | uport->read_status_mask |= M_DUART_RCVD_BRK; | 600 | uport->read_status_mask |= M_DUART_RCVD_BRK; |
601 | 601 | ||
602 | uport->ignore_status_mask = 0; | 602 | uport->ignore_status_mask = 0; |
diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c index 5443b46345ed..e84b6a3bdd18 100644 --- a/drivers/tty/serial/sccnxp.c +++ b/drivers/tty/serial/sccnxp.c | |||
@@ -665,7 +665,7 @@ static void sccnxp_set_termios(struct uart_port *port, | |||
665 | port->read_status_mask = SR_OVR; | 665 | port->read_status_mask = SR_OVR; |
666 | if (termios->c_iflag & INPCK) | 666 | if (termios->c_iflag & INPCK) |
667 | port->read_status_mask |= SR_PE | SR_FE; | 667 | port->read_status_mask |= SR_PE | SR_FE; |
668 | if (termios->c_iflag & (BRKINT | PARMRK)) | 668 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
669 | port->read_status_mask |= SR_BRK; | 669 | port->read_status_mask |= SR_BRK; |
670 | 670 | ||
671 | /* Set status ignore mask */ | 671 | /* Set status ignore mask */ |
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c index e1caa99e3d3b..5c79bdab985d 100644 --- a/drivers/tty/serial/serial_ks8695.c +++ b/drivers/tty/serial/serial_ks8695.c | |||
@@ -437,7 +437,7 @@ static void ks8695uart_set_termios(struct uart_port *port, struct ktermios *term | |||
437 | port->read_status_mask = URLS_URROE; | 437 | port->read_status_mask = URLS_URROE; |
438 | if (termios->c_iflag & INPCK) | 438 | if (termios->c_iflag & INPCK) |
439 | port->read_status_mask |= (URLS_URFE | URLS_URPE); | 439 | port->read_status_mask |= (URLS_URFE | URLS_URPE); |
440 | if (termios->c_iflag & (BRKINT | PARMRK)) | 440 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
441 | port->read_status_mask |= URLS_URBI; | 441 | port->read_status_mask |= URLS_URBI; |
442 | 442 | ||
443 | /* | 443 | /* |
diff --git a/drivers/tty/serial/serial_txx9.c b/drivers/tty/serial/serial_txx9.c index 60f49b9d7e39..ea8546092c7e 100644 --- a/drivers/tty/serial/serial_txx9.c +++ b/drivers/tty/serial/serial_txx9.c | |||
@@ -697,7 +697,7 @@ serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios, | |||
697 | TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS; | 697 | TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS; |
698 | if (termios->c_iflag & INPCK) | 698 | if (termios->c_iflag & INPCK) |
699 | up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER; | 699 | up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER; |
700 | if (termios->c_iflag & (BRKINT | PARMRK)) | 700 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
701 | up->port.read_status_mask |= TXX9_SIDISR_UBRK; | 701 | up->port.read_status_mask |= TXX9_SIDISR_UBRK; |
702 | 702 | ||
703 | /* | 703 | /* |
diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c index 1f2be48c92ce..9b4d71cff00d 100644 --- a/drivers/tty/serial/sirfsoc_uart.c +++ b/drivers/tty/serial/sirfsoc_uart.c | |||
@@ -896,7 +896,7 @@ static void sirfsoc_uart_set_termios(struct uart_port *port, | |||
896 | if (termios->c_iflag & INPCK) | 896 | if (termios->c_iflag & INPCK) |
897 | port->read_status_mask |= uint_en->sirfsoc_frm_err_en; | 897 | port->read_status_mask |= uint_en->sirfsoc_frm_err_en; |
898 | } | 898 | } |
899 | if (termios->c_iflag & (BRKINT | PARMRK)) | 899 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
900 | port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en; | 900 | port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en; |
901 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { | 901 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { |
902 | if (termios->c_iflag & IGNPAR) | 902 | if (termios->c_iflag & IGNPAR) |
diff --git a/drivers/tty/serial/st-asc.c b/drivers/tty/serial/st-asc.c index c7f61ac27132..f48b1cc07eea 100644 --- a/drivers/tty/serial/st-asc.c +++ b/drivers/tty/serial/st-asc.c | |||
@@ -547,7 +547,7 @@ static void asc_set_termios(struct uart_port *port, struct ktermios *termios, | |||
547 | ascport->port.read_status_mask = ASC_RXBUF_DUMMY_OE; | 547 | ascport->port.read_status_mask = ASC_RXBUF_DUMMY_OE; |
548 | if (termios->c_iflag & INPCK) | 548 | if (termios->c_iflag & INPCK) |
549 | ascport->port.read_status_mask |= ASC_RXBUF_FE | ASC_RXBUF_PE; | 549 | ascport->port.read_status_mask |= ASC_RXBUF_FE | ASC_RXBUF_PE; |
550 | if (termios->c_iflag & (BRKINT | PARMRK)) | 550 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
551 | ascport->port.read_status_mask |= ASC_RXBUF_DUMMY_BE; | 551 | ascport->port.read_status_mask |= ASC_RXBUF_DUMMY_BE; |
552 | 552 | ||
553 | /* | 553 | /* |
diff --git a/drivers/tty/serial/sunsab.c b/drivers/tty/serial/sunsab.c index 5faa8e905e98..80a58eca785b 100644 --- a/drivers/tty/serial/sunsab.c +++ b/drivers/tty/serial/sunsab.c | |||
@@ -719,7 +719,7 @@ static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cfla | |||
719 | if (iflag & INPCK) | 719 | if (iflag & INPCK) |
720 | up->port.read_status_mask |= (SAB82532_ISR0_PERR | | 720 | up->port.read_status_mask |= (SAB82532_ISR0_PERR | |
721 | SAB82532_ISR0_FERR); | 721 | SAB82532_ISR0_FERR); |
722 | if (iflag & (BRKINT | PARMRK)) | 722 | if (iflag & (IGNBRK | BRKINT | PARMRK)) |
723 | up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8); | 723 | up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8); |
724 | 724 | ||
725 | /* | 725 | /* |
diff --git a/drivers/tty/serial/sunsu.c b/drivers/tty/serial/sunsu.c index 9a0f24f83720..5326ae195e5f 100644 --- a/drivers/tty/serial/sunsu.c +++ b/drivers/tty/serial/sunsu.c | |||
@@ -834,7 +834,7 @@ sunsu_change_speed(struct uart_port *port, unsigned int cflag, | |||
834 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | 834 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
835 | if (iflag & INPCK) | 835 | if (iflag & INPCK) |
836 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | 836 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
837 | if (iflag & (BRKINT | PARMRK)) | 837 | if (iflag & (IGNBRK | BRKINT | PARMRK)) |
838 | up->port.read_status_mask |= UART_LSR_BI; | 838 | up->port.read_status_mask |= UART_LSR_BI; |
839 | 839 | ||
840 | /* | 840 | /* |
diff --git a/drivers/tty/serial/sunzilog.c b/drivers/tty/serial/sunzilog.c index a2c40ed287d2..a85db8b87156 100644 --- a/drivers/tty/serial/sunzilog.c +++ b/drivers/tty/serial/sunzilog.c | |||
@@ -915,7 +915,7 @@ sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag, | |||
915 | up->port.read_status_mask = Rx_OVR; | 915 | up->port.read_status_mask = Rx_OVR; |
916 | if (iflag & INPCK) | 916 | if (iflag & INPCK) |
917 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; | 917 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; |
918 | if (iflag & (BRKINT | PARMRK)) | 918 | if (iflag & (IGNBRK | BRKINT | PARMRK)) |
919 | up->port.read_status_mask |= BRK_ABRT; | 919 | up->port.read_status_mask |= BRK_ABRT; |
920 | 920 | ||
921 | up->port.ignore_status_mask = 0; | 921 | up->port.ignore_status_mask = 0; |
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c index d569ca58bab6..1c52074c38df 100644 --- a/drivers/tty/serial/ucc_uart.c +++ b/drivers/tty/serial/ucc_uart.c | |||
@@ -936,7 +936,7 @@ static void qe_uart_set_termios(struct uart_port *port, | |||
936 | port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; | 936 | port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; |
937 | if (termios->c_iflag & INPCK) | 937 | if (termios->c_iflag & INPCK) |
938 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | 938 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; |
939 | if (termios->c_iflag & (BRKINT | PARMRK)) | 939 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
940 | port->read_status_mask |= BD_SC_BR; | 940 | port->read_status_mask |= BD_SC_BR; |
941 | 941 | ||
942 | /* | 942 | /* |
diff --git a/drivers/tty/serial/vr41xx_siu.c b/drivers/tty/serial/vr41xx_siu.c index a63c14bc9a24..db0c8a4ab03e 100644 --- a/drivers/tty/serial/vr41xx_siu.c +++ b/drivers/tty/serial/vr41xx_siu.c | |||
@@ -559,7 +559,7 @@ static void siu_set_termios(struct uart_port *port, struct ktermios *new, | |||
559 | port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR; | 559 | port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR; |
560 | if (c_iflag & INPCK) | 560 | if (c_iflag & INPCK) |
561 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; | 561 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
562 | if (c_iflag & (BRKINT | PARMRK)) | 562 | if (c_iflag & (IGNBRK | BRKINT | PARMRK)) |
563 | port->read_status_mask |= UART_LSR_BI; | 563 | port->read_status_mask |= UART_LSR_BI; |
564 | 564 | ||
565 | port->ignore_status_mask = 0; | 565 | port->ignore_status_mask = 0; |
diff --git a/drivers/tty/serial/zs.c b/drivers/tty/serial/zs.c index 6a169877109b..2b65bb7ffb8a 100644 --- a/drivers/tty/serial/zs.c +++ b/drivers/tty/serial/zs.c | |||
@@ -923,7 +923,7 @@ static void zs_set_termios(struct uart_port *uport, struct ktermios *termios, | |||
923 | uport->read_status_mask = Rx_OVR; | 923 | uport->read_status_mask = Rx_OVR; |
924 | if (termios->c_iflag & INPCK) | 924 | if (termios->c_iflag & INPCK) |
925 | uport->read_status_mask |= FRM_ERR | PAR_ERR; | 925 | uport->read_status_mask |= FRM_ERR | PAR_ERR; |
926 | if (termios->c_iflag & (BRKINT | PARMRK)) | 926 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
927 | uport->read_status_mask |= Rx_BRK; | 927 | uport->read_status_mask |= Rx_BRK; |
928 | 928 | ||
929 | uport->ignore_status_mask = 0; | 929 | uport->ignore_status_mask = 0; |
diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c index 5e0f6ff2e2f5..b33b00b386de 100644 --- a/drivers/tty/vt/vt.c +++ b/drivers/tty/vt/vt.c | |||
@@ -3226,8 +3226,7 @@ int do_unbind_con_driver(const struct consw *csw, int first, int last, int deflt | |||
3226 | for (i = 0; i < MAX_NR_CON_DRIVER; i++) { | 3226 | for (i = 0; i < MAX_NR_CON_DRIVER; i++) { |
3227 | con_back = ®istered_con_driver[i]; | 3227 | con_back = ®istered_con_driver[i]; |
3228 | 3228 | ||
3229 | if (con_back->con && | 3229 | if (con_back->con && con_back->con != csw) { |
3230 | !(con_back->flag & CON_DRIVER_FLAG_MODULE)) { | ||
3231 | defcsw = con_back->con; | 3230 | defcsw = con_back->con; |
3232 | retval = 0; | 3231 | retval = 0; |
3233 | break; | 3232 | break; |
@@ -3332,6 +3331,7 @@ static int vt_unbind(struct con_driver *con) | |||
3332 | { | 3331 | { |
3333 | const struct consw *csw = NULL; | 3332 | const struct consw *csw = NULL; |
3334 | int i, more = 1, first = -1, last = -1, deflt = 0; | 3333 | int i, more = 1, first = -1, last = -1, deflt = 0; |
3334 | int ret; | ||
3335 | 3335 | ||
3336 | if (!con->con || !(con->flag & CON_DRIVER_FLAG_MODULE) || | 3336 | if (!con->con || !(con->flag & CON_DRIVER_FLAG_MODULE) || |
3337 | con_is_graphics(con->con, con->first, con->last)) | 3337 | con_is_graphics(con->con, con->first, con->last)) |
@@ -3357,8 +3357,10 @@ static int vt_unbind(struct con_driver *con) | |||
3357 | 3357 | ||
3358 | if (first != -1) { | 3358 | if (first != -1) { |
3359 | console_lock(); | 3359 | console_lock(); |
3360 | do_unbind_con_driver(csw, first, last, deflt); | 3360 | ret = do_unbind_con_driver(csw, first, last, deflt); |
3361 | console_unlock(); | 3361 | console_unlock(); |
3362 | if (ret != 0) | ||
3363 | return ret; | ||
3362 | } | 3364 | } |
3363 | 3365 | ||
3364 | first = -1; | 3366 | first = -1; |
@@ -3645,17 +3647,20 @@ err: | |||
3645 | */ | 3647 | */ |
3646 | int do_unregister_con_driver(const struct consw *csw) | 3648 | int do_unregister_con_driver(const struct consw *csw) |
3647 | { | 3649 | { |
3648 | int i, retval = -ENODEV; | 3650 | int i; |
3649 | 3651 | ||
3650 | /* cannot unregister a bound driver */ | 3652 | /* cannot unregister a bound driver */ |
3651 | if (con_is_bound(csw)) | 3653 | if (con_is_bound(csw)) |
3652 | goto err; | 3654 | return -EBUSY; |
3655 | |||
3656 | if (csw == conswitchp) | ||
3657 | return -EINVAL; | ||
3653 | 3658 | ||
3654 | for (i = 0; i < MAX_NR_CON_DRIVER; i++) { | 3659 | for (i = 0; i < MAX_NR_CON_DRIVER; i++) { |
3655 | struct con_driver *con_driver = ®istered_con_driver[i]; | 3660 | struct con_driver *con_driver = ®istered_con_driver[i]; |
3656 | 3661 | ||
3657 | if (con_driver->con == csw && | 3662 | if (con_driver->con == csw && |
3658 | con_driver->flag & CON_DRIVER_FLAG_MODULE) { | 3663 | con_driver->flag & CON_DRIVER_FLAG_INIT) { |
3659 | vtconsole_deinit_device(con_driver); | 3664 | vtconsole_deinit_device(con_driver); |
3660 | device_destroy(vtconsole_class, | 3665 | device_destroy(vtconsole_class, |
3661 | MKDEV(0, con_driver->node)); | 3666 | MKDEV(0, con_driver->node)); |
@@ -3666,12 +3671,11 @@ int do_unregister_con_driver(const struct consw *csw) | |||
3666 | con_driver->flag = 0; | 3671 | con_driver->flag = 0; |
3667 | con_driver->first = 0; | 3672 | con_driver->first = 0; |
3668 | con_driver->last = 0; | 3673 | con_driver->last = 0; |
3669 | retval = 0; | 3674 | return 0; |
3670 | break; | ||
3671 | } | 3675 | } |
3672 | } | 3676 | } |
3673 | err: | 3677 | |
3674 | return retval; | 3678 | return -ENODEV; |
3675 | } | 3679 | } |
3676 | EXPORT_SYMBOL_GPL(do_unregister_con_driver); | 3680 | EXPORT_SYMBOL_GPL(do_unregister_con_driver); |
3677 | 3681 | ||
diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c index e371f5af11f5..a673e5b6a2e0 100644 --- a/drivers/uio/uio.c +++ b/drivers/uio/uio.c | |||
@@ -655,7 +655,7 @@ static int uio_mmap_physical(struct vm_area_struct *vma) | |||
655 | 655 | ||
656 | if (mem->addr & ~PAGE_MASK) | 656 | if (mem->addr & ~PAGE_MASK) |
657 | return -ENODEV; | 657 | return -ENODEV; |
658 | if (vma->vm_end - vma->vm_start > PAGE_ALIGN(mem->size)) | 658 | if (vma->vm_end - vma->vm_start > mem->size) |
659 | return -EINVAL; | 659 | return -EINVAL; |
660 | 660 | ||
661 | vma->vm_ops = &uio_physical_vm_ops; | 661 | vma->vm_ops = &uio_physical_vm_ops; |
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 879b66e13370..21b99b4b4082 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c | |||
@@ -1526,18 +1526,6 @@ static int hub_configure(struct usb_hub *hub, | |||
1526 | dev_dbg(hub_dev, "%umA bus power budget for each child\n", | 1526 | dev_dbg(hub_dev, "%umA bus power budget for each child\n", |
1527 | hub->mA_per_port); | 1527 | hub->mA_per_port); |
1528 | 1528 | ||
1529 | /* Update the HCD's internal representation of this hub before khubd | ||
1530 | * starts getting port status changes for devices under the hub. | ||
1531 | */ | ||
1532 | if (hcd->driver->update_hub_device) { | ||
1533 | ret = hcd->driver->update_hub_device(hcd, hdev, | ||
1534 | &hub->tt, GFP_KERNEL); | ||
1535 | if (ret < 0) { | ||
1536 | message = "can't update HCD hub info"; | ||
1537 | goto fail; | ||
1538 | } | ||
1539 | } | ||
1540 | |||
1541 | ret = hub_hub_status(hub, &hubstatus, &hubchange); | 1529 | ret = hub_hub_status(hub, &hubstatus, &hubchange); |
1542 | if (ret < 0) { | 1530 | if (ret < 0) { |
1543 | message = "can't get hub status"; | 1531 | message = "can't get hub status"; |
@@ -1589,10 +1577,28 @@ static int hub_configure(struct usb_hub *hub, | |||
1589 | } | 1577 | } |
1590 | } | 1578 | } |
1591 | hdev->maxchild = i; | 1579 | hdev->maxchild = i; |
1580 | for (i = 0; i < hdev->maxchild; i++) { | ||
1581 | struct usb_port *port_dev = hub->ports[i]; | ||
1582 | |||
1583 | pm_runtime_put(&port_dev->dev); | ||
1584 | } | ||
1585 | |||
1592 | mutex_unlock(&usb_port_peer_mutex); | 1586 | mutex_unlock(&usb_port_peer_mutex); |
1593 | if (ret < 0) | 1587 | if (ret < 0) |
1594 | goto fail; | 1588 | goto fail; |
1595 | 1589 | ||
1590 | /* Update the HCD's internal representation of this hub before khubd | ||
1591 | * starts getting port status changes for devices under the hub. | ||
1592 | */ | ||
1593 | if (hcd->driver->update_hub_device) { | ||
1594 | ret = hcd->driver->update_hub_device(hcd, hdev, | ||
1595 | &hub->tt, GFP_KERNEL); | ||
1596 | if (ret < 0) { | ||
1597 | message = "can't update HCD hub info"; | ||
1598 | goto fail; | ||
1599 | } | ||
1600 | } | ||
1601 | |||
1596 | usb_hub_adjust_deviceremovable(hdev, hub->descriptor); | 1602 | usb_hub_adjust_deviceremovable(hdev, hub->descriptor); |
1597 | 1603 | ||
1598 | hub_activate(hub, HUB_INIT); | 1604 | hub_activate(hub, HUB_INIT); |
@@ -3458,7 +3464,8 @@ static int hub_suspend(struct usb_interface *intf, pm_message_t msg) | |||
3458 | struct usb_device *udev = port_dev->child; | 3464 | struct usb_device *udev = port_dev->child; |
3459 | 3465 | ||
3460 | if (udev && udev->can_submit) { | 3466 | if (udev && udev->can_submit) { |
3461 | dev_warn(&port_dev->dev, "not suspended yet\n"); | 3467 | dev_warn(&port_dev->dev, "device %s not suspended yet\n", |
3468 | dev_name(&udev->dev)); | ||
3462 | if (PMSG_IS_AUTO(msg)) | 3469 | if (PMSG_IS_AUTO(msg)) |
3463 | return -EBUSY; | 3470 | return -EBUSY; |
3464 | } | 3471 | } |
diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h index 0a7cdc0ef0a9..326308e53961 100644 --- a/drivers/usb/core/hub.h +++ b/drivers/usb/core/hub.h | |||
@@ -84,6 +84,7 @@ struct usb_hub { | |||
84 | * @dev: generic device interface | 84 | * @dev: generic device interface |
85 | * @port_owner: port's owner | 85 | * @port_owner: port's owner |
86 | * @peer: related usb2 and usb3 ports (share the same connector) | 86 | * @peer: related usb2 and usb3 ports (share the same connector) |
87 | * @req: default pm qos request for hubs without port power control | ||
87 | * @connect_type: port's connect type | 88 | * @connect_type: port's connect type |
88 | * @location: opaque representation of platform connector location | 89 | * @location: opaque representation of platform connector location |
89 | * @status_lock: synchronize port_event() vs usb_port_{suspend|resume} | 90 | * @status_lock: synchronize port_event() vs usb_port_{suspend|resume} |
@@ -95,6 +96,7 @@ struct usb_port { | |||
95 | struct device dev; | 96 | struct device dev; |
96 | struct usb_dev_state *port_owner; | 97 | struct usb_dev_state *port_owner; |
97 | struct usb_port *peer; | 98 | struct usb_port *peer; |
99 | struct dev_pm_qos_request *req; | ||
98 | enum usb_port_connect_type connect_type; | 100 | enum usb_port_connect_type connect_type; |
99 | usb_port_location_t location; | 101 | usb_port_location_t location; |
100 | struct mutex status_lock; | 102 | struct mutex status_lock; |
diff --git a/drivers/usb/core/port.c b/drivers/usb/core/port.c index 62036faf56c0..fe1b6d0967e3 100644 --- a/drivers/usb/core/port.c +++ b/drivers/usb/core/port.c | |||
@@ -21,6 +21,8 @@ | |||
21 | 21 | ||
22 | #include "hub.h" | 22 | #include "hub.h" |
23 | 23 | ||
24 | static int usb_port_block_power_off; | ||
25 | |||
24 | static const struct attribute_group *port_dev_group[]; | 26 | static const struct attribute_group *port_dev_group[]; |
25 | 27 | ||
26 | static ssize_t connect_type_show(struct device *dev, | 28 | static ssize_t connect_type_show(struct device *dev, |
@@ -66,6 +68,7 @@ static void usb_port_device_release(struct device *dev) | |||
66 | { | 68 | { |
67 | struct usb_port *port_dev = to_usb_port(dev); | 69 | struct usb_port *port_dev = to_usb_port(dev); |
68 | 70 | ||
71 | kfree(port_dev->req); | ||
69 | kfree(port_dev); | 72 | kfree(port_dev); |
70 | } | 73 | } |
71 | 74 | ||
@@ -142,6 +145,9 @@ static int usb_port_runtime_suspend(struct device *dev) | |||
142 | == PM_QOS_FLAGS_ALL) | 145 | == PM_QOS_FLAGS_ALL) |
143 | return -EAGAIN; | 146 | return -EAGAIN; |
144 | 147 | ||
148 | if (usb_port_block_power_off) | ||
149 | return -EBUSY; | ||
150 | |||
145 | usb_autopm_get_interface(intf); | 151 | usb_autopm_get_interface(intf); |
146 | retval = usb_hub_set_port_power(hdev, hub, port1, false); | 152 | retval = usb_hub_set_port_power(hdev, hub, port1, false); |
147 | usb_clear_port_feature(hdev, port1, USB_PORT_FEAT_C_CONNECTION); | 153 | usb_clear_port_feature(hdev, port1, USB_PORT_FEAT_C_CONNECTION); |
@@ -190,11 +196,19 @@ static int link_peers(struct usb_port *left, struct usb_port *right) | |||
190 | if (left->peer || right->peer) { | 196 | if (left->peer || right->peer) { |
191 | struct usb_port *lpeer = left->peer; | 197 | struct usb_port *lpeer = left->peer; |
192 | struct usb_port *rpeer = right->peer; | 198 | struct usb_port *rpeer = right->peer; |
193 | 199 | char *method; | |
194 | WARN(1, "failed to peer %s and %s (%s -> %p) (%s -> %p)\n", | 200 | |
195 | dev_name(&left->dev), dev_name(&right->dev), | 201 | if (left->location && left->location == right->location) |
196 | dev_name(&left->dev), lpeer, | 202 | method = "location"; |
197 | dev_name(&right->dev), rpeer); | 203 | else |
204 | method = "default"; | ||
205 | |||
206 | pr_warn("usb: failed to peer %s and %s by %s (%s:%s) (%s:%s)\n", | ||
207 | dev_name(&left->dev), dev_name(&right->dev), method, | ||
208 | dev_name(&left->dev), | ||
209 | lpeer ? dev_name(&lpeer->dev) : "none", | ||
210 | dev_name(&right->dev), | ||
211 | rpeer ? dev_name(&rpeer->dev) : "none"); | ||
198 | return -EBUSY; | 212 | return -EBUSY; |
199 | } | 213 | } |
200 | 214 | ||
@@ -251,6 +265,7 @@ static void link_peers_report(struct usb_port *left, struct usb_port *right) | |||
251 | dev_warn(&left->dev, "failed to peer to %s (%d)\n", | 265 | dev_warn(&left->dev, "failed to peer to %s (%d)\n", |
252 | dev_name(&right->dev), rc); | 266 | dev_name(&right->dev), rc); |
253 | pr_warn_once("usb: port power management may be unreliable\n"); | 267 | pr_warn_once("usb: port power management may be unreliable\n"); |
268 | usb_port_block_power_off = 1; | ||
254 | } | 269 | } |
255 | } | 270 | } |
256 | 271 | ||
@@ -386,9 +401,13 @@ int usb_hub_create_port_device(struct usb_hub *hub, int port1) | |||
386 | int retval; | 401 | int retval; |
387 | 402 | ||
388 | port_dev = kzalloc(sizeof(*port_dev), GFP_KERNEL); | 403 | port_dev = kzalloc(sizeof(*port_dev), GFP_KERNEL); |
389 | if (!port_dev) { | 404 | if (!port_dev) |
390 | retval = -ENOMEM; | 405 | return -ENOMEM; |
391 | goto exit; | 406 | |
407 | port_dev->req = kzalloc(sizeof(*(port_dev->req)), GFP_KERNEL); | ||
408 | if (!port_dev->req) { | ||
409 | kfree(port_dev); | ||
410 | return -ENOMEM; | ||
392 | } | 411 | } |
393 | 412 | ||
394 | hub->ports[port1 - 1] = port_dev; | 413 | hub->ports[port1 - 1] = port_dev; |
@@ -404,31 +423,53 @@ int usb_hub_create_port_device(struct usb_hub *hub, int port1) | |||
404 | port1); | 423 | port1); |
405 | mutex_init(&port_dev->status_lock); | 424 | mutex_init(&port_dev->status_lock); |
406 | retval = device_register(&port_dev->dev); | 425 | retval = device_register(&port_dev->dev); |
407 | if (retval) | 426 | if (retval) { |
408 | goto error_register; | 427 | put_device(&port_dev->dev); |
428 | return retval; | ||
429 | } | ||
430 | |||
431 | /* Set default policy of port-poweroff disabled. */ | ||
432 | retval = dev_pm_qos_add_request(&port_dev->dev, port_dev->req, | ||
433 | DEV_PM_QOS_FLAGS, PM_QOS_FLAG_NO_POWER_OFF); | ||
434 | if (retval < 0) { | ||
435 | device_unregister(&port_dev->dev); | ||
436 | return retval; | ||
437 | } | ||
409 | 438 | ||
410 | find_and_link_peer(hub, port1); | 439 | find_and_link_peer(hub, port1); |
411 | 440 | ||
441 | /* | ||
442 | * Enable runtime pm and hold a refernce that hub_configure() | ||
443 | * will drop once the PM_QOS_NO_POWER_OFF flag state has been set | ||
444 | * and the hub has been fully registered (hdev->maxchild set). | ||
445 | */ | ||
412 | pm_runtime_set_active(&port_dev->dev); | 446 | pm_runtime_set_active(&port_dev->dev); |
447 | pm_runtime_get_noresume(&port_dev->dev); | ||
448 | pm_runtime_enable(&port_dev->dev); | ||
449 | device_enable_async_suspend(&port_dev->dev); | ||
413 | 450 | ||
414 | /* | 451 | /* |
415 | * Do not enable port runtime pm if the hub does not support | 452 | * Keep hidden the ability to enable port-poweroff if the hub |
416 | * power switching. Also, userspace must have final say of | 453 | * does not support power switching. |
417 | * whether a port is permitted to power-off. Do not enable | ||
418 | * runtime pm if we fail to expose pm_qos_no_power_off. | ||
419 | */ | 454 | */ |
420 | if (hub_is_port_power_switchable(hub) | 455 | if (!hub_is_port_power_switchable(hub)) |
421 | && dev_pm_qos_expose_flags(&port_dev->dev, | 456 | return 0; |
422 | PM_QOS_FLAG_NO_POWER_OFF) == 0) | ||
423 | pm_runtime_enable(&port_dev->dev); | ||
424 | 457 | ||
425 | device_enable_async_suspend(&port_dev->dev); | 458 | /* Attempt to let userspace take over the policy. */ |
426 | return 0; | 459 | retval = dev_pm_qos_expose_flags(&port_dev->dev, |
460 | PM_QOS_FLAG_NO_POWER_OFF); | ||
461 | if (retval < 0) { | ||
462 | dev_warn(&port_dev->dev, "failed to expose pm_qos_no_poweroff\n"); | ||
463 | return 0; | ||
464 | } | ||
427 | 465 | ||
428 | error_register: | 466 | /* Userspace owns the policy, drop the kernel 'no_poweroff' request. */ |
429 | put_device(&port_dev->dev); | 467 | retval = dev_pm_qos_remove_request(port_dev->req); |
430 | exit: | 468 | if (retval >= 0) { |
431 | return retval; | 469 | kfree(port_dev->req); |
470 | port_dev->req = NULL; | ||
471 | } | ||
472 | return 0; | ||
432 | } | 473 | } |
433 | 474 | ||
434 | void usb_hub_remove_port_device(struct usb_hub *hub, int port1) | 475 | void usb_hub_remove_port_device(struct usb_hub *hub, int port1) |
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index 4a6d3dd68572..2f3acebb577a 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c | |||
@@ -656,6 +656,14 @@ static const struct dmi_system_id ehci_dmi_nohandoff_table[] = { | |||
656 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), | 656 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), |
657 | }, | 657 | }, |
658 | }, | 658 | }, |
659 | { | ||
660 | /* HASEE E200 */ | ||
661 | .matches = { | ||
662 | DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"), | ||
663 | DMI_MATCH(DMI_BOARD_NAME, "E210"), | ||
664 | DMI_MATCH(DMI_BIOS_VERSION, "6.00"), | ||
665 | }, | ||
666 | }, | ||
659 | { } | 667 | { } |
660 | }; | 668 | }; |
661 | 669 | ||
@@ -665,9 +673,14 @@ static void ehci_bios_handoff(struct pci_dev *pdev, | |||
665 | { | 673 | { |
666 | int try_handoff = 1, tried_handoff = 0; | 674 | int try_handoff = 1, tried_handoff = 0; |
667 | 675 | ||
668 | /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying | 676 | /* |
669 | * the handoff on its unused controller. Skip it. */ | 677 | * The Pegatron Lucid tablet sporadically waits for 98 seconds trying |
670 | if (pdev->vendor == 0x8086 && pdev->device == 0x283a) { | 678 | * the handoff on its unused controller. Skip it. |
679 | * | ||
680 | * The HASEE E200 hangs when the semaphore is set (bugzilla #77021). | ||
681 | */ | ||
682 | if (pdev->vendor == 0x8086 && (pdev->device == 0x283a || | ||
683 | pdev->device == 0x27cc)) { | ||
671 | if (dmi_check_system(ehci_dmi_nohandoff_table)) | 684 | if (dmi_check_system(ehci_dmi_nohandoff_table)) |
672 | try_handoff = 0; | 685 | try_handoff = 0; |
673 | } | 686 | } |
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index 6231ce6aa0c3..2b998c60faf2 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c | |||
@@ -287,7 +287,7 @@ static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |||
287 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { | 287 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { |
288 | struct xhci_command *command; | 288 | struct xhci_command *command; |
289 | command = xhci_alloc_command(xhci, false, false, | 289 | command = xhci_alloc_command(xhci, false, false, |
290 | GFP_NOIO); | 290 | GFP_NOWAIT); |
291 | if (!command) { | 291 | if (!command) { |
292 | spin_unlock_irqrestore(&xhci->lock, flags); | 292 | spin_unlock_irqrestore(&xhci->lock, flags); |
293 | xhci_free_command(xhci, cmd); | 293 | xhci_free_command(xhci, cmd); |
diff --git a/drivers/usb/misc/usbtest.c b/drivers/usb/misc/usbtest.c index 51a6da256772..829f446064ea 100644 --- a/drivers/usb/misc/usbtest.c +++ b/drivers/usb/misc/usbtest.c | |||
@@ -7,7 +7,7 @@ | |||
7 | #include <linux/moduleparam.h> | 7 | #include <linux/moduleparam.h> |
8 | #include <linux/scatterlist.h> | 8 | #include <linux/scatterlist.h> |
9 | #include <linux/mutex.h> | 9 | #include <linux/mutex.h> |
10 | 10 | #include <linux/timer.h> | |
11 | #include <linux/usb.h> | 11 | #include <linux/usb.h> |
12 | 12 | ||
13 | #define SIMPLE_IO_TIMEOUT 10000 /* in milliseconds */ | 13 | #define SIMPLE_IO_TIMEOUT 10000 /* in milliseconds */ |
@@ -484,6 +484,14 @@ alloc_sglist(int nents, int max, int vary) | |||
484 | return sg; | 484 | return sg; |
485 | } | 485 | } |
486 | 486 | ||
487 | static void sg_timeout(unsigned long _req) | ||
488 | { | ||
489 | struct usb_sg_request *req = (struct usb_sg_request *) _req; | ||
490 | |||
491 | req->status = -ETIMEDOUT; | ||
492 | usb_sg_cancel(req); | ||
493 | } | ||
494 | |||
487 | static int perform_sglist( | 495 | static int perform_sglist( |
488 | struct usbtest_dev *tdev, | 496 | struct usbtest_dev *tdev, |
489 | unsigned iterations, | 497 | unsigned iterations, |
@@ -495,6 +503,9 @@ static int perform_sglist( | |||
495 | { | 503 | { |
496 | struct usb_device *udev = testdev_to_usbdev(tdev); | 504 | struct usb_device *udev = testdev_to_usbdev(tdev); |
497 | int retval = 0; | 505 | int retval = 0; |
506 | struct timer_list sg_timer; | ||
507 | |||
508 | setup_timer_on_stack(&sg_timer, sg_timeout, (unsigned long) req); | ||
498 | 509 | ||
499 | while (retval == 0 && iterations-- > 0) { | 510 | while (retval == 0 && iterations-- > 0) { |
500 | retval = usb_sg_init(req, udev, pipe, | 511 | retval = usb_sg_init(req, udev, pipe, |
@@ -505,7 +516,10 @@ static int perform_sglist( | |||
505 | 516 | ||
506 | if (retval) | 517 | if (retval) |
507 | break; | 518 | break; |
519 | mod_timer(&sg_timer, jiffies + | ||
520 | msecs_to_jiffies(SIMPLE_IO_TIMEOUT)); | ||
508 | usb_sg_wait(req); | 521 | usb_sg_wait(req); |
522 | del_timer_sync(&sg_timer); | ||
509 | retval = req->status; | 523 | retval = req->status; |
510 | 524 | ||
511 | /* FIXME check resulting data pattern */ | 525 | /* FIXME check resulting data pattern */ |
diff --git a/drivers/video/console/dummycon.c b/drivers/video/console/dummycon.c index b63860f7beab..40bec8d64b0a 100644 --- a/drivers/video/console/dummycon.c +++ b/drivers/video/console/dummycon.c | |||
@@ -77,3 +77,4 @@ const struct consw dummy_con = { | |||
77 | .con_set_palette = DUMMY, | 77 | .con_set_palette = DUMMY, |
78 | .con_scrolldelta = DUMMY, | 78 | .con_scrolldelta = DUMMY, |
79 | }; | 79 | }; |
80 | EXPORT_SYMBOL_GPL(dummy_con); | ||
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c index f267284b423b..6e6aa704fe84 100644 --- a/drivers/video/console/vgacon.c +++ b/drivers/video/console/vgacon.c | |||
@@ -1441,5 +1441,6 @@ const struct consw vga_con = { | |||
1441 | .con_build_attr = vgacon_build_attr, | 1441 | .con_build_attr = vgacon_build_attr, |
1442 | .con_invert_region = vgacon_invert_region, | 1442 | .con_invert_region = vgacon_invert_region, |
1443 | }; | 1443 | }; |
1444 | EXPORT_SYMBOL(vga_con); | ||
1444 | 1445 | ||
1445 | MODULE_LICENSE("GPL"); | 1446 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/video/fbdev/offb.c b/drivers/video/fbdev/offb.c index 7d44d669d5b6..43a0a52fc527 100644 --- a/drivers/video/fbdev/offb.c +++ b/drivers/video/fbdev/offb.c | |||
@@ -91,15 +91,6 @@ extern boot_infos_t *boot_infos; | |||
91 | #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4 | 91 | #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4 |
92 | #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8 | 92 | #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8 |
93 | 93 | ||
94 | #define FB_RIGHT_POS(p, bpp) (fb_be_math(p) ? 0 : (32 - (bpp))) | ||
95 | |||
96 | static inline u32 offb_cmap_byteswap(struct fb_info *info, u32 value) | ||
97 | { | ||
98 | u32 bpp = info->var.bits_per_pixel; | ||
99 | |||
100 | return cpu_to_be32(value) >> FB_RIGHT_POS(info, bpp); | ||
101 | } | ||
102 | |||
103 | /* | 94 | /* |
104 | * Set a single color register. The values supplied are already | 95 | * Set a single color register. The values supplied are already |
105 | * rounded down to the hardware's capabilities (according to the | 96 | * rounded down to the hardware's capabilities (according to the |
@@ -129,7 +120,7 @@ static int offb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |||
129 | mask <<= info->var.transp.offset; | 120 | mask <<= info->var.transp.offset; |
130 | value |= mask; | 121 | value |= mask; |
131 | } | 122 | } |
132 | pal[regno] = offb_cmap_byteswap(info, value); | 123 | pal[regno] = value; |
133 | return 0; | 124 | return 0; |
134 | } | 125 | } |
135 | 126 | ||
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c index 67b067a3e2ab..a5df5e89d456 100644 --- a/drivers/w1/masters/mxc_w1.c +++ b/drivers/w1/masters/mxc_w1.c | |||
@@ -66,7 +66,7 @@ static u8 mxc_w1_ds2_reset_bus(void *data) | |||
66 | 66 | ||
67 | udelay(100); | 67 | udelay(100); |
68 | } | 68 | } |
69 | return !!(reg_val & MXC_W1_CONTROL_PST); | 69 | return !(reg_val & MXC_W1_CONTROL_PST); |
70 | } | 70 | } |
71 | 71 | ||
72 | /* | 72 | /* |
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index c845527b503a..76dd54122f76 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig | |||
@@ -1280,14 +1280,17 @@ config WATCHDOG_RTAS | |||
1280 | 1280 | ||
1281 | # S390 Architecture | 1281 | # S390 Architecture |
1282 | 1282 | ||
1283 | config ZVM_WATCHDOG | 1283 | config DIAG288_WATCHDOG |
1284 | tristate "z/VM Watchdog Timer" | 1284 | tristate "System z diag288 Watchdog" |
1285 | depends on S390 | 1285 | depends on S390 |
1286 | select WATCHDOG_CORE | ||
1286 | help | 1287 | help |
1287 | IBM s/390 and zSeries machines running under z/VM 5.1 or later | 1288 | IBM s/390 and zSeries machines running under z/VM 5.1 or later |
1288 | provide a virtual watchdog timer to their guest that cause a | 1289 | provide a virtual watchdog timer to their guest that cause a |
1289 | user define Control Program command to be executed after a | 1290 | user define Control Program command to be executed after a |
1290 | timeout. | 1291 | timeout. |
1292 | LPAR provides a very similar interface. This driver handles | ||
1293 | both. | ||
1291 | 1294 | ||
1292 | To compile this driver as a module, choose M here. The module | 1295 | To compile this driver as a module, choose M here. The module |
1293 | will be called vmwatchdog. | 1296 | will be called vmwatchdog. |
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 7b8a91ed20e7..468c3204c3b1 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile | |||
@@ -153,6 +153,7 @@ obj-$(CONFIG_MEN_A21_WDT) += mena21_wdt.o | |||
153 | obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o | 153 | obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o |
154 | 154 | ||
155 | # S390 Architecture | 155 | # S390 Architecture |
156 | obj-$(CONFIG_DIAG288_WATCHDOG) += diag288_wdt.o | ||
156 | 157 | ||
157 | # SUPERH (sh + sh64) Architecture | 158 | # SUPERH (sh + sh64) Architecture |
158 | obj-$(CONFIG_SH_WDT) += shwdt.o | 159 | obj-$(CONFIG_SH_WDT) += shwdt.o |
diff --git a/drivers/watchdog/diag288_wdt.c b/drivers/watchdog/diag288_wdt.c new file mode 100644 index 000000000000..429494b6c822 --- /dev/null +++ b/drivers/watchdog/diag288_wdt.c | |||
@@ -0,0 +1,316 @@ | |||
1 | /* | ||
2 | * Watchdog driver for z/VM and LPAR using the diag 288 interface. | ||
3 | * | ||
4 | * Under z/VM, expiration of the watchdog will send a "system restart" command | ||
5 | * to CP. | ||
6 | * | ||
7 | * The command can be altered using the module parameter "cmd". This is | ||
8 | * not recommended because it's only supported on z/VM but not whith LPAR. | ||
9 | * | ||
10 | * On LPAR, the watchdog will always trigger a system restart. the module | ||
11 | * paramter cmd is meaningless here. | ||
12 | * | ||
13 | * | ||
14 | * Copyright IBM Corp. 2004, 2013 | ||
15 | * Author(s): Arnd Bergmann (arndb@de.ibm.com) | ||
16 | * Philipp Hachtmann (phacht@de.ibm.com) | ||
17 | * | ||
18 | */ | ||
19 | |||
20 | #define KMSG_COMPONENT "diag288_wdt" | ||
21 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | ||
22 | |||
23 | #include <linux/init.h> | ||
24 | #include <linux/kernel.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/moduleparam.h> | ||
27 | #include <linux/slab.h> | ||
28 | #include <linux/miscdevice.h> | ||
29 | #include <linux/watchdog.h> | ||
30 | #include <linux/suspend.h> | ||
31 | #include <asm/ebcdic.h> | ||
32 | #include <linux/io.h> | ||
33 | #include <linux/uaccess.h> | ||
34 | |||
35 | #define MAX_CMDLEN 240 | ||
36 | #define DEFAULT_CMD "SYSTEM RESTART" | ||
37 | |||
38 | #define MIN_INTERVAL 15 /* Minimal time supported by diag88 */ | ||
39 | #define MAX_INTERVAL 3600 /* One hour should be enough - pure estimation */ | ||
40 | |||
41 | #define WDT_DEFAULT_TIMEOUT 30 | ||
42 | |||
43 | /* Function codes - init, change, cancel */ | ||
44 | #define WDT_FUNC_INIT 0 | ||
45 | #define WDT_FUNC_CHANGE 1 | ||
46 | #define WDT_FUNC_CANCEL 2 | ||
47 | #define WDT_FUNC_CONCEAL 0x80000000 | ||
48 | |||
49 | /* Action codes for LPAR watchdog */ | ||
50 | #define LPARWDT_RESTART 0 | ||
51 | |||
52 | static char wdt_cmd[MAX_CMDLEN] = DEFAULT_CMD; | ||
53 | static bool conceal_on; | ||
54 | static bool nowayout_info = WATCHDOG_NOWAYOUT; | ||
55 | |||
56 | MODULE_LICENSE("GPL"); | ||
57 | MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>"); | ||
58 | MODULE_AUTHOR("Philipp Hachtmann <phacht@de.ibm.com>"); | ||
59 | |||
60 | MODULE_DESCRIPTION("System z diag288 Watchdog Timer"); | ||
61 | |||
62 | module_param_string(cmd, wdt_cmd, MAX_CMDLEN, 0644); | ||
63 | MODULE_PARM_DESC(cmd, "CP command that is run when the watchdog triggers (z/VM only)"); | ||
64 | |||
65 | module_param_named(conceal, conceal_on, bool, 0644); | ||
66 | MODULE_PARM_DESC(conceal, "Enable the CONCEAL CP option while the watchdog is active (z/VM only)"); | ||
67 | |||
68 | module_param_named(nowayout, nowayout_info, bool, 0444); | ||
69 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default = CONFIG_WATCHDOG_NOWAYOUT)"); | ||
70 | |||
71 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | ||
72 | MODULE_ALIAS("vmwatchdog"); | ||
73 | |||
74 | static int __diag288(unsigned int func, unsigned int timeout, | ||
75 | unsigned long action, unsigned int len) | ||
76 | { | ||
77 | register unsigned long __func asm("2") = func; | ||
78 | register unsigned long __timeout asm("3") = timeout; | ||
79 | register unsigned long __action asm("4") = action; | ||
80 | register unsigned long __len asm("5") = len; | ||
81 | int err; | ||
82 | |||
83 | err = -EINVAL; | ||
84 | asm volatile( | ||
85 | " diag %1, %3, 0x288\n" | ||
86 | "0: la %0, 0\n" | ||
87 | "1:\n" | ||
88 | EX_TABLE(0b, 1b) | ||
89 | : "+d" (err) : "d"(__func), "d"(__timeout), | ||
90 | "d"(__action), "d"(__len) : "1", "cc"); | ||
91 | return err; | ||
92 | } | ||
93 | |||
94 | static int __diag288_vm(unsigned int func, unsigned int timeout, | ||
95 | char *cmd, size_t len) | ||
96 | { | ||
97 | return __diag288(func, timeout, virt_to_phys(cmd), len); | ||
98 | } | ||
99 | |||
100 | static int __diag288_lpar(unsigned int func, unsigned int timeout, | ||
101 | unsigned long action) | ||
102 | { | ||
103 | return __diag288(func, timeout, action, 0); | ||
104 | } | ||
105 | |||
106 | static int wdt_start(struct watchdog_device *dev) | ||
107 | { | ||
108 | char *ebc_cmd; | ||
109 | size_t len; | ||
110 | int ret; | ||
111 | unsigned int func; | ||
112 | |||
113 | ret = -ENODEV; | ||
114 | |||
115 | if (MACHINE_IS_VM) { | ||
116 | ebc_cmd = kmalloc(MAX_CMDLEN, GFP_KERNEL); | ||
117 | if (!ebc_cmd) | ||
118 | return -ENOMEM; | ||
119 | len = strlcpy(ebc_cmd, wdt_cmd, MAX_CMDLEN); | ||
120 | ASCEBC(ebc_cmd, MAX_CMDLEN); | ||
121 | EBC_TOUPPER(ebc_cmd, MAX_CMDLEN); | ||
122 | |||
123 | func = conceal_on ? (WDT_FUNC_INIT | WDT_FUNC_CONCEAL) | ||
124 | : WDT_FUNC_INIT; | ||
125 | ret = __diag288_vm(func, dev->timeout, ebc_cmd, len); | ||
126 | WARN_ON(ret != 0); | ||
127 | kfree(ebc_cmd); | ||
128 | } | ||
129 | |||
130 | if (MACHINE_IS_LPAR) { | ||
131 | ret = __diag288_lpar(WDT_FUNC_INIT, | ||
132 | dev->timeout, LPARWDT_RESTART); | ||
133 | } | ||
134 | |||
135 | if (ret) { | ||
136 | pr_err("The watchdog cannot be activated\n"); | ||
137 | return ret; | ||
138 | } | ||
139 | pr_info("The watchdog was activated\n"); | ||
140 | return 0; | ||
141 | } | ||
142 | |||
143 | static int wdt_stop(struct watchdog_device *dev) | ||
144 | { | ||
145 | int ret; | ||
146 | |||
147 | ret = __diag288(WDT_FUNC_CANCEL, 0, 0, 0); | ||
148 | pr_info("The watchdog was deactivated\n"); | ||
149 | return ret; | ||
150 | } | ||
151 | |||
152 | static int wdt_ping(struct watchdog_device *dev) | ||
153 | { | ||
154 | char *ebc_cmd; | ||
155 | size_t len; | ||
156 | int ret; | ||
157 | unsigned int func; | ||
158 | |||
159 | ret = -ENODEV; | ||
160 | |||
161 | if (MACHINE_IS_VM) { | ||
162 | ebc_cmd = kmalloc(MAX_CMDLEN, GFP_KERNEL); | ||
163 | if (!ebc_cmd) | ||
164 | return -ENOMEM; | ||
165 | len = strlcpy(ebc_cmd, wdt_cmd, MAX_CMDLEN); | ||
166 | ASCEBC(ebc_cmd, MAX_CMDLEN); | ||
167 | EBC_TOUPPER(ebc_cmd, MAX_CMDLEN); | ||
168 | |||
169 | /* | ||
170 | * It seems to be ok to z/VM to use the init function to | ||
171 | * retrigger the watchdog. On LPAR WDT_FUNC_CHANGE must | ||
172 | * be used when the watchdog is running. | ||
173 | */ | ||
174 | func = conceal_on ? (WDT_FUNC_INIT | WDT_FUNC_CONCEAL) | ||
175 | : WDT_FUNC_INIT; | ||
176 | |||
177 | ret = __diag288_vm(func, dev->timeout, ebc_cmd, len); | ||
178 | WARN_ON(ret != 0); | ||
179 | kfree(ebc_cmd); | ||
180 | } | ||
181 | |||
182 | if (MACHINE_IS_LPAR) | ||
183 | ret = __diag288_lpar(WDT_FUNC_CHANGE, dev->timeout, 0); | ||
184 | |||
185 | if (ret) | ||
186 | pr_err("The watchdog timer cannot be started or reset\n"); | ||
187 | return ret; | ||
188 | } | ||
189 | |||
190 | static int wdt_set_timeout(struct watchdog_device * dev, unsigned int new_to) | ||
191 | { | ||
192 | dev->timeout = new_to; | ||
193 | return wdt_ping(dev); | ||
194 | } | ||
195 | |||
196 | static struct watchdog_ops wdt_ops = { | ||
197 | .owner = THIS_MODULE, | ||
198 | .start = wdt_start, | ||
199 | .stop = wdt_stop, | ||
200 | .ping = wdt_ping, | ||
201 | .set_timeout = wdt_set_timeout, | ||
202 | }; | ||
203 | |||
204 | static struct watchdog_info wdt_info = { | ||
205 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | ||
206 | .firmware_version = 0, | ||
207 | .identity = "z Watchdog", | ||
208 | }; | ||
209 | |||
210 | static struct watchdog_device wdt_dev = { | ||
211 | .parent = NULL, | ||
212 | .info = &wdt_info, | ||
213 | .ops = &wdt_ops, | ||
214 | .bootstatus = 0, | ||
215 | .timeout = WDT_DEFAULT_TIMEOUT, | ||
216 | .min_timeout = MIN_INTERVAL, | ||
217 | .max_timeout = MAX_INTERVAL, | ||
218 | }; | ||
219 | |||
220 | /* | ||
221 | * It makes no sense to go into suspend while the watchdog is running. | ||
222 | * Depending on the memory size, the watchdog might trigger, while we | ||
223 | * are still saving the memory. | ||
224 | * We reuse the open flag to ensure that suspend and watchdog open are | ||
225 | * exclusive operations | ||
226 | */ | ||
227 | static int wdt_suspend(void) | ||
228 | { | ||
229 | if (test_and_set_bit(WDOG_DEV_OPEN, &wdt_dev.status)) { | ||
230 | pr_err("Linux cannot be suspended while the watchdog is in use\n"); | ||
231 | return notifier_from_errno(-EBUSY); | ||
232 | } | ||
233 | if (test_bit(WDOG_ACTIVE, &wdt_dev.status)) { | ||
234 | clear_bit(WDOG_DEV_OPEN, &wdt_dev.status); | ||
235 | pr_err("Linux cannot be suspended while the watchdog is in use\n"); | ||
236 | return notifier_from_errno(-EBUSY); | ||
237 | } | ||
238 | return NOTIFY_DONE; | ||
239 | } | ||
240 | |||
241 | static int wdt_resume(void) | ||
242 | { | ||
243 | clear_bit(WDOG_DEV_OPEN, &wdt_dev.status); | ||
244 | return NOTIFY_DONE; | ||
245 | } | ||
246 | |||
247 | static int wdt_power_event(struct notifier_block *this, unsigned long event, | ||
248 | void *ptr) | ||
249 | { | ||
250 | switch (event) { | ||
251 | case PM_POST_HIBERNATION: | ||
252 | case PM_POST_SUSPEND: | ||
253 | return wdt_resume(); | ||
254 | case PM_HIBERNATION_PREPARE: | ||
255 | case PM_SUSPEND_PREPARE: | ||
256 | return wdt_suspend(); | ||
257 | default: | ||
258 | return NOTIFY_DONE; | ||
259 | } | ||
260 | } | ||
261 | |||
262 | static struct notifier_block wdt_power_notifier = { | ||
263 | .notifier_call = wdt_power_event, | ||
264 | }; | ||
265 | |||
266 | static int __init diag288_init(void) | ||
267 | { | ||
268 | int ret; | ||
269 | char ebc_begin[] = { | ||
270 | 194, 197, 199, 201, 213 | ||
271 | }; | ||
272 | |||
273 | watchdog_set_nowayout(&wdt_dev, nowayout_info); | ||
274 | |||
275 | if (MACHINE_IS_VM) { | ||
276 | pr_info("The watchdog device driver detected a z/VM environment\n"); | ||
277 | if (__diag288_vm(WDT_FUNC_INIT, 15, | ||
278 | ebc_begin, sizeof(ebc_begin)) != 0) { | ||
279 | pr_err("The watchdog cannot be initialized\n"); | ||
280 | return -EINVAL; | ||
281 | } | ||
282 | } else if (MACHINE_IS_LPAR) { | ||
283 | pr_info("The watchdog device driver detected an LPAR environment\n"); | ||
284 | if (__diag288_lpar(WDT_FUNC_INIT, 30, LPARWDT_RESTART)) { | ||
285 | pr_err("The watchdog cannot be initialized\n"); | ||
286 | return -EINVAL; | ||
287 | } | ||
288 | } else { | ||
289 | pr_err("Linux runs in an environment that does not support the diag288 watchdog\n"); | ||
290 | return -ENODEV; | ||
291 | } | ||
292 | |||
293 | if (__diag288_lpar(WDT_FUNC_CANCEL, 0, 0)) { | ||
294 | pr_err("The watchdog cannot be deactivated\n"); | ||
295 | return -EINVAL; | ||
296 | } | ||
297 | |||
298 | ret = register_pm_notifier(&wdt_power_notifier); | ||
299 | if (ret) | ||
300 | return ret; | ||
301 | |||
302 | ret = watchdog_register_device(&wdt_dev); | ||
303 | if (ret) | ||
304 | unregister_pm_notifier(&wdt_power_notifier); | ||
305 | |||
306 | return ret; | ||
307 | } | ||
308 | |||
309 | static void __exit diag288_exit(void) | ||
310 | { | ||
311 | watchdog_unregister_device(&wdt_dev); | ||
312 | unregister_pm_notifier(&wdt_power_notifier); | ||
313 | } | ||
314 | |||
315 | module_init(diag288_init); | ||
316 | module_exit(diag288_exit); | ||
diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c index 6d325bda76da..5d4de88fe5b8 100644 --- a/drivers/xen/grant-table.c +++ b/drivers/xen/grant-table.c | |||
@@ -1168,7 +1168,8 @@ int gnttab_resume(void) | |||
1168 | 1168 | ||
1169 | int gnttab_suspend(void) | 1169 | int gnttab_suspend(void) |
1170 | { | 1170 | { |
1171 | gnttab_interface->unmap_frames(); | 1171 | if (!xen_feature(XENFEAT_auto_translated_physmap)) |
1172 | gnttab_interface->unmap_frames(); | ||
1172 | return 0; | 1173 | return 0; |
1173 | } | 1174 | } |
1174 | 1175 | ||