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authorChris Wilson <chris@chris-wilson.co.uk>2013-07-19 15:36:56 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-07-25 09:22:07 -0400
commited71f1b48e95408d0b3ded014a15fb9d52ac5a86 (patch)
treefdb9503542836b76b9553762f4c466bce41242da /drivers
parenta7f31ee0b00203fcf47fb74a1d61a1c9be8d142e (diff)
drm/i915: Convert the register access tracepoint to be conditional
The TRACE_EVENT_CONDITION is supposed to generate more efficient code than if (cond) trace(), which is what we are currently using inside the register access functions. v2: Rebase onto uncore Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c2
-rw-r--r--drivers/gpu/drm/i915/i915_trace.h8
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c4
3 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0e904986f3e9..ed72fe08217c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1004,7 +1004,7 @@ static int gen6_drpc_info(struct seq_file *m)
1004 } 1004 }
1005 1005
1006 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); 1006 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1007 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); 1007 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1008 1008
1009 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1009 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1010 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1010 rcctl1 = I915_READ(GEN6_RC_CONTROL);
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 7d283b5fcbf9..2933e2ffeaa4 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -406,10 +406,12 @@ TRACE_EVENT(i915_flip_complete,
406 TP_printk("plane=%d, obj=%p", __entry->plane, __entry->obj) 406 TP_printk("plane=%d, obj=%p", __entry->plane, __entry->obj)
407); 407);
408 408
409TRACE_EVENT(i915_reg_rw, 409TRACE_EVENT_CONDITION(i915_reg_rw,
410 TP_PROTO(bool write, u32 reg, u64 val, int len), 410 TP_PROTO(bool write, u32 reg, u64 val, int len, bool trace),
411 411
412 TP_ARGS(write, reg, val, len), 412 TP_ARGS(write, reg, val, len, trace),
413
414 TP_CONDITION(trace),
413 415
414 TP_STRUCT__entry( 416 TP_STRUCT__entry(
415 __field(u64, val) 417 __field(u64, val)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 89bb9da377fc..8f5bc869c023 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -359,7 +359,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
359 val = __raw_i915_read##x(dev_priv, reg); \ 359 val = __raw_i915_read##x(dev_priv, reg); \
360 } \ 360 } \
361 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ 361 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
362 if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \ 362 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
363 return val; \ 363 return val; \
364} 364}
365 365
@@ -373,7 +373,7 @@ __i915_read(64)
373void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace) { \ 373void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace) { \
374 unsigned long irqflags; \ 374 unsigned long irqflags; \
375 u32 __fifo_ret = 0; \ 375 u32 __fifo_ret = 0; \
376 if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \ 376 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
377 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ 377 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
378 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 378 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
379 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 379 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \