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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:27:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:27:22 -0500
commitbab588fcfb6335c767d811a8955979f5440328e0 (patch)
tree2a862ddf47a82be885a8e7945a17cc3ff7a658b9 /drivers
parent3298a3511f1e73255a8dc023efd909e569eea037 (diff)
parent9cb0d1babfcb1b4ac248c09425f7d5de1e771133 (diff)
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann: "This is a larger set of new functionality for the existing SoC families, including: - vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850 - prima2 gains support for the "marco" SoC family, its SMP based cousin - tegra gains support for the new Tegra4 (Tegra114) family - socfpga now supports a newer version of the hardware including SMP - i.mx31 and bcm2835 are now using DT probing for their clocks - lots of updates for sh-mobile - OMAP updates for clocks, power management and USB - i.mx6q and tegra now support cpuidle - kirkwood now supports PCIe hot plugging - tegra clock support is updated - tegra USB PHY probing gets implemented diffently" * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits) ARM: prima2: remove duplicate v7_invalidate_l1 ARM: shmobile: r8a7779: Correct TMU clock support again ARM: prima2: fix __init section for cpu hotplug ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3) ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3) arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC ARM: tegra: Fix build error for gic update ARM: tegra: remove empty tegra_smp_init_cpus() ARM: shmobile: Register ARM architected timer ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move ARM: shmobile: r8a7779: Correct TMU clock support ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/clk-bcm2835.c9
-rw-r--r--drivers/clk/mxs/clk-imx28.c2
-rw-r--r--drivers/clk/tegra/Makefile11
-rw-r--r--drivers/clk/tegra/clk-audio-sync.c87
-rw-r--r--drivers/clk/tegra/clk-divider.c187
-rw-r--r--drivers/clk/tegra/clk-periph-gate.c179
-rw-r--r--drivers/clk/tegra/clk-periph.c218
-rw-r--r--drivers/clk/tegra/clk-pll-out.c123
-rw-r--r--drivers/clk/tegra/clk-pll.c648
-rw-r--r--drivers/clk/tegra/clk-super.c154
-rw-r--r--drivers/clk/tegra/clk-tegra20.c1349
-rw-r--r--drivers/clk/tegra/clk-tegra30.c1987
-rw-r--r--drivers/clk/tegra/clk.c85
-rw-r--r--drivers/clk/tegra/clk.h502
-rw-r--r--drivers/cpuidle/Kconfig6
-rw-r--r--drivers/cpuidle/Makefile1
-rw-r--r--drivers/cpuidle/cpuidle-kirkwood.c106
-rw-r--r--drivers/dma/tegra20-apb-dma.c2
-rw-r--r--drivers/gpu/drm/tegra/dc.c3
-rw-r--r--drivers/gpu/drm/tegra/drm.c1
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c3
-rw-r--r--drivers/i2c/busses/i2c-tegra.c3
-rw-r--r--drivers/input/keyboard/tegra-kbc.c2
-rw-r--r--drivers/rtc/Kconfig2
-rw-r--r--drivers/spi/spi-tegra20-sflash.c4
-rw-r--r--drivers/spi/spi-tegra20-slink.c4
-rw-r--r--drivers/staging/nvec/TODO4
-rw-r--r--drivers/staging/nvec/nvec.c5
-rw-r--r--drivers/usb/host/ehci-tegra.c97
-rw-r--r--drivers/usb/phy/tegra_usb_phy.c132
31 files changed, 5777 insertions, 141 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 14fde73ea6ff..300d4775d926 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
26obj-$(CONFIG_ARCH_U8500) += ux500/ 26obj-$(CONFIG_ARCH_U8500) += ux500/
27obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 27obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
28obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o 28obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
29obj-$(CONFIG_ARCH_TEGRA) += tegra/
30
29obj-$(CONFIG_X86) += x86/ 31obj-$(CONFIG_X86) += x86/
30 32
31# Chip specific 33# Chip specific
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c
index e69991aab43a..792bc57a9db7 100644
--- a/drivers/clk/clk-bcm2835.c
+++ b/drivers/clk/clk-bcm2835.c
@@ -20,6 +20,13 @@
20#include <linux/clk-provider.h> 20#include <linux/clk-provider.h>
21#include <linux/clkdev.h> 21#include <linux/clkdev.h>
22#include <linux/clk/bcm2835.h> 22#include <linux/clk/bcm2835.h>
23#include <linux/clk-provider.h>
24#include <linux/of.h>
25
26static const __initconst struct of_device_id clk_match[] = {
27 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
28 { }
29};
23 30
24/* 31/*
25 * These are fixed clocks. They're probably not all root clocks and it may 32 * These are fixed clocks. They're probably not all root clocks and it may
@@ -56,4 +63,6 @@ void __init bcm2835_init_clocks(void)
56 ret = clk_register_clkdev(clk, NULL, "20215000.uart"); 63 ret = clk_register_clkdev(clk, NULL, "20215000.uart");
57 if (ret) 64 if (ret)
58 pr_err("uart1_pclk alias not registered\n"); 65 pr_err("uart1_pclk alias not registered\n");
66
67 of_clk_init(clk_match);
59} 68}
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 126370a62ce2..76ce6c6d1113 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -238,7 +238,7 @@ int __init mx28_clocks_init(void)
238 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 238 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
239 } 239 }
240 240
241 clk_register_clkdev(clks[clk32k], NULL, "timrot"); 241 clk_register_clkdev(clks[xbus], NULL, "timrot");
242 clk_register_clkdev(clks[enet_out], NULL, "enet_out"); 242 clk_register_clkdev(clks[enet_out], NULL, "enet_out");
243 243
244 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 244 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
new file mode 100644
index 000000000000..2b41b0f4f731
--- /dev/null
+++ b/drivers/clk/tegra/Makefile
@@ -0,0 +1,11 @@
1obj-y += clk.o
2obj-y += clk-audio-sync.o
3obj-y += clk-divider.o
4obj-y += clk-periph.o
5obj-y += clk-periph-gate.o
6obj-y += clk-pll.o
7obj-y += clk-pll-out.o
8obj-y += clk-super.o
9
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c
new file mode 100644
index 000000000000..c0f7843e80e6
--- /dev/null
+++ b/drivers/clk/tegra/clk-audio-sync.c
@@ -0,0 +1,87 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/slab.h>
19#include <linux/err.h>
20
21#include "clk.h"
22
23static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
24 unsigned long parent_rate)
25{
26 struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
27
28 return sync->rate;
29}
30
31static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
32 unsigned long *prate)
33{
34 struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
35
36 if (rate > sync->max_rate)
37 return -EINVAL;
38 else
39 return rate;
40}
41
42static int clk_sync_source_set_rate(struct clk_hw *hw, unsigned long rate,
43 unsigned long parent_rate)
44{
45 struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
46
47 sync->rate = rate;
48 return 0;
49}
50
51const struct clk_ops tegra_clk_sync_source_ops = {
52 .round_rate = clk_sync_source_round_rate,
53 .set_rate = clk_sync_source_set_rate,
54 .recalc_rate = clk_sync_source_recalc_rate,
55};
56
57struct clk *tegra_clk_register_sync_source(const char *name,
58 unsigned long rate, unsigned long max_rate)
59{
60 struct tegra_clk_sync_source *sync;
61 struct clk_init_data init;
62 struct clk *clk;
63
64 sync = kzalloc(sizeof(*sync), GFP_KERNEL);
65 if (!sync) {
66 pr_err("%s: could not allocate sync source clk\n", __func__);
67 return ERR_PTR(-ENOMEM);
68 }
69
70 sync->rate = rate;
71 sync->max_rate = max_rate;
72
73 init.ops = &tegra_clk_sync_source_ops;
74 init.name = name;
75 init.flags = CLK_IS_ROOT;
76 init.parent_names = NULL;
77 init.num_parents = 0;
78
79 /* Data in .init is copied by clk_register(), so stack variable OK */
80 sync->hw.init = &init;
81
82 clk = clk_register(NULL, &sync->hw);
83 if (IS_ERR(clk))
84 kfree(sync);
85
86 return clk;
87}
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
new file mode 100644
index 000000000000..4d75b1f37e3a
--- /dev/null
+++ b/drivers/clk/tegra/clk-divider.c
@@ -0,0 +1,187 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/slab.h>
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23
24#include "clk.h"
25
26#define pll_out_override(p) (BIT((p->shift - 6)))
27#define div_mask(d) ((1 << (d->width)) - 1)
28#define get_mul(d) (1 << d->frac_width)
29#define get_max_div(d) div_mask(d)
30
31#define PERIPH_CLK_UART_DIV_ENB BIT(24)
32
33static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
34 unsigned long parent_rate)
35{
36 s64 divider_ux1 = parent_rate;
37 u8 flags = divider->flags;
38 int mul;
39
40 if (!rate)
41 return 0;
42
43 mul = get_mul(divider);
44
45 if (!(flags & TEGRA_DIVIDER_INT))
46 divider_ux1 *= mul;
47
48 if (flags & TEGRA_DIVIDER_ROUND_UP)
49 divider_ux1 += rate - 1;
50
51 do_div(divider_ux1, rate);
52
53 if (flags & TEGRA_DIVIDER_INT)
54 divider_ux1 *= mul;
55
56 divider_ux1 -= mul;
57
58 if (divider_ux1 < 0)
59 return 0;
60
61 if (divider_ux1 > get_max_div(divider))
62 return -EINVAL;
63
64 return divider_ux1;
65}
66
67static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
68 unsigned long parent_rate)
69{
70 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
71 u32 reg;
72 int div, mul;
73 u64 rate = parent_rate;
74
75 reg = readl_relaxed(divider->reg) >> divider->shift;
76 div = reg & div_mask(divider);
77
78 mul = get_mul(divider);
79 div += mul;
80
81 rate *= mul;
82 rate += div - 1;
83 do_div(rate, div);
84
85 return rate;
86}
87
88static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
89 unsigned long *prate)
90{
91 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
92 int div, mul;
93 unsigned long output_rate = *prate;
94
95 if (!rate)
96 return output_rate;
97
98 div = get_div(divider, rate, output_rate);
99 if (div < 0)
100 return *prate;
101
102 mul = get_mul(divider);
103
104 return DIV_ROUND_UP(output_rate * mul, div + mul);
105}
106
107static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
108 unsigned long parent_rate)
109{
110 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
111 int div;
112 unsigned long flags = 0;
113 u32 val;
114
115 div = get_div(divider, rate, parent_rate);
116 if (div < 0)
117 return div;
118
119 if (divider->lock)
120 spin_lock_irqsave(divider->lock, flags);
121
122 val = readl_relaxed(divider->reg);
123 val &= ~(div_mask(divider) << divider->shift);
124 val |= div << divider->shift;
125
126 if (divider->flags & TEGRA_DIVIDER_UART) {
127 if (div)
128 val |= PERIPH_CLK_UART_DIV_ENB;
129 else
130 val &= ~PERIPH_CLK_UART_DIV_ENB;
131 }
132
133 if (divider->flags & TEGRA_DIVIDER_FIXED)
134 val |= pll_out_override(divider);
135
136 writel_relaxed(val, divider->reg);
137
138 if (divider->lock)
139 spin_unlock_irqrestore(divider->lock, flags);
140
141 return 0;
142}
143
144const struct clk_ops tegra_clk_frac_div_ops = {
145 .recalc_rate = clk_frac_div_recalc_rate,
146 .set_rate = clk_frac_div_set_rate,
147 .round_rate = clk_frac_div_round_rate,
148};
149
150struct clk *tegra_clk_register_divider(const char *name,
151 const char *parent_name, void __iomem *reg,
152 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
153 u8 frac_width, spinlock_t *lock)
154{
155 struct tegra_clk_frac_div *divider;
156 struct clk *clk;
157 struct clk_init_data init;
158
159 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
160 if (!divider) {
161 pr_err("%s: could not allocate fractional divider clk\n",
162 __func__);
163 return ERR_PTR(-ENOMEM);
164 }
165
166 init.name = name;
167 init.ops = &tegra_clk_frac_div_ops;
168 init.flags = flags;
169 init.parent_names = parent_name ? &parent_name : NULL;
170 init.num_parents = parent_name ? 1 : 0;
171
172 divider->reg = reg;
173 divider->shift = shift;
174 divider->width = width;
175 divider->frac_width = frac_width;
176 divider->lock = lock;
177 divider->flags = clk_divider_flags;
178
179 /* Data in .init is copied by clk_register(), so stack variable OK */
180 divider->hw.init = &init;
181
182 clk = clk_register(NULL, &divider->hw);
183 if (IS_ERR(clk))
184 kfree(divider);
185
186 return clk;
187}
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
new file mode 100644
index 000000000000..6dd533251e7b
--- /dev/null
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -0,0 +1,179 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/io.h>
21#include <linux/delay.h>
22#include <linux/err.h>
23#include <linux/tegra-soc.h>
24
25#include "clk.h"
26
27static DEFINE_SPINLOCK(periph_ref_lock);
28
29/* Macros to assist peripheral gate clock */
30#define read_enb(gate) \
31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
32#define write_enb_set(val, gate) \
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
34#define write_enb_clr(val, gate) \
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
36
37#define read_rst(gate) \
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
39#define write_rst_set(val, gate) \
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
41#define write_rst_clr(val, gate) \
42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
43
44#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
45
46/* Peripheral gate clock ops */
47static int clk_periph_is_enabled(struct clk_hw *hw)
48{
49 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
50 int state = 1;
51
52 if (!(read_enb(gate) & periph_clk_to_bit(gate)))
53 state = 0;
54
55 if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
56 if (read_rst(gate) & periph_clk_to_bit(gate))
57 state = 0;
58
59 return state;
60}
61
62static int clk_periph_enable(struct clk_hw *hw)
63{
64 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
65 unsigned long flags = 0;
66
67 spin_lock_irqsave(&periph_ref_lock, flags);
68
69 gate->enable_refcnt[gate->clk_num]++;
70 if (gate->enable_refcnt[gate->clk_num] > 1) {
71 spin_unlock_irqrestore(&periph_ref_lock, flags);
72 return 0;
73 }
74
75 write_enb_set(periph_clk_to_bit(gate), gate);
76 udelay(2);
77
78 if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
79 !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
80 if (read_rst(gate) & periph_clk_to_bit(gate)) {
81 udelay(5); /* reset propogation delay */
82 write_rst_clr(periph_clk_to_bit(gate), gate);
83 }
84 }
85
86 spin_unlock_irqrestore(&periph_ref_lock, flags);
87
88 return 0;
89}
90
91static void clk_periph_disable(struct clk_hw *hw)
92{
93 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
94 unsigned long flags = 0;
95
96 spin_lock_irqsave(&periph_ref_lock, flags);
97
98 gate->enable_refcnt[gate->clk_num]--;
99 if (gate->enable_refcnt[gate->clk_num] > 0) {
100 spin_unlock_irqrestore(&periph_ref_lock, flags);
101 return;
102 }
103
104 /*
105 * If peripheral is in the APB bus then read the APB bus to
106 * flush the write operation in apb bus. This will avoid the
107 * peripheral access after disabling clock
108 */
109 if (gate->flags & TEGRA_PERIPH_ON_APB)
110 tegra_read_chipid();
111
112 write_enb_clr(periph_clk_to_bit(gate), gate);
113
114 spin_unlock_irqrestore(&periph_ref_lock, flags);
115}
116
117void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
118{
119 if (gate->flags & TEGRA_PERIPH_NO_RESET)
120 return;
121
122 if (assert) {
123 /*
124 * If peripheral is in the APB bus then read the APB bus to
125 * flush the write operation in apb bus. This will avoid the
126 * peripheral access after disabling clock
127 */
128 if (gate->flags & TEGRA_PERIPH_ON_APB)
129 tegra_read_chipid();
130
131 write_rst_set(periph_clk_to_bit(gate), gate);
132 } else {
133 write_rst_clr(periph_clk_to_bit(gate), gate);
134 }
135}
136
137const struct clk_ops tegra_clk_periph_gate_ops = {
138 .is_enabled = clk_periph_is_enabled,
139 .enable = clk_periph_enable,
140 .disable = clk_periph_disable,
141};
142
143struct clk *tegra_clk_register_periph_gate(const char *name,
144 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
145 unsigned long flags, int clk_num,
146 struct tegra_clk_periph_regs *pregs, int *enable_refcnt)
147{
148 struct tegra_clk_periph_gate *gate;
149 struct clk *clk;
150 struct clk_init_data init;
151
152 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
153 if (!gate) {
154 pr_err("%s: could not allocate periph gate clk\n", __func__);
155 return ERR_PTR(-ENOMEM);
156 }
157
158 init.name = name;
159 init.flags = flags;
160 init.parent_names = parent_name ? &parent_name : NULL;
161 init.num_parents = parent_name ? 1 : 0;
162 init.ops = &tegra_clk_periph_gate_ops;
163
164 gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
165 gate->clk_base = clk_base;
166 gate->clk_num = clk_num;
167 gate->flags = gate_flags;
168 gate->enable_refcnt = enable_refcnt;
169 gate->regs = pregs;
170
171 /* Data in .init is copied by clk_register(), so stack variable OK */
172 gate->hw.init = &init;
173
174 clk = clk_register(NULL, &gate->hw);
175 if (IS_ERR(clk))
176 kfree(gate);
177
178 return clk;
179}
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
new file mode 100644
index 000000000000..788486e6331a
--- /dev/null
+++ b/drivers/clk/tegra/clk-periph.c
@@ -0,0 +1,218 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21
22#include "clk.h"
23
24static u8 clk_periph_get_parent(struct clk_hw *hw)
25{
26 struct tegra_clk_periph *periph = to_clk_periph(hw);
27 const struct clk_ops *mux_ops = periph->mux_ops;
28 struct clk_hw *mux_hw = &periph->mux.hw;
29
30 mux_hw->clk = hw->clk;
31
32 return mux_ops->get_parent(mux_hw);
33}
34
35static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
36{
37 struct tegra_clk_periph *periph = to_clk_periph(hw);
38 const struct clk_ops *mux_ops = periph->mux_ops;
39 struct clk_hw *mux_hw = &periph->mux.hw;
40
41 mux_hw->clk = hw->clk;
42
43 return mux_ops->set_parent(mux_hw, index);
44}
45
46static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
47 unsigned long parent_rate)
48{
49 struct tegra_clk_periph *periph = to_clk_periph(hw);
50 const struct clk_ops *div_ops = periph->div_ops;
51 struct clk_hw *div_hw = &periph->divider.hw;
52
53 div_hw->clk = hw->clk;
54
55 return div_ops->recalc_rate(div_hw, parent_rate);
56}
57
58static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long *prate)
60{
61 struct tegra_clk_periph *periph = to_clk_periph(hw);
62 const struct clk_ops *div_ops = periph->div_ops;
63 struct clk_hw *div_hw = &periph->divider.hw;
64
65 div_hw->clk = hw->clk;
66
67 return div_ops->round_rate(div_hw, rate, prate);
68}
69
70static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate,
71 unsigned long parent_rate)
72{
73 struct tegra_clk_periph *periph = to_clk_periph(hw);
74 const struct clk_ops *div_ops = periph->div_ops;
75 struct clk_hw *div_hw = &periph->divider.hw;
76
77 div_hw->clk = hw->clk;
78
79 return div_ops->set_rate(div_hw, rate, parent_rate);
80}
81
82static int clk_periph_is_enabled(struct clk_hw *hw)
83{
84 struct tegra_clk_periph *periph = to_clk_periph(hw);
85 const struct clk_ops *gate_ops = periph->gate_ops;
86 struct clk_hw *gate_hw = &periph->gate.hw;
87
88 gate_hw->clk = hw->clk;
89
90 return gate_ops->is_enabled(gate_hw);
91}
92
93static int clk_periph_enable(struct clk_hw *hw)
94{
95 struct tegra_clk_periph *periph = to_clk_periph(hw);
96 const struct clk_ops *gate_ops = periph->gate_ops;
97 struct clk_hw *gate_hw = &periph->gate.hw;
98
99 gate_hw->clk = hw->clk;
100
101 return gate_ops->enable(gate_hw);
102}
103
104static void clk_periph_disable(struct clk_hw *hw)
105{
106 struct tegra_clk_periph *periph = to_clk_periph(hw);
107 const struct clk_ops *gate_ops = periph->gate_ops;
108 struct clk_hw *gate_hw = &periph->gate.hw;
109
110 gate_ops->disable(gate_hw);
111}
112
113void tegra_periph_reset_deassert(struct clk *c)
114{
115 struct clk_hw *hw = __clk_get_hw(c);
116 struct tegra_clk_periph *periph = to_clk_periph(hw);
117 struct tegra_clk_periph_gate *gate;
118
119 if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
120 gate = to_clk_periph_gate(hw);
121 if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
122 WARN_ON(1);
123 return;
124 }
125 } else {
126 gate = &periph->gate;
127 }
128
129 tegra_periph_reset(gate, 0);
130}
131
132void tegra_periph_reset_assert(struct clk *c)
133{
134 struct clk_hw *hw = __clk_get_hw(c);
135 struct tegra_clk_periph *periph = to_clk_periph(hw);
136 struct tegra_clk_periph_gate *gate;
137
138 if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
139 gate = to_clk_periph_gate(hw);
140 if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
141 WARN_ON(1);
142 return;
143 }
144 } else {
145 gate = &periph->gate;
146 }
147
148 tegra_periph_reset(gate, 1);
149}
150
151const struct clk_ops tegra_clk_periph_ops = {
152 .get_parent = clk_periph_get_parent,
153 .set_parent = clk_periph_set_parent,
154 .recalc_rate = clk_periph_recalc_rate,
155 .round_rate = clk_periph_round_rate,
156 .set_rate = clk_periph_set_rate,
157 .is_enabled = clk_periph_is_enabled,
158 .enable = clk_periph_enable,
159 .disable = clk_periph_disable,
160};
161
162const struct clk_ops tegra_clk_periph_nodiv_ops = {
163 .get_parent = clk_periph_get_parent,
164 .set_parent = clk_periph_set_parent,
165 .is_enabled = clk_periph_is_enabled,
166 .enable = clk_periph_enable,
167 .disable = clk_periph_disable,
168};
169
170static struct clk *_tegra_clk_register_periph(const char *name,
171 const char **parent_names, int num_parents,
172 struct tegra_clk_periph *periph,
173 void __iomem *clk_base, u32 offset, bool div)
174{
175 struct clk *clk;
176 struct clk_init_data init;
177
178 init.name = name;
179 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
180 init.flags = div ? 0 : CLK_SET_RATE_PARENT;
181 init.parent_names = parent_names;
182 init.num_parents = num_parents;
183
184 /* Data in .init is copied by clk_register(), so stack variable OK */
185 periph->hw.init = &init;
186 periph->magic = TEGRA_CLK_PERIPH_MAGIC;
187 periph->mux.reg = clk_base + offset;
188 periph->divider.reg = div ? (clk_base + offset) : NULL;
189 periph->gate.clk_base = clk_base;
190
191 clk = clk_register(NULL, &periph->hw);
192 if (IS_ERR(clk))
193 return clk;
194
195 periph->mux.hw.clk = clk;
196 periph->divider.hw.clk = div ? clk : NULL;
197 periph->gate.hw.clk = clk;
198
199 return clk;
200}
201
202struct clk *tegra_clk_register_periph(const char *name,
203 const char **parent_names, int num_parents,
204 struct tegra_clk_periph *periph, void __iomem *clk_base,
205 u32 offset)
206{
207 return _tegra_clk_register_periph(name, parent_names, num_parents,
208 periph, clk_base, offset, true);
209}
210
211struct clk *tegra_clk_register_periph_nodiv(const char *name,
212 const char **parent_names, int num_parents,
213 struct tegra_clk_periph *periph, void __iomem *clk_base,
214 u32 offset)
215{
216 return _tegra_clk_register_periph(name, parent_names, num_parents,
217 periph, clk_base, offset, false);
218}
diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c
new file mode 100644
index 000000000000..3598987a451d
--- /dev/null
+++ b/drivers/clk/tegra/clk-pll-out.c
@@ -0,0 +1,123 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/clk-provider.h>
23#include <linux/clk.h>
24
25#include "clk.h"
26
27#define pll_out_enb(p) (BIT(p->enb_bit_idx))
28#define pll_out_rst(p) (BIT(p->rst_bit_idx))
29
30static int clk_pll_out_is_enabled(struct clk_hw *hw)
31{
32 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
33 u32 val = readl_relaxed(pll_out->reg);
34 int state;
35
36 state = (val & pll_out_enb(pll_out)) ? 1 : 0;
37 if (!(val & (pll_out_rst(pll_out))))
38 state = 0;
39 return state;
40}
41
42static int clk_pll_out_enable(struct clk_hw *hw)
43{
44 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
45 unsigned long flags = 0;
46 u32 val;
47
48 if (pll_out->lock)
49 spin_lock_irqsave(pll_out->lock, flags);
50
51 val = readl_relaxed(pll_out->reg);
52
53 val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
54
55 writel_relaxed(val, pll_out->reg);
56 udelay(2);
57
58 if (pll_out->lock)
59 spin_unlock_irqrestore(pll_out->lock, flags);
60
61 return 0;
62}
63
64static void clk_pll_out_disable(struct clk_hw *hw)
65{
66 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
67 unsigned long flags = 0;
68 u32 val;
69
70 if (pll_out->lock)
71 spin_lock_irqsave(pll_out->lock, flags);
72
73 val = readl_relaxed(pll_out->reg);
74
75 val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
76
77 writel_relaxed(val, pll_out->reg);
78 udelay(2);
79
80 if (pll_out->lock)
81 spin_unlock_irqrestore(pll_out->lock, flags);
82}
83
84const struct clk_ops tegra_clk_pll_out_ops = {
85 .is_enabled = clk_pll_out_is_enabled,
86 .enable = clk_pll_out_enable,
87 .disable = clk_pll_out_disable,
88};
89
90struct clk *tegra_clk_register_pll_out(const char *name,
91 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
92 u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
93 spinlock_t *lock)
94{
95 struct tegra_clk_pll_out *pll_out;
96 struct clk *clk;
97 struct clk_init_data init;
98
99 pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
100 if (!pll_out)
101 return ERR_PTR(-ENOMEM);
102
103 init.name = name;
104 init.ops = &tegra_clk_pll_out_ops;
105 init.parent_names = (parent_name ? &parent_name : NULL);
106 init.num_parents = (parent_name ? 1 : 0);
107 init.flags = flags;
108
109 pll_out->reg = reg;
110 pll_out->enb_bit_idx = enb_bit_idx;
111 pll_out->rst_bit_idx = rst_bit_idx;
112 pll_out->flags = pll_out_flags;
113 pll_out->lock = lock;
114
115 /* Data in .init is copied by clk_register(), so stack variable OK */
116 pll_out->hw.init = &init;
117
118 clk = clk_register(NULL, &pll_out->hw);
119 if (IS_ERR(clk))
120 kfree(pll_out);
121
122 return clk;
123}
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
new file mode 100644
index 000000000000..165f24734c1b
--- /dev/null
+++ b/drivers/clk/tegra/clk-pll.c
@@ -0,0 +1,648 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/slab.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23
24#include "clk.h"
25
26#define PLL_BASE_BYPASS BIT(31)
27#define PLL_BASE_ENABLE BIT(30)
28#define PLL_BASE_REF_ENABLE BIT(29)
29#define PLL_BASE_OVERRIDE BIT(28)
30
31#define PLL_BASE_DIVP_SHIFT 20
32#define PLL_BASE_DIVP_WIDTH 3
33#define PLL_BASE_DIVN_SHIFT 8
34#define PLL_BASE_DIVN_WIDTH 10
35#define PLL_BASE_DIVM_SHIFT 0
36#define PLL_BASE_DIVM_WIDTH 5
37#define PLLU_POST_DIVP_MASK 0x1
38
39#define PLL_MISC_DCCON_SHIFT 20
40#define PLL_MISC_CPCON_SHIFT 8
41#define PLL_MISC_CPCON_WIDTH 4
42#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43#define PLL_MISC_LFCON_SHIFT 4
44#define PLL_MISC_LFCON_WIDTH 4
45#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46#define PLL_MISC_VCOCON_SHIFT 0
47#define PLL_MISC_VCOCON_WIDTH 4
48#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
49
50#define OUT_OF_TABLE_CPCON 8
51
52#define PMC_PLLP_WB0_OVERRIDE 0xf8
53#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
55
56#define PLL_POST_LOCK_DELAY 50
57
58#define PLLDU_LFCON_SET_DIVN 600
59
60#define PLLE_BASE_DIVCML_SHIFT 24
61#define PLLE_BASE_DIVCML_WIDTH 4
62#define PLLE_BASE_DIVP_SHIFT 16
63#define PLLE_BASE_DIVP_WIDTH 7
64#define PLLE_BASE_DIVN_SHIFT 8
65#define PLLE_BASE_DIVN_WIDTH 8
66#define PLLE_BASE_DIVM_SHIFT 0
67#define PLLE_BASE_DIVM_WIDTH 8
68
69#define PLLE_MISC_SETUP_BASE_SHIFT 16
70#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71#define PLLE_MISC_LOCK_ENABLE BIT(9)
72#define PLLE_MISC_READY BIT(15)
73#define PLLE_MISC_SETUP_EX_SHIFT 2
74#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78
79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_DISABLE (7 << 10)
81
82#define PMC_SATA_PWRGT 0x1ac
83#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
84#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
85
86#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
87#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
88#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
89
90#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
91#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
92#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
93
94#define mask(w) ((1 << (w)) - 1)
95#define divm_mask(p) mask(p->divm_width)
96#define divn_mask(p) mask(p->divn_width)
97#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \
98 mask(p->divp_width))
99
100#define divm_max(p) (divm_mask(p))
101#define divn_max(p) (divn_mask(p))
102#define divp_max(p) (1 << (divp_mask(p)))
103
104static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
105{
106 u32 val;
107
108 if (!(pll->flags & TEGRA_PLL_USE_LOCK))
109 return;
110
111 val = pll_readl_misc(pll);
112 val |= BIT(pll->params->lock_enable_bit_idx);
113 pll_writel_misc(val, pll);
114}
115
116static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
117 void __iomem *lock_addr, u32 lock_bit_idx)
118{
119 int i;
120 u32 val;
121
122 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
123 udelay(pll->params->lock_delay);
124 return 0;
125 }
126
127 for (i = 0; i < pll->params->lock_delay; i++) {
128 val = readl_relaxed(lock_addr);
129 if (val & BIT(lock_bit_idx)) {
130 udelay(PLL_POST_LOCK_DELAY);
131 return 0;
132 }
133 udelay(2); /* timeout = 2 * lock time */
134 }
135
136 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
137 __clk_get_name(pll->hw.clk));
138
139 return -1;
140}
141
142static int clk_pll_is_enabled(struct clk_hw *hw)
143{
144 struct tegra_clk_pll *pll = to_clk_pll(hw);
145 u32 val;
146
147 if (pll->flags & TEGRA_PLLM) {
148 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
149 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
150 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
151 }
152
153 val = pll_readl_base(pll);
154
155 return val & PLL_BASE_ENABLE ? 1 : 0;
156}
157
158static int _clk_pll_enable(struct clk_hw *hw)
159{
160 struct tegra_clk_pll *pll = to_clk_pll(hw);
161 u32 val;
162
163 clk_pll_enable_lock(pll);
164
165 val = pll_readl_base(pll);
166 val &= ~PLL_BASE_BYPASS;
167 val |= PLL_BASE_ENABLE;
168 pll_writel_base(val, pll);
169
170 if (pll->flags & TEGRA_PLLM) {
171 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
172 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
173 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
174 }
175
176 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
177 pll->params->lock_bit_idx);
178
179 return 0;
180}
181
182static void _clk_pll_disable(struct clk_hw *hw)
183{
184 struct tegra_clk_pll *pll = to_clk_pll(hw);
185 u32 val;
186
187 val = pll_readl_base(pll);
188 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
189 pll_writel_base(val, pll);
190
191 if (pll->flags & TEGRA_PLLM) {
192 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
193 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
194 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
195 }
196}
197
198static int clk_pll_enable(struct clk_hw *hw)
199{
200 struct tegra_clk_pll *pll = to_clk_pll(hw);
201 unsigned long flags = 0;
202 int ret;
203
204 if (pll->lock)
205 spin_lock_irqsave(pll->lock, flags);
206
207 ret = _clk_pll_enable(hw);
208
209 if (pll->lock)
210 spin_unlock_irqrestore(pll->lock, flags);
211
212 return ret;
213}
214
215static void clk_pll_disable(struct clk_hw *hw)
216{
217 struct tegra_clk_pll *pll = to_clk_pll(hw);
218 unsigned long flags = 0;
219
220 if (pll->lock)
221 spin_lock_irqsave(pll->lock, flags);
222
223 _clk_pll_disable(hw);
224
225 if (pll->lock)
226 spin_unlock_irqrestore(pll->lock, flags);
227}
228
229static int _get_table_rate(struct clk_hw *hw,
230 struct tegra_clk_pll_freq_table *cfg,
231 unsigned long rate, unsigned long parent_rate)
232{
233 struct tegra_clk_pll *pll = to_clk_pll(hw);
234 struct tegra_clk_pll_freq_table *sel;
235
236 for (sel = pll->freq_table; sel->input_rate != 0; sel++)
237 if (sel->input_rate == parent_rate &&
238 sel->output_rate == rate)
239 break;
240
241 if (sel->input_rate == 0)
242 return -EINVAL;
243
244 BUG_ON(sel->p < 1);
245
246 cfg->input_rate = sel->input_rate;
247 cfg->output_rate = sel->output_rate;
248 cfg->m = sel->m;
249 cfg->n = sel->n;
250 cfg->p = sel->p;
251 cfg->cpcon = sel->cpcon;
252
253 return 0;
254}
255
256static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
257 unsigned long rate, unsigned long parent_rate)
258{
259 struct tegra_clk_pll *pll = to_clk_pll(hw);
260 unsigned long cfreq;
261 u32 p_div = 0;
262
263 switch (parent_rate) {
264 case 12000000:
265 case 26000000:
266 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
267 break;
268 case 13000000:
269 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
270 break;
271 case 16800000:
272 case 19200000:
273 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
274 break;
275 case 9600000:
276 case 28800000:
277 /*
278 * PLL_P_OUT1 rate is not listed in PLLA table
279 */
280 cfreq = parent_rate/(parent_rate/1000000);
281 break;
282 default:
283 pr_err("%s Unexpected reference rate %lu\n",
284 __func__, parent_rate);
285 BUG();
286 }
287
288 /* Raise VCO to guarantee 0.5% accuracy */
289 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
290 cfg->output_rate <<= 1)
291 p_div++;
292
293 cfg->p = 1 << p_div;
294 cfg->m = parent_rate / cfreq;
295 cfg->n = cfg->output_rate / cfreq;
296 cfg->cpcon = OUT_OF_TABLE_CPCON;
297
298 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
299 cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
300 pr_err("%s: Failed to set %s rate %lu\n",
301 __func__, __clk_get_name(hw->clk), rate);
302 return -EINVAL;
303 }
304
305 return 0;
306}
307
308static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
309 unsigned long rate)
310{
311 struct tegra_clk_pll *pll = to_clk_pll(hw);
312 unsigned long flags = 0;
313 u32 divp, val, old_base;
314 int state;
315
316 divp = __ffs(cfg->p);
317
318 if (pll->flags & TEGRA_PLLU)
319 divp ^= 1;
320
321 if (pll->lock)
322 spin_lock_irqsave(pll->lock, flags);
323
324 old_base = val = pll_readl_base(pll);
325 val &= ~((divm_mask(pll) << pll->divm_shift) |
326 (divn_mask(pll) << pll->divn_shift) |
327 (divp_mask(pll) << pll->divp_shift));
328 val |= ((cfg->m << pll->divm_shift) |
329 (cfg->n << pll->divn_shift) |
330 (divp << pll->divp_shift));
331 if (val == old_base) {
332 if (pll->lock)
333 spin_unlock_irqrestore(pll->lock, flags);
334 return 0;
335 }
336
337 state = clk_pll_is_enabled(hw);
338
339 if (state) {
340 _clk_pll_disable(hw);
341 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
342 }
343 pll_writel_base(val, pll);
344
345 if (pll->flags & TEGRA_PLL_HAS_CPCON) {
346 val = pll_readl_misc(pll);
347 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
348 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
349 if (pll->flags & TEGRA_PLL_SET_LFCON) {
350 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
351 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
352 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
353 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
354 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
355 if (rate >= (pll->params->vco_max >> 1))
356 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
357 }
358 pll_writel_misc(val, pll);
359 }
360
361 if (pll->lock)
362 spin_unlock_irqrestore(pll->lock, flags);
363
364 if (state)
365 clk_pll_enable(hw);
366
367 return 0;
368}
369
370static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate)
372{
373 struct tegra_clk_pll *pll = to_clk_pll(hw);
374 struct tegra_clk_pll_freq_table cfg;
375
376 if (pll->flags & TEGRA_PLL_FIXED) {
377 if (rate != pll->fixed_rate) {
378 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
379 __func__, __clk_get_name(hw->clk),
380 pll->fixed_rate, rate);
381 return -EINVAL;
382 }
383 return 0;
384 }
385
386 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
387 _calc_rate(hw, &cfg, rate, parent_rate))
388 return -EINVAL;
389
390 return _program_pll(hw, &cfg, rate);
391}
392
393static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
394 unsigned long *prate)
395{
396 struct tegra_clk_pll *pll = to_clk_pll(hw);
397 struct tegra_clk_pll_freq_table cfg;
398 u64 output_rate = *prate;
399
400 if (pll->flags & TEGRA_PLL_FIXED)
401 return pll->fixed_rate;
402
403 /* PLLM is used for memory; we do not change rate */
404 if (pll->flags & TEGRA_PLLM)
405 return __clk_get_rate(hw->clk);
406
407 if (_get_table_rate(hw, &cfg, rate, *prate) &&
408 _calc_rate(hw, &cfg, rate, *prate))
409 return -EINVAL;
410
411 output_rate *= cfg.n;
412 do_div(output_rate, cfg.m * cfg.p);
413
414 return output_rate;
415}
416
417static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
418 unsigned long parent_rate)
419{
420 struct tegra_clk_pll *pll = to_clk_pll(hw);
421 u32 val = pll_readl_base(pll);
422 u32 divn = 0, divm = 0, divp = 0;
423 u64 rate = parent_rate;
424
425 if (val & PLL_BASE_BYPASS)
426 return parent_rate;
427
428 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
429 struct tegra_clk_pll_freq_table sel;
430 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
431 pr_err("Clock %s has unknown fixed frequency\n",
432 __clk_get_name(hw->clk));
433 BUG();
434 }
435 return pll->fixed_rate;
436 }
437
438 divp = (val >> pll->divp_shift) & (divp_mask(pll));
439 if (pll->flags & TEGRA_PLLU)
440 divp ^= 1;
441
442 divn = (val >> pll->divn_shift) & (divn_mask(pll));
443 divm = (val >> pll->divm_shift) & (divm_mask(pll));
444 divm *= (1 << divp);
445
446 rate *= divn;
447 do_div(rate, divm);
448 return rate;
449}
450
451static int clk_plle_training(struct tegra_clk_pll *pll)
452{
453 u32 val;
454 unsigned long timeout;
455
456 if (!pll->pmc)
457 return -ENOSYS;
458
459 /*
460 * PLLE is already disabled, and setup cleared;
461 * create falling edge on PLLE IDDQ input.
462 */
463 val = readl(pll->pmc + PMC_SATA_PWRGT);
464 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
465 writel(val, pll->pmc + PMC_SATA_PWRGT);
466
467 val = readl(pll->pmc + PMC_SATA_PWRGT);
468 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
469 writel(val, pll->pmc + PMC_SATA_PWRGT);
470
471 val = readl(pll->pmc + PMC_SATA_PWRGT);
472 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
473 writel(val, pll->pmc + PMC_SATA_PWRGT);
474
475 val = pll_readl_misc(pll);
476
477 timeout = jiffies + msecs_to_jiffies(100);
478 while (1) {
479 val = pll_readl_misc(pll);
480 if (val & PLLE_MISC_READY)
481 break;
482 if (time_after(jiffies, timeout)) {
483 pr_err("%s: timeout waiting for PLLE\n", __func__);
484 return -EBUSY;
485 }
486 udelay(300);
487 }
488
489 return 0;
490}
491
492static int clk_plle_enable(struct clk_hw *hw)
493{
494 struct tegra_clk_pll *pll = to_clk_pll(hw);
495 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
496 struct tegra_clk_pll_freq_table sel;
497 u32 val;
498 int err;
499
500 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
501 return -EINVAL;
502
503 clk_pll_disable(hw);
504
505 val = pll_readl_misc(pll);
506 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
507 pll_writel_misc(val, pll);
508
509 val = pll_readl_misc(pll);
510 if (!(val & PLLE_MISC_READY)) {
511 err = clk_plle_training(pll);
512 if (err)
513 return err;
514 }
515
516 if (pll->flags & TEGRA_PLLE_CONFIGURE) {
517 /* configure dividers */
518 val = pll_readl_base(pll);
519 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
520 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
521 val |= sel.m << pll->divm_shift;
522 val |= sel.n << pll->divn_shift;
523 val |= sel.p << pll->divp_shift;
524 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
525 pll_writel_base(val, pll);
526 }
527
528 val = pll_readl_misc(pll);
529 val |= PLLE_MISC_SETUP_VALUE;
530 val |= PLLE_MISC_LOCK_ENABLE;
531 pll_writel_misc(val, pll);
532
533 val = readl(pll->clk_base + PLLE_SS_CTRL);
534 val |= PLLE_SS_DISABLE;
535 writel(val, pll->clk_base + PLLE_SS_CTRL);
536
537 val |= pll_readl_base(pll);
538 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
539 pll_writel_base(val, pll);
540
541 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
542 pll->params->lock_bit_idx);
543 return 0;
544}
545
546static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
547 unsigned long parent_rate)
548{
549 struct tegra_clk_pll *pll = to_clk_pll(hw);
550 u32 val = pll_readl_base(pll);
551 u32 divn = 0, divm = 0, divp = 0;
552 u64 rate = parent_rate;
553
554 divp = (val >> pll->divp_shift) & (divp_mask(pll));
555 divn = (val >> pll->divn_shift) & (divn_mask(pll));
556 divm = (val >> pll->divm_shift) & (divm_mask(pll));
557 divm *= divp;
558
559 rate *= divn;
560 do_div(rate, divm);
561 return rate;
562}
563
564const struct clk_ops tegra_clk_pll_ops = {
565 .is_enabled = clk_pll_is_enabled,
566 .enable = clk_pll_enable,
567 .disable = clk_pll_disable,
568 .recalc_rate = clk_pll_recalc_rate,
569 .round_rate = clk_pll_round_rate,
570 .set_rate = clk_pll_set_rate,
571};
572
573const struct clk_ops tegra_clk_plle_ops = {
574 .recalc_rate = clk_plle_recalc_rate,
575 .is_enabled = clk_pll_is_enabled,
576 .disable = clk_pll_disable,
577 .enable = clk_plle_enable,
578};
579
580static struct clk *_tegra_clk_register_pll(const char *name,
581 const char *parent_name, void __iomem *clk_base,
582 void __iomem *pmc, unsigned long flags,
583 unsigned long fixed_rate,
584 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
585 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock,
586 const struct clk_ops *ops)
587{
588 struct tegra_clk_pll *pll;
589 struct clk *clk;
590 struct clk_init_data init;
591
592 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
593 if (!pll)
594 return ERR_PTR(-ENOMEM);
595
596 init.name = name;
597 init.ops = ops;
598 init.flags = flags;
599 init.parent_names = (parent_name ? &parent_name : NULL);
600 init.num_parents = (parent_name ? 1 : 0);
601
602 pll->clk_base = clk_base;
603 pll->pmc = pmc;
604
605 pll->freq_table = freq_table;
606 pll->params = pll_params;
607 pll->fixed_rate = fixed_rate;
608 pll->flags = pll_flags;
609 pll->lock = lock;
610
611 pll->divp_shift = PLL_BASE_DIVP_SHIFT;
612 pll->divp_width = PLL_BASE_DIVP_WIDTH;
613 pll->divn_shift = PLL_BASE_DIVN_SHIFT;
614 pll->divn_width = PLL_BASE_DIVN_WIDTH;
615 pll->divm_shift = PLL_BASE_DIVM_SHIFT;
616 pll->divm_width = PLL_BASE_DIVM_WIDTH;
617
618 /* Data in .init is copied by clk_register(), so stack variable OK */
619 pll->hw.init = &init;
620
621 clk = clk_register(NULL, &pll->hw);
622 if (IS_ERR(clk))
623 kfree(pll);
624
625 return clk;
626}
627
628struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
629 void __iomem *clk_base, void __iomem *pmc,
630 unsigned long flags, unsigned long fixed_rate,
631 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
632 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
633{
634 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
635 flags, fixed_rate, pll_params, pll_flags, freq_table,
636 lock, &tegra_clk_pll_ops);
637}
638
639struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
640 void __iomem *clk_base, void __iomem *pmc,
641 unsigned long flags, unsigned long fixed_rate,
642 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
643 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
644{
645 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
646 flags, fixed_rate, pll_params, pll_flags, freq_table,
647 lock, &tegra_clk_plle_ops);
648}
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
new file mode 100644
index 000000000000..7ad48a832334
--- /dev/null
+++ b/drivers/clk/tegra/clk-super.c
@@ -0,0 +1,154 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/slab.h>
22#include <linux/clk-provider.h>
23#include <linux/clk.h>
24
25#include "clk.h"
26
27#define SUPER_STATE_IDLE 0
28#define SUPER_STATE_RUN 1
29#define SUPER_STATE_IRQ 2
30#define SUPER_STATE_FIQ 3
31
32#define SUPER_STATE_SHIFT 28
33#define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \
34 BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ)) \
35 << SUPER_STATE_SHIFT)
36
37#define SUPER_LP_DIV2_BYPASS (1 << 16)
38
39#define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
40#define super_state_to_src_shift(m, s) ((m->width * s))
41#define super_state_to_src_mask(m) (((1 << m->width) - 1))
42
43static u8 clk_super_get_parent(struct clk_hw *hw)
44{
45 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
46 u32 val, state;
47 u8 source, shift;
48
49 val = readl_relaxed(mux->reg);
50
51 state = val & SUPER_STATE_MASK;
52
53 BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
54 (state != super_state(SUPER_STATE_IDLE)));
55 shift = (state == super_state(SUPER_STATE_IDLE)) ?
56 super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
57 super_state_to_src_shift(mux, SUPER_STATE_RUN);
58
59 source = (val >> shift) & super_state_to_src_mask(mux);
60
61 /*
62 * If LP_DIV2_BYPASS is not set and PLLX is current parent then
63 * PLLX/2 is the input source to CCLKLP.
64 */
65 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
66 (source == mux->pllx_index))
67 source = mux->div2_index;
68
69 return source;
70}
71
72static int clk_super_set_parent(struct clk_hw *hw, u8 index)
73{
74 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
75 u32 val, state;
76 u8 parent_index, shift;
77
78 val = readl_relaxed(mux->reg);
79 state = val & SUPER_STATE_MASK;
80 BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
81 (state != super_state(SUPER_STATE_IDLE)));
82 shift = (state == super_state(SUPER_STATE_IDLE)) ?
83 super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
84 super_state_to_src_shift(mux, SUPER_STATE_RUN);
85
86 /*
87 * For LP mode super-clock switch between PLLX direct
88 * and divided-by-2 outputs is allowed only when other
89 * than PLLX clock source is current parent.
90 */
91 if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||
92 (index == mux->pllx_index))) {
93 parent_index = clk_super_get_parent(hw);
94 if ((parent_index == mux->div2_index) ||
95 (parent_index == mux->pllx_index))
96 return -EINVAL;
97
98 val ^= SUPER_LP_DIV2_BYPASS;
99 writel_relaxed(val, mux->reg);
100 udelay(2);
101
102 if (index == mux->div2_index)
103 index = mux->pllx_index;
104 }
105 val &= ~((super_state_to_src_mask(mux)) << shift);
106 val |= (index & (super_state_to_src_mask(mux))) << shift;
107
108 writel_relaxed(val, mux->reg);
109 udelay(2);
110 return 0;
111}
112
113const struct clk_ops tegra_clk_super_ops = {
114 .get_parent = clk_super_get_parent,
115 .set_parent = clk_super_set_parent,
116};
117
118struct clk *tegra_clk_register_super_mux(const char *name,
119 const char **parent_names, u8 num_parents,
120 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
121 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock)
122{
123 struct tegra_clk_super_mux *super;
124 struct clk *clk;
125 struct clk_init_data init;
126
127 super = kzalloc(sizeof(*super), GFP_KERNEL);
128 if (!super) {
129 pr_err("%s: could not allocate super clk\n", __func__);
130 return ERR_PTR(-ENOMEM);
131 }
132
133 init.name = name;
134 init.ops = &tegra_clk_super_ops;
135 init.flags = flags;
136 init.parent_names = parent_names;
137 init.num_parents = num_parents;
138
139 super->reg = reg;
140 super->pllx_index = pllx_index;
141 super->div2_index = div2_index;
142 super->lock = lock;
143 super->width = width;
144 super->flags = clk_super_flags;
145
146 /* Data in .init is copied by clk_register(), so stack variable OK */
147 super->hw.init = &init;
148
149 clk = clk_register(NULL, &super->hw);
150 if (IS_ERR(clk))
151 kfree(super);
152
153 return clk;
154}
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
new file mode 100644
index 000000000000..5d41569883a7
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -0,0 +1,1349 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/tegra.h>
24#include <linux/delay.h>
25
26#include "clk.h"
27
28#define RST_DEVICES_L 0x004
29#define RST_DEVICES_H 0x008
30#define RST_DEVICES_U 0x00c
31#define RST_DEVICES_SET_L 0x300
32#define RST_DEVICES_CLR_L 0x304
33#define RST_DEVICES_SET_H 0x308
34#define RST_DEVICES_CLR_H 0x30c
35#define RST_DEVICES_SET_U 0x310
36#define RST_DEVICES_CLR_U 0x314
37#define RST_DEVICES_NUM 3
38
39#define CLK_OUT_ENB_L 0x010
40#define CLK_OUT_ENB_H 0x014
41#define CLK_OUT_ENB_U 0x018
42#define CLK_OUT_ENB_SET_L 0x320
43#define CLK_OUT_ENB_CLR_L 0x324
44#define CLK_OUT_ENB_SET_H 0x328
45#define CLK_OUT_ENB_CLR_H 0x32c
46#define CLK_OUT_ENB_SET_U 0x330
47#define CLK_OUT_ENB_CLR_U 0x334
48#define CLK_OUT_ENB_NUM 3
49
50#define OSC_CTRL 0x50
51#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
52#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
53#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
54#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
55#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
56#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
57
58#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
59#define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
60#define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
61#define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
62
63#define OSC_FREQ_DET 0x58
64#define OSC_FREQ_DET_TRIG (1<<31)
65
66#define OSC_FREQ_DET_STATUS 0x5c
67#define OSC_FREQ_DET_BUSY (1<<31)
68#define OSC_FREQ_DET_CNT_MASK 0xFFFF
69
70#define PLLS_BASE 0xf0
71#define PLLS_MISC 0xf4
72#define PLLC_BASE 0x80
73#define PLLC_MISC 0x8c
74#define PLLM_BASE 0x90
75#define PLLM_MISC 0x9c
76#define PLLP_BASE 0xa0
77#define PLLP_MISC 0xac
78#define PLLA_BASE 0xb0
79#define PLLA_MISC 0xbc
80#define PLLU_BASE 0xc0
81#define PLLU_MISC 0xcc
82#define PLLD_BASE 0xd0
83#define PLLD_MISC 0xdc
84#define PLLX_BASE 0xe0
85#define PLLX_MISC 0xe4
86#define PLLE_BASE 0xe8
87#define PLLE_MISC 0xec
88
89#define PLL_BASE_LOCK 27
90#define PLLE_MISC_LOCK 11
91
92#define PLL_MISC_LOCK_ENABLE 18
93#define PLLDU_MISC_LOCK_ENABLE 22
94#define PLLE_MISC_LOCK_ENABLE 9
95
96#define PLLC_OUT 0x84
97#define PLLM_OUT 0x94
98#define PLLP_OUTA 0xa4
99#define PLLP_OUTB 0xa8
100#define PLLA_OUT 0xb4
101
102#define CCLK_BURST_POLICY 0x20
103#define SUPER_CCLK_DIVIDER 0x24
104#define SCLK_BURST_POLICY 0x28
105#define SUPER_SCLK_DIVIDER 0x2c
106#define CLK_SYSTEM_RATE 0x30
107
108#define CCLK_BURST_POLICY_SHIFT 28
109#define CCLK_RUN_POLICY_SHIFT 4
110#define CCLK_IDLE_POLICY_SHIFT 0
111#define CCLK_IDLE_POLICY 1
112#define CCLK_RUN_POLICY 2
113#define CCLK_BURST_POLICY_PLLX 8
114
115#define CLK_SOURCE_I2S1 0x100
116#define CLK_SOURCE_I2S2 0x104
117#define CLK_SOURCE_SPDIF_OUT 0x108
118#define CLK_SOURCE_SPDIF_IN 0x10c
119#define CLK_SOURCE_PWM 0x110
120#define CLK_SOURCE_SPI 0x114
121#define CLK_SOURCE_SBC1 0x134
122#define CLK_SOURCE_SBC2 0x118
123#define CLK_SOURCE_SBC3 0x11c
124#define CLK_SOURCE_SBC4 0x1b4
125#define CLK_SOURCE_XIO 0x120
126#define CLK_SOURCE_TWC 0x12c
127#define CLK_SOURCE_IDE 0x144
128#define CLK_SOURCE_NDFLASH 0x160
129#define CLK_SOURCE_VFIR 0x168
130#define CLK_SOURCE_SDMMC1 0x150
131#define CLK_SOURCE_SDMMC2 0x154
132#define CLK_SOURCE_SDMMC3 0x1bc
133#define CLK_SOURCE_SDMMC4 0x164
134#define CLK_SOURCE_CVE 0x140
135#define CLK_SOURCE_TVO 0x188
136#define CLK_SOURCE_TVDAC 0x194
137#define CLK_SOURCE_HDMI 0x18c
138#define CLK_SOURCE_DISP1 0x138
139#define CLK_SOURCE_DISP2 0x13c
140#define CLK_SOURCE_CSITE 0x1d4
141#define CLK_SOURCE_LA 0x1f8
142#define CLK_SOURCE_OWR 0x1cc
143#define CLK_SOURCE_NOR 0x1d0
144#define CLK_SOURCE_MIPI 0x174
145#define CLK_SOURCE_I2C1 0x124
146#define CLK_SOURCE_I2C2 0x198
147#define CLK_SOURCE_I2C3 0x1b8
148#define CLK_SOURCE_DVC 0x128
149#define CLK_SOURCE_UARTA 0x178
150#define CLK_SOURCE_UARTB 0x17c
151#define CLK_SOURCE_UARTC 0x1a0
152#define CLK_SOURCE_UARTD 0x1c0
153#define CLK_SOURCE_UARTE 0x1c4
154#define CLK_SOURCE_3D 0x158
155#define CLK_SOURCE_2D 0x15c
156#define CLK_SOURCE_MPE 0x170
157#define CLK_SOURCE_EPP 0x16c
158#define CLK_SOURCE_HOST1X 0x180
159#define CLK_SOURCE_VDE 0x1c8
160#define CLK_SOURCE_VI 0x148
161#define CLK_SOURCE_VI_SENSOR 0x1a8
162#define CLK_SOURCE_EMC 0x19c
163
164#define AUDIO_SYNC_CLK 0x38
165
166#define PMC_CTRL 0x0
167#define PMC_CTRL_BLINK_ENB 7
168#define PMC_DPD_PADS_ORIDE 0x1c
169#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
170#define PMC_BLINK_TIMER 0x40
171
172/* Tegra CPU clock and reset control regs */
173#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
174#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
175#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
176
177#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
178#define CPU_RESET(cpu) (0x1111ul << (cpu))
179
180#ifdef CONFIG_PM_SLEEP
181static struct cpu_clk_suspend_context {
182 u32 pllx_misc;
183 u32 pllx_base;
184
185 u32 cpu_burst;
186 u32 clk_csite_src;
187 u32 cclk_divider;
188} tegra20_cpu_clk_sctx;
189#endif
190
191static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
192
193static void __iomem *clk_base;
194static void __iomem *pmc_base;
195
196static DEFINE_SPINLOCK(pll_div_lock);
197
198#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
199 _clk_num, _regs, _gate_flags, _clk_id) \
200 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
201 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
202 _regs, _clk_num, periph_clk_enb_refcnt, \
203 _gate_flags, _clk_id)
204
205#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
206 _clk_num, _regs, _gate_flags, _clk_id) \
207 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
208 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
209 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
210 _clk_id)
211
212#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
213 _clk_num, _regs, _gate_flags, _clk_id) \
214 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
215 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \
216 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
217 _clk_id)
218
219#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
220 _mux_shift, _mux_width, _clk_num, _regs, \
221 _gate_flags, _clk_id) \
222 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
223 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \
224 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
225 _clk_id)
226
227/* IDs assigned here must be in sync with DT bindings definition
228 * for Tegra20 clocks .
229 */
230enum tegra20_clk {
231 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
232 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
233 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
234 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
235 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
236 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
237 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
238 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
239 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
240 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
241 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
242 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
243 pll_x, audio, pll_ref, twd, clk_max,
244};
245
246static struct clk *clks[clk_max];
247static struct clk_onecell_data clk_data;
248
249static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
250 { 12000000, 600000000, 600, 12, 1, 8 },
251 { 13000000, 600000000, 600, 13, 1, 8 },
252 { 19200000, 600000000, 500, 16, 1, 6 },
253 { 26000000, 600000000, 600, 26, 1, 8 },
254 { 0, 0, 0, 0, 0, 0 },
255};
256
257static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
258 { 12000000, 666000000, 666, 12, 1, 8},
259 { 13000000, 666000000, 666, 13, 1, 8},
260 { 19200000, 666000000, 555, 16, 1, 8},
261 { 26000000, 666000000, 666, 26, 1, 8},
262 { 12000000, 600000000, 600, 12, 1, 8},
263 { 13000000, 600000000, 600, 13, 1, 8},
264 { 19200000, 600000000, 375, 12, 1, 6},
265 { 26000000, 600000000, 600, 26, 1, 8},
266 { 0, 0, 0, 0, 0, 0 },
267};
268
269static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
270 { 12000000, 216000000, 432, 12, 2, 8},
271 { 13000000, 216000000, 432, 13, 2, 8},
272 { 19200000, 216000000, 90, 4, 2, 1},
273 { 26000000, 216000000, 432, 26, 2, 8},
274 { 12000000, 432000000, 432, 12, 1, 8},
275 { 13000000, 432000000, 432, 13, 1, 8},
276 { 19200000, 432000000, 90, 4, 1, 1},
277 { 26000000, 432000000, 432, 26, 1, 8},
278 { 0, 0, 0, 0, 0, 0 },
279};
280
281static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
282 { 28800000, 56448000, 49, 25, 1, 1},
283 { 28800000, 73728000, 64, 25, 1, 1},
284 { 28800000, 24000000, 5, 6, 1, 1},
285 { 0, 0, 0, 0, 0, 0 },
286};
287
288static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
289 { 12000000, 216000000, 216, 12, 1, 4},
290 { 13000000, 216000000, 216, 13, 1, 4},
291 { 19200000, 216000000, 135, 12, 1, 3},
292 { 26000000, 216000000, 216, 26, 1, 4},
293
294 { 12000000, 594000000, 594, 12, 1, 8},
295 { 13000000, 594000000, 594, 13, 1, 8},
296 { 19200000, 594000000, 495, 16, 1, 8},
297 { 26000000, 594000000, 594, 26, 1, 8},
298
299 { 12000000, 1000000000, 1000, 12, 1, 12},
300 { 13000000, 1000000000, 1000, 13, 1, 12},
301 { 19200000, 1000000000, 625, 12, 1, 8},
302 { 26000000, 1000000000, 1000, 26, 1, 12},
303
304 { 0, 0, 0, 0, 0, 0 },
305};
306
307static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
308 { 12000000, 480000000, 960, 12, 2, 0},
309 { 13000000, 480000000, 960, 13, 2, 0},
310 { 19200000, 480000000, 200, 4, 2, 0},
311 { 26000000, 480000000, 960, 26, 2, 0},
312 { 0, 0, 0, 0, 0, 0 },
313};
314
315static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
316 /* 1 GHz */
317 { 12000000, 1000000000, 1000, 12, 1, 12},
318 { 13000000, 1000000000, 1000, 13, 1, 12},
319 { 19200000, 1000000000, 625, 12, 1, 8},
320 { 26000000, 1000000000, 1000, 26, 1, 12},
321
322 /* 912 MHz */
323 { 12000000, 912000000, 912, 12, 1, 12},
324 { 13000000, 912000000, 912, 13, 1, 12},
325 { 19200000, 912000000, 760, 16, 1, 8},
326 { 26000000, 912000000, 912, 26, 1, 12},
327
328 /* 816 MHz */
329 { 12000000, 816000000, 816, 12, 1, 12},
330 { 13000000, 816000000, 816, 13, 1, 12},
331 { 19200000, 816000000, 680, 16, 1, 8},
332 { 26000000, 816000000, 816, 26, 1, 12},
333
334 /* 760 MHz */
335 { 12000000, 760000000, 760, 12, 1, 12},
336 { 13000000, 760000000, 760, 13, 1, 12},
337 { 19200000, 760000000, 950, 24, 1, 8},
338 { 26000000, 760000000, 760, 26, 1, 12},
339
340 /* 750 MHz */
341 { 12000000, 750000000, 750, 12, 1, 12},
342 { 13000000, 750000000, 750, 13, 1, 12},
343 { 19200000, 750000000, 625, 16, 1, 8},
344 { 26000000, 750000000, 750, 26, 1, 12},
345
346 /* 608 MHz */
347 { 12000000, 608000000, 608, 12, 1, 12},
348 { 13000000, 608000000, 608, 13, 1, 12},
349 { 19200000, 608000000, 380, 12, 1, 8},
350 { 26000000, 608000000, 608, 26, 1, 12},
351
352 /* 456 MHz */
353 { 12000000, 456000000, 456, 12, 1, 12},
354 { 13000000, 456000000, 456, 13, 1, 12},
355 { 19200000, 456000000, 380, 16, 1, 8},
356 { 26000000, 456000000, 456, 26, 1, 12},
357
358 /* 312 MHz */
359 { 12000000, 312000000, 312, 12, 1, 12},
360 { 13000000, 312000000, 312, 13, 1, 12},
361 { 19200000, 312000000, 260, 16, 1, 8},
362 { 26000000, 312000000, 312, 26, 1, 12},
363
364 { 0, 0, 0, 0, 0, 0 },
365};
366
367static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
368 { 12000000, 100000000, 200, 24, 1, 0 },
369 { 0, 0, 0, 0, 0, 0 },
370};
371
372/* PLL parameters */
373static struct tegra_clk_pll_params pll_c_params = {
374 .input_min = 2000000,
375 .input_max = 31000000,
376 .cf_min = 1000000,
377 .cf_max = 6000000,
378 .vco_min = 20000000,
379 .vco_max = 1400000000,
380 .base_reg = PLLC_BASE,
381 .misc_reg = PLLC_MISC,
382 .lock_bit_idx = PLL_BASE_LOCK,
383 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
384 .lock_delay = 300,
385};
386
387static struct tegra_clk_pll_params pll_m_params = {
388 .input_min = 2000000,
389 .input_max = 31000000,
390 .cf_min = 1000000,
391 .cf_max = 6000000,
392 .vco_min = 20000000,
393 .vco_max = 1200000000,
394 .base_reg = PLLM_BASE,
395 .misc_reg = PLLM_MISC,
396 .lock_bit_idx = PLL_BASE_LOCK,
397 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
398 .lock_delay = 300,
399};
400
401static struct tegra_clk_pll_params pll_p_params = {
402 .input_min = 2000000,
403 .input_max = 31000000,
404 .cf_min = 1000000,
405 .cf_max = 6000000,
406 .vco_min = 20000000,
407 .vco_max = 1400000000,
408 .base_reg = PLLP_BASE,
409 .misc_reg = PLLP_MISC,
410 .lock_bit_idx = PLL_BASE_LOCK,
411 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
412 .lock_delay = 300,
413};
414
415static struct tegra_clk_pll_params pll_a_params = {
416 .input_min = 2000000,
417 .input_max = 31000000,
418 .cf_min = 1000000,
419 .cf_max = 6000000,
420 .vco_min = 20000000,
421 .vco_max = 1400000000,
422 .base_reg = PLLA_BASE,
423 .misc_reg = PLLA_MISC,
424 .lock_bit_idx = PLL_BASE_LOCK,
425 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
426 .lock_delay = 300,
427};
428
429static struct tegra_clk_pll_params pll_d_params = {
430 .input_min = 2000000,
431 .input_max = 40000000,
432 .cf_min = 1000000,
433 .cf_max = 6000000,
434 .vco_min = 40000000,
435 .vco_max = 1000000000,
436 .base_reg = PLLD_BASE,
437 .misc_reg = PLLD_MISC,
438 .lock_bit_idx = PLL_BASE_LOCK,
439 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
440 .lock_delay = 1000,
441};
442
443static struct tegra_clk_pll_params pll_u_params = {
444 .input_min = 2000000,
445 .input_max = 40000000,
446 .cf_min = 1000000,
447 .cf_max = 6000000,
448 .vco_min = 48000000,
449 .vco_max = 960000000,
450 .base_reg = PLLU_BASE,
451 .misc_reg = PLLU_MISC,
452 .lock_bit_idx = PLL_BASE_LOCK,
453 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
454 .lock_delay = 1000,
455};
456
457static struct tegra_clk_pll_params pll_x_params = {
458 .input_min = 2000000,
459 .input_max = 31000000,
460 .cf_min = 1000000,
461 .cf_max = 6000000,
462 .vco_min = 20000000,
463 .vco_max = 1200000000,
464 .base_reg = PLLX_BASE,
465 .misc_reg = PLLX_MISC,
466 .lock_bit_idx = PLL_BASE_LOCK,
467 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
468 .lock_delay = 300,
469};
470
471static struct tegra_clk_pll_params pll_e_params = {
472 .input_min = 12000000,
473 .input_max = 12000000,
474 .cf_min = 0,
475 .cf_max = 0,
476 .vco_min = 0,
477 .vco_max = 0,
478 .base_reg = PLLE_BASE,
479 .misc_reg = PLLE_MISC,
480 .lock_bit_idx = PLLE_MISC_LOCK,
481 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
482 .lock_delay = 0,
483};
484
485/* Peripheral clock registers */
486static struct tegra_clk_periph_regs periph_l_regs = {
487 .enb_reg = CLK_OUT_ENB_L,
488 .enb_set_reg = CLK_OUT_ENB_SET_L,
489 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
490 .rst_reg = RST_DEVICES_L,
491 .rst_set_reg = RST_DEVICES_SET_L,
492 .rst_clr_reg = RST_DEVICES_CLR_L,
493};
494
495static struct tegra_clk_periph_regs periph_h_regs = {
496 .enb_reg = CLK_OUT_ENB_H,
497 .enb_set_reg = CLK_OUT_ENB_SET_H,
498 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
499 .rst_reg = RST_DEVICES_H,
500 .rst_set_reg = RST_DEVICES_SET_H,
501 .rst_clr_reg = RST_DEVICES_CLR_H,
502};
503
504static struct tegra_clk_periph_regs periph_u_regs = {
505 .enb_reg = CLK_OUT_ENB_U,
506 .enb_set_reg = CLK_OUT_ENB_SET_U,
507 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
508 .rst_reg = RST_DEVICES_U,
509 .rst_set_reg = RST_DEVICES_SET_U,
510 .rst_clr_reg = RST_DEVICES_CLR_U,
511};
512
513static unsigned long tegra20_clk_measure_input_freq(void)
514{
515 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
516 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
517 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
518 unsigned long input_freq;
519
520 switch (auto_clk_control) {
521 case OSC_CTRL_OSC_FREQ_12MHZ:
522 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
523 input_freq = 12000000;
524 break;
525 case OSC_CTRL_OSC_FREQ_13MHZ:
526 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
527 input_freq = 13000000;
528 break;
529 case OSC_CTRL_OSC_FREQ_19_2MHZ:
530 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
531 input_freq = 19200000;
532 break;
533 case OSC_CTRL_OSC_FREQ_26MHZ:
534 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
535 input_freq = 26000000;
536 break;
537 default:
538 pr_err("Unexpected clock autodetect value %d",
539 auto_clk_control);
540 BUG();
541 return 0;
542 }
543
544 return input_freq;
545}
546
547static unsigned int tegra20_get_pll_ref_div(void)
548{
549 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
550 OSC_CTRL_PLL_REF_DIV_MASK;
551
552 switch (pll_ref_div) {
553 case OSC_CTRL_PLL_REF_DIV_1:
554 return 1;
555 case OSC_CTRL_PLL_REF_DIV_2:
556 return 2;
557 case OSC_CTRL_PLL_REF_DIV_4:
558 return 4;
559 default:
560 pr_err("Invalied pll ref divider %d\n", pll_ref_div);
561 BUG();
562 }
563 return 0;
564}
565
566static void tegra20_pll_init(void)
567{
568 struct clk *clk;
569
570 /* PLLC */
571 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
572 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
573 pll_c_freq_table, NULL);
574 clk_register_clkdev(clk, "pll_c", NULL);
575 clks[pll_c] = clk;
576
577 /* PLLC_OUT1 */
578 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
579 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
580 8, 8, 1, NULL);
581 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
582 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
583 0, NULL);
584 clk_register_clkdev(clk, "pll_c_out1", NULL);
585 clks[pll_c_out1] = clk;
586
587 /* PLLP */
588 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0,
589 216000000, &pll_p_params, TEGRA_PLL_FIXED |
590 TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL);
591 clk_register_clkdev(clk, "pll_p", NULL);
592 clks[pll_p] = clk;
593
594 /* PLLP_OUT1 */
595 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
596 clk_base + PLLP_OUTA, 0,
597 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
598 8, 8, 1, &pll_div_lock);
599 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
600 clk_base + PLLP_OUTA, 1, 0,
601 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
602 &pll_div_lock);
603 clk_register_clkdev(clk, "pll_p_out1", NULL);
604 clks[pll_p_out1] = clk;
605
606 /* PLLP_OUT2 */
607 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
608 clk_base + PLLP_OUTA, 0,
609 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
610 24, 8, 1, &pll_div_lock);
611 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
612 clk_base + PLLP_OUTA, 17, 16,
613 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
614 &pll_div_lock);
615 clk_register_clkdev(clk, "pll_p_out2", NULL);
616 clks[pll_p_out2] = clk;
617
618 /* PLLP_OUT3 */
619 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
620 clk_base + PLLP_OUTB, 0,
621 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
622 8, 8, 1, &pll_div_lock);
623 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
624 clk_base + PLLP_OUTB, 1, 0,
625 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
626 &pll_div_lock);
627 clk_register_clkdev(clk, "pll_p_out3", NULL);
628 clks[pll_p_out3] = clk;
629
630 /* PLLP_OUT4 */
631 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
632 clk_base + PLLP_OUTB, 0,
633 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
634 24, 8, 1, &pll_div_lock);
635 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
636 clk_base + PLLP_OUTB, 17, 16,
637 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
638 &pll_div_lock);
639 clk_register_clkdev(clk, "pll_p_out4", NULL);
640 clks[pll_p_out4] = clk;
641
642 /* PLLM */
643 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
644 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
645 &pll_m_params, TEGRA_PLL_HAS_CPCON,
646 pll_m_freq_table, NULL);
647 clk_register_clkdev(clk, "pll_m", NULL);
648 clks[pll_m] = clk;
649
650 /* PLLM_OUT1 */
651 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
652 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
653 8, 8, 1, NULL);
654 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
655 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
656 CLK_SET_RATE_PARENT, 0, NULL);
657 clk_register_clkdev(clk, "pll_m_out1", NULL);
658 clks[pll_m_out1] = clk;
659
660 /* PLLX */
661 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
662 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
663 pll_x_freq_table, NULL);
664 clk_register_clkdev(clk, "pll_x", NULL);
665 clks[pll_x] = clk;
666
667 /* PLLU */
668 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
669 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
670 pll_u_freq_table, NULL);
671 clk_register_clkdev(clk, "pll_u", NULL);
672 clks[pll_u] = clk;
673
674 /* PLLD */
675 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
676 0, &pll_d_params, TEGRA_PLL_HAS_CPCON,
677 pll_d_freq_table, NULL);
678 clk_register_clkdev(clk, "pll_d", NULL);
679 clks[pll_d] = clk;
680
681 /* PLLD_OUT0 */
682 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
683 CLK_SET_RATE_PARENT, 1, 2);
684 clk_register_clkdev(clk, "pll_d_out0", NULL);
685 clks[pll_d_out0] = clk;
686
687 /* PLLA */
688 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
689 0, &pll_a_params, TEGRA_PLL_HAS_CPCON,
690 pll_a_freq_table, NULL);
691 clk_register_clkdev(clk, "pll_a", NULL);
692 clks[pll_a] = clk;
693
694 /* PLLA_OUT0 */
695 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
696 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
697 8, 8, 1, NULL);
698 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
699 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
700 CLK_SET_RATE_PARENT, 0, NULL);
701 clk_register_clkdev(clk, "pll_a_out0", NULL);
702 clks[pll_a_out0] = clk;
703
704 /* PLLE */
705 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
706 0, 100000000, &pll_e_params,
707 0, pll_e_freq_table, NULL);
708 clk_register_clkdev(clk, "pll_e", NULL);
709 clks[pll_e] = clk;
710}
711
712static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
713 "pll_p_cclk", "pll_p_out4_cclk",
714 "pll_p_out3_cclk", "clk_d", "pll_x" };
715static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
716 "pll_p_out3", "pll_p_out2", "clk_d",
717 "clk_32k", "pll_m_out1" };
718
719static void tegra20_super_clk_init(void)
720{
721 struct clk *clk;
722
723 /*
724 * DIV_U71 dividers for CCLK, these dividers are used only
725 * if parent clock is fixed rate.
726 */
727
728 /*
729 * Clock input to cclk divided from pll_p using
730 * U71 divider of cclk.
731 */
732 clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
733 clk_base + SUPER_CCLK_DIVIDER, 0,
734 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
735 clk_register_clkdev(clk, "pll_p_cclk", NULL);
736
737 /*
738 * Clock input to cclk divided from pll_p_out3 using
739 * U71 divider of cclk.
740 */
741 clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
742 clk_base + SUPER_CCLK_DIVIDER, 0,
743 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
744 clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
745
746 /*
747 * Clock input to cclk divided from pll_p_out4 using
748 * U71 divider of cclk.
749 */
750 clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
751 clk_base + SUPER_CCLK_DIVIDER, 0,
752 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
753 clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
754
755 /* CCLK */
756 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
757 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
758 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
759 clk_register_clkdev(clk, "cclk", NULL);
760 clks[cclk] = clk;
761
762 /* SCLK */
763 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
764 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
765 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
766 clk_register_clkdev(clk, "sclk", NULL);
767 clks[sclk] = clk;
768
769 /* HCLK */
770 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
771 clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
772 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
773 clk_base + CLK_SYSTEM_RATE, 7,
774 CLK_GATE_SET_TO_DISABLE, NULL);
775 clk_register_clkdev(clk, "hclk", NULL);
776 clks[hclk] = clk;
777
778 /* PCLK */
779 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
780 clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
781 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
782 clk_base + CLK_SYSTEM_RATE, 3,
783 CLK_GATE_SET_TO_DISABLE, NULL);
784 clk_register_clkdev(clk, "pclk", NULL);
785 clks[pclk] = clk;
786
787 /* twd */
788 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
789 clk_register_clkdev(clk, "twd", NULL);
790 clks[twd] = clk;
791}
792
793static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
794 "pll_a_out0", "unused", "unused",
795 "unused"};
796
797static void __init tegra20_audio_clk_init(void)
798{
799 struct clk *clk;
800
801 /* audio */
802 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
803 ARRAY_SIZE(audio_parents), 0,
804 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
805 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
806 clk_base + AUDIO_SYNC_CLK, 4,
807 CLK_GATE_SET_TO_DISABLE, NULL);
808 clk_register_clkdev(clk, "audio", NULL);
809 clks[audio] = clk;
810
811 /* audio_2x */
812 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
813 CLK_SET_RATE_PARENT, 2, 1);
814 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
815 TEGRA_PERIPH_NO_RESET, clk_base,
816 CLK_SET_RATE_PARENT, 89, &periph_u_regs,
817 periph_clk_enb_refcnt);
818 clk_register_clkdev(clk, "audio_2x", NULL);
819 clks[audio_2x] = clk;
820
821}
822
823static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
824 "clk_m"};
825static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
826 "clk_m"};
827static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
828 "clk_m"};
829static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"};
830static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
831 "clk_32k"};
832static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
833static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"};
834static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
835 "clk_m"};
836static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
837
838static struct tegra_periph_init_data tegra_periph_clk_list[] = {
839 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
840 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
841 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
842 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
843 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
844 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
845 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
846 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
847 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, &periph_h_regs, TEGRA_PERIPH_ON_APB, spi),
848 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, &periph_h_regs, 0, xio),
849 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, &periph_l_regs, TEGRA_PERIPH_ON_APB, twc),
850 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, &periph_l_regs, 0, ide),
851 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, 0, ndflash),
852 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
853 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, 0, csite),
854 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, 0, la),
855 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
856 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
857 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
858 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
859 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
860 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
861 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
862 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
863 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
864 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
865 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
866 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
867 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
868 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
869 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
870 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
871 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
872 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
873 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
874 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
875 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
876 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc),
877 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
878 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm),
879};
880
881static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
882 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta),
883 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb),
884 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc),
885 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd),
886 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte),
887 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1),
888 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2),
889};
890
891static void __init tegra20_periph_clk_init(void)
892{
893 struct tegra_periph_init_data *data;
894 struct clk *clk;
895 int i;
896
897 /* apbdma */
898 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
899 0, 34, &periph_h_regs,
900 periph_clk_enb_refcnt);
901 clk_register_clkdev(clk, NULL, "tegra-apbdma");
902 clks[apbdma] = clk;
903
904 /* rtc */
905 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
906 TEGRA_PERIPH_NO_RESET,
907 clk_base, 0, 4, &periph_l_regs,
908 periph_clk_enb_refcnt);
909 clk_register_clkdev(clk, NULL, "rtc-tegra");
910 clks[rtc] = clk;
911
912 /* timer */
913 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
914 0, 5, &periph_l_regs,
915 periph_clk_enb_refcnt);
916 clk_register_clkdev(clk, NULL, "timer");
917 clks[timer] = clk;
918
919 /* kbc */
920 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
921 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
922 clk_base, 0, 36, &periph_h_regs,
923 periph_clk_enb_refcnt);
924 clk_register_clkdev(clk, NULL, "tegra-kbc");
925 clks[kbc] = clk;
926
927 /* csus */
928 clk = tegra_clk_register_periph_gate("csus", "clk_m",
929 TEGRA_PERIPH_NO_RESET,
930 clk_base, 0, 92, &periph_u_regs,
931 periph_clk_enb_refcnt);
932 clk_register_clkdev(clk, "csus", "tengra_camera");
933 clks[csus] = clk;
934
935 /* vcp */
936 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0,
937 clk_base, 0, 29, &periph_l_regs,
938 periph_clk_enb_refcnt);
939 clk_register_clkdev(clk, "vcp", "tegra-avp");
940 clks[vcp] = clk;
941
942 /* bsea */
943 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0,
944 clk_base, 0, 62, &periph_h_regs,
945 periph_clk_enb_refcnt);
946 clk_register_clkdev(clk, "bsea", "tegra-avp");
947 clks[bsea] = clk;
948
949 /* bsev */
950 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0,
951 clk_base, 0, 63, &periph_h_regs,
952 periph_clk_enb_refcnt);
953 clk_register_clkdev(clk, "bsev", "tegra-aes");
954 clks[bsev] = clk;
955
956 /* emc */
957 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
958 ARRAY_SIZE(mux_pllmcp_clkm), 0,
959 clk_base + CLK_SOURCE_EMC,
960 30, 2, 0, NULL);
961 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
962 57, &periph_h_regs, periph_clk_enb_refcnt);
963 clk_register_clkdev(clk, "emc", NULL);
964 clks[emc] = clk;
965
966 /* usbd */
967 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
968 22, &periph_l_regs, periph_clk_enb_refcnt);
969 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
970 clks[usbd] = clk;
971
972 /* usb2 */
973 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
974 58, &periph_h_regs, periph_clk_enb_refcnt);
975 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
976 clks[usb2] = clk;
977
978 /* usb3 */
979 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
980 59, &periph_h_regs, periph_clk_enb_refcnt);
981 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
982 clks[usb3] = clk;
983
984 /* dsi */
985 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
986 48, &periph_h_regs, periph_clk_enb_refcnt);
987 clk_register_clkdev(clk, NULL, "dsi");
988 clks[dsi] = clk;
989
990 /* csi */
991 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
992 0, 52, &periph_h_regs,
993 periph_clk_enb_refcnt);
994 clk_register_clkdev(clk, "csi", "tegra_camera");
995 clks[csi] = clk;
996
997 /* isp */
998 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
999 &periph_l_regs, periph_clk_enb_refcnt);
1000 clk_register_clkdev(clk, "isp", "tegra_camera");
1001 clks[isp] = clk;
1002
1003 /* pex */
1004 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
1005 &periph_u_regs, periph_clk_enb_refcnt);
1006 clk_register_clkdev(clk, "pex", NULL);
1007 clks[pex] = clk;
1008
1009 /* afi */
1010 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1011 &periph_u_regs, periph_clk_enb_refcnt);
1012 clk_register_clkdev(clk, "afi", NULL);
1013 clks[afi] = clk;
1014
1015 /* pcie_xclk */
1016 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
1017 0, 74, &periph_u_regs,
1018 periph_clk_enb_refcnt);
1019 clk_register_clkdev(clk, "pcie_xclk", NULL);
1020 clks[pcie_xclk] = clk;
1021
1022 /* cdev1 */
1023 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
1024 26000000);
1025 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
1026 clk_base, 0, 94, &periph_u_regs,
1027 periph_clk_enb_refcnt);
1028 clk_register_clkdev(clk, "cdev1", NULL);
1029 clks[cdev1] = clk;
1030
1031 /* cdev2 */
1032 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
1033 26000000);
1034 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
1035 clk_base, 0, 93, &periph_u_regs,
1036 periph_clk_enb_refcnt);
1037 clk_register_clkdev(clk, "cdev2", NULL);
1038 clks[cdev2] = clk;
1039
1040 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1041 data = &tegra_periph_clk_list[i];
1042 clk = tegra_clk_register_periph(data->name, data->parent_names,
1043 data->num_parents, &data->periph,
1044 clk_base, data->offset);
1045 clk_register_clkdev(clk, data->con_id, data->dev_id);
1046 clks[data->clk_id] = clk;
1047 }
1048
1049 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1050 data = &tegra_periph_nodiv_clk_list[i];
1051 clk = tegra_clk_register_periph_nodiv(data->name,
1052 data->parent_names,
1053 data->num_parents, &data->periph,
1054 clk_base, data->offset);
1055 clk_register_clkdev(clk, data->con_id, data->dev_id);
1056 clks[data->clk_id] = clk;
1057 }
1058}
1059
1060
1061static void __init tegra20_fixed_clk_init(void)
1062{
1063 struct clk *clk;
1064
1065 /* clk_32k */
1066 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1067 32768);
1068 clk_register_clkdev(clk, "clk_32k", NULL);
1069 clks[clk_32k] = clk;
1070}
1071
1072static void __init tegra20_pmc_clk_init(void)
1073{
1074 struct clk *clk;
1075
1076 /* blink */
1077 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1078 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1079 pmc_base + PMC_DPD_PADS_ORIDE,
1080 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1081 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1082 pmc_base + PMC_CTRL,
1083 PMC_CTRL_BLINK_ENB, 0, NULL);
1084 clk_register_clkdev(clk, "blink", NULL);
1085 clks[blink] = clk;
1086}
1087
1088static void __init tegra20_osc_clk_init(void)
1089{
1090 struct clk *clk;
1091 unsigned long input_freq;
1092 unsigned int pll_ref_div;
1093
1094 input_freq = tegra20_clk_measure_input_freq();
1095
1096 /* clk_m */
1097 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
1098 CLK_IGNORE_UNUSED, input_freq);
1099 clk_register_clkdev(clk, "clk_m", NULL);
1100 clks[clk_m] = clk;
1101
1102 /* pll_ref */
1103 pll_ref_div = tegra20_get_pll_ref_div();
1104 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1105 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1106 clk_register_clkdev(clk, "pll_ref", NULL);
1107 clks[pll_ref] = clk;
1108}
1109
1110/* Tegra20 CPU clock and reset control functions */
1111static void tegra20_wait_cpu_in_reset(u32 cpu)
1112{
1113 unsigned int reg;
1114
1115 do {
1116 reg = readl(clk_base +
1117 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1118 cpu_relax();
1119 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1120
1121 return;
1122}
1123
1124static void tegra20_put_cpu_in_reset(u32 cpu)
1125{
1126 writel(CPU_RESET(cpu),
1127 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1128 dmb();
1129}
1130
1131static void tegra20_cpu_out_of_reset(u32 cpu)
1132{
1133 writel(CPU_RESET(cpu),
1134 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1135 wmb();
1136}
1137
1138static void tegra20_enable_cpu_clock(u32 cpu)
1139{
1140 unsigned int reg;
1141
1142 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1143 writel(reg & ~CPU_CLOCK(cpu),
1144 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1145 barrier();
1146 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1147}
1148
1149static void tegra20_disable_cpu_clock(u32 cpu)
1150{
1151 unsigned int reg;
1152
1153 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1154 writel(reg | CPU_CLOCK(cpu),
1155 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1156}
1157
1158#ifdef CONFIG_PM_SLEEP
1159static bool tegra20_cpu_rail_off_ready(void)
1160{
1161 unsigned int cpu_rst_status;
1162
1163 cpu_rst_status = readl(clk_base +
1164 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1165
1166 return !!(cpu_rst_status & 0x2);
1167}
1168
1169static void tegra20_cpu_clock_suspend(void)
1170{
1171 /* switch coresite to clk_m, save off original source */
1172 tegra20_cpu_clk_sctx.clk_csite_src =
1173 readl(clk_base + CLK_SOURCE_CSITE);
1174 writel(3<<30, clk_base + CLK_SOURCE_CSITE);
1175
1176 tegra20_cpu_clk_sctx.cpu_burst =
1177 readl(clk_base + CCLK_BURST_POLICY);
1178 tegra20_cpu_clk_sctx.pllx_base =
1179 readl(clk_base + PLLX_BASE);
1180 tegra20_cpu_clk_sctx.pllx_misc =
1181 readl(clk_base + PLLX_MISC);
1182 tegra20_cpu_clk_sctx.cclk_divider =
1183 readl(clk_base + SUPER_CCLK_DIVIDER);
1184}
1185
1186static void tegra20_cpu_clock_resume(void)
1187{
1188 unsigned int reg, policy;
1189
1190 /* Is CPU complex already running on PLLX? */
1191 reg = readl(clk_base + CCLK_BURST_POLICY);
1192 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
1193
1194 if (policy == CCLK_IDLE_POLICY)
1195 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
1196 else if (policy == CCLK_RUN_POLICY)
1197 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
1198 else
1199 BUG();
1200
1201 if (reg != CCLK_BURST_POLICY_PLLX) {
1202 /* restore PLLX settings if CPU is on different PLL */
1203 writel(tegra20_cpu_clk_sctx.pllx_misc,
1204 clk_base + PLLX_MISC);
1205 writel(tegra20_cpu_clk_sctx.pllx_base,
1206 clk_base + PLLX_BASE);
1207
1208 /* wait for PLL stabilization if PLLX was enabled */
1209 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
1210 udelay(300);
1211 }
1212
1213 /*
1214 * Restore original burst policy setting for calls resulting from CPU
1215 * LP2 in idle or system suspend.
1216 */
1217 writel(tegra20_cpu_clk_sctx.cclk_divider,
1218 clk_base + SUPER_CCLK_DIVIDER);
1219 writel(tegra20_cpu_clk_sctx.cpu_burst,
1220 clk_base + CCLK_BURST_POLICY);
1221
1222 writel(tegra20_cpu_clk_sctx.clk_csite_src,
1223 clk_base + CLK_SOURCE_CSITE);
1224}
1225#endif
1226
1227static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1228 .wait_for_reset = tegra20_wait_cpu_in_reset,
1229 .put_in_reset = tegra20_put_cpu_in_reset,
1230 .out_of_reset = tegra20_cpu_out_of_reset,
1231 .enable_clock = tegra20_enable_cpu_clock,
1232 .disable_clock = tegra20_disable_cpu_clock,
1233#ifdef CONFIG_PM_SLEEP
1234 .rail_off_ready = tegra20_cpu_rail_off_ready,
1235 .suspend = tegra20_cpu_clock_suspend,
1236 .resume = tegra20_cpu_clock_resume,
1237#endif
1238};
1239
1240static __initdata struct tegra_clk_init_table init_table[] = {
1241 {pll_p, clk_max, 216000000, 1},
1242 {pll_p_out1, clk_max, 28800000, 1},
1243 {pll_p_out2, clk_max, 48000000, 1},
1244 {pll_p_out3, clk_max, 72000000, 1},
1245 {pll_p_out4, clk_max, 24000000, 1},
1246 {pll_c, clk_max, 600000000, 1},
1247 {pll_c_out1, clk_max, 120000000, 1},
1248 {sclk, pll_c_out1, 0, 1},
1249 {hclk, clk_max, 0, 1},
1250 {pclk, clk_max, 60000000, 1},
1251 {csite, clk_max, 0, 1},
1252 {emc, clk_max, 0, 1},
1253 {cclk, clk_max, 0, 1},
1254 {uarta, pll_p, 0, 1},
1255 {uartd, pll_p, 0, 1},
1256 {usbd, clk_max, 12000000, 0},
1257 {usb2, clk_max, 12000000, 0},
1258 {usb3, clk_max, 12000000, 0},
1259 {pll_a, clk_max, 56448000, 1},
1260 {pll_a_out0, clk_max, 11289600, 1},
1261 {cdev1, clk_max, 0, 1},
1262 {blink, clk_max, 32768, 1},
1263 {i2s1, pll_a_out0, 11289600, 0},
1264 {i2s2, pll_a_out0, 11289600, 0},
1265 {sdmmc1, pll_p, 48000000, 0},
1266 {sdmmc3, pll_p, 48000000, 0},
1267 {sdmmc4, pll_p, 48000000, 0},
1268 {spi, pll_p, 20000000, 0},
1269 {sbc1, pll_p, 100000000, 0},
1270 {sbc2, pll_p, 100000000, 0},
1271 {sbc3, pll_p, 100000000, 0},
1272 {sbc4, pll_p, 100000000, 0},
1273 {host1x, pll_c, 150000000, 0},
1274 {disp1, pll_p, 600000000, 0},
1275 {disp2, pll_p, 600000000, 0},
1276 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
1277};
1278
1279/*
1280 * Some clocks may be used by different drivers depending on the board
1281 * configuration. List those here to register them twice in the clock lookup
1282 * table under two names.
1283 */
1284static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1285 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1286 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1287 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1288 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"),
1289 TEGRA_CLK_DUPLICATE(twd, "smp_twd", NULL),
1290 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */
1291};
1292
1293static const struct of_device_id pmc_match[] __initconst = {
1294 { .compatible = "nvidia,tegra20-pmc" },
1295 {},
1296};
1297
1298void __init tegra20_clock_init(struct device_node *np)
1299{
1300 int i;
1301 struct device_node *node;
1302
1303 clk_base = of_iomap(np, 0);
1304 if (!clk_base) {
1305 pr_err("Can't map CAR registers\n");
1306 BUG();
1307 }
1308
1309 node = of_find_matching_node(NULL, pmc_match);
1310 if (!node) {
1311 pr_err("Failed to find pmc node\n");
1312 BUG();
1313 }
1314
1315 pmc_base = of_iomap(node, 0);
1316 if (!pmc_base) {
1317 pr_err("Can't map pmc registers\n");
1318 BUG();
1319 }
1320
1321 tegra20_osc_clk_init();
1322 tegra20_pmc_clk_init();
1323 tegra20_fixed_clk_init();
1324 tegra20_pll_init();
1325 tegra20_super_clk_init();
1326 tegra20_periph_clk_init();
1327 tegra20_audio_clk_init();
1328
1329
1330 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1331 if (IS_ERR(clks[i])) {
1332 pr_err("Tegra20 clk %d: register failed with %ld\n",
1333 i, PTR_ERR(clks[i]));
1334 BUG();
1335 }
1336 if (!clks[i])
1337 clks[i] = ERR_PTR(-EINVAL);
1338 }
1339
1340 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1341
1342 clk_data.clks = clks;
1343 clk_data.clk_num = ARRAY_SIZE(clks);
1344 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1345
1346 tegra_init_from_table(init_table, clks, clk_max);
1347
1348 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1349}
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
new file mode 100644
index 000000000000..a1638129eba4
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -0,0 +1,1987 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/clk/tegra.h>
25
26#include <mach/powergate.h>
27
28#include "clk.h"
29
30#define RST_DEVICES_L 0x004
31#define RST_DEVICES_H 0x008
32#define RST_DEVICES_U 0x00c
33#define RST_DEVICES_V 0x358
34#define RST_DEVICES_W 0x35c
35#define RST_DEVICES_SET_L 0x300
36#define RST_DEVICES_CLR_L 0x304
37#define RST_DEVICES_SET_H 0x308
38#define RST_DEVICES_CLR_H 0x30c
39#define RST_DEVICES_SET_U 0x310
40#define RST_DEVICES_CLR_U 0x314
41#define RST_DEVICES_SET_V 0x430
42#define RST_DEVICES_CLR_V 0x434
43#define RST_DEVICES_SET_W 0x438
44#define RST_DEVICES_CLR_W 0x43c
45#define RST_DEVICES_NUM 5
46
47#define CLK_OUT_ENB_L 0x010
48#define CLK_OUT_ENB_H 0x014
49#define CLK_OUT_ENB_U 0x018
50#define CLK_OUT_ENB_V 0x360
51#define CLK_OUT_ENB_W 0x364
52#define CLK_OUT_ENB_SET_L 0x320
53#define CLK_OUT_ENB_CLR_L 0x324
54#define CLK_OUT_ENB_SET_H 0x328
55#define CLK_OUT_ENB_CLR_H 0x32c
56#define CLK_OUT_ENB_SET_U 0x330
57#define CLK_OUT_ENB_CLR_U 0x334
58#define CLK_OUT_ENB_SET_V 0x440
59#define CLK_OUT_ENB_CLR_V 0x444
60#define CLK_OUT_ENB_SET_W 0x448
61#define CLK_OUT_ENB_CLR_W 0x44c
62#define CLK_OUT_ENB_NUM 5
63
64#define OSC_CTRL 0x50
65#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
66#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
67#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
68#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
69#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
70#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
71#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
72#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
73#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
74
75#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
76#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
77#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
78#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
79
80#define OSC_FREQ_DET 0x58
81#define OSC_FREQ_DET_TRIG BIT(31)
82
83#define OSC_FREQ_DET_STATUS 0x5c
84#define OSC_FREQ_DET_BUSY BIT(31)
85#define OSC_FREQ_DET_CNT_MASK 0xffff
86
87#define CCLKG_BURST_POLICY 0x368
88#define SUPER_CCLKG_DIVIDER 0x36c
89#define CCLKLP_BURST_POLICY 0x370
90#define SUPER_CCLKLP_DIVIDER 0x374
91#define SCLK_BURST_POLICY 0x028
92#define SUPER_SCLK_DIVIDER 0x02c
93
94#define SYSTEM_CLK_RATE 0x030
95
96#define PLLC_BASE 0x80
97#define PLLC_MISC 0x8c
98#define PLLM_BASE 0x90
99#define PLLM_MISC 0x9c
100#define PLLP_BASE 0xa0
101#define PLLP_MISC 0xac
102#define PLLX_BASE 0xe0
103#define PLLX_MISC 0xe4
104#define PLLD_BASE 0xd0
105#define PLLD_MISC 0xdc
106#define PLLD2_BASE 0x4b8
107#define PLLD2_MISC 0x4bc
108#define PLLE_BASE 0xe8
109#define PLLE_MISC 0xec
110#define PLLA_BASE 0xb0
111#define PLLA_MISC 0xbc
112#define PLLU_BASE 0xc0
113#define PLLU_MISC 0xcc
114
115#define PLL_MISC_LOCK_ENABLE 18
116#define PLLDU_MISC_LOCK_ENABLE 22
117#define PLLE_MISC_LOCK_ENABLE 9
118
119#define PLL_BASE_LOCK 27
120#define PLLE_MISC_LOCK 11
121
122#define PLLE_AUX 0x48c
123#define PLLC_OUT 0x84
124#define PLLM_OUT 0x94
125#define PLLP_OUTA 0xa4
126#define PLLP_OUTB 0xa8
127#define PLLA_OUT 0xb4
128
129#define AUDIO_SYNC_CLK_I2S0 0x4a0
130#define AUDIO_SYNC_CLK_I2S1 0x4a4
131#define AUDIO_SYNC_CLK_I2S2 0x4a8
132#define AUDIO_SYNC_CLK_I2S3 0x4ac
133#define AUDIO_SYNC_CLK_I2S4 0x4b0
134#define AUDIO_SYNC_CLK_SPDIF 0x4b4
135
136#define PMC_CLK_OUT_CNTRL 0x1a8
137
138#define CLK_SOURCE_I2S0 0x1d8
139#define CLK_SOURCE_I2S1 0x100
140#define CLK_SOURCE_I2S2 0x104
141#define CLK_SOURCE_I2S3 0x3bc
142#define CLK_SOURCE_I2S4 0x3c0
143#define CLK_SOURCE_SPDIF_OUT 0x108
144#define CLK_SOURCE_SPDIF_IN 0x10c
145#define CLK_SOURCE_PWM 0x110
146#define CLK_SOURCE_D_AUDIO 0x3d0
147#define CLK_SOURCE_DAM0 0x3d8
148#define CLK_SOURCE_DAM1 0x3dc
149#define CLK_SOURCE_DAM2 0x3e0
150#define CLK_SOURCE_HDA 0x428
151#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
152#define CLK_SOURCE_SBC1 0x134
153#define CLK_SOURCE_SBC2 0x118
154#define CLK_SOURCE_SBC3 0x11c
155#define CLK_SOURCE_SBC4 0x1b4
156#define CLK_SOURCE_SBC5 0x3c8
157#define CLK_SOURCE_SBC6 0x3cc
158#define CLK_SOURCE_SATA_OOB 0x420
159#define CLK_SOURCE_SATA 0x424
160#define CLK_SOURCE_NDFLASH 0x160
161#define CLK_SOURCE_NDSPEED 0x3f8
162#define CLK_SOURCE_VFIR 0x168
163#define CLK_SOURCE_SDMMC1 0x150
164#define CLK_SOURCE_SDMMC2 0x154
165#define CLK_SOURCE_SDMMC3 0x1bc
166#define CLK_SOURCE_SDMMC4 0x164
167#define CLK_SOURCE_VDE 0x1c8
168#define CLK_SOURCE_CSITE 0x1d4
169#define CLK_SOURCE_LA 0x1f8
170#define CLK_SOURCE_OWR 0x1cc
171#define CLK_SOURCE_NOR 0x1d0
172#define CLK_SOURCE_MIPI 0x174
173#define CLK_SOURCE_I2C1 0x124
174#define CLK_SOURCE_I2C2 0x198
175#define CLK_SOURCE_I2C3 0x1b8
176#define CLK_SOURCE_I2C4 0x3c4
177#define CLK_SOURCE_I2C5 0x128
178#define CLK_SOURCE_UARTA 0x178
179#define CLK_SOURCE_UARTB 0x17c
180#define CLK_SOURCE_UARTC 0x1a0
181#define CLK_SOURCE_UARTD 0x1c0
182#define CLK_SOURCE_UARTE 0x1c4
183#define CLK_SOURCE_VI 0x148
184#define CLK_SOURCE_VI_SENSOR 0x1a8
185#define CLK_SOURCE_3D 0x158
186#define CLK_SOURCE_3D2 0x3b0
187#define CLK_SOURCE_2D 0x15c
188#define CLK_SOURCE_EPP 0x16c
189#define CLK_SOURCE_MPE 0x170
190#define CLK_SOURCE_HOST1X 0x180
191#define CLK_SOURCE_CVE 0x140
192#define CLK_SOURCE_TVO 0x188
193#define CLK_SOURCE_DTV 0x1dc
194#define CLK_SOURCE_HDMI 0x18c
195#define CLK_SOURCE_TVDAC 0x194
196#define CLK_SOURCE_DISP1 0x138
197#define CLK_SOURCE_DISP2 0x13c
198#define CLK_SOURCE_DSIB 0xd0
199#define CLK_SOURCE_TSENSOR 0x3b8
200#define CLK_SOURCE_ACTMON 0x3e8
201#define CLK_SOURCE_EXTERN1 0x3ec
202#define CLK_SOURCE_EXTERN2 0x3f0
203#define CLK_SOURCE_EXTERN3 0x3f4
204#define CLK_SOURCE_I2CSLOW 0x3fc
205#define CLK_SOURCE_SE 0x42c
206#define CLK_SOURCE_MSELECT 0x3b4
207#define CLK_SOURCE_EMC 0x19c
208
209#define AUDIO_SYNC_DOUBLER 0x49c
210
211#define PMC_CTRL 0
212#define PMC_CTRL_BLINK_ENB 7
213
214#define PMC_DPD_PADS_ORIDE 0x1c
215#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
216#define PMC_BLINK_TIMER 0x40
217
218#define UTMIP_PLL_CFG2 0x488
219#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
220#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
221#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
222#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
223#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
224
225#define UTMIP_PLL_CFG1 0x484
226#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
227#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
228#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
229#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
230#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
231
232/* Tegra CPU clock and reset control regs */
233#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
234#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
235#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
236#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
237#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
238
239#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
240#define CPU_RESET(cpu) (0x1111ul << (cpu))
241
242#define CLK_RESET_CCLK_BURST 0x20
243#define CLK_RESET_CCLK_DIVIDER 0x24
244#define CLK_RESET_PLLX_BASE 0xe0
245#define CLK_RESET_PLLX_MISC 0xe4
246
247#define CLK_RESET_SOURCE_CSITE 0x1d4
248
249#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
250#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
251#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
252#define CLK_RESET_CCLK_IDLE_POLICY 1
253#define CLK_RESET_CCLK_RUN_POLICY 2
254#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
255
256#ifdef CONFIG_PM_SLEEP
257static struct cpu_clk_suspend_context {
258 u32 pllx_misc;
259 u32 pllx_base;
260
261 u32 cpu_burst;
262 u32 clk_csite_src;
263 u32 cclk_divider;
264} tegra30_cpu_clk_sctx;
265#endif
266
267static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
268
269static void __iomem *clk_base;
270static void __iomem *pmc_base;
271static unsigned long input_freq;
272
273static DEFINE_SPINLOCK(clk_doubler_lock);
274static DEFINE_SPINLOCK(clk_out_lock);
275static DEFINE_SPINLOCK(pll_div_lock);
276static DEFINE_SPINLOCK(cml_lock);
277static DEFINE_SPINLOCK(pll_d_lock);
278
279#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
280 _clk_num, _regs, _gate_flags, _clk_id) \
281 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
282 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
283 periph_clk_enb_refcnt, _gate_flags, _clk_id)
284
285#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
286 _clk_num, _regs, _gate_flags, _clk_id) \
287 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
288 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
289 _regs, _clk_num, periph_clk_enb_refcnt, \
290 _gate_flags, _clk_id)
291
292#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
293 _clk_num, _regs, _gate_flags, _clk_id) \
294 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
295 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
296 periph_clk_enb_refcnt, _gate_flags, _clk_id)
297
298#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
299 _clk_num, _regs, _gate_flags, _clk_id) \
300 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
301 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
302 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
303 _clk_id)
304
305#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
306 _clk_num, _regs, _clk_id) \
307 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
308 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \
309 _clk_num, periph_clk_enb_refcnt, 0, _clk_id)
310
311#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
312 _mux_shift, _mux_width, _clk_num, _regs, \
313 _gate_flags, _clk_id) \
314 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
315 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \
316 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
317 _clk_id)
318
319/*
320 * IDs assigned here must be in sync with DT bindings definition
321 * for Tegra30 clocks.
322 */
323enum tegra30_clk {
324 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
325 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
326 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
327 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
328 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2c_slow,
331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
332 cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, se,
336 hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, vi,
337 vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
338 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
339 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
340 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
341 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
342 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
343 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
344 i2cslow, hclk, pclk, clk_out_1_mux = 300, clk_max
345};
346
347static struct clk *clks[clk_max];
348static struct clk_onecell_data clk_data;
349
350/*
351 * Structure defining the fields for USB UTMI clocks Parameters.
352 */
353struct utmi_clk_param {
354 /* Oscillator Frequency in KHz */
355 u32 osc_frequency;
356 /* UTMIP PLL Enable Delay Count */
357 u8 enable_delay_count;
358 /* UTMIP PLL Stable count */
359 u8 stable_count;
360 /* UTMIP PLL Active delay count */
361 u8 active_delay_count;
362 /* UTMIP PLL Xtal frequency count */
363 u8 xtal_freq_count;
364};
365
366static const struct utmi_clk_param utmi_parameters[] = {
367/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
368 {13000000, 0x02, 0x33, 0x05, 0x7F},
369 {19200000, 0x03, 0x4B, 0x06, 0xBB},
370 {12000000, 0x02, 0x2F, 0x04, 0x76},
371 {26000000, 0x04, 0x66, 0x09, 0xFE},
372 {16800000, 0x03, 0x41, 0x0A, 0xA4},
373};
374
375static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
376 { 12000000, 1040000000, 520, 6, 1, 8},
377 { 13000000, 1040000000, 480, 6, 1, 8},
378 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
379 { 19200000, 1040000000, 325, 6, 1, 6},
380 { 26000000, 1040000000, 520, 13, 1, 8},
381
382 { 12000000, 832000000, 416, 6, 1, 8},
383 { 13000000, 832000000, 832, 13, 1, 8},
384 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
385 { 19200000, 832000000, 260, 6, 1, 8},
386 { 26000000, 832000000, 416, 13, 1, 8},
387
388 { 12000000, 624000000, 624, 12, 1, 8},
389 { 13000000, 624000000, 624, 13, 1, 8},
390 { 16800000, 600000000, 520, 14, 1, 8},
391 { 19200000, 624000000, 520, 16, 1, 8},
392 { 26000000, 624000000, 624, 26, 1, 8},
393
394 { 12000000, 600000000, 600, 12, 1, 8},
395 { 13000000, 600000000, 600, 13, 1, 8},
396 { 16800000, 600000000, 500, 14, 1, 8},
397 { 19200000, 600000000, 375, 12, 1, 6},
398 { 26000000, 600000000, 600, 26, 1, 8},
399
400 { 12000000, 520000000, 520, 12, 1, 8},
401 { 13000000, 520000000, 520, 13, 1, 8},
402 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
403 { 19200000, 520000000, 325, 12, 1, 6},
404 { 26000000, 520000000, 520, 26, 1, 8},
405
406 { 12000000, 416000000, 416, 12, 1, 8},
407 { 13000000, 416000000, 416, 13, 1, 8},
408 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
409 { 19200000, 416000000, 260, 12, 1, 6},
410 { 26000000, 416000000, 416, 26, 1, 8},
411 { 0, 0, 0, 0, 0, 0 },
412};
413
414static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
415 { 12000000, 666000000, 666, 12, 1, 8},
416 { 13000000, 666000000, 666, 13, 1, 8},
417 { 16800000, 666000000, 555, 14, 1, 8},
418 { 19200000, 666000000, 555, 16, 1, 8},
419 { 26000000, 666000000, 666, 26, 1, 8},
420 { 12000000, 600000000, 600, 12, 1, 8},
421 { 13000000, 600000000, 600, 13, 1, 8},
422 { 16800000, 600000000, 500, 14, 1, 8},
423 { 19200000, 600000000, 375, 12, 1, 6},
424 { 26000000, 600000000, 600, 26, 1, 8},
425 { 0, 0, 0, 0, 0, 0 },
426};
427
428static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
429 { 12000000, 216000000, 432, 12, 2, 8},
430 { 13000000, 216000000, 432, 13, 2, 8},
431 { 16800000, 216000000, 360, 14, 2, 8},
432 { 19200000, 216000000, 360, 16, 2, 8},
433 { 26000000, 216000000, 432, 26, 2, 8},
434 { 0, 0, 0, 0, 0, 0 },
435};
436
437static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
438 { 9600000, 564480000, 294, 5, 1, 4},
439 { 9600000, 552960000, 288, 5, 1, 4},
440 { 9600000, 24000000, 5, 2, 1, 1},
441
442 { 28800000, 56448000, 49, 25, 1, 1},
443 { 28800000, 73728000, 64, 25, 1, 1},
444 { 28800000, 24000000, 5, 6, 1, 1},
445 { 0, 0, 0, 0, 0, 0 },
446};
447
448static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
449 { 12000000, 216000000, 216, 12, 1, 4},
450 { 13000000, 216000000, 216, 13, 1, 4},
451 { 16800000, 216000000, 180, 14, 1, 4},
452 { 19200000, 216000000, 180, 16, 1, 4},
453 { 26000000, 216000000, 216, 26, 1, 4},
454
455 { 12000000, 594000000, 594, 12, 1, 8},
456 { 13000000, 594000000, 594, 13, 1, 8},
457 { 16800000, 594000000, 495, 14, 1, 8},
458 { 19200000, 594000000, 495, 16, 1, 8},
459 { 26000000, 594000000, 594, 26, 1, 8},
460
461 { 12000000, 1000000000, 1000, 12, 1, 12},
462 { 13000000, 1000000000, 1000, 13, 1, 12},
463 { 19200000, 1000000000, 625, 12, 1, 8},
464 { 26000000, 1000000000, 1000, 26, 1, 12},
465
466 { 0, 0, 0, 0, 0, 0 },
467};
468
469static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
470 { 12000000, 480000000, 960, 12, 2, 12},
471 { 13000000, 480000000, 960, 13, 2, 12},
472 { 16800000, 480000000, 400, 7, 2, 5},
473 { 19200000, 480000000, 200, 4, 2, 3},
474 { 26000000, 480000000, 960, 26, 2, 12},
475 { 0, 0, 0, 0, 0, 0 },
476};
477
478static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
479 /* 1.7 GHz */
480 { 12000000, 1700000000, 850, 6, 1, 8},
481 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
482 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
483 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
484 { 26000000, 1700000000, 850, 13, 1, 8},
485
486 /* 1.6 GHz */
487 { 12000000, 1600000000, 800, 6, 1, 8},
488 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
489 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
490 { 19200000, 1600000000, 500, 6, 1, 8},
491 { 26000000, 1600000000, 800, 13, 1, 8},
492
493 /* 1.5 GHz */
494 { 12000000, 1500000000, 750, 6, 1, 8},
495 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
496 { 16800000, 1500000000, 625, 7, 1, 8},
497 { 19200000, 1500000000, 625, 8, 1, 8},
498 { 26000000, 1500000000, 750, 13, 1, 8},
499
500 /* 1.4 GHz */
501 { 12000000, 1400000000, 700, 6, 1, 8},
502 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
503 { 16800000, 1400000000, 1000, 12, 1, 8},
504 { 19200000, 1400000000, 875, 12, 1, 8},
505 { 26000000, 1400000000, 700, 13, 1, 8},
506
507 /* 1.3 GHz */
508 { 12000000, 1300000000, 975, 9, 1, 8},
509 { 13000000, 1300000000, 1000, 10, 1, 8},
510 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
511 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
512 { 26000000, 1300000000, 650, 13, 1, 8},
513
514 /* 1.2 GHz */
515 { 12000000, 1200000000, 1000, 10, 1, 8},
516 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
517 { 16800000, 1200000000, 1000, 14, 1, 8},
518 { 19200000, 1200000000, 1000, 16, 1, 8},
519 { 26000000, 1200000000, 600, 13, 1, 8},
520
521 /* 1.1 GHz */
522 { 12000000, 1100000000, 825, 9, 1, 8},
523 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
524 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
525 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
526 { 26000000, 1100000000, 550, 13, 1, 8},
527
528 /* 1 GHz */
529 { 12000000, 1000000000, 1000, 12, 1, 8},
530 { 13000000, 1000000000, 1000, 13, 1, 8},
531 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
532 { 19200000, 1000000000, 625, 12, 1, 8},
533 { 26000000, 1000000000, 1000, 26, 1, 8},
534
535 { 0, 0, 0, 0, 0, 0 },
536};
537
538static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
539 /* PLLE special case: use cpcon field to store cml divider value */
540 { 12000000, 100000000, 150, 1, 18, 11},
541 { 216000000, 100000000, 200, 18, 24, 13},
542 { 0, 0, 0, 0, 0, 0 },
543};
544
545/* PLL parameters */
546static struct tegra_clk_pll_params pll_c_params = {
547 .input_min = 2000000,
548 .input_max = 31000000,
549 .cf_min = 1000000,
550 .cf_max = 6000000,
551 .vco_min = 20000000,
552 .vco_max = 1400000000,
553 .base_reg = PLLC_BASE,
554 .misc_reg = PLLC_MISC,
555 .lock_bit_idx = PLL_BASE_LOCK,
556 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
557 .lock_delay = 300,
558};
559
560static struct tegra_clk_pll_params pll_m_params = {
561 .input_min = 2000000,
562 .input_max = 31000000,
563 .cf_min = 1000000,
564 .cf_max = 6000000,
565 .vco_min = 20000000,
566 .vco_max = 1200000000,
567 .base_reg = PLLM_BASE,
568 .misc_reg = PLLM_MISC,
569 .lock_bit_idx = PLL_BASE_LOCK,
570 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
571 .lock_delay = 300,
572};
573
574static struct tegra_clk_pll_params pll_p_params = {
575 .input_min = 2000000,
576 .input_max = 31000000,
577 .cf_min = 1000000,
578 .cf_max = 6000000,
579 .vco_min = 20000000,
580 .vco_max = 1400000000,
581 .base_reg = PLLP_BASE,
582 .misc_reg = PLLP_MISC,
583 .lock_bit_idx = PLL_BASE_LOCK,
584 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
585 .lock_delay = 300,
586};
587
588static struct tegra_clk_pll_params pll_a_params = {
589 .input_min = 2000000,
590 .input_max = 31000000,
591 .cf_min = 1000000,
592 .cf_max = 6000000,
593 .vco_min = 20000000,
594 .vco_max = 1400000000,
595 .base_reg = PLLA_BASE,
596 .misc_reg = PLLA_MISC,
597 .lock_bit_idx = PLL_BASE_LOCK,
598 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
599 .lock_delay = 300,
600};
601
602static struct tegra_clk_pll_params pll_d_params = {
603 .input_min = 2000000,
604 .input_max = 40000000,
605 .cf_min = 1000000,
606 .cf_max = 6000000,
607 .vco_min = 40000000,
608 .vco_max = 1000000000,
609 .base_reg = PLLD_BASE,
610 .misc_reg = PLLD_MISC,
611 .lock_bit_idx = PLL_BASE_LOCK,
612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
613 .lock_delay = 1000,
614};
615
616static struct tegra_clk_pll_params pll_d2_params = {
617 .input_min = 2000000,
618 .input_max = 40000000,
619 .cf_min = 1000000,
620 .cf_max = 6000000,
621 .vco_min = 40000000,
622 .vco_max = 1000000000,
623 .base_reg = PLLD2_BASE,
624 .misc_reg = PLLD2_MISC,
625 .lock_bit_idx = PLL_BASE_LOCK,
626 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
627 .lock_delay = 1000,
628};
629
630static struct tegra_clk_pll_params pll_u_params = {
631 .input_min = 2000000,
632 .input_max = 40000000,
633 .cf_min = 1000000,
634 .cf_max = 6000000,
635 .vco_min = 48000000,
636 .vco_max = 960000000,
637 .base_reg = PLLU_BASE,
638 .misc_reg = PLLU_MISC,
639 .lock_bit_idx = PLL_BASE_LOCK,
640 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
641 .lock_delay = 1000,
642};
643
644static struct tegra_clk_pll_params pll_x_params = {
645 .input_min = 2000000,
646 .input_max = 31000000,
647 .cf_min = 1000000,
648 .cf_max = 6000000,
649 .vco_min = 20000000,
650 .vco_max = 1700000000,
651 .base_reg = PLLX_BASE,
652 .misc_reg = PLLX_MISC,
653 .lock_bit_idx = PLL_BASE_LOCK,
654 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
655 .lock_delay = 300,
656};
657
658static struct tegra_clk_pll_params pll_e_params = {
659 .input_min = 12000000,
660 .input_max = 216000000,
661 .cf_min = 12000000,
662 .cf_max = 12000000,
663 .vco_min = 1200000000,
664 .vco_max = 2400000000U,
665 .base_reg = PLLE_BASE,
666 .misc_reg = PLLE_MISC,
667 .lock_bit_idx = PLLE_MISC_LOCK,
668 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
669 .lock_delay = 300,
670};
671
672/* Peripheral clock registers */
673static struct tegra_clk_periph_regs periph_l_regs = {
674 .enb_reg = CLK_OUT_ENB_L,
675 .enb_set_reg = CLK_OUT_ENB_SET_L,
676 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
677 .rst_reg = RST_DEVICES_L,
678 .rst_set_reg = RST_DEVICES_SET_L,
679 .rst_clr_reg = RST_DEVICES_CLR_L,
680};
681
682static struct tegra_clk_periph_regs periph_h_regs = {
683 .enb_reg = CLK_OUT_ENB_H,
684 .enb_set_reg = CLK_OUT_ENB_SET_H,
685 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
686 .rst_reg = RST_DEVICES_H,
687 .rst_set_reg = RST_DEVICES_SET_H,
688 .rst_clr_reg = RST_DEVICES_CLR_H,
689};
690
691static struct tegra_clk_periph_regs periph_u_regs = {
692 .enb_reg = CLK_OUT_ENB_U,
693 .enb_set_reg = CLK_OUT_ENB_SET_U,
694 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
695 .rst_reg = RST_DEVICES_U,
696 .rst_set_reg = RST_DEVICES_SET_U,
697 .rst_clr_reg = RST_DEVICES_CLR_U,
698};
699
700static struct tegra_clk_periph_regs periph_v_regs = {
701 .enb_reg = CLK_OUT_ENB_V,
702 .enb_set_reg = CLK_OUT_ENB_SET_V,
703 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
704 .rst_reg = RST_DEVICES_V,
705 .rst_set_reg = RST_DEVICES_SET_V,
706 .rst_clr_reg = RST_DEVICES_CLR_V,
707};
708
709static struct tegra_clk_periph_regs periph_w_regs = {
710 .enb_reg = CLK_OUT_ENB_W,
711 .enb_set_reg = CLK_OUT_ENB_SET_W,
712 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
713 .rst_reg = RST_DEVICES_W,
714 .rst_set_reg = RST_DEVICES_SET_W,
715 .rst_clr_reg = RST_DEVICES_CLR_W,
716};
717
718static void tegra30_clk_measure_input_freq(void)
719{
720 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
721 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
722 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
723
724 switch (auto_clk_control) {
725 case OSC_CTRL_OSC_FREQ_12MHZ:
726 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
727 input_freq = 12000000;
728 break;
729 case OSC_CTRL_OSC_FREQ_13MHZ:
730 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
731 input_freq = 13000000;
732 break;
733 case OSC_CTRL_OSC_FREQ_19_2MHZ:
734 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
735 input_freq = 19200000;
736 break;
737 case OSC_CTRL_OSC_FREQ_26MHZ:
738 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
739 input_freq = 26000000;
740 break;
741 case OSC_CTRL_OSC_FREQ_16_8MHZ:
742 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
743 input_freq = 16800000;
744 break;
745 case OSC_CTRL_OSC_FREQ_38_4MHZ:
746 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
747 input_freq = 38400000;
748 break;
749 case OSC_CTRL_OSC_FREQ_48MHZ:
750 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
751 input_freq = 48000000;
752 break;
753 default:
754 pr_err("Unexpected auto clock control value %d",
755 auto_clk_control);
756 BUG();
757 return;
758 }
759}
760
761static unsigned int tegra30_get_pll_ref_div(void)
762{
763 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
764 OSC_CTRL_PLL_REF_DIV_MASK;
765
766 switch (pll_ref_div) {
767 case OSC_CTRL_PLL_REF_DIV_1:
768 return 1;
769 case OSC_CTRL_PLL_REF_DIV_2:
770 return 2;
771 case OSC_CTRL_PLL_REF_DIV_4:
772 return 4;
773 default:
774 pr_err("Invalid pll ref divider %d", pll_ref_div);
775 BUG();
776 }
777 return 0;
778}
779
780static void tegra30_utmi_param_configure(void)
781{
782 u32 reg;
783 int i;
784
785 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
786 if (input_freq == utmi_parameters[i].osc_frequency)
787 break;
788 }
789
790 if (i >= ARRAY_SIZE(utmi_parameters)) {
791 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
792 return;
793 }
794
795 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
796
797 /* Program UTMIP PLL stable and active counts */
798 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
799 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
800 utmi_parameters[i].stable_count);
801
802 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
803
804 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
805 utmi_parameters[i].active_delay_count);
806
807 /* Remove power downs from UTMIP PLL control bits */
808 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
809 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
810 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
811
812 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
813
814 /* Program UTMIP PLL delay and oscillator frequency counts */
815 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
816 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
817
818 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
819 utmi_parameters[i].enable_delay_count);
820
821 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
822 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
823 utmi_parameters[i].xtal_freq_count);
824
825 /* Remove power downs from UTMIP PLL control bits */
826 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
827 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
828 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
829
830 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
831}
832
833static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
834
835static void __init tegra30_pll_init(void)
836{
837 struct clk *clk;
838
839 /* PLLC */
840 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
841 0, &pll_c_params,
842 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
843 pll_c_freq_table, NULL);
844 clk_register_clkdev(clk, "pll_c", NULL);
845 clks[pll_c] = clk;
846
847 /* PLLC_OUT1 */
848 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
849 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
850 8, 8, 1, NULL);
851 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
852 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
853 0, NULL);
854 clk_register_clkdev(clk, "pll_c_out1", NULL);
855 clks[pll_c_out1] = clk;
856
857 /* PLLP */
858 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
859 408000000, &pll_p_params,
860 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
861 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
862 clk_register_clkdev(clk, "pll_p", NULL);
863 clks[pll_p] = clk;
864
865 /* PLLP_OUT1 */
866 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
867 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
868 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
869 &pll_div_lock);
870 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
871 clk_base + PLLP_OUTA, 1, 0,
872 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
873 &pll_div_lock);
874 clk_register_clkdev(clk, "pll_p_out1", NULL);
875 clks[pll_p_out1] = clk;
876
877 /* PLLP_OUT2 */
878 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
879 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
880 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
881 &pll_div_lock);
882 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
883 clk_base + PLLP_OUTA, 17, 16,
884 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
885 &pll_div_lock);
886 clk_register_clkdev(clk, "pll_p_out2", NULL);
887 clks[pll_p_out2] = clk;
888
889 /* PLLP_OUT3 */
890 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
891 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
892 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
893 &pll_div_lock);
894 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
895 clk_base + PLLP_OUTB, 1, 0,
896 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
897 &pll_div_lock);
898 clk_register_clkdev(clk, "pll_p_out3", NULL);
899 clks[pll_p_out3] = clk;
900
901 /* PLLP_OUT4 */
902 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
903 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
904 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
905 &pll_div_lock);
906 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
907 clk_base + PLLP_OUTB, 17, 16,
908 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
909 &pll_div_lock);
910 clk_register_clkdev(clk, "pll_p_out4", NULL);
911 clks[pll_p_out4] = clk;
912
913 /* PLLM */
914 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
915 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
916 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
917 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
918 pll_m_freq_table, NULL);
919 clk_register_clkdev(clk, "pll_m", NULL);
920 clks[pll_m] = clk;
921
922 /* PLLM_OUT1 */
923 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
924 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
925 8, 8, 1, NULL);
926 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
927 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
928 CLK_SET_RATE_PARENT, 0, NULL);
929 clk_register_clkdev(clk, "pll_m_out1", NULL);
930 clks[pll_m_out1] = clk;
931
932 /* PLLX */
933 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
934 0, &pll_x_params, TEGRA_PLL_HAS_CPCON |
935 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
936 pll_x_freq_table, NULL);
937 clk_register_clkdev(clk, "pll_x", NULL);
938 clks[pll_x] = clk;
939
940 /* PLLX_OUT0 */
941 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
942 CLK_SET_RATE_PARENT, 1, 2);
943 clk_register_clkdev(clk, "pll_x_out0", NULL);
944 clks[pll_x_out0] = clk;
945
946 /* PLLU */
947 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
948 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
949 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
950 pll_u_freq_table,
951 NULL);
952 clk_register_clkdev(clk, "pll_u", NULL);
953 clks[pll_u] = clk;
954
955 tegra30_utmi_param_configure();
956
957 /* PLLD */
958 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
959 0, &pll_d_params, TEGRA_PLL_HAS_CPCON |
960 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
961 pll_d_freq_table, &pll_d_lock);
962 clk_register_clkdev(clk, "pll_d", NULL);
963 clks[pll_d] = clk;
964
965 /* PLLD_OUT0 */
966 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
967 CLK_SET_RATE_PARENT, 1, 2);
968 clk_register_clkdev(clk, "pll_d_out0", NULL);
969 clks[pll_d_out0] = clk;
970
971 /* PLLD2 */
972 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
973 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON |
974 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
975 pll_d_freq_table, NULL);
976 clk_register_clkdev(clk, "pll_d2", NULL);
977 clks[pll_d2] = clk;
978
979 /* PLLD2_OUT0 */
980 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
981 CLK_SET_RATE_PARENT, 1, 2);
982 clk_register_clkdev(clk, "pll_d2_out0", NULL);
983 clks[pll_d2_out0] = clk;
984
985 /* PLLA */
986 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
987 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
988 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
989 clk_register_clkdev(clk, "pll_a", NULL);
990 clks[pll_a] = clk;
991
992 /* PLLA_OUT0 */
993 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
994 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
995 8, 8, 1, NULL);
996 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
997 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
998 CLK_SET_RATE_PARENT, 0, NULL);
999 clk_register_clkdev(clk, "pll_a_out0", NULL);
1000 clks[pll_a_out0] = clk;
1001
1002 /* PLLE */
1003 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1004 ARRAY_SIZE(pll_e_parents), 0,
1005 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1006 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1007 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
1008 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL);
1009 clk_register_clkdev(clk, "pll_e", NULL);
1010 clks[pll_e] = clk;
1011}
1012
1013static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1014 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1015static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1016 "clk_m_div4", "extern1", };
1017static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1018 "clk_m_div4", "extern2", };
1019static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1020 "clk_m_div4", "extern3", };
1021
1022static void __init tegra30_audio_clk_init(void)
1023{
1024 struct clk *clk;
1025
1026 /* spdif_in_sync */
1027 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1028 24000000);
1029 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1030 clks[spdif_in_sync] = clk;
1031
1032 /* i2s0_sync */
1033 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1034 clk_register_clkdev(clk, "i2s0_sync", NULL);
1035 clks[i2s0_sync] = clk;
1036
1037 /* i2s1_sync */
1038 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1039 clk_register_clkdev(clk, "i2s1_sync", NULL);
1040 clks[i2s1_sync] = clk;
1041
1042 /* i2s2_sync */
1043 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1044 clk_register_clkdev(clk, "i2s2_sync", NULL);
1045 clks[i2s2_sync] = clk;
1046
1047 /* i2s3_sync */
1048 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1049 clk_register_clkdev(clk, "i2s3_sync", NULL);
1050 clks[i2s3_sync] = clk;
1051
1052 /* i2s4_sync */
1053 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1054 clk_register_clkdev(clk, "i2s4_sync", NULL);
1055 clks[i2s4_sync] = clk;
1056
1057 /* vimclk_sync */
1058 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1059 clk_register_clkdev(clk, "vimclk_sync", NULL);
1060 clks[vimclk_sync] = clk;
1061
1062 /* audio0 */
1063 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1064 ARRAY_SIZE(mux_audio_sync_clk), 0,
1065 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1066 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1067 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1068 CLK_GATE_SET_TO_DISABLE, NULL);
1069 clk_register_clkdev(clk, "audio0", NULL);
1070 clks[audio0] = clk;
1071
1072 /* audio1 */
1073 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1074 ARRAY_SIZE(mux_audio_sync_clk), 0,
1075 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1076 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1077 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1078 CLK_GATE_SET_TO_DISABLE, NULL);
1079 clk_register_clkdev(clk, "audio1", NULL);
1080 clks[audio1] = clk;
1081
1082 /* audio2 */
1083 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1084 ARRAY_SIZE(mux_audio_sync_clk), 0,
1085 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1086 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1087 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1088 CLK_GATE_SET_TO_DISABLE, NULL);
1089 clk_register_clkdev(clk, "audio2", NULL);
1090 clks[audio2] = clk;
1091
1092 /* audio3 */
1093 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1094 ARRAY_SIZE(mux_audio_sync_clk), 0,
1095 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1096 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1097 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1098 CLK_GATE_SET_TO_DISABLE, NULL);
1099 clk_register_clkdev(clk, "audio3", NULL);
1100 clks[audio3] = clk;
1101
1102 /* audio4 */
1103 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1104 ARRAY_SIZE(mux_audio_sync_clk), 0,
1105 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1106 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1107 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1108 CLK_GATE_SET_TO_DISABLE, NULL);
1109 clk_register_clkdev(clk, "audio4", NULL);
1110 clks[audio4] = clk;
1111
1112 /* spdif */
1113 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1114 ARRAY_SIZE(mux_audio_sync_clk), 0,
1115 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1116 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1117 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1118 CLK_GATE_SET_TO_DISABLE, NULL);
1119 clk_register_clkdev(clk, "spdif", NULL);
1120 clks[spdif] = clk;
1121
1122 /* audio0_2x */
1123 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1124 CLK_SET_RATE_PARENT, 2, 1);
1125 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1126 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1127 &clk_doubler_lock);
1128 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1129 TEGRA_PERIPH_NO_RESET, clk_base,
1130 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1131 periph_clk_enb_refcnt);
1132 clk_register_clkdev(clk, "audio0_2x", NULL);
1133 clks[audio0_2x] = clk;
1134
1135 /* audio1_2x */
1136 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1137 CLK_SET_RATE_PARENT, 2, 1);
1138 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1139 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1140 &clk_doubler_lock);
1141 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1142 TEGRA_PERIPH_NO_RESET, clk_base,
1143 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1144 periph_clk_enb_refcnt);
1145 clk_register_clkdev(clk, "audio1_2x", NULL);
1146 clks[audio1_2x] = clk;
1147
1148 /* audio2_2x */
1149 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1150 CLK_SET_RATE_PARENT, 2, 1);
1151 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1152 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1153 &clk_doubler_lock);
1154 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1155 TEGRA_PERIPH_NO_RESET, clk_base,
1156 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1157 periph_clk_enb_refcnt);
1158 clk_register_clkdev(clk, "audio2_2x", NULL);
1159 clks[audio2_2x] = clk;
1160
1161 /* audio3_2x */
1162 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1163 CLK_SET_RATE_PARENT, 2, 1);
1164 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1165 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1166 &clk_doubler_lock);
1167 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1168 TEGRA_PERIPH_NO_RESET, clk_base,
1169 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1170 periph_clk_enb_refcnt);
1171 clk_register_clkdev(clk, "audio3_2x", NULL);
1172 clks[audio3_2x] = clk;
1173
1174 /* audio4_2x */
1175 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1176 CLK_SET_RATE_PARENT, 2, 1);
1177 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1178 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1179 &clk_doubler_lock);
1180 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1181 TEGRA_PERIPH_NO_RESET, clk_base,
1182 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1183 periph_clk_enb_refcnt);
1184 clk_register_clkdev(clk, "audio4_2x", NULL);
1185 clks[audio4_2x] = clk;
1186
1187 /* spdif_2x */
1188 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1189 CLK_SET_RATE_PARENT, 2, 1);
1190 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1191 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1192 &clk_doubler_lock);
1193 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1194 TEGRA_PERIPH_NO_RESET, clk_base,
1195 CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1196 periph_clk_enb_refcnt);
1197 clk_register_clkdev(clk, "spdif_2x", NULL);
1198 clks[spdif_2x] = clk;
1199}
1200
1201static void __init tegra30_pmc_clk_init(void)
1202{
1203 struct clk *clk;
1204
1205 /* clk_out_1 */
1206 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1207 ARRAY_SIZE(clk_out1_parents), 0,
1208 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1209 &clk_out_lock);
1210 clks[clk_out_1_mux] = clk;
1211 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1212 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1213 &clk_out_lock);
1214 clk_register_clkdev(clk, "extern1", "clk_out_1");
1215 clks[clk_out_1] = clk;
1216
1217 /* clk_out_2 */
1218 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1219 ARRAY_SIZE(clk_out1_parents), 0,
1220 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1221 &clk_out_lock);
1222 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1223 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1224 &clk_out_lock);
1225 clk_register_clkdev(clk, "extern2", "clk_out_2");
1226 clks[clk_out_2] = clk;
1227
1228 /* clk_out_3 */
1229 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1230 ARRAY_SIZE(clk_out1_parents), 0,
1231 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1232 &clk_out_lock);
1233 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1234 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1235 &clk_out_lock);
1236 clk_register_clkdev(clk, "extern3", "clk_out_3");
1237 clks[clk_out_3] = clk;
1238
1239 /* blink */
1240 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1241 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1242 pmc_base + PMC_DPD_PADS_ORIDE,
1243 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1244 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1245 pmc_base + PMC_CTRL,
1246 PMC_CTRL_BLINK_ENB, 0, NULL);
1247 clk_register_clkdev(clk, "blink", NULL);
1248 clks[blink] = clk;
1249
1250}
1251
1252const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1253 "pll_p_cclkg", "pll_p_out4_cclkg",
1254 "pll_p_out3_cclkg", "unused", "pll_x" };
1255const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1256 "pll_p_cclklp", "pll_p_out4_cclklp",
1257 "pll_p_out3_cclklp", "unused", "pll_x",
1258 "pll_x_out0" };
1259const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1260 "pll_p_out3", "pll_p_out2", "unused",
1261 "clk_32k", "pll_m_out1" };
1262
1263static void __init tegra30_super_clk_init(void)
1264{
1265 struct clk *clk;
1266
1267 /*
1268 * Clock input to cclk_g divided from pll_p using
1269 * U71 divider of cclk_g.
1270 */
1271 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1272 clk_base + SUPER_CCLKG_DIVIDER, 0,
1273 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1274 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1275
1276 /*
1277 * Clock input to cclk_g divided from pll_p_out3 using
1278 * U71 divider of cclk_g.
1279 */
1280 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1281 clk_base + SUPER_CCLKG_DIVIDER, 0,
1282 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1283 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1284
1285 /*
1286 * Clock input to cclk_g divided from pll_p_out4 using
1287 * U71 divider of cclk_g.
1288 */
1289 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1290 clk_base + SUPER_CCLKG_DIVIDER, 0,
1291 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1292 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1293
1294 /* CCLKG */
1295 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1296 ARRAY_SIZE(cclk_g_parents),
1297 CLK_SET_RATE_PARENT,
1298 clk_base + CCLKG_BURST_POLICY,
1299 0, 4, 0, 0, NULL);
1300 clk_register_clkdev(clk, "cclk_g", NULL);
1301 clks[cclk_g] = clk;
1302
1303 /*
1304 * Clock input to cclk_lp divided from pll_p using
1305 * U71 divider of cclk_lp.
1306 */
1307 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1308 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1309 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1310 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1311
1312 /*
1313 * Clock input to cclk_lp divided from pll_p_out3 using
1314 * U71 divider of cclk_lp.
1315 */
1316 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1317 clk_base + SUPER_CCLKG_DIVIDER, 0,
1318 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1319 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1320
1321 /*
1322 * Clock input to cclk_lp divided from pll_p_out4 using
1323 * U71 divider of cclk_lp.
1324 */
1325 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1326 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1327 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1328 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1329
1330 /* CCLKLP */
1331 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1332 ARRAY_SIZE(cclk_lp_parents),
1333 CLK_SET_RATE_PARENT,
1334 clk_base + CCLKLP_BURST_POLICY,
1335 TEGRA_DIVIDER_2, 4, 8, 9,
1336 NULL);
1337 clk_register_clkdev(clk, "cclk_lp", NULL);
1338 clks[cclk_lp] = clk;
1339
1340 /* SCLK */
1341 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1342 ARRAY_SIZE(sclk_parents),
1343 CLK_SET_RATE_PARENT,
1344 clk_base + SCLK_BURST_POLICY,
1345 0, 4, 0, 0, NULL);
1346 clk_register_clkdev(clk, "sclk", NULL);
1347 clks[sclk] = clk;
1348
1349 /* HCLK */
1350 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1351 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
1352 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1353 clk_base + SYSTEM_CLK_RATE, 7,
1354 CLK_GATE_SET_TO_DISABLE, NULL);
1355 clk_register_clkdev(clk, "hclk", NULL);
1356 clks[hclk] = clk;
1357
1358 /* PCLK */
1359 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1360 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
1361 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1362 clk_base + SYSTEM_CLK_RATE, 3,
1363 CLK_GATE_SET_TO_DISABLE, NULL);
1364 clk_register_clkdev(clk, "pclk", NULL);
1365 clks[pclk] = clk;
1366
1367 /* twd */
1368 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1369 CLK_SET_RATE_PARENT, 1, 2);
1370 clk_register_clkdev(clk, "twd", NULL);
1371 clks[twd] = clk;
1372}
1373
1374static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1375 "clk_m" };
1376static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1377static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1378static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1379 "clk_m" };
1380static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1381 "clk_m" };
1382static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1383 "clk_m" };
1384static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1385 "clk_m" };
1386static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1387 "clk_m" };
1388static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1389 "clk_m" };
1390static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1391static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1392 "clk_m" };
1393static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1394 "clk_32k" };
1395static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1396static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1397 "clk_m" };
1398static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1399static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1400 "pll_a_out0", "pll_c",
1401 "pll_d2_out0", "clk_m" };
1402static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1403 "clk_32k", "pll_p",
1404 "clk_m", "pll_e" };
1405static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1406 "pll_d2_out0" };
1407
1408static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1409 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1410 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1411 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1412 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1413 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1414 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1415 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1416 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio),
1417 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0),
1418 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1),
1419 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2),
1420 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda),
1421 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x),
1422 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1423 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1424 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1425 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1426 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1427 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1428 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1429 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1430 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1431 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1432 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1433 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1434 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1435 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1436 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1437 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1438 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1439 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1440 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1441 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1442 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
1443 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1444 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1445 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1446 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
1447 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se),
1448 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect),
1449 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1450 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1451 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1452 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1453 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1454 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
1455 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
1456 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
1457 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1458 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1459 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1460 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1461 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1462 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1463 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1464 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1465 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1466 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1467 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1468 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte),
1469 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1470 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1471 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1472 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1473 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1474};
1475
1476static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1477 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1),
1478 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2),
1479 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib),
1480};
1481
1482static void __init tegra30_periph_clk_init(void)
1483{
1484 struct tegra_periph_init_data *data;
1485 struct clk *clk;
1486 int i;
1487
1488 /* apbdma */
1489 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1490 &periph_h_regs, periph_clk_enb_refcnt);
1491 clk_register_clkdev(clk, NULL, "tegra-apbdma");
1492 clks[apbdma] = clk;
1493
1494 /* rtc */
1495 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1496 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1497 clk_base, 0, 4, &periph_l_regs,
1498 periph_clk_enb_refcnt);
1499 clk_register_clkdev(clk, NULL, "rtc-tegra");
1500 clks[rtc] = clk;
1501
1502 /* timer */
1503 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1504 5, &periph_l_regs, periph_clk_enb_refcnt);
1505 clk_register_clkdev(clk, NULL, "timer");
1506 clks[timer] = clk;
1507
1508 /* kbc */
1509 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1510 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1511 clk_base, 0, 36, &periph_h_regs,
1512 periph_clk_enb_refcnt);
1513 clk_register_clkdev(clk, NULL, "tegra-kbc");
1514 clks[kbc] = clk;
1515
1516 /* csus */
1517 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1518 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1519 clk_base, 0, 92, &periph_u_regs,
1520 periph_clk_enb_refcnt);
1521 clk_register_clkdev(clk, "csus", "tengra_camera");
1522 clks[csus] = clk;
1523
1524 /* vcp */
1525 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1526 &periph_l_regs, periph_clk_enb_refcnt);
1527 clk_register_clkdev(clk, "vcp", "tegra-avp");
1528 clks[vcp] = clk;
1529
1530 /* bsea */
1531 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1532 62, &periph_h_regs, periph_clk_enb_refcnt);
1533 clk_register_clkdev(clk, "bsea", "tegra-avp");
1534 clks[bsea] = clk;
1535
1536 /* bsev */
1537 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1538 63, &periph_h_regs, periph_clk_enb_refcnt);
1539 clk_register_clkdev(clk, "bsev", "tegra-aes");
1540 clks[bsev] = clk;
1541
1542 /* usbd */
1543 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1544 22, &periph_l_regs, periph_clk_enb_refcnt);
1545 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1546 clks[usbd] = clk;
1547
1548 /* usb2 */
1549 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1550 58, &periph_h_regs, periph_clk_enb_refcnt);
1551 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1552 clks[usb2] = clk;
1553
1554 /* usb3 */
1555 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1556 59, &periph_h_regs, periph_clk_enb_refcnt);
1557 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1558 clks[usb3] = clk;
1559
1560 /* dsia */
1561 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1562 0, 48, &periph_h_regs,
1563 periph_clk_enb_refcnt);
1564 clk_register_clkdev(clk, "dsia", "tegradc.0");
1565 clks[dsia] = clk;
1566
1567 /* csi */
1568 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1569 0, 52, &periph_h_regs,
1570 periph_clk_enb_refcnt);
1571 clk_register_clkdev(clk, "csi", "tegra_camera");
1572 clks[csi] = clk;
1573
1574 /* isp */
1575 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1576 &periph_l_regs, periph_clk_enb_refcnt);
1577 clk_register_clkdev(clk, "isp", "tegra_camera");
1578 clks[isp] = clk;
1579
1580 /* pcie */
1581 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1582 70, &periph_u_regs, periph_clk_enb_refcnt);
1583 clk_register_clkdev(clk, "pcie", "tegra-pcie");
1584 clks[pcie] = clk;
1585
1586 /* afi */
1587 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1588 &periph_u_regs, periph_clk_enb_refcnt);
1589 clk_register_clkdev(clk, "afi", "tegra-pcie");
1590 clks[afi] = clk;
1591
1592 /* kfuse */
1593 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1594 TEGRA_PERIPH_ON_APB,
1595 clk_base, 0, 40, &periph_h_regs,
1596 periph_clk_enb_refcnt);
1597 clk_register_clkdev(clk, NULL, "kfuse-tegra");
1598 clks[kfuse] = clk;
1599
1600 /* fuse */
1601 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1602 TEGRA_PERIPH_ON_APB,
1603 clk_base, 0, 39, &periph_h_regs,
1604 periph_clk_enb_refcnt);
1605 clk_register_clkdev(clk, "fuse", "fuse-tegra");
1606 clks[fuse] = clk;
1607
1608 /* fuse_burn */
1609 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1610 TEGRA_PERIPH_ON_APB,
1611 clk_base, 0, 39, &periph_h_regs,
1612 periph_clk_enb_refcnt);
1613 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1614 clks[fuse_burn] = clk;
1615
1616 /* apbif */
1617 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1618 clk_base, 0, 107, &periph_v_regs,
1619 periph_clk_enb_refcnt);
1620 clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1621 clks[apbif] = clk;
1622
1623 /* hda2hdmi */
1624 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1625 TEGRA_PERIPH_ON_APB,
1626 clk_base, 0, 128, &periph_w_regs,
1627 periph_clk_enb_refcnt);
1628 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1629 clks[hda2hdmi] = clk;
1630
1631 /* sata_cold */
1632 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1633 TEGRA_PERIPH_ON_APB,
1634 clk_base, 0, 129, &periph_w_regs,
1635 periph_clk_enb_refcnt);
1636 clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1637 clks[sata_cold] = clk;
1638
1639 /* dtv */
1640 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1641 TEGRA_PERIPH_ON_APB,
1642 clk_base, 0, 79, &periph_u_regs,
1643 periph_clk_enb_refcnt);
1644 clk_register_clkdev(clk, NULL, "dtv");
1645 clks[dtv] = clk;
1646
1647 /* emc */
1648 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1649 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1650 clk_base + CLK_SOURCE_EMC,
1651 30, 2, 0, NULL);
1652 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1653 57, &periph_h_regs, periph_clk_enb_refcnt);
1654 clk_register_clkdev(clk, "emc", NULL);
1655 clks[emc] = clk;
1656
1657 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1658 data = &tegra_periph_clk_list[i];
1659 clk = tegra_clk_register_periph(data->name, data->parent_names,
1660 data->num_parents, &data->periph,
1661 clk_base, data->offset);
1662 clk_register_clkdev(clk, data->con_id, data->dev_id);
1663 clks[data->clk_id] = clk;
1664 }
1665
1666 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1667 data = &tegra_periph_nodiv_clk_list[i];
1668 clk = tegra_clk_register_periph_nodiv(data->name,
1669 data->parent_names,
1670 data->num_parents, &data->periph,
1671 clk_base, data->offset);
1672 clk_register_clkdev(clk, data->con_id, data->dev_id);
1673 clks[data->clk_id] = clk;
1674 }
1675}
1676
1677static void __init tegra30_fixed_clk_init(void)
1678{
1679 struct clk *clk;
1680
1681 /* clk_32k */
1682 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1683 32768);
1684 clk_register_clkdev(clk, "clk_32k", NULL);
1685 clks[clk_32k] = clk;
1686
1687 /* clk_m_div2 */
1688 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1689 CLK_SET_RATE_PARENT, 1, 2);
1690 clk_register_clkdev(clk, "clk_m_div2", NULL);
1691 clks[clk_m_div2] = clk;
1692
1693 /* clk_m_div4 */
1694 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1695 CLK_SET_RATE_PARENT, 1, 4);
1696 clk_register_clkdev(clk, "clk_m_div4", NULL);
1697 clks[clk_m_div4] = clk;
1698
1699 /* cml0 */
1700 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1701 0, 0, &cml_lock);
1702 clk_register_clkdev(clk, "cml0", NULL);
1703 clks[cml0] = clk;
1704
1705 /* cml1 */
1706 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1707 1, 0, &cml_lock);
1708 clk_register_clkdev(clk, "cml1", NULL);
1709 clks[cml1] = clk;
1710
1711 /* pciex */
1712 clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
1713 clk_register_clkdev(clk, "pciex", NULL);
1714 clks[pciex] = clk;
1715}
1716
1717static void __init tegra30_osc_clk_init(void)
1718{
1719 struct clk *clk;
1720 unsigned int pll_ref_div;
1721
1722 tegra30_clk_measure_input_freq();
1723
1724 /* clk_m */
1725 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1726 input_freq);
1727 clk_register_clkdev(clk, "clk_m", NULL);
1728 clks[clk_m] = clk;
1729
1730 /* pll_ref */
1731 pll_ref_div = tegra30_get_pll_ref_div();
1732 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1733 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1734 clk_register_clkdev(clk, "pll_ref", NULL);
1735 clks[pll_ref] = clk;
1736}
1737
1738/* Tegra30 CPU clock and reset control functions */
1739static void tegra30_wait_cpu_in_reset(u32 cpu)
1740{
1741 unsigned int reg;
1742
1743 do {
1744 reg = readl(clk_base +
1745 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1746 cpu_relax();
1747 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1748
1749 return;
1750}
1751
1752static void tegra30_put_cpu_in_reset(u32 cpu)
1753{
1754 writel(CPU_RESET(cpu),
1755 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1756 dmb();
1757}
1758
1759static void tegra30_cpu_out_of_reset(u32 cpu)
1760{
1761 writel(CPU_RESET(cpu),
1762 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1763 wmb();
1764}
1765
1766
1767static void tegra30_enable_cpu_clock(u32 cpu)
1768{
1769 unsigned int reg;
1770
1771 writel(CPU_CLOCK(cpu),
1772 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1773 reg = readl(clk_base +
1774 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1775}
1776
1777static void tegra30_disable_cpu_clock(u32 cpu)
1778{
1779
1780 unsigned int reg;
1781
1782 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1783 writel(reg | CPU_CLOCK(cpu),
1784 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1785}
1786
1787#ifdef CONFIG_PM_SLEEP
1788static bool tegra30_cpu_rail_off_ready(void)
1789{
1790 unsigned int cpu_rst_status;
1791 int cpu_pwr_status;
1792
1793 cpu_rst_status = readl(clk_base +
1794 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1795 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1796 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1797 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1798
1799 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1800 return false;
1801
1802 return true;
1803}
1804
1805static void tegra30_cpu_clock_suspend(void)
1806{
1807 /* switch coresite to clk_m, save off original source */
1808 tegra30_cpu_clk_sctx.clk_csite_src =
1809 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1810 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1811
1812 tegra30_cpu_clk_sctx.cpu_burst =
1813 readl(clk_base + CLK_RESET_CCLK_BURST);
1814 tegra30_cpu_clk_sctx.pllx_base =
1815 readl(clk_base + CLK_RESET_PLLX_BASE);
1816 tegra30_cpu_clk_sctx.pllx_misc =
1817 readl(clk_base + CLK_RESET_PLLX_MISC);
1818 tegra30_cpu_clk_sctx.cclk_divider =
1819 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1820}
1821
1822static void tegra30_cpu_clock_resume(void)
1823{
1824 unsigned int reg, policy;
1825
1826 /* Is CPU complex already running on PLLX? */
1827 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1828 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1829
1830 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1831 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1832 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1833 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1834 else
1835 BUG();
1836
1837 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1838 /* restore PLLX settings if CPU is on different PLL */
1839 writel(tegra30_cpu_clk_sctx.pllx_misc,
1840 clk_base + CLK_RESET_PLLX_MISC);
1841 writel(tegra30_cpu_clk_sctx.pllx_base,
1842 clk_base + CLK_RESET_PLLX_BASE);
1843
1844 /* wait for PLL stabilization if PLLX was enabled */
1845 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1846 udelay(300);
1847 }
1848
1849 /*
1850 * Restore original burst policy setting for calls resulting from CPU
1851 * LP2 in idle or system suspend.
1852 */
1853 writel(tegra30_cpu_clk_sctx.cclk_divider,
1854 clk_base + CLK_RESET_CCLK_DIVIDER);
1855 writel(tegra30_cpu_clk_sctx.cpu_burst,
1856 clk_base + CLK_RESET_CCLK_BURST);
1857
1858 writel(tegra30_cpu_clk_sctx.clk_csite_src,
1859 clk_base + CLK_RESET_SOURCE_CSITE);
1860}
1861#endif
1862
1863static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1864 .wait_for_reset = tegra30_wait_cpu_in_reset,
1865 .put_in_reset = tegra30_put_cpu_in_reset,
1866 .out_of_reset = tegra30_cpu_out_of_reset,
1867 .enable_clock = tegra30_enable_cpu_clock,
1868 .disable_clock = tegra30_disable_cpu_clock,
1869#ifdef CONFIG_PM_SLEEP
1870 .rail_off_ready = tegra30_cpu_rail_off_ready,
1871 .suspend = tegra30_cpu_clock_suspend,
1872 .resume = tegra30_cpu_clock_resume,
1873#endif
1874};
1875
1876static __initdata struct tegra_clk_init_table init_table[] = {
1877 {uarta, pll_p, 408000000, 1},
1878 {pll_a, clk_max, 564480000, 1},
1879 {pll_a_out0, clk_max, 11289600, 1},
1880 {extern1, pll_a_out0, 0, 1},
1881 {clk_out_1_mux, extern1, 0, 0},
1882 {clk_out_1, clk_max, 0, 1},
1883 {blink, clk_max, 0, 1},
1884 {i2s0, pll_a_out0, 11289600, 0},
1885 {i2s1, pll_a_out0, 11289600, 0},
1886 {i2s2, pll_a_out0, 11289600, 0},
1887 {i2s3, pll_a_out0, 11289600, 0},
1888 {i2s4, pll_a_out0, 11289600, 0},
1889 {sdmmc1, pll_p, 48000000, 0},
1890 {sdmmc2, pll_p, 48000000, 0},
1891 {sdmmc3, pll_p, 48000000, 0},
1892 {pll_m, clk_max, 0, 1},
1893 {pclk, clk_max, 0, 1},
1894 {csite, clk_max, 0, 1},
1895 {emc, clk_max, 0, 1},
1896 {mselect, clk_max, 0, 1},
1897 {sbc1, pll_p, 100000000, 0},
1898 {sbc2, pll_p, 100000000, 0},
1899 {sbc3, pll_p, 100000000, 0},
1900 {sbc4, pll_p, 100000000, 0},
1901 {sbc5, pll_p, 100000000, 0},
1902 {sbc6, pll_p, 100000000, 0},
1903 {host1x, pll_c, 150000000, 0},
1904 {disp1, pll_p, 600000000, 0},
1905 {disp2, pll_p, 600000000, 0},
1906 {twd, clk_max, 0, 1},
1907 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1908};
1909
1910/*
1911 * Some clocks may be used by different drivers depending on the board
1912 * configuration. List those here to register them twice in the clock lookup
1913 * table under two names.
1914 */
1915static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1916 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1917 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1918 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1919 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"),
1920 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"),
1921 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"),
1922 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"),
1923 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
1924 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
1925 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
1926 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
1927 TEGRA_CLK_DUPLICATE(twd, "smp_twd", NULL),
1928 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
1929 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
1930};
1931
1932static const struct of_device_id pmc_match[] __initconst = {
1933 { .compatible = "nvidia,tegra30-pmc" },
1934 {},
1935};
1936
1937void __init tegra30_clock_init(struct device_node *np)
1938{
1939 struct device_node *node;
1940 int i;
1941
1942 clk_base = of_iomap(np, 0);
1943 if (!clk_base) {
1944 pr_err("ioremap tegra30 CAR failed\n");
1945 return;
1946 }
1947
1948 node = of_find_matching_node(NULL, pmc_match);
1949 if (!node) {
1950 pr_err("Failed to find pmc node\n");
1951 BUG();
1952 }
1953
1954 pmc_base = of_iomap(node, 0);
1955 if (!pmc_base) {
1956 pr_err("Can't map pmc registers\n");
1957 BUG();
1958 }
1959
1960 tegra30_osc_clk_init();
1961 tegra30_fixed_clk_init();
1962 tegra30_pll_init();
1963 tegra30_super_clk_init();
1964 tegra30_periph_clk_init();
1965 tegra30_audio_clk_init();
1966 tegra30_pmc_clk_init();
1967
1968 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1969 if (IS_ERR(clks[i])) {
1970 pr_err("Tegra30 clk %d: register failed with %ld\n",
1971 i, PTR_ERR(clks[i]));
1972 BUG();
1973 }
1974 if (!clks[i])
1975 clks[i] = ERR_PTR(-EINVAL);
1976 }
1977
1978 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1979
1980 clk_data.clks = clks;
1981 clk_data.clk_num = ARRAY_SIZE(clks);
1982 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1983
1984 tegra_init_from_table(init_table, clks, clk_max);
1985
1986 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1987}
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
new file mode 100644
index 000000000000..a603b9af0ad3
--- /dev/null
+++ b/drivers/clk/tegra/clk.c
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/of.h>
20#include <linux/clk/tegra.h>
21
22#include "clk.h"
23
24/* Global data of Tegra CPU CAR ops */
25struct tegra_cpu_car_ops *tegra_cpu_car_ops;
26
27void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
28 struct clk *clks[], int clk_max)
29{
30 struct clk *clk;
31
32 for (; dup_list->clk_id < clk_max; dup_list++) {
33 clk = clks[dup_list->clk_id];
34 dup_list->lookup.clk = clk;
35 clkdev_add(&dup_list->lookup);
36 }
37}
38
39void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
40 struct clk *clks[], int clk_max)
41{
42 struct clk *clk;
43
44 for (; tbl->clk_id < clk_max; tbl++) {
45 clk = clks[tbl->clk_id];
46 if (IS_ERR_OR_NULL(clk))
47 return;
48
49 if (tbl->parent_id < clk_max) {
50 struct clk *parent = clks[tbl->parent_id];
51 if (clk_set_parent(clk, parent)) {
52 pr_err("%s: Failed to set parent %s of %s\n",
53 __func__, __clk_get_name(parent),
54 __clk_get_name(clk));
55 WARN_ON(1);
56 }
57 }
58
59 if (tbl->rate)
60 if (clk_set_rate(clk, tbl->rate)) {
61 pr_err("%s: Failed to set rate %lu of %s\n",
62 __func__, tbl->rate,
63 __clk_get_name(clk));
64 WARN_ON(1);
65 }
66
67 if (tbl->state)
68 if (clk_prepare_enable(clk)) {
69 pr_err("%s: Failed to enable %s\n", __func__,
70 __clk_get_name(clk));
71 WARN_ON(1);
72 }
73 }
74}
75
76static const struct of_device_id tegra_dt_clk_match[] = {
77 { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
78 { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
79 { }
80};
81
82void __init tegra_clocks_init(void)
83{
84 of_clk_init(tegra_dt_clk_match);
85}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
new file mode 100644
index 000000000000..0744731c6229
--- /dev/null
+++ b/drivers/clk/tegra/clk.h
@@ -0,0 +1,502 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __TEGRA_CLK_H
18#define __TEGRA_CLK_H
19
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22
23/**
24 * struct tegra_clk_sync_source - external clock source from codec
25 *
26 * @hw: handle between common and hardware-specific interfaces
27 * @rate: input frequency from source
28 * @max_rate: max rate allowed
29 */
30struct tegra_clk_sync_source {
31 struct clk_hw hw;
32 unsigned long rate;
33 unsigned long max_rate;
34};
35
36#define to_clk_sync_source(_hw) \
37 container_of(_hw, struct tegra_clk_sync_source, hw)
38
39extern const struct clk_ops tegra_clk_sync_source_ops;
40struct clk *tegra_clk_register_sync_source(const char *name,
41 unsigned long fixed_rate, unsigned long max_rate);
42
43/**
44 * struct tegra_clk_frac_div - fractional divider clock
45 *
46 * @hw: handle between common and hardware-specific interfaces
47 * @reg: register containing divider
48 * @flags: hardware-specific flags
49 * @shift: shift to the divider bit field
50 * @width: width of the divider bit field
51 * @frac_width: width of the fractional bit field
52 * @lock: register lock
53 *
54 * Flags:
55 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
56 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
57 * flag indicates that this divider is for fixed rate PLL.
58 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
59 * fraction bit is set. This flags indicates to calculate divider for which
60 * fracton bit will be zero.
61 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
62 * set when divider value is not 0. This flags indicates that the divider
63 * is for UART module.
64 */
65struct tegra_clk_frac_div {
66 struct clk_hw hw;
67 void __iomem *reg;
68 u8 flags;
69 u8 shift;
70 u8 width;
71 u8 frac_width;
72 spinlock_t *lock;
73};
74
75#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
76
77#define TEGRA_DIVIDER_ROUND_UP BIT(0)
78#define TEGRA_DIVIDER_FIXED BIT(1)
79#define TEGRA_DIVIDER_INT BIT(2)
80#define TEGRA_DIVIDER_UART BIT(3)
81
82extern const struct clk_ops tegra_clk_frac_div_ops;
83struct clk *tegra_clk_register_divider(const char *name,
84 const char *parent_name, void __iomem *reg,
85 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
86 u8 frac_width, spinlock_t *lock);
87
88/*
89 * Tegra PLL:
90 *
91 * In general, there are 3 requirements for each PLL
92 * that SW needs to be comply with.
93 * (1) Input frequency range (REF).
94 * (2) Comparison frequency range (CF). CF = REF/DIVM.
95 * (3) VCO frequency range (VCO). VCO = CF * DIVN.
96 *
97 * The final PLL output frequency (FO) = VCO >> DIVP.
98 */
99
100/**
101 * struct tegra_clk_pll_freq_table - PLL frequecy table
102 *
103 * @input_rate: input rate from source
104 * @output_rate: output rate from PLL for the input rate
105 * @n: feedback divider
106 * @m: input divider
107 * @p: post divider
108 * @cpcon: charge pump current
109 */
110struct tegra_clk_pll_freq_table {
111 unsigned long input_rate;
112 unsigned long output_rate;
113 u16 n;
114 u16 m;
115 u8 p;
116 u8 cpcon;
117};
118
119/**
120 * struct clk_pll_params - PLL parameters
121 *
122 * @input_min: Minimum input frequency
123 * @input_max: Maximum input frequency
124 * @cf_min: Minimum comparison frequency
125 * @cf_max: Maximum comparison frequency
126 * @vco_min: Minimum VCO frequency
127 * @vco_max: Maximum VCO frequency
128 * @base_reg: PLL base reg offset
129 * @misc_reg: PLL misc reg offset
130 * @lock_reg: PLL lock reg offset
131 * @lock_bit_idx: Bit index for PLL lock status
132 * @lock_enable_bit_idx: Bit index to enable PLL lock
133 * @lock_delay: Delay in us if PLL lock is not used
134 */
135struct tegra_clk_pll_params {
136 unsigned long input_min;
137 unsigned long input_max;
138 unsigned long cf_min;
139 unsigned long cf_max;
140 unsigned long vco_min;
141 unsigned long vco_max;
142
143 u32 base_reg;
144 u32 misc_reg;
145 u32 lock_reg;
146 u32 lock_bit_idx;
147 u32 lock_enable_bit_idx;
148 int lock_delay;
149};
150
151/**
152 * struct tegra_clk_pll - Tegra PLL clock
153 *
154 * @hw: handle between common and hardware-specifix interfaces
155 * @clk_base: address of CAR controller
156 * @pmc: address of PMC, required to read override bits
157 * @freq_table: array of frequencies supported by PLL
158 * @params: PLL parameters
159 * @flags: PLL flags
160 * @fixed_rate: PLL rate if it is fixed
161 * @lock: register lock
162 * @divn_shift: shift to the feedback divider bit field
163 * @divn_width: width of the feedback divider bit field
164 * @divm_shift: shift to the input divider bit field
165 * @divm_width: width of the input divider bit field
166 * @divp_shift: shift to the post divider bit field
167 * @divp_width: width of the post divider bit field
168 *
169 * Flags:
170 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
171 * PLL locking. If not set it will use lock_delay value to wait.
172 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
173 * to be programmed to change output frequency of the PLL.
174 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
175 * to be programmed to change output frequency of the PLL.
176 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
177 * to be programmed to change output frequency of the PLL.
178 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
179 * that it is PLLU and invert post divider value.
180 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
181 * flag indicates that it is PLLM and use override settings.
182 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
183 * of some plls.
184 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
185 */
186struct tegra_clk_pll {
187 struct clk_hw hw;
188 void __iomem *clk_base;
189 void __iomem *pmc;
190 u8 flags;
191 unsigned long fixed_rate;
192 spinlock_t *lock;
193 u8 divn_shift;
194 u8 divn_width;
195 u8 divm_shift;
196 u8 divm_width;
197 u8 divp_shift;
198 u8 divp_width;
199 struct tegra_clk_pll_freq_table *freq_table;
200 struct tegra_clk_pll_params *params;
201};
202
203#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
204
205#define TEGRA_PLL_USE_LOCK BIT(0)
206#define TEGRA_PLL_HAS_CPCON BIT(1)
207#define TEGRA_PLL_SET_LFCON BIT(2)
208#define TEGRA_PLL_SET_DCCON BIT(3)
209#define TEGRA_PLLU BIT(4)
210#define TEGRA_PLLM BIT(5)
211#define TEGRA_PLL_FIXED BIT(6)
212#define TEGRA_PLLE_CONFIGURE BIT(7)
213
214extern const struct clk_ops tegra_clk_pll_ops;
215extern const struct clk_ops tegra_clk_plle_ops;
216struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
217 void __iomem *clk_base, void __iomem *pmc,
218 unsigned long flags, unsigned long fixed_rate,
219 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
220 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
221struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
222 void __iomem *clk_base, void __iomem *pmc,
223 unsigned long flags, unsigned long fixed_rate,
224 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
225 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
226
227/**
228 * struct tegra_clk_pll_out - PLL divider down clock
229 *
230 * @hw: handle between common and hardware-specific interfaces
231 * @reg: register containing the PLL divider
232 * @enb_bit_idx: bit to enable/disable PLL divider
233 * @rst_bit_idx: bit to reset PLL divider
234 * @lock: register lock
235 * @flags: hardware-specific flags
236 */
237struct tegra_clk_pll_out {
238 struct clk_hw hw;
239 void __iomem *reg;
240 u8 enb_bit_idx;
241 u8 rst_bit_idx;
242 spinlock_t *lock;
243 u8 flags;
244};
245
246#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
247
248extern const struct clk_ops tegra_clk_pll_out_ops;
249struct clk *tegra_clk_register_pll_out(const char *name,
250 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
251 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
252 spinlock_t *lock);
253
254/**
255 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
256 *
257 * @enb_reg: read the enable status
258 * @enb_set_reg: write 1 to enable clock
259 * @enb_clr_reg: write 1 to disable clock
260 * @rst_reg: read the reset status
261 * @rst_set_reg: write 1 to assert the reset of peripheral
262 * @rst_clr_reg: write 1 to deassert the reset of peripheral
263 */
264struct tegra_clk_periph_regs {
265 u32 enb_reg;
266 u32 enb_set_reg;
267 u32 enb_clr_reg;
268 u32 rst_reg;
269 u32 rst_set_reg;
270 u32 rst_clr_reg;
271};
272
273/**
274 * struct tegra_clk_periph_gate - peripheral gate clock
275 *
276 * @magic: magic number to validate type
277 * @hw: handle between common and hardware-specific interfaces
278 * @clk_base: address of CAR controller
279 * @regs: Registers to control the peripheral
280 * @flags: hardware-specific flags
281 * @clk_num: Clock number
282 * @enable_refcnt: array to maintain reference count of the clock
283 *
284 * Flags:
285 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
286 * for this module.
287 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
288 * after clock enable and driver for the module is responsible for
289 * doing reset.
290 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
291 * bus to flush the write operation in apb bus. This flag indicates
292 * that this peripheral is in apb bus.
293 */
294struct tegra_clk_periph_gate {
295 u32 magic;
296 struct clk_hw hw;
297 void __iomem *clk_base;
298 u8 flags;
299 int clk_num;
300 int *enable_refcnt;
301 struct tegra_clk_periph_regs *regs;
302};
303
304#define to_clk_periph_gate(_hw) \
305 container_of(_hw, struct tegra_clk_periph_gate, hw)
306
307#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
308
309#define TEGRA_PERIPH_NO_RESET BIT(0)
310#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
311#define TEGRA_PERIPH_ON_APB BIT(2)
312
313void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
314extern const struct clk_ops tegra_clk_periph_gate_ops;
315struct clk *tegra_clk_register_periph_gate(const char *name,
316 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
317 unsigned long flags, int clk_num,
318 struct tegra_clk_periph_regs *pregs, int *enable_refcnt);
319
320/**
321 * struct clk-periph - peripheral clock
322 *
323 * @magic: magic number to validate type
324 * @hw: handle between common and hardware-specific interfaces
325 * @mux: mux clock
326 * @divider: divider clock
327 * @gate: gate clock
328 * @mux_ops: mux clock ops
329 * @div_ops: divider clock ops
330 * @gate_ops: gate clock ops
331 */
332struct tegra_clk_periph {
333 u32 magic;
334 struct clk_hw hw;
335 struct clk_mux mux;
336 struct tegra_clk_frac_div divider;
337 struct tegra_clk_periph_gate gate;
338
339 const struct clk_ops *mux_ops;
340 const struct clk_ops *div_ops;
341 const struct clk_ops *gate_ops;
342};
343
344#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
345
346#define TEGRA_CLK_PERIPH_MAGIC 0x18221223
347
348extern const struct clk_ops tegra_clk_periph_ops;
349struct clk *tegra_clk_register_periph(const char *name,
350 const char **parent_names, int num_parents,
351 struct tegra_clk_periph *periph, void __iomem *clk_base,
352 u32 offset);
353struct clk *tegra_clk_register_periph_nodiv(const char *name,
354 const char **parent_names, int num_parents,
355 struct tegra_clk_periph *periph, void __iomem *clk_base,
356 u32 offset);
357
358#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \
359 _div_shift, _div_width, _div_frac_width, \
360 _div_flags, _clk_num, _enb_refcnt, _regs, \
361 _gate_flags) \
362 { \
363 .mux = { \
364 .flags = _mux_flags, \
365 .shift = _mux_shift, \
366 .width = _mux_width, \
367 }, \
368 .divider = { \
369 .flags = _div_flags, \
370 .shift = _div_shift, \
371 .width = _div_width, \
372 .frac_width = _div_frac_width, \
373 }, \
374 .gate = { \
375 .flags = _gate_flags, \
376 .clk_num = _clk_num, \
377 .enable_refcnt = _enb_refcnt, \
378 .regs = _regs, \
379 }, \
380 .mux_ops = &clk_mux_ops, \
381 .div_ops = &tegra_clk_frac_div_ops, \
382 .gate_ops = &tegra_clk_periph_gate_ops, \
383 }
384
385struct tegra_periph_init_data {
386 const char *name;
387 int clk_id;
388 const char **parent_names;
389 int num_parents;
390 struct tegra_clk_periph periph;
391 u32 offset;
392 const char *con_id;
393 const char *dev_id;
394};
395
396#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \
397 _mux_shift, _mux_width, _mux_flags, _div_shift, \
398 _div_width, _div_frac_width, _div_flags, _regs, \
399 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \
400 { \
401 .name = _name, \
402 .clk_id = _clk_id, \
403 .parent_names = _parent_names, \
404 .num_parents = ARRAY_SIZE(_parent_names), \
405 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \
406 _mux_flags, _div_shift, \
407 _div_width, _div_frac_width, \
408 _div_flags, _clk_num, \
409 _enb_refcnt, _regs, \
410 _gate_flags), \
411 .offset = _offset, \
412 .con_id = _con_id, \
413 .dev_id = _dev_id, \
414 }
415
416/**
417 * struct clk_super_mux - super clock
418 *
419 * @hw: handle between common and hardware-specific interfaces
420 * @reg: register controlling multiplexer
421 * @width: width of the multiplexer bit field
422 * @flags: hardware-specific flags
423 * @div2_index: bit controlling divide-by-2
424 * @pllx_index: PLLX index in the parent list
425 * @lock: register lock
426 *
427 * Flags:
428 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
429 * that this is LP cluster clock.
430 */
431struct tegra_clk_super_mux {
432 struct clk_hw hw;
433 void __iomem *reg;
434 u8 width;
435 u8 flags;
436 u8 div2_index;
437 u8 pllx_index;
438 spinlock_t *lock;
439};
440
441#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
442
443#define TEGRA_DIVIDER_2 BIT(0)
444
445extern const struct clk_ops tegra_clk_super_ops;
446struct clk *tegra_clk_register_super_mux(const char *name,
447 const char **parent_names, u8 num_parents,
448 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
449 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
450
451/**
452 * struct clk_init_tabel - clock initialization table
453 * @clk_id: clock id as mentioned in device tree bindings
454 * @parent_id: parent clock id as mentioned in device tree bindings
455 * @rate: rate to set
456 * @state: enable/disable
457 */
458struct tegra_clk_init_table {
459 unsigned int clk_id;
460 unsigned int parent_id;
461 unsigned long rate;
462 int state;
463};
464
465/**
466 * struct clk_duplicate - duplicate clocks
467 * @clk_id: clock id as mentioned in device tree bindings
468 * @lookup: duplicate lookup entry for the clock
469 */
470struct tegra_clk_duplicate {
471 int clk_id;
472 struct clk_lookup lookup;
473};
474
475#define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
476 { \
477 .clk_id = _clk_id, \
478 .lookup = { \
479 .dev_id = _dev, \
480 .con_id = _con, \
481 }, \
482 }
483
484void tegra_init_from_table(struct tegra_clk_init_table *tbl,
485 struct clk *clks[], int clk_max);
486
487void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
488 struct clk *clks[], int clk_max);
489
490#ifdef CONFIG_ARCH_TEGRA_2x_SOC
491void tegra20_clock_init(struct device_node *np);
492#else
493static inline void tegra20_clock_init(struct device_node *np) {}
494#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
495
496#ifdef CONFIG_ARCH_TEGRA_3x_SOC
497void tegra30_clock_init(struct device_node *np);
498#else
499static inline void tegra30_clock_init(struct device_node *np) {}
500#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
501
502#endif /* TEGRA_CLK_H */
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index c4cc27e5c8a5..071e2c3eec4f 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -39,4 +39,10 @@ config CPU_IDLE_CALXEDA
39 help 39 help
40 Select this to enable cpuidle on Calxeda processors. 40 Select this to enable cpuidle on Calxeda processors.
41 41
42config CPU_IDLE_KIRKWOOD
43 bool "CPU Idle Driver for Kirkwood processors"
44 depends on ARCH_KIRKWOOD
45 help
46 Select this to enable cpuidle on Kirkwood processors.
47
42endif 48endif
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 03ee87482c71..24c6e7d945ed 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -6,3 +6,4 @@ obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
6obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o 6obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
7 7
8obj-$(CONFIG_CPU_IDLE_CALXEDA) += cpuidle-calxeda.o 8obj-$(CONFIG_CPU_IDLE_CALXEDA) += cpuidle-calxeda.o
9obj-$(CONFIG_CPU_IDLE_KIRKWOOD) += cpuidle-kirkwood.o
diff --git a/drivers/cpuidle/cpuidle-kirkwood.c b/drivers/cpuidle/cpuidle-kirkwood.c
new file mode 100644
index 000000000000..670aa1e55cd6
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-kirkwood.c
@@ -0,0 +1,106 @@
1/*
2 * arch/arm/mach-kirkwood/cpuidle.c
3 *
4 * CPU idle Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * The cpu idle uses wait-for-interrupt and DDR self refresh in order
11 * to implement two idle states -
12 * #1 wait-for-interrupt
13 * #2 wait-for-interrupt and DDR self refresh
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/cpuidle.h>
21#include <linux/io.h>
22#include <linux/export.h>
23#include <asm/proc-fns.h>
24#include <asm/cpuidle.h>
25
26#define KIRKWOOD_MAX_STATES 2
27
28static void __iomem *ddr_operation_base;
29
30/* Actual code that puts the SoC in different idle states */
31static int kirkwood_enter_idle(struct cpuidle_device *dev,
32 struct cpuidle_driver *drv,
33 int index)
34{
35 writel(0x7, ddr_operation_base);
36 cpu_do_idle();
37
38 return index;
39}
40
41static struct cpuidle_driver kirkwood_idle_driver = {
42 .name = "kirkwood_idle",
43 .owner = THIS_MODULE,
44 .en_core_tk_irqen = 1,
45 .states[0] = ARM_CPUIDLE_WFI_STATE,
46 .states[1] = {
47 .enter = kirkwood_enter_idle,
48 .exit_latency = 10,
49 .target_residency = 100000,
50 .flags = CPUIDLE_FLAG_TIME_VALID,
51 .name = "DDR SR",
52 .desc = "WFI and DDR Self Refresh",
53 },
54 .state_count = KIRKWOOD_MAX_STATES,
55};
56static struct cpuidle_device *device;
57
58static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
59
60/* Initialize CPU idle by registering the idle states */
61static int kirkwood_cpuidle_probe(struct platform_device *pdev)
62{
63 struct resource *res;
64
65 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
66 if (res == NULL)
67 return -EINVAL;
68
69 ddr_operation_base = devm_request_and_ioremap(&pdev->dev, res);
70 if (!ddr_operation_base)
71 return -EADDRNOTAVAIL;
72
73 device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id());
74 device->state_count = KIRKWOOD_MAX_STATES;
75
76 cpuidle_register_driver(&kirkwood_idle_driver);
77 if (cpuidle_register_device(device)) {
78 pr_err("kirkwood_init_cpuidle: Failed registering\n");
79 return -EIO;
80 }
81 return 0;
82}
83
84int kirkwood_cpuidle_remove(struct platform_device *pdev)
85{
86 cpuidle_unregister_device(device);
87 cpuidle_unregister_driver(&kirkwood_idle_driver);
88
89 return 0;
90}
91
92static struct platform_driver kirkwood_cpuidle_driver = {
93 .probe = kirkwood_cpuidle_probe,
94 .remove = kirkwood_cpuidle_remove,
95 .driver = {
96 .name = "kirkwood_cpuidle",
97 .owner = THIS_MODULE,
98 },
99};
100
101module_platform_driver(kirkwood_cpuidle_driver);
102
103MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
104MODULE_DESCRIPTION("Kirkwood cpu idle driver");
105MODULE_LICENSE("GPL v2");
106MODULE_ALIAS("platform:kirkwood-cpuidle");
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 58c1896271e1..f6c018f1b453 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -32,8 +32,8 @@
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/pm_runtime.h> 33#include <linux/pm_runtime.h>
34#include <linux/slab.h> 34#include <linux/slab.h>
35#include <linux/clk/tegra.h>
35 36
36#include <mach/clk.h>
37#include "dmaengine.h" 37#include "dmaengine.h"
38 38
39#define TEGRA_APBDMA_GENERAL 0x0 39#define TEGRA_APBDMA_GENERAL 0x0
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index d365c6dff0fb..b6679b36700f 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -12,8 +12,7 @@
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15 15#include <linux/clk/tegra.h>
16#include <mach/clk.h>
17 16
18#include "drm.h" 17#include "drm.h"
19#include "dc.h" 18#include "dc.h"
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 3a503c9e4686..d980dc75788c 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -11,7 +11,6 @@
11#include <linux/of_address.h> 11#include <linux/of_address.h>
12#include <linux/of_platform.h> 12#include <linux/of_platform.h>
13 13
14#include <mach/clk.h>
15#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
16#include <asm/dma-iommu.h> 15#include <asm/dma-iommu.h>
17 16
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 266af7879240..d4f3fb9f0c29 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -14,8 +14,7 @@
14#include <linux/of.h> 14#include <linux/of.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/regulator/consumer.h> 16#include <linux/regulator/consumer.h>
17 17#include <linux/clk/tegra.h>
18#include <mach/clk.h>
19 18
20#include "hdmi.h" 19#include "hdmi.h"
21#include "drm.h" 20#include "drm.h"
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 1fb30099dac4..f0d9923323ea 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -29,11 +29,10 @@
29#include <linux/of_i2c.h> 29#include <linux/of_i2c.h>
30#include <linux/of_device.h> 30#include <linux/of_device.h>
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/clk/tegra.h>
32 33
33#include <asm/unaligned.h> 34#include <asm/unaligned.h>
34 35
35#include <mach/clk.h>
36
37#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 36#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
38#define BYTES_PER_FIFO_WORD 4 37#define BYTES_PER_FIFO_WORD 4
39 38
diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
index d89e7d392d1e..0e138ebcc768 100644
--- a/drivers/input/keyboard/tegra-kbc.c
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -30,7 +30,7 @@
30#include <linux/clk.h> 30#include <linux/clk.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/input/matrix_keypad.h> 32#include <linux/input/matrix_keypad.h>
33#include <mach/clk.h> 33#include <linux/clk/tegra.h>
34 34
35#define KBC_MAX_GPIO 24 35#define KBC_MAX_GPIO 24
36#define KBC_MAX_KPENT 8 36#define KBC_MAX_KPENT 8
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index aa64d5d3fb20..476d06452af8 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1033,7 +1033,7 @@ config RTC_DRV_TX4939
1033 1033
1034config RTC_DRV_MV 1034config RTC_DRV_MV
1035 tristate "Marvell SoC RTC" 1035 tristate "Marvell SoC RTC"
1036 depends on ARCH_KIRKWOOD || ARCH_DOVE 1036 depends on ARCH_KIRKWOOD || ARCH_DOVE || ARCH_MVEBU
1037 help 1037 help
1038 If you say yes here you will get support for the in-chip RTC 1038 If you say yes here you will get support for the in-chip RTC
1039 that can be found in some of Marvell's SoC devices, such as 1039 that can be found in some of Marvell's SoC devices, such as
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 8a61b27a9f2d..3d6a12b2af04 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -34,7 +34,7 @@
34#include <linux/of_device.h> 34#include <linux/of_device.h>
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/spi-tegra.h> 36#include <linux/spi/spi-tegra.h>
37#include <mach/clk.h> 37#include <linux/clk/tegra.h>
38 38
39#define SPI_COMMAND 0x000 39#define SPI_COMMAND 0x000
40#define SPI_GO BIT(30) 40#define SPI_GO BIT(30)
@@ -531,7 +531,7 @@ static int tegra_sflash_probe(struct platform_device *pdev)
531 goto exit_free_master; 531 goto exit_free_master;
532 } 532 }
533 533
534 tsd->clk = devm_clk_get(&pdev->dev, "spi"); 534 tsd->clk = devm_clk_get(&pdev->dev, NULL);
535 if (IS_ERR(tsd->clk)) { 535 if (IS_ERR(tsd->clk)) {
536 dev_err(&pdev->dev, "can not get clock\n"); 536 dev_err(&pdev->dev, "can not get clock\n");
537 ret = PTR_ERR(tsd->clk); 537 ret = PTR_ERR(tsd->clk);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 8458c4bf7172..b8698b389ef3 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -35,7 +35,7 @@
35#include <linux/of_device.h> 35#include <linux/of_device.h>
36#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
37#include <linux/spi/spi-tegra.h> 37#include <linux/spi/spi-tegra.h>
38#include <mach/clk.h> 38#include <linux/clk/tegra.h>
39 39
40#define SLINK_COMMAND 0x000 40#define SLINK_COMMAND 0x000
41#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 41#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
@@ -1186,7 +1186,7 @@ static int tegra_slink_probe(struct platform_device *pdev)
1186 goto exit_free_master; 1186 goto exit_free_master;
1187 } 1187 }
1188 1188
1189 tspi->clk = devm_clk_get(&pdev->dev, "slink"); 1189 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1190 if (IS_ERR(tspi->clk)) { 1190 if (IS_ERR(tspi->clk)) {
1191 dev_err(&pdev->dev, "can not get clock\n"); 1191 dev_err(&pdev->dev, "can not get clock\n");
1192 ret = PTR_ERR(tspi->clk); 1192 ret = PTR_ERR(tspi->clk);
diff --git a/drivers/staging/nvec/TODO b/drivers/staging/nvec/TODO
index f950ab890e2e..e5ae42a0b44a 100644
--- a/drivers/staging/nvec/TODO
+++ b/drivers/staging/nvec/TODO
@@ -1,9 +1,5 @@
1ToDo list (incomplete, unordered) 1ToDo list (incomplete, unordered)
2 - add compile as module support 2 - add compile as module support
3 - fix clk usage
4 should not be using clk_get_sys(), but clk_get(&pdev->dev, conn)
5 where conn is either NULL if the device only has one clock, or
6 the device specific name if it has multiple clocks.
7 - move half of the nvec init stuff to i2c-tegra.c 3 - move half of the nvec init stuff to i2c-tegra.c
8 - move event handling to nvec_events 4 - move event handling to nvec_events
9 - finish suspend/resume support 5 - finish suspend/resume support
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 6a0b6eccf1e6..cf159365b0ee 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -37,8 +37,7 @@
37#include <linux/slab.h> 37#include <linux/slab.h>
38#include <linux/spinlock.h> 38#include <linux/spinlock.h>
39#include <linux/workqueue.h> 39#include <linux/workqueue.h>
40 40#include <linux/clk/tegra.h>
41#include <mach/clk.h>
42 41
43#include "nvec.h" 42#include "nvec.h"
44 43
@@ -816,7 +815,7 @@ static int tegra_nvec_probe(struct platform_device *pdev)
816 return -ENODEV; 815 return -ENODEV;
817 } 816 }
818 817
819 i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk"); 818 i2c_clk = clk_get(&pdev->dev, "div-clk");
820 if (IS_ERR(i2c_clk)) { 819 if (IS_ERR(i2c_clk)) {
821 dev_err(nvec->dev, "failed to get controller clock\n"); 820 dev_err(nvec->dev, "failed to get controller clock\n");
822 return -ENODEV; 821 return -ENODEV;
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index acf17556bd87..568aecc7075b 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -2,7 +2,7 @@
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs 2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 NVIDIA Corporation 5 * Copyright (C) 2009 - 2013 NVIDIA Corporation
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -26,23 +26,28 @@
26#include <linux/of.h> 26#include <linux/of.h>
27#include <linux/of_gpio.h> 27#include <linux/of_gpio.h>
28#include <linux/pm_runtime.h> 28#include <linux/pm_runtime.h>
29 29#include <linux/usb/ehci_def.h>
30#include <linux/usb/tegra_usb_phy.h> 30#include <linux/usb/tegra_usb_phy.h>
31 31
32#define TEGRA_USB_BASE 0xC5000000 32#define TEGRA_USB_BASE 0xC5000000
33#define TEGRA_USB2_BASE 0xC5004000 33#define TEGRA_USB2_BASE 0xC5004000
34#define TEGRA_USB3_BASE 0xC5008000 34#define TEGRA_USB3_BASE 0xC5008000
35 35
36/* PORTSC registers */
37#define TEGRA_USB_PORTSC1 0x184
38#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
39#define TEGRA_USB_PORTSC1_PHCD (1 << 23)
40
36#define TEGRA_USB_DMA_ALIGN 32 41#define TEGRA_USB_DMA_ALIGN 32
37 42
38struct tegra_ehci_hcd { 43struct tegra_ehci_hcd {
39 struct ehci_hcd *ehci; 44 struct ehci_hcd *ehci;
40 struct tegra_usb_phy *phy; 45 struct tegra_usb_phy *phy;
41 struct clk *clk; 46 struct clk *clk;
42 struct clk *emc_clk;
43 struct usb_phy *transceiver; 47 struct usb_phy *transceiver;
44 int host_resumed; 48 int host_resumed;
45 int port_resuming; 49 int port_resuming;
50 bool needs_double_reset;
46 enum tegra_usb_phy_port_speed port_speed; 51 enum tegra_usb_phy_port_speed port_speed;
47}; 52};
48 53
@@ -50,9 +55,8 @@ static void tegra_ehci_power_up(struct usb_hcd *hcd)
50{ 55{
51 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 56 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
52 57
53 clk_prepare_enable(tegra->emc_clk);
54 clk_prepare_enable(tegra->clk); 58 clk_prepare_enable(tegra->clk);
55 usb_phy_set_suspend(&tegra->phy->u_phy, 0); 59 usb_phy_set_suspend(hcd->phy, 0);
56 tegra->host_resumed = 1; 60 tegra->host_resumed = 1;
57} 61}
58 62
@@ -61,9 +65,8 @@ static void tegra_ehci_power_down(struct usb_hcd *hcd)
61 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 65 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
62 66
63 tegra->host_resumed = 0; 67 tegra->host_resumed = 0;
64 usb_phy_set_suspend(&tegra->phy->u_phy, 1); 68 usb_phy_set_suspend(hcd->phy, 1);
65 clk_disable_unprepare(tegra->clk); 69 clk_disable_unprepare(tegra->clk);
66 clk_disable_unprepare(tegra->emc_clk);
67} 70}
68 71
69static int tegra_ehci_internal_port_reset( 72static int tegra_ehci_internal_port_reset(
@@ -156,7 +159,7 @@ static int tegra_ehci_hub_control(
156 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { 159 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
157 /* Resume completed, re-enable disconnect detection */ 160 /* Resume completed, re-enable disconnect detection */
158 tegra->port_resuming = 0; 161 tegra->port_resuming = 0;
159 tegra_usb_phy_postresume(tegra->phy); 162 tegra_usb_phy_postresume(hcd->phy);
160 } 163 }
161 } 164 }
162 165
@@ -184,7 +187,7 @@ static int tegra_ehci_hub_control(
184 } 187 }
185 188
186 /* For USB1 port we need to issue Port Reset twice internally */ 189 /* For USB1 port we need to issue Port Reset twice internally */
187 if (tegra->phy->instance == 0 && 190 if (tegra->needs_double_reset &&
188 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { 191 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
189 spin_unlock_irqrestore(&ehci->lock, flags); 192 spin_unlock_irqrestore(&ehci->lock, flags);
190 return tegra_ehci_internal_port_reset(ehci, status_reg); 193 return tegra_ehci_internal_port_reset(ehci, status_reg);
@@ -209,7 +212,7 @@ static int tegra_ehci_hub_control(
209 goto done; 212 goto done;
210 213
211 /* Disable disconnect detection during port resume */ 214 /* Disable disconnect detection during port resume */
212 tegra_usb_phy_preresume(tegra->phy); 215 tegra_usb_phy_preresume(hcd->phy);
213 216
214 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); 217 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
215 218
@@ -473,7 +476,7 @@ static int controller_resume(struct device *dev)
473 } 476 }
474 477
475 /* Force the phy to keep data lines in suspend state */ 478 /* Force the phy to keep data lines in suspend state */
476 tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed); 479 tegra_ehci_phy_restore_start(hcd->phy, tegra->port_speed);
477 480
478 /* Enable host mode */ 481 /* Enable host mode */
479 tdi_reset(ehci); 482 tdi_reset(ehci);
@@ -540,17 +543,17 @@ static int controller_resume(struct device *dev)
540 } 543 }
541 } 544 }
542 545
543 tegra_ehci_phy_restore_end(tegra->phy); 546 tegra_ehci_phy_restore_end(hcd->phy);
544 goto done; 547 goto done;
545 548
546 restart: 549 restart:
547 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) 550 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
548 tegra_ehci_phy_restore_end(tegra->phy); 551 tegra_ehci_phy_restore_end(hcd->phy);
549 552
550 tegra_ehci_restart(hcd); 553 tegra_ehci_restart(hcd);
551 554
552 done: 555 done:
553 tegra_usb_phy_preresume(tegra->phy); 556 tegra_usb_phy_preresume(hcd->phy);
554 tegra->port_resuming = 1; 557 tegra->port_resuming = 1;
555 return 0; 558 return 0;
556} 559}
@@ -604,6 +607,37 @@ static const struct dev_pm_ops tegra_ehci_pm_ops = {
604 607
605#endif 608#endif
606 609
610/* Bits of PORTSC1, which will get cleared by writing 1 into them */
611#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
612
613void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val)
614{
615 unsigned long val;
616 struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
617 void __iomem *base = hcd->regs;
618
619 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
620 val &= ~TEGRA_USB_PORTSC1_PTS(3);
621 val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
622 writel(val, base + TEGRA_USB_PORTSC1);
623}
624EXPORT_SYMBOL_GPL(tegra_ehci_set_pts);
625
626void tegra_ehci_set_phcd(struct usb_phy *x, bool enable)
627{
628 unsigned long val;
629 struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
630 void __iomem *base = hcd->regs;
631
632 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
633 if (enable)
634 val |= TEGRA_USB_PORTSC1_PHCD;
635 else
636 val &= ~TEGRA_USB_PORTSC1_PHCD;
637 writel(val, base + TEGRA_USB_PORTSC1);
638}
639EXPORT_SYMBOL_GPL(tegra_ehci_set_phcd);
640
607static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32); 641static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
608 642
609static int tegra_ehci_probe(struct platform_device *pdev) 643static int tegra_ehci_probe(struct platform_device *pdev)
@@ -615,6 +649,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
615 int err = 0; 649 int err = 0;
616 int irq; 650 int irq;
617 int instance = pdev->id; 651 int instance = pdev->id;
652 struct usb_phy *u_phy;
618 653
619 pdata = pdev->dev.platform_data; 654 pdata = pdev->dev.platform_data;
620 if (!pdata) { 655 if (!pdata) {
@@ -656,15 +691,8 @@ static int tegra_ehci_probe(struct platform_device *pdev)
656 if (err) 691 if (err)
657 goto fail_clk; 692 goto fail_clk;
658 693
659 tegra->emc_clk = devm_clk_get(&pdev->dev, "emc"); 694 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
660 if (IS_ERR(tegra->emc_clk)) { 695 "nvidia,needs-double-reset");
661 dev_err(&pdev->dev, "Can't get emc clock\n");
662 err = PTR_ERR(tegra->emc_clk);
663 goto fail_emc_clk;
664 }
665
666 clk_prepare_enable(tegra->emc_clk);
667 clk_set_rate(tegra->emc_clk, 400000000);
668 696
669 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 697 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
670 if (!res) { 698 if (!res) {
@@ -712,9 +740,19 @@ static int tegra_ehci_probe(struct platform_device *pdev)
712 goto fail_io; 740 goto fail_io;
713 } 741 }
714 742
715 usb_phy_init(&tegra->phy->u_phy); 743 hcd->phy = u_phy = &tegra->phy->u_phy;
744 usb_phy_init(hcd->phy);
745
746 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
747 GFP_KERNEL);
748 if (!u_phy->otg) {
749 dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
750 err = -ENOMEM;
751 goto fail_io;
752 }
753 u_phy->otg->host = hcd_to_bus(hcd);
716 754
717 err = usb_phy_set_suspend(&tegra->phy->u_phy, 0); 755 err = usb_phy_set_suspend(hcd->phy, 0);
718 if (err) { 756 if (err) {
719 dev_err(&pdev->dev, "Failed to power on the phy\n"); 757 dev_err(&pdev->dev, "Failed to power on the phy\n");
720 goto fail; 758 goto fail;
@@ -760,10 +798,8 @@ fail:
760 if (!IS_ERR_OR_NULL(tegra->transceiver)) 798 if (!IS_ERR_OR_NULL(tegra->transceiver))
761 otg_set_host(tegra->transceiver->otg, NULL); 799 otg_set_host(tegra->transceiver->otg, NULL);
762#endif 800#endif
763 usb_phy_shutdown(&tegra->phy->u_phy); 801 usb_phy_shutdown(hcd->phy);
764fail_io: 802fail_io:
765 clk_disable_unprepare(tegra->emc_clk);
766fail_emc_clk:
767 clk_disable_unprepare(tegra->clk); 803 clk_disable_unprepare(tegra->clk);
768fail_clk: 804fail_clk:
769 usb_put_hcd(hcd); 805 usb_put_hcd(hcd);
@@ -784,15 +820,12 @@ static int tegra_ehci_remove(struct platform_device *pdev)
784 otg_set_host(tegra->transceiver->otg, NULL); 820 otg_set_host(tegra->transceiver->otg, NULL);
785#endif 821#endif
786 822
823 usb_phy_shutdown(hcd->phy);
787 usb_remove_hcd(hcd); 824 usb_remove_hcd(hcd);
788 usb_put_hcd(hcd); 825 usb_put_hcd(hcd);
789 826
790 usb_phy_shutdown(&tegra->phy->u_phy);
791
792 clk_disable_unprepare(tegra->clk); 827 clk_disable_unprepare(tegra->clk);
793 828
794 clk_disable_unprepare(tegra->emc_clk);
795
796 return 0; 829 return 0;
797} 830}
798 831
diff --git a/drivers/usb/phy/tegra_usb_phy.c b/drivers/usb/phy/tegra_usb_phy.c
index 9d13c81754e0..5487d38481af 100644
--- a/drivers/usb/phy/tegra_usb_phy.c
+++ b/drivers/usb/phy/tegra_usb_phy.c
@@ -24,6 +24,7 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/of.h>
27#include <linux/of_gpio.h> 28#include <linux/of_gpio.h>
28#include <linux/usb/otg.h> 29#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h> 30#include <linux/usb/ulpi.h>
@@ -35,19 +36,6 @@
35 36
36#define ULPI_VIEWPORT 0x170 37#define ULPI_VIEWPORT 0x170
37 38
38#define USB_PORTSC1 0x184
39#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
40#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
41#define USB_PORTSC1_PHCD (1 << 23)
42#define USB_PORTSC1_WKOC (1 << 22)
43#define USB_PORTSC1_WKDS (1 << 21)
44#define USB_PORTSC1_WKCN (1 << 20)
45#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
46#define USB_PORTSC1_PP (1 << 12)
47#define USB_PORTSC1_SUSP (1 << 7)
48#define USB_PORTSC1_PE (1 << 2)
49#define USB_PORTSC1_CCS (1 << 0)
50
51#define USB_SUSP_CTRL 0x400 39#define USB_SUSP_CTRL 0x400
52#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) 40#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
53#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) 41#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
@@ -208,11 +196,6 @@ static struct tegra_utmip_config utmip_default[] = {
208 }, 196 },
209}; 197};
210 198
211static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
212{
213 return (phy->instance == 1);
214}
215
216static int utmip_pad_open(struct tegra_usb_phy *phy) 199static int utmip_pad_open(struct tegra_usb_phy *phy)
217{ 200{
218 phy->pad_clk = clk_get_sys("utmip-pad", NULL); 201 phy->pad_clk = clk_get_sys("utmip-pad", NULL);
@@ -221,7 +204,7 @@ static int utmip_pad_open(struct tegra_usb_phy *phy)
221 return PTR_ERR(phy->pad_clk); 204 return PTR_ERR(phy->pad_clk);
222 } 205 }
223 206
224 if (phy->instance == 0) { 207 if (phy->is_legacy_phy) {
225 phy->pad_regs = phy->regs; 208 phy->pad_regs = phy->regs;
226 } else { 209 } else {
227 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE); 210 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
@@ -236,7 +219,7 @@ static int utmip_pad_open(struct tegra_usb_phy *phy)
236 219
237static void utmip_pad_close(struct tegra_usb_phy *phy) 220static void utmip_pad_close(struct tegra_usb_phy *phy)
238{ 221{
239 if (phy->instance != 0) 222 if (!phy->is_legacy_phy)
240 iounmap(phy->pad_regs); 223 iounmap(phy->pad_regs);
241 clk_put(phy->pad_clk); 224 clk_put(phy->pad_clk);
242} 225}
@@ -305,7 +288,7 @@ static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
305 unsigned long val; 288 unsigned long val;
306 void __iomem *base = phy->regs; 289 void __iomem *base = phy->regs;
307 290
308 if (phy->instance == 0) { 291 if (phy->is_legacy_phy) {
309 val = readl(base + USB_SUSP_CTRL); 292 val = readl(base + USB_SUSP_CTRL);
310 val |= USB_SUSP_SET; 293 val |= USB_SUSP_SET;
311 writel(val, base + USB_SUSP_CTRL); 294 writel(val, base + USB_SUSP_CTRL);
@@ -315,13 +298,8 @@ static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
315 val = readl(base + USB_SUSP_CTRL); 298 val = readl(base + USB_SUSP_CTRL);
316 val &= ~USB_SUSP_SET; 299 val &= ~USB_SUSP_SET;
317 writel(val, base + USB_SUSP_CTRL); 300 writel(val, base + USB_SUSP_CTRL);
318 } 301 } else
319 302 tegra_ehci_set_phcd(&phy->u_phy, true);
320 if (phy->instance == 2) {
321 val = readl(base + USB_PORTSC1);
322 val |= USB_PORTSC1_PHCD;
323 writel(val, base + USB_PORTSC1);
324 }
325 303
326 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) 304 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
327 pr_err("%s: timeout waiting for phy to stabilize\n", __func__); 305 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
@@ -332,7 +310,7 @@ static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
332 unsigned long val; 310 unsigned long val;
333 void __iomem *base = phy->regs; 311 void __iomem *base = phy->regs;
334 312
335 if (phy->instance == 0) { 313 if (phy->is_legacy_phy) {
336 val = readl(base + USB_SUSP_CTRL); 314 val = readl(base + USB_SUSP_CTRL);
337 val |= USB_SUSP_CLR; 315 val |= USB_SUSP_CLR;
338 writel(val, base + USB_SUSP_CTRL); 316 writel(val, base + USB_SUSP_CTRL);
@@ -342,13 +320,8 @@ static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
342 val = readl(base + USB_SUSP_CTRL); 320 val = readl(base + USB_SUSP_CTRL);
343 val &= ~USB_SUSP_CLR; 321 val &= ~USB_SUSP_CLR;
344 writel(val, base + USB_SUSP_CTRL); 322 writel(val, base + USB_SUSP_CTRL);
345 } 323 } else
346 324 tegra_ehci_set_phcd(&phy->u_phy, false);
347 if (phy->instance == 2) {
348 val = readl(base + USB_PORTSC1);
349 val &= ~USB_PORTSC1_PHCD;
350 writel(val, base + USB_PORTSC1);
351 }
352 325
353 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 326 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
354 USB_PHY_CLK_VALID)) 327 USB_PHY_CLK_VALID))
@@ -365,7 +338,7 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
365 val |= UTMIP_RESET; 338 val |= UTMIP_RESET;
366 writel(val, base + USB_SUSP_CTRL); 339 writel(val, base + USB_SUSP_CTRL);
367 340
368 if (phy->instance == 0) { 341 if (phy->is_legacy_phy) {
369 val = readl(base + USB1_LEGACY_CTRL); 342 val = readl(base + USB1_LEGACY_CTRL);
370 val |= USB1_NO_LEGACY_MODE; 343 val |= USB1_NO_LEGACY_MODE;
371 writel(val, base + USB1_LEGACY_CTRL); 344 writel(val, base + USB1_LEGACY_CTRL);
@@ -440,16 +413,14 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
440 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); 413 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
441 writel(val, base + UTMIP_BIAS_CFG1); 414 writel(val, base + UTMIP_BIAS_CFG1);
442 415
443 if (phy->instance == 0) { 416 if (phy->is_legacy_phy) {
444 val = readl(base + UTMIP_SPARE_CFG0); 417 val = readl(base + UTMIP_SPARE_CFG0);
445 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) 418 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
446 val &= ~FUSE_SETUP_SEL; 419 val &= ~FUSE_SETUP_SEL;
447 else 420 else
448 val |= FUSE_SETUP_SEL; 421 val |= FUSE_SETUP_SEL;
449 writel(val, base + UTMIP_SPARE_CFG0); 422 writel(val, base + UTMIP_SPARE_CFG0);
450 } 423 } else {
451
452 if (phy->instance == 2) {
453 val = readl(base + USB_SUSP_CTRL); 424 val = readl(base + USB_SUSP_CTRL);
454 val |= UTMIP_PHY_ENABLE; 425 val |= UTMIP_PHY_ENABLE;
455 writel(val, base + USB_SUSP_CTRL); 426 writel(val, base + USB_SUSP_CTRL);
@@ -459,7 +430,7 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
459 val &= ~UTMIP_RESET; 430 val &= ~UTMIP_RESET;
460 writel(val, base + USB_SUSP_CTRL); 431 writel(val, base + USB_SUSP_CTRL);
461 432
462 if (phy->instance == 0) { 433 if (phy->is_legacy_phy) {
463 val = readl(base + USB1_LEGACY_CTRL); 434 val = readl(base + USB1_LEGACY_CTRL);
464 val &= ~USB1_VBUS_SENSE_CTL_MASK; 435 val &= ~USB1_VBUS_SENSE_CTL_MASK;
465 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; 436 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
@@ -472,11 +443,8 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
472 443
473 utmi_phy_clk_enable(phy); 444 utmi_phy_clk_enable(phy);
474 445
475 if (phy->instance == 2) { 446 if (!phy->is_legacy_phy)
476 val = readl(base + USB_PORTSC1); 447 tegra_ehci_set_pts(&phy->u_phy, 0);
477 val &= ~USB_PORTSC1_PTS(~0);
478 writel(val, base + USB_PORTSC1);
479 }
480 448
481 return 0; 449 return 0;
482} 450}
@@ -621,10 +589,6 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
621 return ret; 589 return ret;
622 } 590 }
623 591
624 val = readl(base + USB_PORTSC1);
625 val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
626 writel(val, base + USB_PORTSC1);
627
628 val = readl(base + USB_SUSP_CTRL); 592 val = readl(base + USB_SUSP_CTRL);
629 val |= USB_SUSP_CLR; 593 val |= USB_SUSP_CLR;
630 writel(val, base + USB_SUSP_CTRL); 594 writel(val, base + USB_SUSP_CTRL);
@@ -639,17 +603,8 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
639 603
640static int ulpi_phy_power_off(struct tegra_usb_phy *phy) 604static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
641{ 605{
642 unsigned long val;
643 void __iomem *base = phy->regs;
644 struct tegra_ulpi_config *config = phy->config; 606 struct tegra_ulpi_config *config = phy->config;
645 607
646 /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
647 * Controller to immediately bring the ULPI PHY out of low power
648 */
649 val = readl(base + USB_PORTSC1);
650 val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
651 writel(val, base + USB_PORTSC1);
652
653 clk_disable(phy->clk); 608 clk_disable(phy->clk);
654 return gpio_direction_output(config->reset_gpio, 0); 609 return gpio_direction_output(config->reset_gpio, 0);
655} 610}
@@ -660,7 +615,7 @@ static int tegra_phy_init(struct usb_phy *x)
660 struct tegra_ulpi_config *ulpi_config; 615 struct tegra_ulpi_config *ulpi_config;
661 int err; 616 int err;
662 617
663 if (phy_is_ulpi(phy)) { 618 if (phy->is_ulpi_phy) {
664 ulpi_config = phy->config; 619 ulpi_config = phy->config;
665 phy->clk = clk_get_sys(NULL, ulpi_config->clk); 620 phy->clk = clk_get_sys(NULL, ulpi_config->clk);
666 if (IS_ERR(phy->clk)) { 621 if (IS_ERR(phy->clk)) {
@@ -698,7 +653,7 @@ static void tegra_usb_phy_close(struct usb_phy *x)
698{ 653{
699 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 654 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
700 655
701 if (phy_is_ulpi(phy)) 656 if (phy->is_ulpi_phy)
702 clk_put(phy->clk); 657 clk_put(phy->clk);
703 else 658 else
704 utmip_pad_close(phy); 659 utmip_pad_close(phy);
@@ -709,7 +664,7 @@ static void tegra_usb_phy_close(struct usb_phy *x)
709 664
710static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) 665static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
711{ 666{
712 if (phy_is_ulpi(phy)) 667 if (phy->is_ulpi_phy)
713 return ulpi_phy_power_on(phy); 668 return ulpi_phy_power_on(phy);
714 else 669 else
715 return utmi_phy_power_on(phy); 670 return utmi_phy_power_on(phy);
@@ -717,7 +672,7 @@ static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
717 672
718static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) 673static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
719{ 674{
720 if (phy_is_ulpi(phy)) 675 if (phy->is_ulpi_phy)
721 return ulpi_phy_power_off(phy); 676 return ulpi_phy_power_off(phy);
722 else 677 else
723 return utmi_phy_power_off(phy); 678 return utmi_phy_power_off(phy);
@@ -739,8 +694,9 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
739 unsigned long parent_rate; 694 unsigned long parent_rate;
740 int i; 695 int i;
741 int err; 696 int err;
697 struct device_node *np = dev->of_node;
742 698
743 phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL); 699 phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
744 if (!phy) 700 if (!phy)
745 return ERR_PTR(-ENOMEM); 701 return ERR_PTR(-ENOMEM);
746 702
@@ -749,9 +705,16 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
749 phy->config = config; 705 phy->config = config;
750 phy->mode = phy_mode; 706 phy->mode = phy_mode;
751 phy->dev = dev; 707 phy->dev = dev;
708 phy->is_legacy_phy =
709 of_property_read_bool(np, "nvidia,has-legacy-mode");
710 err = of_property_match_string(np, "phy_type", "ulpi");
711 if (err < 0)
712 phy->is_ulpi_phy = false;
713 else
714 phy->is_ulpi_phy = true;
752 715
753 if (!phy->config) { 716 if (!phy->config) {
754 if (phy_is_ulpi(phy)) { 717 if (phy->is_ulpi_phy) {
755 pr_err("%s: ulpi phy configuration missing", __func__); 718 pr_err("%s: ulpi phy configuration missing", __func__);
756 err = -EINVAL; 719 err = -EINVAL;
757 goto err0; 720 goto err0;
@@ -796,45 +759,40 @@ err0:
796} 759}
797EXPORT_SYMBOL_GPL(tegra_usb_phy_open); 760EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
798 761
799void tegra_usb_phy_preresume(struct tegra_usb_phy *phy) 762void tegra_usb_phy_preresume(struct usb_phy *x)
800{ 763{
801 if (!phy_is_ulpi(phy)) 764 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
765
766 if (!phy->is_ulpi_phy)
802 utmi_phy_preresume(phy); 767 utmi_phy_preresume(phy);
803} 768}
804EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); 769EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
805 770
806void tegra_usb_phy_postresume(struct tegra_usb_phy *phy) 771void tegra_usb_phy_postresume(struct usb_phy *x)
807{ 772{
808 if (!phy_is_ulpi(phy)) 773 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
774
775 if (!phy->is_ulpi_phy)
809 utmi_phy_postresume(phy); 776 utmi_phy_postresume(phy);
810} 777}
811EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); 778EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
812 779
813void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy, 780void tegra_ehci_phy_restore_start(struct usb_phy *x,
814 enum tegra_usb_phy_port_speed port_speed) 781 enum tegra_usb_phy_port_speed port_speed)
815{ 782{
816 if (!phy_is_ulpi(phy)) 783 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
784
785 if (!phy->is_ulpi_phy)
817 utmi_phy_restore_start(phy, port_speed); 786 utmi_phy_restore_start(phy, port_speed);
818} 787}
819EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); 788EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
820 789
821void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy) 790void tegra_ehci_phy_restore_end(struct usb_phy *x)
822{ 791{
823 if (!phy_is_ulpi(phy)) 792 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
793
794 if (!phy->is_ulpi_phy)
824 utmi_phy_restore_end(phy); 795 utmi_phy_restore_end(phy);
825} 796}
826EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); 797EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
827 798
828void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
829{
830 if (!phy_is_ulpi(phy))
831 utmi_phy_clk_disable(phy);
832}
833EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
834
835void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
836{
837 if (!phy_is_ulpi(phy))
838 utmi_phy_clk_enable(phy);
839}
840EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 00:12:53 -0500