diff options
author | Alan Cox <alan@linux.intel.com> | 2011-12-29 09:37:03 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-01-03 04:30:07 -0500 |
commit | b6195aab9ca63a4f6911365f36eb091666fcb15a (patch) | |
tree | 3852d3a68333948e8d20ee9c66d16eb1c4154761 /drivers | |
parent | 56125db1eecf8d34d84f7925686110d90724edf0 (diff) |
gma500: Fix Cedarview support (Correct version)
And update to the actual product naming as the press release is now out.
http://newsroom.intel.com/docs/DOC-2553#pressmaterials
- Fixes the wrong ifdef check
- Fixes the missing crtc count declaration
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/gma500/Kconfig | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/gma500/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/gma500/cdv_device.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/gma500/psb_drv.c | 2 |
4 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig index 78e46e82cdbd..754e14bdc801 100644 --- a/drivers/gpu/drm/gma500/Kconfig +++ b/drivers/gpu/drm/gma500/Kconfig | |||
@@ -19,8 +19,9 @@ config DRM_GMA600 | |||
19 | platforms with LVDS ports. HDMI and MIPI are not currently | 19 | platforms with LVDS ports. HDMI and MIPI are not currently |
20 | supported. | 20 | supported. |
21 | 21 | ||
22 | config DRM_CEDARVIEW | 22 | config DRM_GMA3600 |
23 | bool "Intel Cedarview support (Experimental)" | 23 | bool "Intel GMA3600/3650 support (Experimental)" |
24 | depends on DRM_GMA500 | 24 | depends on DRM_GMA500 |
25 | help | 25 | help |
26 | Say yes to include support for Intel Cedarview platforms | 26 | Say yes to include basic support for Intel GMA3600/3650 (Intel |
27 | Cedar Trail) platforms. | ||
diff --git a/drivers/gpu/drm/gma500/Makefile b/drivers/gpu/drm/gma500/Makefile index 96658ec057e2..81c103be5e21 100644 --- a/drivers/gpu/drm/gma500/Makefile +++ b/drivers/gpu/drm/gma500/Makefile | |||
@@ -25,7 +25,7 @@ gma500_gfx-y += gem_glue.o \ | |||
25 | psb_device.o \ | 25 | psb_device.o \ |
26 | mid_bios.o | 26 | mid_bios.o |
27 | 27 | ||
28 | gma500_gfx-$(CONFIG_DRM_CEDARVIEW) += cdv_device.o \ | 28 | gma500_gfx-$(CONFIG_DRM_GMA3600) += cdv_device.o \ |
29 | cdv_intel_crt.o \ | 29 | cdv_intel_crt.o \ |
30 | cdv_intel_display.o \ | 30 | cdv_intel_display.o \ |
31 | cdv_intel_hdmi.o \ | 31 | cdv_intel_hdmi.o \ |
diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c index 7e8028abcc99..4a5b099c3bc5 100644 --- a/drivers/gpu/drm/gma500/cdv_device.c +++ b/drivers/gpu/drm/gma500/cdv_device.c | |||
@@ -327,9 +327,10 @@ static int cdv_chip_setup(struct drm_device *dev) | |||
327 | /* CDV is much like Poulsbo but has MID like SGX offsets and PM */ | 327 | /* CDV is much like Poulsbo but has MID like SGX offsets and PM */ |
328 | 328 | ||
329 | const struct psb_ops cdv_chip_ops = { | 329 | const struct psb_ops cdv_chip_ops = { |
330 | .name = "Cedartrail", | 330 | .name = "GMA3600/3650", |
331 | .accel_2d = 0, | 331 | .accel_2d = 0, |
332 | .pipes = 2, | 332 | .pipes = 2, |
333 | .crtcs = 2, | ||
333 | .sgx_offset = MRST_SGX_OFFSET, | 334 | .sgx_offset = MRST_SGX_OFFSET, |
334 | .chip_setup = cdv_chip_setup, | 335 | .chip_setup = cdv_chip_setup, |
335 | 336 | ||
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c index 962b92df02e2..96756ccaa07c 100644 --- a/drivers/gpu/drm/gma500/psb_drv.c +++ b/drivers/gpu/drm/gma500/psb_drv.c | |||
@@ -64,7 +64,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = { | |||
64 | /* Atom E620 */ | 64 | /* Atom E620 */ |
65 | { 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops}, | 65 | { 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops}, |
66 | #endif | 66 | #endif |
67 | #if defined(CONFIG_DRM_CDV) | 67 | #if defined(CONFIG_DRM_GMA3600) |
68 | { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, | 68 | { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, |
69 | { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, | 69 | { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, |
70 | { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, | 70 | { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, |