diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2012-08-19 01:53:15 -0400 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-02 23:13:05 -0400 |
| commit | 9456f7d1beb8f7cfd99300e6028b3b2667c2ebd5 (patch) | |
| tree | 8a7a8429bcde2cfb9c454a2202ec47471255caa6 /drivers | |
| parent | 368be5f1b84b3356eb03ad2ccaf073e2fbb7fc4e (diff) | |
drm/nouveau: add defines for internal class names
Will probably flesh the documentation of the classes out a bit too at some
later point.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/include/core/class.h | 49 |
1 files changed, 35 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h index b0e1948f4e71..6180ae9800fc 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/class.h +++ b/drivers/gpu/drm/nouveau/core/include/core/class.h | |||
| @@ -1,8 +1,11 @@ | |||
| 1 | #ifndef __NOUVEAU_CLASS_H__ | 1 | #ifndef __NOUVEAU_CLASS_H__ |
| 2 | #define __NOUVEAU_CLASS_H__ | 2 | #define __NOUVEAU_CLASS_H__ |
| 3 | 3 | ||
| 4 | /* 0080: NV_DEVICE | 4 | /* Device class |
| 5 | * | ||
| 6 | * 0080: NV_DEVICE | ||
| 5 | */ | 7 | */ |
| 8 | #define NV_DEVICE_CLASS 0x00000080 | ||
| 6 | 9 | ||
| 7 | #define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL | 10 | #define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL |
| 8 | #define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL | 11 | #define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL |
| @@ -27,10 +30,15 @@ struct nv_device_class { | |||
| 27 | u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ | 30 | u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ |
| 28 | }; | 31 | }; |
| 29 | 32 | ||
| 30 | /* 0002: NV_DMA_FROM_MEMORY | 33 | /* DMA object classes |
| 34 | * | ||
| 35 | * 0002: NV_DMA_FROM_MEMORY | ||
| 31 | * 0003: NV_DMA_TO_MEMORY | 36 | * 0003: NV_DMA_TO_MEMORY |
| 32 | * 003d: NV_DMA_IN_MEMORY | 37 | * 003d: NV_DMA_IN_MEMORY |
| 33 | */ | 38 | */ |
| 39 | #define NV_DMA_FROM_MEMORY_CLASS 0x00000002 | ||
| 40 | #define NV_DMA_TO_MEMORY_CLASS 0x00000003 | ||
| 41 | #define NV_DMA_IN_MEMORY_CLASS 0x0000003d | ||
| 34 | 42 | ||
| 35 | #define NV_DMA_TARGET_MASK 0x000000ff | 43 | #define NV_DMA_TARGET_MASK 0x000000ff |
| 36 | #define NV_DMA_TARGET_VM 0x00000000 | 44 | #define NV_DMA_TARGET_VM 0x00000000 |
| @@ -51,13 +59,21 @@ struct nv_dma_class { | |||
| 51 | u64 limit; | 59 | u64 limit; |
| 52 | }; | 60 | }; |
| 53 | 61 | ||
| 54 | /* 006b: NV03_CHANNEL_DMA | 62 | /* DMA FIFO channel classes |
| 63 | * | ||
| 64 | * 006b: NV03_CHANNEL_DMA | ||
| 55 | * 006e: NV10_CHANNEL_DMA | 65 | * 006e: NV10_CHANNEL_DMA |
| 56 | * 176e: NV17_CHANNEL_DMA | 66 | * 176e: NV17_CHANNEL_DMA |
| 57 | * 406e: NV40_CHANNEL_DMA | 67 | * 406e: NV40_CHANNEL_DMA |
| 58 | * 506e: NV50_CHANNEL_DMA | 68 | * 506e: NV50_CHANNEL_DMA |
| 59 | * 826e: NV84_CHANNEL_DMA | 69 | * 826e: NV84_CHANNEL_DMA |
| 60 | */ | 70 | */ |
| 71 | #define NV03_CHANNEL_DMA_CLASS 0x0000006b | ||
| 72 | #define NV10_CHANNEL_DMA_CLASS 0x0000006e | ||
| 73 | #define NV17_CHANNEL_DMA_CLASS 0x0000176e | ||
| 74 | #define NV40_CHANNEL_DMA_CLASS 0x0000406e | ||
| 75 | #define NV50_CHANNEL_DMA_CLASS 0x0000506e | ||
| 76 | #define NV84_CHANNEL_DMA_CLASS 0x0000826e | ||
| 61 | 77 | ||
| 62 | struct nv03_channel_dma_class { | 78 | struct nv03_channel_dma_class { |
| 63 | u32 pushbuf; | 79 | u32 pushbuf; |
| @@ -65,27 +81,32 @@ struct nv03_channel_dma_class { | |||
| 65 | u64 offset; | 81 | u64 offset; |
| 66 | }; | 82 | }; |
| 67 | 83 | ||
| 68 | /* 506f: NV50_CHANNEL_IND | 84 | /* Indirect FIFO channel classes |
| 85 | * | ||
| 86 | * 506f: NV50_CHANNEL_IND | ||
| 69 | * 826f: NV84_CHANNEL_IND | 87 | * 826f: NV84_CHANNEL_IND |
| 70 | * 906f: NVC0_CHANNEL_IND | 88 | * 906f: NVC0_CHANNEL_IND |
| 89 | * a06f: NVE0_CHANNEL_IND | ||
| 71 | */ | 90 | */ |
| 72 | 91 | ||
| 92 | #define NV50_CHANNEL_IND_CLASS 0x0000506f | ||
| 93 | #define NV84_CHANNEL_IND_CLASS 0x0000826f | ||
| 94 | #define NVC0_CHANNEL_IND_CLASS 0x0000906f | ||
| 95 | #define NVE0_CHANNEL_IND_CLASS 0x0000a06f | ||
| 96 | |||
| 73 | struct nv50_channel_ind_class { | 97 | struct nv50_channel_ind_class { |
| 74 | u32 pushbuf; | 98 | u32 pushbuf; |
| 75 | u32 ilength; | 99 | u32 ilength; |
| 76 | u64 ioffset; | 100 | u64 ioffset; |
| 77 | }; | 101 | }; |
| 78 | 102 | ||
| 79 | /* a06f: NVE0_CHANNEL_IND | 103 | #define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001 |
| 80 | */ | 104 | #define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002 |
| 81 | 105 | #define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004 | |
| 82 | #define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001 | 106 | #define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008 |
| 83 | #define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002 | 107 | #define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010 |
| 84 | #define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004 | 108 | #define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020 |
| 85 | #define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008 | 109 | #define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040 |
| 86 | #define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010 | ||
| 87 | #define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020 | ||
| 88 | #define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040 | ||
| 89 | 110 | ||
| 90 | struct nve0_channel_ind_class { | 111 | struct nve0_channel_ind_class { |
| 91 | u32 pushbuf; | 112 | u32 pushbuf; |