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authorTomoya <tomoya-linux@dsn.okisemi.com>2010-12-12 15:24:11 -0500
committerDavid S. Miller <davem@davemloft.net>2010-12-13 15:24:20 -0500
commit7f2bc50efeaeb1dff62ef7e128ae36499fbcf35d (patch)
tree3ad13a28f36021e76b94425a38833716dc7c083e /drivers
parent1d5b4b2778e8e40f42ae5d9556777583f3556d81 (diff)
pch_can: Fix warnings
Currently, in case CONFIG_PM is disabled, compiler outputs warnings. Move six functions which are used only CONFIG_PM is enabled, into "#ifdef CONFIG_PM" area. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/can/pch_can.c146
1 files changed, 73 insertions, 73 deletions
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index d646fbcd546a..5fc99cb10df0 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -245,23 +245,6 @@ static void pch_can_set_optmode(struct pch_can_priv *priv)
245 iowrite32(reg_val, &priv->regs->opt); 245 iowrite32(reg_val, &priv->regs->opt);
246} 246}
247 247
248static void pch_can_set_int_custom(struct pch_can_priv *priv)
249{
250 /* Clearing the IE, SIE and EIE bits of Can control register. */
251 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
252
253 /* Appropriately setting them. */
254 pch_can_bit_set(&priv->regs->cont,
255 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
256}
257
258/* This function retrieves interrupt enabled for the CAN device. */
259static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
260{
261 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
262 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
263}
264
265static void pch_can_set_int_enables(struct pch_can_priv *priv, 248static void pch_can_set_int_enables(struct pch_can_priv *priv,
266 enum pch_can_mode interrupt_no) 249 enum pch_can_mode interrupt_no)
267{ 250{
@@ -355,61 +338,11 @@ static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
355 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); 338 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
356} 339}
357 340
358static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
359 enum pch_ifreg dir)
360{
361 u32 ie, enable;
362
363 if (dir)
364 ie = PCH_IF_MCONT_RXIE;
365 else
366 ie = PCH_IF_MCONT_TXIE;
367
368 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
369 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
370
371 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
372 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
373 enable = 1;
374 } else {
375 enable = 0;
376 }
377 return enable;
378}
379
380static int pch_can_int_pending(struct pch_can_priv *priv) 341static int pch_can_int_pending(struct pch_can_priv *priv)
381{ 342{
382 return ioread32(&priv->regs->intr) & 0xffff; 343 return ioread32(&priv->regs->intr) & 0xffff;
383} 344}
384 345
385static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
386 u32 buffer_num, u32 set)
387{
388 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
389 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
390 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
391 &priv->regs->ifregs[0].cmask);
392 if (set == PCH_ENABLE)
393 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
394 PCH_IF_MCONT_EOB);
395 else
396 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
397
398 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
399}
400
401static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
402 u32 buffer_num, u32 *link)
403{
404 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
405 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
406
407 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
408 *link = PCH_DISABLE;
409 else
410 *link = PCH_ENABLE;
411}
412
413static void pch_can_clear_buffers(struct pch_can_priv *priv) 346static void pch_can_clear_buffers(struct pch_can_priv *priv)
414{ 347{
415 int i; 348 int i;
@@ -583,12 +516,6 @@ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
583 } 516 }
584} 517}
585 518
586static int pch_can_get_buffer_status(struct pch_can_priv *priv)
587{
588 return (ioread32(&priv->regs->treq1) & 0xffff) |
589 ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
590}
591
592static void pch_can_reset(struct pch_can_priv *priv) 519static void pch_can_reset(struct pch_can_priv *priv)
593{ 520{
594 /* write to sw reset register */ 521 /* write to sw reset register */
@@ -1109,6 +1036,79 @@ static void __devexit pch_can_remove(struct pci_dev *pdev)
1109} 1036}
1110 1037
1111#ifdef CONFIG_PM 1038#ifdef CONFIG_PM
1039static void pch_can_set_int_custom(struct pch_can_priv *priv)
1040{
1041 /* Clearing the IE, SIE and EIE bits of Can control register. */
1042 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
1043
1044 /* Appropriately setting them. */
1045 pch_can_bit_set(&priv->regs->cont,
1046 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
1047}
1048
1049/* This function retrieves interrupt enabled for the CAN device. */
1050static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
1051{
1052 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
1053 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
1054}
1055
1056static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
1057 enum pch_ifreg dir)
1058{
1059 u32 ie, enable;
1060
1061 if (dir)
1062 ie = PCH_IF_MCONT_RXIE;
1063 else
1064 ie = PCH_IF_MCONT_TXIE;
1065
1066 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
1067 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
1068
1069 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
1070 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
1071 enable = 1;
1072 } else {
1073 enable = 0;
1074 }
1075 return enable;
1076}
1077
1078static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
1079 u32 buffer_num, u32 set)
1080{
1081 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1082 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
1083 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1084 &priv->regs->ifregs[0].cmask);
1085 if (set == PCH_ENABLE)
1086 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1087 PCH_IF_MCONT_EOB);
1088 else
1089 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1090
1091 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
1092}
1093
1094static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
1095 u32 buffer_num, u32 *link)
1096{
1097 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1098 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
1099
1100 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
1101 *link = PCH_DISABLE;
1102 else
1103 *link = PCH_ENABLE;
1104}
1105
1106static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1107{
1108 return (ioread32(&priv->regs->treq1) & 0xffff) |
1109 ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
1110}
1111
1112static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) 1112static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1113{ 1113{
1114 int i; /* Counter variable. */ 1114 int i; /* Counter variable. */