diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-09-13 11:52:08 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2012-09-20 13:10:44 -0400 |
commit | 5df3196bac972138fa62ea17ed036161ae710062 (patch) | |
tree | 970fbbcd1a8a1d0e1b9c4eb51e4278398ea6a270 /drivers | |
parent | 19eca43e5a52a8e47fdd40e940912b2417c7c055 (diff) |
drm/radeon: store the encoder in the radeon_crtc
This saves lots of lookups later.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 373 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 1 |
2 files changed, 166 insertions, 208 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index cf8ac5a5d8ca..53a3b29d2d9d 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -83,25 +83,19 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) | |||
83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
84 | ENABLE_SCALER_PS_ALLOCATION args; | 84 | ENABLE_SCALER_PS_ALLOCATION args; |
85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); | 85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
86 | 86 | struct radeon_encoder *radeon_encoder = | |
87 | to_radeon_encoder(radeon_crtc->encoder); | ||
87 | /* fixme - fill in enc_priv for atom dac */ | 88 | /* fixme - fill in enc_priv for atom dac */ |
88 | enum radeon_tv_std tv_std = TV_STD_NTSC; | 89 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
89 | bool is_tv = false, is_cv = false; | 90 | bool is_tv = false, is_cv = false; |
90 | struct drm_encoder *encoder; | ||
91 | 91 | ||
92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) | 92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
93 | return; | 93 | return; |
94 | 94 | ||
95 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 95 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
96 | /* find tv std */ | 96 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
97 | if (encoder->crtc == crtc) { | 97 | tv_std = tv_dac->tv_std; |
98 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 98 | is_tv = true; |
99 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { | ||
100 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; | ||
101 | tv_std = tv_dac->tv_std; | ||
102 | is_tv = true; | ||
103 | } | ||
104 | } | ||
105 | } | 99 | } |
106 | 100 | ||
107 | memset(&args, 0, sizeof(args)); | 101 | memset(&args, 0, sizeof(args)); |
@@ -538,14 +532,14 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
538 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 532 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
539 | struct drm_device *dev = crtc->dev; | 533 | struct drm_device *dev = crtc->dev; |
540 | struct radeon_device *rdev = dev->dev_private; | 534 | struct radeon_device *rdev = dev->dev_private; |
541 | struct drm_encoder *encoder = NULL; | 535 | struct drm_encoder *encoder = radeon_crtc->encoder; |
542 | struct radeon_encoder *radeon_encoder = NULL; | 536 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
543 | struct drm_connector *connector = NULL; | 537 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
544 | u32 adjusted_clock = mode->clock; | 538 | u32 adjusted_clock = mode->clock; |
545 | int encoder_mode = 0; | 539 | int encoder_mode = atombios_get_encoder_mode(encoder); |
546 | u32 dp_clock = mode->clock; | 540 | u32 dp_clock = mode->clock; |
547 | int bpc = 8; | 541 | int bpc = radeon_get_monitor_bpc(connector); |
548 | bool is_duallink = false; | 542 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
549 | 543 | ||
550 | /* reset the pll flags */ | 544 | /* reset the pll flags */ |
551 | radeon_crtc->pll_flags = 0; | 545 | radeon_crtc->pll_flags = 0; |
@@ -576,54 +570,44 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
576 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; | 570 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
577 | } | 571 | } |
578 | 572 | ||
579 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 573 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
580 | if (encoder->crtc == crtc) { | 574 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
581 | radeon_encoder = to_radeon_encoder(encoder); | 575 | if (connector) { |
582 | connector = radeon_get_connector_for_encoder(encoder); | 576 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
583 | bpc = radeon_get_monitor_bpc(connector); | 577 | struct radeon_connector_atom_dig *dig_connector = |
584 | encoder_mode = atombios_get_encoder_mode(encoder); | 578 | radeon_connector->con_priv; |
585 | is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); | ||
586 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || | ||
587 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { | ||
588 | if (connector) { | ||
589 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | ||
590 | struct radeon_connector_atom_dig *dig_connector = | ||
591 | radeon_connector->con_priv; | ||
592 | |||
593 | dp_clock = dig_connector->dp_clock; | ||
594 | } | ||
595 | } | ||
596 | 579 | ||
597 | /* use recommended ref_div for ss */ | 580 | dp_clock = dig_connector->dp_clock; |
598 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | 581 | } |
599 | if (radeon_crtc->ss_enabled) { | 582 | } |
600 | if (radeon_crtc->ss.refdiv) { | ||
601 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | ||
602 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; | ||
603 | if (ASIC_IS_AVIVO(rdev)) | ||
604 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; | ||
605 | } | ||
606 | } | ||
607 | } | ||
608 | 583 | ||
609 | if (ASIC_IS_AVIVO(rdev)) { | 584 | /* use recommended ref_div for ss */ |
610 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ | 585 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
611 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) | 586 | if (radeon_crtc->ss_enabled) { |
612 | adjusted_clock = mode->clock * 2; | 587 | if (radeon_crtc->ss.refdiv) { |
613 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | 588 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
614 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; | 589 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; |
615 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | 590 | if (ASIC_IS_AVIVO(rdev)) |
616 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; | 591 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
617 | } else { | ||
618 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) | ||
619 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; | ||
620 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) | ||
621 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | ||
622 | } | 592 | } |
623 | break; | ||
624 | } | 593 | } |
625 | } | 594 | } |
626 | 595 | ||
596 | if (ASIC_IS_AVIVO(rdev)) { | ||
597 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ | ||
598 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) | ||
599 | adjusted_clock = mode->clock * 2; | ||
600 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | ||
601 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; | ||
602 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | ||
603 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; | ||
604 | } else { | ||
605 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) | ||
606 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; | ||
607 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) | ||
608 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | ||
609 | } | ||
610 | |||
627 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock | 611 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
628 | * accordingly based on the encoder/transmitter to work around | 612 | * accordingly based on the encoder/transmitter to work around |
629 | * special hw requirements. | 613 | * special hw requirements. |
@@ -913,29 +897,18 @@ static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_ | |||
913 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 897 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
914 | struct drm_device *dev = crtc->dev; | 898 | struct drm_device *dev = crtc->dev; |
915 | struct radeon_device *rdev = dev->dev_private; | 899 | struct radeon_device *rdev = dev->dev_private; |
916 | struct drm_encoder *encoder = NULL; | 900 | struct radeon_encoder *radeon_encoder = |
917 | struct radeon_encoder *radeon_encoder = NULL; | 901 | to_radeon_encoder(radeon_crtc->encoder); |
918 | int encoder_mode = 0; | 902 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
919 | 903 | ||
920 | radeon_crtc->bpc = 8; | 904 | radeon_crtc->bpc = 8; |
921 | radeon_crtc->ss_enabled = false; | 905 | radeon_crtc->ss_enabled = false; |
922 | 906 | ||
923 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | ||
924 | if (encoder->crtc == crtc) { | ||
925 | radeon_encoder = to_radeon_encoder(encoder); | ||
926 | encoder_mode = atombios_get_encoder_mode(encoder); | ||
927 | break; | ||
928 | } | ||
929 | } | ||
930 | |||
931 | if (!radeon_encoder) | ||
932 | return false; | ||
933 | |||
934 | if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || | 907 | if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
935 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { | 908 | (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { |
936 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 909 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
937 | struct drm_connector *connector = | 910 | struct drm_connector *connector = |
938 | radeon_get_connector_for_encoder(encoder); | 911 | radeon_get_connector_for_encoder(radeon_crtc->encoder); |
939 | struct radeon_connector *radeon_connector = | 912 | struct radeon_connector *radeon_connector = |
940 | to_radeon_connector(connector); | 913 | to_radeon_connector(connector); |
941 | struct radeon_connector_atom_dig *dig_connector = | 914 | struct radeon_connector_atom_dig *dig_connector = |
@@ -1016,23 +989,12 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode | |||
1016 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 989 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1017 | struct drm_device *dev = crtc->dev; | 990 | struct drm_device *dev = crtc->dev; |
1018 | struct radeon_device *rdev = dev->dev_private; | 991 | struct radeon_device *rdev = dev->dev_private; |
1019 | struct drm_encoder *encoder = NULL; | 992 | struct radeon_encoder *radeon_encoder = |
1020 | struct radeon_encoder *radeon_encoder = NULL; | 993 | to_radeon_encoder(radeon_crtc->encoder); |
1021 | u32 pll_clock = mode->clock; | 994 | u32 pll_clock = mode->clock; |
1022 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; | 995 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
1023 | struct radeon_pll *pll; | 996 | struct radeon_pll *pll; |
1024 | int encoder_mode = 0; | 997 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
1025 | |||
1026 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | ||
1027 | if (encoder->crtc == crtc) { | ||
1028 | radeon_encoder = to_radeon_encoder(encoder); | ||
1029 | encoder_mode = atombios_get_encoder_mode(encoder); | ||
1030 | break; | ||
1031 | } | ||
1032 | } | ||
1033 | |||
1034 | if (!radeon_encoder) | ||
1035 | return; | ||
1036 | 998 | ||
1037 | switch (radeon_crtc->pll_id) { | 999 | switch (radeon_crtc->pll_id) { |
1038 | case ATOM_PPLL1: | 1000 | case ATOM_PPLL1: |
@@ -1557,15 +1519,15 @@ static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) | |||
1557 | { | 1519 | { |
1558 | struct drm_device *dev = crtc->dev; | 1520 | struct drm_device *dev = crtc->dev; |
1559 | struct drm_encoder *test_encoder; | 1521 | struct drm_encoder *test_encoder; |
1560 | struct radeon_crtc *radeon_test_crtc; | 1522 | struct radeon_crtc *test_radeon_crtc; |
1561 | 1523 | ||
1562 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | 1524 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1563 | if (test_encoder->crtc && (test_encoder->crtc != crtc)) { | 1525 | if (test_encoder->crtc && (test_encoder->crtc != crtc)) { |
1564 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | 1526 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { |
1565 | /* for DP use the same PLL for all */ | 1527 | /* for DP use the same PLL for all */ |
1566 | radeon_test_crtc = to_radeon_crtc(test_encoder->crtc); | 1528 | test_radeon_crtc = to_radeon_crtc(test_encoder->crtc); |
1567 | if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID) | 1529 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1568 | return radeon_test_crtc->pll_id; | 1530 | return test_radeon_crtc->pll_id; |
1569 | } | 1531 | } |
1570 | } | 1532 | } |
1571 | } | 1533 | } |
@@ -1581,13 +1543,14 @@ static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) | |||
1581 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can | 1543 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can |
1582 | * be shared (i.e., same clock). | 1544 | * be shared (i.e., same clock). |
1583 | */ | 1545 | */ |
1584 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc, | 1546 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
1585 | struct drm_encoder *encoder) | ||
1586 | { | 1547 | { |
1548 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
1587 | struct drm_device *dev = crtc->dev; | 1549 | struct drm_device *dev = crtc->dev; |
1588 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 1550 | struct radeon_encoder *radeon_encoder = |
1551 | to_radeon_encoder(radeon_crtc->encoder); | ||
1589 | struct drm_encoder *test_encoder; | 1552 | struct drm_encoder *test_encoder; |
1590 | struct radeon_crtc *radeon_test_crtc; | 1553 | struct radeon_crtc *test_radeon_crtc; |
1591 | struct radeon_encoder *test_radeon_encoder; | 1554 | struct radeon_encoder *test_radeon_encoder; |
1592 | u32 target_clock, test_clock; | 1555 | u32 target_clock, test_clock; |
1593 | 1556 | ||
@@ -1600,15 +1563,15 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc, | |||
1600 | if (test_encoder->crtc && (test_encoder->crtc != crtc)) { | 1563 | if (test_encoder->crtc && (test_encoder->crtc != crtc)) { |
1601 | if (!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | 1564 | if (!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { |
1602 | test_radeon_encoder = to_radeon_encoder(test_encoder); | 1565 | test_radeon_encoder = to_radeon_encoder(test_encoder); |
1603 | radeon_test_crtc = to_radeon_crtc(test_encoder->crtc); | 1566 | test_radeon_crtc = to_radeon_crtc(test_encoder->crtc); |
1604 | /* for non-DP check the clock */ | 1567 | /* for non-DP check the clock */ |
1605 | if (test_radeon_encoder->native_mode.clock) | 1568 | if (test_radeon_encoder->native_mode.clock) |
1606 | test_clock = test_radeon_encoder->native_mode.clock; | 1569 | test_clock = test_radeon_encoder->native_mode.clock; |
1607 | else | 1570 | else |
1608 | test_clock = test_encoder->crtc->mode.clock; | 1571 | test_clock = test_encoder->crtc->mode.clock; |
1609 | if ((target_clock == test_clock) && | 1572 | if ((target_clock == test_clock) && |
1610 | (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)) | 1573 | (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) |
1611 | return radeon_test_crtc->pll_id; | 1574 | return test_radeon_crtc->pll_id; |
1612 | } | 1575 | } |
1613 | } | 1576 | } |
1614 | } | 1577 | } |
@@ -1648,44 +1611,38 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc, | |||
1648 | */ | 1611 | */ |
1649 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) | 1612 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1650 | { | 1613 | { |
1614 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
1651 | struct drm_device *dev = crtc->dev; | 1615 | struct drm_device *dev = crtc->dev; |
1652 | struct radeon_device *rdev = dev->dev_private; | 1616 | struct radeon_device *rdev = dev->dev_private; |
1653 | struct drm_encoder *test_encoder; | 1617 | struct radeon_encoder *radeon_encoder = |
1618 | to_radeon_encoder(radeon_crtc->encoder); | ||
1654 | u32 pll_in_use; | 1619 | u32 pll_in_use; |
1655 | int pll; | 1620 | int pll; |
1656 | 1621 | ||
1657 | if (ASIC_IS_DCE61(rdev)) { | 1622 | if (ASIC_IS_DCE61(rdev)) { |
1658 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | 1623 | struct radeon_encoder_atom_dig *dig = |
1659 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { | 1624 | radeon_encoder->enc_priv; |
1660 | struct radeon_encoder *test_radeon_encoder = | 1625 | |
1661 | to_radeon_encoder(test_encoder); | 1626 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && |
1662 | struct radeon_encoder_atom_dig *dig = | 1627 | (dig->linkb == false)) |
1663 | test_radeon_encoder->enc_priv; | 1628 | /* UNIPHY A uses PPLL2 */ |
1664 | 1629 | return ATOM_PPLL2; | |
1665 | if ((test_radeon_encoder->encoder_id == | 1630 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1666 | ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && | 1631 | /* UNIPHY B/C/D/E/F */ |
1667 | (dig->linkb == false)) | 1632 | if (rdev->clock.dp_extclk) |
1668 | /* UNIPHY A uses PPLL2 */ | 1633 | /* skip PPLL programming if using ext clock */ |
1669 | return ATOM_PPLL2; | 1634 | return ATOM_PPLL_INVALID; |
1670 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | 1635 | else { |
1671 | /* UNIPHY B/C/D/E/F */ | 1636 | /* use the same PPLL for all DP monitors */ |
1672 | if (rdev->clock.dp_extclk) | 1637 | pll = radeon_get_shared_dp_ppll(crtc); |
1673 | /* skip PPLL programming if using ext clock */ | 1638 | if (pll != ATOM_PPLL_INVALID) |
1674 | return ATOM_PPLL_INVALID; | 1639 | return pll; |
1675 | else { | ||
1676 | /* use the same PPLL for all DP monitors */ | ||
1677 | pll = radeon_get_shared_dp_ppll(crtc); | ||
1678 | if (pll != ATOM_PPLL_INVALID) | ||
1679 | return pll; | ||
1680 | } | ||
1681 | } else { | ||
1682 | /* use the same PPLL for all monitors with the same clock */ | ||
1683 | pll = radeon_get_shared_nondp_ppll(crtc, test_encoder); | ||
1684 | if (pll != ATOM_PPLL_INVALID) | ||
1685 | return pll; | ||
1686 | } | ||
1687 | break; | ||
1688 | } | 1640 | } |
1641 | } else { | ||
1642 | /* use the same PPLL for all monitors with the same clock */ | ||
1643 | pll = radeon_get_shared_nondp_ppll(crtc); | ||
1644 | if (pll != ATOM_PPLL_INVALID) | ||
1645 | return pll; | ||
1689 | } | 1646 | } |
1690 | /* UNIPHY B/C/D/E/F */ | 1647 | /* UNIPHY B/C/D/E/F */ |
1691 | pll_in_use = radeon_get_pll_use_mask(crtc); | 1648 | pll_in_use = radeon_get_pll_use_mask(crtc); |
@@ -1696,42 +1653,37 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1696 | DRM_ERROR("unable to allocate a PPLL\n"); | 1653 | DRM_ERROR("unable to allocate a PPLL\n"); |
1697 | return ATOM_PPLL_INVALID; | 1654 | return ATOM_PPLL_INVALID; |
1698 | } else if (ASIC_IS_DCE4(rdev)) { | 1655 | } else if (ASIC_IS_DCE4(rdev)) { |
1699 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | 1656 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1700 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { | 1657 | * depending on the asic: |
1701 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, | 1658 | * DCE4: PPLL or ext clock |
1702 | * depending on the asic: | 1659 | * DCE5: PPLL, DCPLL, or ext clock |
1703 | * DCE4: PPLL or ext clock | 1660 | * DCE6: PPLL, PPLL0, or ext clock |
1704 | * DCE5: PPLL, DCPLL, or ext clock | 1661 | * |
1705 | * DCE6: PPLL, PPLL0, or ext clock | 1662 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip |
1706 | * | 1663 | * PPLL/DCPLL programming and only program the DP DTO for the |
1707 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip | 1664 | * crtc virtual pixel clock. |
1708 | * PPLL/DCPLL programming and only program the DP DTO for the | 1665 | */ |
1709 | * crtc virtual pixel clock. | 1666 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1710 | */ | 1667 | if (rdev->clock.dp_extclk) |
1711 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | 1668 | /* skip PPLL programming if using ext clock */ |
1712 | if (rdev->clock.dp_extclk) | 1669 | return ATOM_PPLL_INVALID; |
1713 | /* skip PPLL programming if using ext clock */ | 1670 | else if (ASIC_IS_DCE6(rdev)) |
1714 | return ATOM_PPLL_INVALID; | 1671 | /* use PPLL0 for all DP */ |
1715 | else if (ASIC_IS_DCE6(rdev)) | 1672 | return ATOM_PPLL0; |
1716 | /* use PPLL0 for all DP */ | 1673 | else if (ASIC_IS_DCE5(rdev)) |
1717 | return ATOM_PPLL0; | 1674 | /* use DCPLL for all DP */ |
1718 | else if (ASIC_IS_DCE5(rdev)) | 1675 | return ATOM_DCPLL; |
1719 | /* use DCPLL for all DP */ | 1676 | else { |
1720 | return ATOM_DCPLL; | 1677 | /* use the same PPLL for all DP monitors */ |
1721 | else { | 1678 | pll = radeon_get_shared_dp_ppll(crtc); |
1722 | /* use the same PPLL for all DP monitors */ | 1679 | if (pll != ATOM_PPLL_INVALID) |
1723 | pll = radeon_get_shared_dp_ppll(crtc); | 1680 | return pll; |
1724 | if (pll != ATOM_PPLL_INVALID) | ||
1725 | return pll; | ||
1726 | } | ||
1727 | } else { | ||
1728 | /* use the same PPLL for all monitors with the same clock */ | ||
1729 | pll = radeon_get_shared_nondp_ppll(crtc, test_encoder); | ||
1730 | if (pll != ATOM_PPLL_INVALID) | ||
1731 | return pll; | ||
1732 | } | ||
1733 | break; | ||
1734 | } | 1681 | } |
1682 | } else { | ||
1683 | /* use the same PPLL for all monitors with the same clock */ | ||
1684 | pll = radeon_get_shared_nondp_ppll(crtc); | ||
1685 | if (pll != ATOM_PPLL_INVALID) | ||
1686 | return pll; | ||
1735 | } | 1687 | } |
1736 | /* all other cases */ | 1688 | /* all other cases */ |
1737 | pll_in_use = radeon_get_pll_use_mask(crtc); | 1689 | pll_in_use = radeon_get_pll_use_mask(crtc); |
@@ -1742,39 +1694,34 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1742 | DRM_ERROR("unable to allocate a PPLL\n"); | 1694 | DRM_ERROR("unable to allocate a PPLL\n"); |
1743 | return ATOM_PPLL_INVALID; | 1695 | return ATOM_PPLL_INVALID; |
1744 | } else { | 1696 | } else { |
1745 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ | 1697 | if (ASIC_IS_AVIVO(rdev)) { |
1746 | if (!ASIC_IS_AVIVO(rdev)) { | 1698 | /* in DP mode, the DP ref clock can come from either PPLL |
1747 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 1699 | * depending on the asic: |
1748 | return radeon_crtc->crtc_id; | 1700 | * DCE3: PPLL1 or PPLL2 |
1749 | } | 1701 | */ |
1750 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | 1702 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1751 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { | 1703 | /* use the same PPLL for all DP monitors */ |
1752 | /* in DP mode, the DP ref clock can come from either PPLL | 1704 | pll = radeon_get_shared_dp_ppll(crtc); |
1753 | * depending on the asic: | 1705 | if (pll != ATOM_PPLL_INVALID) |
1754 | * DCE3: PPLL1 or PPLL2 | 1706 | return pll; |
1755 | */ | 1707 | } else { |
1756 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | 1708 | /* use the same PPLL for all monitors with the same clock */ |
1757 | /* use the same PPLL for all DP monitors */ | 1709 | pll = radeon_get_shared_nondp_ppll(crtc); |
1758 | pll = radeon_get_shared_dp_ppll(crtc); | 1710 | if (pll != ATOM_PPLL_INVALID) |
1759 | if (pll != ATOM_PPLL_INVALID) | 1711 | return pll; |
1760 | return pll; | ||
1761 | } else { | ||
1762 | /* use the same PPLL for all monitors with the same clock */ | ||
1763 | pll = radeon_get_shared_nondp_ppll(crtc, test_encoder); | ||
1764 | if (pll != ATOM_PPLL_INVALID) | ||
1765 | return pll; | ||
1766 | } | ||
1767 | break; | ||
1768 | } | 1712 | } |
1713 | /* all other cases */ | ||
1714 | pll_in_use = radeon_get_pll_use_mask(crtc); | ||
1715 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | ||
1716 | return ATOM_PPLL2; | ||
1717 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | ||
1718 | return ATOM_PPLL1; | ||
1719 | DRM_ERROR("unable to allocate a PPLL\n"); | ||
1720 | return ATOM_PPLL_INVALID; | ||
1721 | } else { | ||
1722 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ | ||
1723 | return radeon_crtc->crtc_id; | ||
1769 | } | 1724 | } |
1770 | /* all other cases */ | ||
1771 | pll_in_use = radeon_get_pll_use_mask(crtc); | ||
1772 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | ||
1773 | return ATOM_PPLL2; | ||
1774 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | ||
1775 | return ATOM_PPLL1; | ||
1776 | DRM_ERROR("unable to allocate a PPLL\n"); | ||
1777 | return ATOM_PPLL_INVALID; | ||
1778 | } | 1725 | } |
1779 | } | 1726 | } |
1780 | 1727 | ||
@@ -1806,18 +1753,13 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, | |||
1806 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 1753 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1807 | struct drm_device *dev = crtc->dev; | 1754 | struct drm_device *dev = crtc->dev; |
1808 | struct radeon_device *rdev = dev->dev_private; | 1755 | struct radeon_device *rdev = dev->dev_private; |
1809 | struct drm_encoder *encoder; | 1756 | struct radeon_encoder *radeon_encoder = |
1757 | to_radeon_encoder(radeon_crtc->encoder); | ||
1810 | bool is_tvcv = false; | 1758 | bool is_tvcv = false; |
1811 | 1759 | ||
1812 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 1760 | if (radeon_encoder->active_device & |
1813 | /* find tv std */ | 1761 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1814 | if (encoder->crtc == crtc) { | 1762 | is_tvcv = true; |
1815 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
1816 | if (radeon_encoder->active_device & | ||
1817 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | ||
1818 | is_tvcv = true; | ||
1819 | } | ||
1820 | } | ||
1821 | 1763 | ||
1822 | atombios_crtc_set_pll(crtc, adjusted_mode); | 1764 | atombios_crtc_set_pll(crtc, adjusted_mode); |
1823 | 1765 | ||
@@ -1844,6 +1786,19 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, | |||
1844 | const struct drm_display_mode *mode, | 1786 | const struct drm_display_mode *mode, |
1845 | struct drm_display_mode *adjusted_mode) | 1787 | struct drm_display_mode *adjusted_mode) |
1846 | { | 1788 | { |
1789 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
1790 | struct drm_device *dev = crtc->dev; | ||
1791 | struct drm_encoder *encoder; | ||
1792 | |||
1793 | /* assign the encoder to the radeon crtc to avoid repeated lookups later */ | ||
1794 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | ||
1795 | if (encoder->crtc == crtc) { | ||
1796 | radeon_crtc->encoder = encoder; | ||
1797 | break; | ||
1798 | } | ||
1799 | } | ||
1800 | if (radeon_crtc->encoder == NULL) | ||
1801 | return false; | ||
1847 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) | 1802 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1848 | return false; | 1803 | return false; |
1849 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) | 1804 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
@@ -1918,6 +1873,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) | |||
1918 | } | 1873 | } |
1919 | done: | 1874 | done: |
1920 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; | 1875 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
1876 | radeon_crtc->encoder = NULL; | ||
1921 | } | 1877 | } |
1922 | 1878 | ||
1923 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { | 1879 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
@@ -1967,5 +1923,6 @@ void radeon_atombios_init_crtc(struct drm_device *dev, | |||
1967 | radeon_crtc->crtc_offset = 0; | 1923 | radeon_crtc->crtc_offset = 0; |
1968 | } | 1924 | } |
1969 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; | 1925 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
1926 | radeon_crtc->encoder = NULL; | ||
1970 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); | 1927 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
1971 | } | 1928 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 9f45e4bf06e9..2d78645576d7 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -326,6 +326,7 @@ struct radeon_crtc { | |||
326 | u32 pll_reference_div; | 326 | u32 pll_reference_div; |
327 | u32 pll_post_div; | 327 | u32 pll_post_div; |
328 | u32 pll_flags; | 328 | u32 pll_flags; |
329 | struct drm_encoder *encoder; | ||
329 | }; | 330 | }; |
330 | 331 | ||
331 | struct radeon_encoder_primary_dac { | 332 | struct radeon_encoder_primary_dac { |