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authorSonic Zhang <sonic.zhang@analog.com>2012-05-16 02:22:26 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-05-17 16:25:56 -0400
commit59bd234b72fc29887839d792b7d6c7e8d2a577a6 (patch)
tree88bf5f49e90ccb7300621c23076355b392574715 /drivers
parent3c2d0ed221a22ce2c1c9fe1e2d6142374917642e (diff)
serial: bfin_uart: Make MMR access compatible with 32 bits bf609 style controller.
Simplify serial data width calculation and adapt to bf609 LCR bit mask. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/tty/serial/bfin_uart.c20
1 files changed, 4 insertions, 16 deletions
diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c
index 7924ba6d5dfb..bd97db23985b 100644
--- a/drivers/tty/serial/bfin_uart.c
+++ b/drivers/tty/serial/bfin_uart.c
@@ -594,7 +594,7 @@ static unsigned int bfin_serial_tx_empty(struct uart_port *port)
594static void bfin_serial_break_ctl(struct uart_port *port, int break_state) 594static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
595{ 595{
596 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 596 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
597 u16 lcr = UART_GET_LCR(uart); 597 u32 lcr = UART_GET_LCR(uart);
598 if (break_state) 598 if (break_state)
599 lcr |= SB; 599 lcr |= SB;
600 else 600 else
@@ -1068,7 +1068,7 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1068 status = UART_GET_IER(uart) & (ERBFI | ETBEI); 1068 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1069 if (status == (ERBFI | ETBEI)) { 1069 if (status == (ERBFI | ETBEI)) {
1070 /* ok, the port was enabled */ 1070 /* ok, the port was enabled */
1071 u16 lcr, clk; 1071 u32 lcr, clk;
1072 1072
1073 lcr = UART_GET_LCR(uart); 1073 lcr = UART_GET_LCR(uart);
1074 1074
@@ -1079,20 +1079,8 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1079 else 1079 else
1080 *parity = 'o'; 1080 *parity = 'o';
1081 } 1081 }
1082 switch (lcr & 0x03) { 1082 *bits = ((lcr & WLS_MASK) >> WLS_OFFSET) + 5;
1083 case 0: 1083
1084 *bits = 5;
1085 break;
1086 case 1:
1087 *bits = 6;
1088 break;
1089 case 2:
1090 *bits = 7;
1091 break;
1092 case 3:
1093 *bits = 8;
1094 break;
1095 }
1096 /* Set DLAB in LCR to Access CLK */ 1084 /* Set DLAB in LCR to Access CLK */
1097 UART_SET_DLAB(uart); 1085 UART_SET_DLAB(uart);
1098 1086