diff options
author | Brian Niebuhr <bniebuhr@efjohnson.com> | 2010-10-06 08:55:43 -0400 |
---|---|---|
committer | Sekhar Nori <nsekhar@ti.com> | 2010-11-18 08:08:36 -0500 |
commit | 3f27b57c1684efbe11fcc9449df898b1d0feb753 (patch) | |
tree | a86d646987b05e4306eaf145bc7c2609dd9b7566 /drivers | |
parent | 3409e408ab0d7171ae81d198110a1f293852959f (diff) |
spi: davinci: enable and power-up SPI only when required
Enable SPI only when active transfers are in progress. Keep
it in local low power when not in use.
Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com>
Tested-By: Michael Williamson <michael.williamson@criticallink.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/spi/davinci_spi.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 2e74fcd2f423..1652bba955e2 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c | |||
@@ -49,7 +49,6 @@ | |||
49 | #define SPIFMT_WDELAY_SHIFT 24 | 49 | #define SPIFMT_WDELAY_SHIFT 24 |
50 | #define SPIFMT_PRESCALE_SHIFT 8 | 50 | #define SPIFMT_PRESCALE_SHIFT 8 |
51 | 51 | ||
52 | |||
53 | /* SPIPC0 */ | 52 | /* SPIPC0 */ |
54 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | 53 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ |
55 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | 54 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ |
@@ -67,6 +66,7 @@ | |||
67 | /* SPIGCR1 */ | 66 | /* SPIGCR1 */ |
68 | #define SPIGCR1_CLKMOD_MASK BIT(1) | 67 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
69 | #define SPIGCR1_MASTER_MASK BIT(0) | 68 | #define SPIGCR1_MASTER_MASK BIT(0) |
69 | #define SPIGCR1_POWERDOWN_MASK BIT(8) | ||
70 | #define SPIGCR1_LOOPBACK_MASK BIT(16) | 70 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
71 | #define SPIGCR1_SPIENA_MASK BIT(24) | 71 | #define SPIGCR1_SPIENA_MASK BIT(24) |
72 | 72 | ||
@@ -556,7 +556,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | |||
556 | 556 | ||
557 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); | 557 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
558 | 558 | ||
559 | /* Enable SPI */ | 559 | clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
560 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | 560 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
561 | 561 | ||
562 | INIT_COMPLETION(davinci_spi->done); | 562 | INIT_COMPLETION(davinci_spi->done); |
@@ -693,6 +693,9 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | |||
693 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | 693 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); |
694 | } | 694 | } |
695 | 695 | ||
696 | clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | ||
697 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | ||
698 | |||
696 | /* | 699 | /* |
697 | * Check for bit error, desync error,parity error,timeout error and | 700 | * Check for bit error, desync error,parity error,timeout error and |
698 | * receive overflow errors | 701 | * receive overflow errors |
@@ -937,6 +940,7 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
937 | /* master mode default */ | 940 | /* master mode default */ |
938 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); | 941 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
939 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | 942 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); |
943 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | ||
940 | 944 | ||
941 | ret = spi_bitbang_start(&davinci_spi->bitbang); | 945 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
942 | if (ret) | 946 | if (ret) |