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authorRoland Vossen <rvossen@broadcom.com>2011-10-18 08:03:00 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-11-08 15:54:03 -0500
commit3b64bd3e4d0ae667062893a6ef30326f7103144e (patch)
tree6e7553e5d284dbd3459f83efdc1be729bae1c873 /drivers
parent6b1a89afbf97f40797255b9543d441ce361dbb52 (diff)
brcm80211: smac: removed support for SROM rev < 8
Supported chips contain SROM rev 8 and upwards. Reported-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.c376
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.h5
2 files changed, 34 insertions, 347 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.c b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
index b52b0d29f61d..a884fe072dac 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
@@ -63,9 +63,6 @@
63#define SROM_MACHI_ET1 42 63#define SROM_MACHI_ET1 42
64#define SROM_MACMID_ET1 43 64#define SROM_MACMID_ET1 43
65#define SROM_MACLO_ET1 44 65#define SROM_MACLO_ET1 44
66#define SROM3_MACHI 37
67#define SROM3_MACMID 38
68#define SROM3_MACLO 39
69 66
70#define SROM_BXARSSI2G 40 67#define SROM_BXARSSI2G 40
71#define SROM_BXARSSI5G 41 68#define SROM_BXARSSI5G 41
@@ -102,7 +99,6 @@
102 99
103#define SROM_BFL 57 100#define SROM_BFL 57
104#define SROM_BFL2 28 101#define SROM_BFL2 28
105#define SROM3_BFL2 61
106 102
107#define SROM_AG10 58 103#define SROM_AG10 58
108 104
@@ -110,99 +106,16 @@
110 106
111#define SROM_OPO 60 107#define SROM_OPO 60
112 108
113#define SROM3_LEDDC 62
114
115#define SROM_CRCREV 63 109#define SROM_CRCREV 63
116 110
117/* SROM Rev 4: Reallocate the software part of the srom to accommodate
118 * MIMO features. It assumes up to two PCIE functions and 440 bytes
119 * of usable srom i.e. the usable storage in chips with OTP that
120 * implements hardware redundancy.
121 */
122
123#define SROM4_WORDS 220 111#define SROM4_WORDS 220
124 112
125#define SROM4_SIGN 32
126#define SROM4_SIGNATURE 0x5372
127
128#define SROM4_BREV 33
129
130#define SROM4_BFL0 34
131#define SROM4_BFL1 35
132#define SROM4_BFL2 36
133#define SROM4_BFL3 37
134#define SROM5_BFL0 37
135#define SROM5_BFL1 38
136#define SROM5_BFL2 39
137#define SROM5_BFL3 40
138
139#define SROM4_MACHI 38
140#define SROM4_MACMID 39
141#define SROM4_MACLO 40
142#define SROM5_MACHI 41
143#define SROM5_MACMID 42
144#define SROM5_MACLO 43
145
146#define SROM4_CCODE 41
147#define SROM4_REGREV 42
148#define SROM5_CCODE 34
149#define SROM5_REGREV 35
150
151#define SROM4_LEDBH10 43
152#define SROM4_LEDBH32 44
153#define SROM5_LEDBH10 59
154#define SROM5_LEDBH32 60
155
156#define SROM4_LEDDC 45
157#define SROM5_LEDDC 45
158
159#define SROM4_AA 46
160
161#define SROM4_AG10 47
162#define SROM4_AG32 48
163
164#define SROM4_TXPID2G 49
165#define SROM4_TXPID5G 51
166#define SROM4_TXPID5GL 53
167#define SROM4_TXPID5GH 55
168
169#define SROM4_TXRXC 61
170#define SROM4_TXCHAIN_MASK 0x000f 113#define SROM4_TXCHAIN_MASK 0x000f
171#define SROM4_TXCHAIN_SHIFT 0
172#define SROM4_RXCHAIN_MASK 0x00f0 114#define SROM4_RXCHAIN_MASK 0x00f0
173#define SROM4_RXCHAIN_SHIFT 4
174#define SROM4_SWITCH_MASK 0xff00 115#define SROM4_SWITCH_MASK 0xff00
175#define SROM4_SWITCH_SHIFT 8
176 116
177/* Per-path fields */ 117/* Per-path fields */
178#define MAX_PATH_SROM 4 118#define MAX_PATH_SROM 4
179#define SROM4_PATH0 64
180#define SROM4_PATH1 87
181#define SROM4_PATH2 110
182#define SROM4_PATH3 133
183
184#define SROM4_2G_ITT_MAXP 0
185#define SROM4_2G_PA 1
186#define SROM4_5G_ITT_MAXP 5
187#define SROM4_5GLH_MAXP 6
188#define SROM4_5G_PA 7
189#define SROM4_5GL_PA 11
190#define SROM4_5GH_PA 15
191
192/* All the miriad power offsets */
193#define SROM4_2G_CCKPO 156
194#define SROM4_2G_OFDMPO 157
195#define SROM4_5G_OFDMPO 159
196#define SROM4_5GL_OFDMPO 161
197#define SROM4_5GH_OFDMPO 163
198#define SROM4_2G_MCSPO 165
199#define SROM4_5G_MCSPO 173
200#define SROM4_5GL_MCSPO 181
201#define SROM4_5GH_MCSPO 189
202#define SROM4_CDDPO 197
203#define SROM4_STBCPO 198
204#define SROM4_BW40PO 199
205#define SROM4_BWDUPPO 200
206 119
207#define SROM4_CRCREV 219 120#define SROM4_CRCREV 219
208 121
@@ -425,103 +338,32 @@ struct brcms_varbuf {
425static const struct brcms_sromvar pci_sromvars[] = { 338static const struct brcms_sromvar pci_sromvars[] = {
426 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 339 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
427 0xffff}, 340 0xffff},
428 {BRCMS_SROM_BOARDREV, 0x0000000e, SRFL_PRHEX, SROM_AABREV,
429 SROM_BR_MASK},
430 {BRCMS_SROM_BOARDREV, 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
431 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, 341 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
432 {BRCMS_SROM_BOARDFLAGS, 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
433 {BRCMS_SROM_BOARDFLAGS, 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
434 0xffff},
435 {BRCMS_SROM_CONT, 0, 0, SROM_BFL2, 0xffff},
436 {BRCMS_SROM_BOARDFLAGS, 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
437 0xffff},
438 {BRCMS_SROM_CONT, 0, 0, SROM3_BFL2, 0xffff},
439 {BRCMS_SROM_BOARDFLAGS, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0,
440 0xffff},
441 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL1, 0xffff},
442 {BRCMS_SROM_BOARDFLAGS, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0,
443 0xffff},
444 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL1, 0xffff},
445 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 342 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
446 0xffff}, 343 0xffff},
447 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff}, 344 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
448 {BRCMS_SROM_BOARDFLAGS2, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2,
449 0xffff},
450 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL3, 0xffff},
451 {BRCMS_SROM_BOARDFLAGS2, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2,
452 0xffff},
453 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL3, 0xffff},
454 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 345 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
455 0xffff}, 346 0xffff},
456 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff}, 347 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
457 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, 348 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
458 {BRCMS_SROM_BOARDNUM, 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
459 {BRCMS_SROM_BOARDNUM, 0x00000008, 0, SROM3_MACLO, 0xffff},
460 {BRCMS_SROM_BOARDNUM, 0x00000010, 0, SROM4_MACLO, 0xffff},
461 {BRCMS_SROM_BOARDNUM, 0x000000e0, 0, SROM5_MACLO, 0xffff},
462 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff}, 349 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
463 {BRCMS_SROM_CC, 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
464 {BRCMS_SROM_REGREV, 0x00000008, 0, SROM_OPO, 0xff00},
465 {BRCMS_SROM_REGREV, 0x00000010, 0, SROM4_REGREV, 0x00ff},
466 {BRCMS_SROM_REGREV, 0x000000e0, 0, SROM5_REGREV, 0x00ff},
467 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff}, 350 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
468 {BRCMS_SROM_LEDBH0, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
469 {BRCMS_SROM_LEDBH1, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
470 {BRCMS_SROM_LEDBH2, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
471 {BRCMS_SROM_LEDBH3, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
472 {BRCMS_SROM_LEDBH0, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
473 {BRCMS_SROM_LEDBH1, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
474 {BRCMS_SROM_LEDBH2, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
475 {BRCMS_SROM_LEDBH3, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
476 {BRCMS_SROM_LEDBH0, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
477 {BRCMS_SROM_LEDBH1, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
478 {BRCMS_SROM_LEDBH2, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
479 {BRCMS_SROM_LEDBH3, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
480 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, 351 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
481 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, 352 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
482 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, 353 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
483 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, 354 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
484 {BRCMS_SROM_PA0B0, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
485 {BRCMS_SROM_PA0B1, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
486 {BRCMS_SROM_PA0B2, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
487 {BRCMS_SROM_PA0ITSSIT, 0x0000000e, 0, SROM_ITT, 0x00ff},
488 {BRCMS_SROM_PA0MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
489 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, 355 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
490 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, 356 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
491 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, 357 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
492 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00}, 358 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
493 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff}, 359 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
494 {BRCMS_SROM_OPO, 0x0000000c, 0, SROM_OPO, 0x00ff},
495 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff}, 360 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
496 {BRCMS_SROM_AA2G, 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
497 {BRCMS_SROM_AA2G, 0x000000f0, 0, SROM4_AA, 0x00ff},
498 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff}, 361 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
499 {BRCMS_SROM_AA5G, 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
500 {BRCMS_SROM_AA5G, 0x000000f0, 0, SROM4_AA, 0xff00},
501 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00}, 362 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
502 {BRCMS_SROM_AG0, 0x0000000e, 0, SROM_AG10, 0x00ff},
503 {BRCMS_SROM_AG1, 0x0000000e, 0, SROM_AG10, 0xff00},
504 {BRCMS_SROM_AG0, 0x000000f0, 0, SROM4_AG10, 0x00ff},
505 {BRCMS_SROM_AG1, 0x000000f0, 0, SROM4_AG10, 0xff00},
506 {BRCMS_SROM_AG2, 0x000000f0, 0, SROM4_AG32, 0x00ff},
507 {BRCMS_SROM_AG3, 0x000000f0, 0, SROM4_AG32, 0xff00},
508 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff}, 363 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
509 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00}, 364 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
510 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff}, 365 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
511 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00}, 366 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
512 {BRCMS_SROM_PA1B0, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
513 {BRCMS_SROM_PA1B1, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
514 {BRCMS_SROM_PA1B2, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
515 {BRCMS_SROM_PA1LOB0, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
516 {BRCMS_SROM_PA1LOB1, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
517 {BRCMS_SROM_PA1LOB2, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
518 {BRCMS_SROM_PA1HIB0, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
519 {BRCMS_SROM_PA1HIB1, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
520 {BRCMS_SROM_PA1HIB2, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
521 {BRCMS_SROM_PA1ITSSIT, 0x0000000e, 0, SROM_ITT, 0xff00},
522 {BRCMS_SROM_PA1MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
523 {BRCMS_SROM_PA1LOMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
524 {BRCMS_SROM_PA1HIMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
525 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, 367 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
526 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, 368 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
527 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, 369 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
@@ -535,40 +377,20 @@ static const struct brcms_sromvar pci_sromvars[] = {
535 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff}, 377 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
536 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00}, 378 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
537 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, 379 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
538 {BRCMS_SROM_BXA2G, 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
539 {BRCMS_SROM_RSSISAV2G, 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
540 {BRCMS_SROM_RSSISMC2G, 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
541 {BRCMS_SROM_RSSISMF2G, 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
542 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800}, 380 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
543 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700}, 381 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
544 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0}, 382 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
545 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f}, 383 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
546 {BRCMS_SROM_BXA5G, 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
547 {BRCMS_SROM_RSSISAV5G, 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
548 {BRCMS_SROM_RSSISMC5G, 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
549 {BRCMS_SROM_RSSISMF5G, 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
550 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800}, 384 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
551 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700}, 385 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
552 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0}, 386 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
553 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f}, 387 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
554 {BRCMS_SROM_TRI2G, 0x00000008, 0, SROM_TRI52G, 0x00ff},
555 {BRCMS_SROM_TRI5G, 0x00000008, 0, SROM_TRI52G, 0xff00},
556 {BRCMS_SROM_TRI5GL, 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
557 {BRCMS_SROM_TRI5GH, 0x00000008, 0, SROM_TRI5GHL, 0xff00},
558 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff}, 388 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
559 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00}, 389 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
560 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff}, 390 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
561 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00}, 391 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
562 {BRCMS_SROM_RXPO2G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
563 {BRCMS_SROM_RXPO5G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
564 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, 392 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
565 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, 393 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
566 {BRCMS_SROM_TXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
567 SROM4_TXCHAIN_MASK},
568 {BRCMS_SROM_RXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
569 SROM4_RXCHAIN_MASK},
570 {BRCMS_SROM_ANTSWITCH, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
571 SROM4_SWITCH_MASK},
572 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, 394 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
573 SROM4_TXCHAIN_MASK}, 395 SROM4_TXCHAIN_MASK},
574 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, 396 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
@@ -595,43 +417,11 @@ static const struct brcms_sromvar pci_sromvars[] = {
595 SROM8_FEM_ANTSWLUT_MASK}, 417 SROM8_FEM_ANTSWLUT_MASK},
596 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00}, 418 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
597 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff}, 419 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
598 {BRCMS_SROM_TXPID2GA0, 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, 420
599 {BRCMS_SROM_TXPID2GA1, 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
600 {BRCMS_SROM_TXPID2GA2, 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
601 {BRCMS_SROM_TXPID2GA3, 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
602 {BRCMS_SROM_TXPID5GA0, 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
603 {BRCMS_SROM_TXPID5GA1, 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
604 {BRCMS_SROM_TXPID5GA2, 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
605 {BRCMS_SROM_TXPID5GA3, 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
606 {BRCMS_SROM_TXPID5GLA0, 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
607 {BRCMS_SROM_TXPID5GLA1, 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
608 {BRCMS_SROM_TXPID5GLA2, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
609 {BRCMS_SROM_TXPID5GLA3, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
610 {BRCMS_SROM_TXPID5GHA0, 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
611 {BRCMS_SROM_TXPID5GHA1, 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
612 {BRCMS_SROM_TXPID5GHA2, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
613 {BRCMS_SROM_TXPID5GHA3, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
614
615 {BRCMS_SROM_CCODE, 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
616 {BRCMS_SROM_CCODE, 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
617 {BRCMS_SROM_CCODE, 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
618 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff}, 421 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
619 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, 422 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
620 {BRCMS_SROM_MACADDR, 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
621 {BRCMS_SROM_MACADDR, 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
622 {BRCMS_SROM_MACADDR, 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
623 {BRCMS_SROM_IL0MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0,
624 0xffff},
625 {BRCMS_SROM_ET1MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1,
626 0xffff},
627 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 423 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
628 0xffff}, 424 0xffff},
629 {BRCMS_SROM_LEDDC, 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC,
630 0xffff},
631 {BRCMS_SROM_LEDDC, 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC,
632 0xffff},
633 {BRCMS_SROM_LEDDC, 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC,
634 0xffff},
635 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 425 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
636 0x01ff}, 426 0x01ff},
637 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 427 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
@@ -651,16 +441,7 @@ static const struct brcms_sromvar pci_sromvars[] = {
651 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 441 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
652 0x00ff}, 442 0x00ff},
653 443
654 {BRCMS_SROM_CCK2GPO, 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
655 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, 444 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
656 {BRCMS_SROM_OFDM2GPO, 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
657 {BRCMS_SROM_CONT, 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
658 {BRCMS_SROM_OFDM5GPO, 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
659 {BRCMS_SROM_CONT, 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
660 {BRCMS_SROM_OFDM5GLPO, 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
661 {BRCMS_SROM_CONT, 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
662 {BRCMS_SROM_OFDM5GHPO, 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
663 {BRCMS_SROM_CONT, 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
664 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, 445 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
665 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, 446 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
666 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, 447 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
@@ -669,38 +450,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
669 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, 450 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
670 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, 451 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
671 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, 452 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
672 {BRCMS_SROM_MCS2GPO0, 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
673 {BRCMS_SROM_MCS2GPO1, 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
674 {BRCMS_SROM_MCS2GPO2, 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
675 {BRCMS_SROM_MCS2GPO3, 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
676 {BRCMS_SROM_MCS2GPO4, 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
677 {BRCMS_SROM_MCS2GPO5, 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
678 {BRCMS_SROM_MCS2GPO6, 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
679 {BRCMS_SROM_MCS2GPO7, 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
680 {BRCMS_SROM_MCS5GPO0, 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
681 {BRCMS_SROM_MCS5GPO1, 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
682 {BRCMS_SROM_MCS5GPO2, 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
683 {BRCMS_SROM_MCS5GPO3, 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
684 {BRCMS_SROM_MCS5GPO4, 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
685 {BRCMS_SROM_MCS5GPO5, 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
686 {BRCMS_SROM_MCS5GPO6, 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
687 {BRCMS_SROM_MCS5GPO7, 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
688 {BRCMS_SROM_MCS5GLPO0, 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
689 {BRCMS_SROM_MCS5GLPO1, 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
690 {BRCMS_SROM_MCS5GLPO2, 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
691 {BRCMS_SROM_MCS5GLPO3, 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
692 {BRCMS_SROM_MCS5GLPO4, 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
693 {BRCMS_SROM_MCS5GLPO5, 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
694 {BRCMS_SROM_MCS5GLPO6, 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
695 {BRCMS_SROM_MCS5GLPO7, 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
696 {BRCMS_SROM_MCS5GHPO0, 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
697 {BRCMS_SROM_MCS5GHPO1, 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
698 {BRCMS_SROM_MCS5GHPO2, 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
699 {BRCMS_SROM_MCS5GHPO3, 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
700 {BRCMS_SROM_MCS5GHPO4, 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
701 {BRCMS_SROM_MCS5GHPO5, 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
702 {BRCMS_SROM_MCS5GHPO6, 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
703 {BRCMS_SROM_MCS5GHPO7, 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
704 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, 453 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
705 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, 454 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
706 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, 455 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
@@ -733,10 +482,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
733 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, 482 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
734 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, 483 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
735 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, 484 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
736 {BRCMS_SROM_CDDPO, 0x000000f0, 0, SROM4_CDDPO, 0xffff},
737 {BRCMS_SROM_STBCPO, 0x000000f0, 0, SROM4_STBCPO, 0xffff},
738 {BRCMS_SROM_BW40PO, 0x000000f0, 0, SROM4_BW40PO, 0xffff},
739 {BRCMS_SROM_BWDUPPO, 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
740 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff}, 485 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
741 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff}, 486 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
742 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff}, 487 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
@@ -812,34 +557,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
812}; 557};
813 558
814static const struct brcms_sromvar perpath_pci_sromvars[] = { 559static const struct brcms_sromvar perpath_pci_sromvars[] = {
815 {BRCMS_SROM_MAXP2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
816 {BRCMS_SROM_ITT2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
817 {BRCMS_SROM_ITT5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
818 {BRCMS_SROM_PA2GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
819 {BRCMS_SROM_PA2GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
820 {BRCMS_SROM_PA2GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
821 {BRCMS_SROM_PA2GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
822 {BRCMS_SROM_MAXP5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
823 {BRCMS_SROM_MAXP5GHA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
824 {BRCMS_SROM_MAXP5GLA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
825 {BRCMS_SROM_PA5GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
826 {BRCMS_SROM_PA5GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
827 {BRCMS_SROM_PA5GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
828 {BRCMS_SROM_PA5GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
829 {BRCMS_SROM_PA5GLW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
830 {BRCMS_SROM_PA5GLW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1,
831 0xffff},
832 {BRCMS_SROM_PA5GLW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2,
833 0xffff},
834 {BRCMS_SROM_PA5GLW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3,
835 0xffff},
836 {BRCMS_SROM_PA5GHW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
837 {BRCMS_SROM_PA5GHW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1,
838 0xffff},
839 {BRCMS_SROM_PA5GHW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2,
840 0xffff},
841 {BRCMS_SROM_PA5GHW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3,
842 0xffff},
843 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff}, 560 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
844 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00}, 561 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
845 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00}, 562 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
@@ -881,12 +598,6 @@ srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
881 return NULL; 598 return NULL;
882} 599}
883 600
884/* Parse SROM and create name=value pairs. 'srom' points to
885 * the SROM word array. 'off' specifies the offset of the
886 * first word 'srom' points to, which should be either 0 or
887 * SROM3_SWRG_OFF (full SROM or software region).
888 */
889
890static uint mask_shift(u16 mask) 601static uint mask_shift(u16 mask)
891{ 602{
892 uint i; 603 uint i;
@@ -935,6 +646,9 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
935 uint width; 646 uint width;
936 uint flags; 647 uint flags;
937 u32 sr = (1 << sromrev); 648 u32 sr = (1 << sromrev);
649 uint p;
650 uint pb = SROM8_PATH0;
651 const uint psz = SROM8_PATH1 - SROM8_PATH0;
938 652
939 /* first store the srom revision */ 653 /* first store the srom revision */
940 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL); 654 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
@@ -1032,47 +746,34 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
1032 list_add(&entry->var_list, var_list); 746 list_add(&entry->var_list, var_list);
1033 } 747 }
1034 748
1035 if (sromrev >= 4) { 749 for (p = 0; p < MAX_PATH_SROM; p++) {
1036 /* Do per-path variables */ 750 for (srv = perpath_pci_sromvars;
1037 uint p, pb, psz; 751 srv->varid != BRCMS_SROM_NULL; srv++) {
1038 752 if ((srv->revmask & sr) == 0)
1039 if (sromrev >= 8) { 753 continue;
1040 pb = SROM8_PATH0;
1041 psz = SROM8_PATH1 - SROM8_PATH0;
1042 } else {
1043 pb = SROM4_PATH0;
1044 psz = SROM4_PATH1 - SROM4_PATH0;
1045 }
1046
1047 for (p = 0; p < MAX_PATH_SROM; p++) {
1048 for (srv = perpath_pci_sromvars;
1049 srv->varid != BRCMS_SROM_NULL; srv++) {
1050 if ((srv->revmask & sr) == 0)
1051 continue;
1052 754
1053 if (srv->flags & SRFL_NOVAR) 755 if (srv->flags & SRFL_NOVAR)
1054 continue; 756 continue;
1055 757
1056 w = srom[pb + srv->off]; 758 w = srom[pb + srv->off];
1057 val = (w & srv->mask) >> mask_shift(srv->mask); 759 val = (w & srv->mask) >> mask_shift(srv->mask);
1058 width = mask_width(srv->mask); 760 width = mask_width(srv->mask);
1059 761
1060 /* Cheating: no per-path var is more than 762 /* Cheating: no per-path var is more than
1061 * 1 word */ 763 * 1 word */
1062 if ((srv->flags & SRFL_NOFFS) 764 if ((srv->flags & SRFL_NOFFS)
1063 && ((int)val == (1 << width) - 1)) 765 && ((int)val == (1 << width) - 1))
1064 continue; 766 continue;
1065 767
1066 entry = 768 entry =
1067 kzalloc(sizeof(struct brcms_srom_list_head), 769 kzalloc(sizeof(struct brcms_srom_list_head),
1068 GFP_KERNEL); 770 GFP_KERNEL);
1069 entry->varid = srv->varid+p; 771 entry->varid = srv->varid+p;
1070 entry->var_type = BRCMS_SROM_UNUMBER; 772 entry->var_type = BRCMS_SROM_UNUMBER;
1071 entry->uval = val; 773 entry->uval = val;
1072 list_add(&entry->var_list, var_list); 774 list_add(&entry->var_list, var_list);
1073 }
1074 pb += psz;
1075 } 775 }
776 pb += psz;
1076 } 777 }
1077} 778}
1078 779
@@ -1177,22 +878,14 @@ static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1177 err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS, 878 err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
1178 true); 879 true);
1179 880
1180 if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) || 881 if ((sih->buscoretype == PCIE_CORE_ID && sih->buscorerev >= 6)
1181 (((sih->buscoretype == PCIE_CORE_ID) 882 || (sih->buscoretype == PCI_CORE_ID &&
1182 && (sih->buscorerev >= 6)) 883 sih->buscorerev >= 0xe)) {
1183 || ((sih->buscoretype == PCI_CORE_ID)
1184 && (sih->buscorerev >= 0xe)))) {
1185 /* sromrev >= 4, read more */
1186 err = sprom_read_pci(sih, sromwindow, 0, srom, 884 err = sprom_read_pci(sih, sromwindow, 0, srom,
1187 SROM4_WORDS, true); 885 SROM4_WORDS, true);
1188 sromrev = srom[SROM4_CRCREV] & 0xff; 886 sromrev = srom[SROM4_CRCREV] & 0xff;
1189 } else if (err == 0) { 887 } else {
1190 /* srom is good and is rev < 4 */ 888 err = -EIO;
1191 /* top word of sprom contains version and crc8 */
1192 sromrev = srom[SROM_CRCREV] & 0xff;
1193 /* bcm4401 sroms misprogrammed */
1194 if (sromrev == 0x10)
1195 sromrev = 1;
1196 } 889 }
1197 } else { 890 } else {
1198 /* Use OTP if SPROM not available */ 891 /* Use OTP if SPROM not available */
@@ -1209,10 +902,9 @@ static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1209 sr = 1 << sromrev; 902 sr = 1 << sromrev;
1210 903
1211 /* 904 /*
1212 * srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 905 * srom version check: Current valid versions: 8, 9
1213 * 9
1214 */ 906 */
1215 if ((sr & 0x33e) == 0) { 907 if ((sr & 0x300) == 0) {
1216 err = -EINVAL; 908 err = -EINVAL;
1217 goto errout; 909 goto errout;
1218 } 910 }
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.h b/drivers/net/wireless/brcm80211/brcmsmac/srom.h
index 708c43ff51cc..c81df9798e50 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/srom.h
@@ -26,9 +26,4 @@ extern void srom_free_vars(struct si_pub *sih);
26extern int srom_read(struct si_pub *sih, uint bus, void *curmap, 26extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
27 uint byteoff, uint nbytes, u16 *buf, bool check_crc); 27 uint byteoff, uint nbytes, u16 *buf, bool check_crc);
28 28
29/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
30 * and extract from it into name=value pairs
31 */
32extern int srom_parsecis(u8 **pcis, uint ciscnt,
33 char **vars, uint *count);
34#endif /* _BRCM_SROM_H_ */ 29#endif /* _BRCM_SROM_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 20:38:54 -0500