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authorBen Skeggs <bskeggs@redhat.com>2012-05-07 20:24:27 -0400
committerBen Skeggs <bskeggs@redhat.com>2012-07-25 20:28:15 -0400
commit2a259a3d84c4409918c5d094f0969da58283a947 (patch)
treee261df7f7f038bbb9761c91ee5784a4fdfb0bfb5 /drivers
parentce22af03da2cd700332a384e240378cae1355773 (diff)
drm/nouveau: mark most of our ioctls as deprecated, move to compat layer
These will be replaced in the near future, the code isn't yet stable enough for this merge window however. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/nouveau/Makefile1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_abi16.c245
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_abi16.h83
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c95
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c18
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h14
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gpuobj.c60
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_notifier.c23
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c74
9 files changed, 346 insertions, 267 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index efa1aef35f3a..1cece6a78f39 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -12,6 +12,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
12 nouveau_hdmi.o nouveau_dp.o nouveau_ramht.o \ 12 nouveau_hdmi.o nouveau_dp.o nouveau_ramht.o \
13 nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \ 13 nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \
14 nouveau_mm.o nouveau_vm.o nouveau_mxm.o nouveau_gpio.o \ 14 nouveau_mm.o nouveau_vm.o nouveau_mxm.o nouveau_gpio.o \
15 nouveau_abi16.o \
15 nv04_timer.o \ 16 nv04_timer.o \
16 nv04_mc.o nv40_mc.o nv50_mc.o \ 17 nv04_mc.o nv40_mc.o nv50_mc.o \
17 nv04_fb.o nv10_fb.o nv20_fb.o nv30_fb.o nv40_fb.o \ 18 nv04_fb.o nv10_fb.o nv20_fb.o nv30_fb.o nv40_fb.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
new file mode 100644
index 000000000000..ff23d88880e5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -0,0 +1,245 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25
26#include "nouveau_drv.h"
27#include "nouveau_dma.h"
28#include "nouveau_abi16.h"
29#include "nouveau_ramht.h"
30#include "nouveau_software.h"
31
32int
33nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
34{
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct drm_nouveau_getparam *getparam = data;
37
38 switch (getparam->param) {
39 case NOUVEAU_GETPARAM_CHIPSET_ID:
40 getparam->value = dev_priv->chipset;
41 break;
42 case NOUVEAU_GETPARAM_PCI_VENDOR:
43 getparam->value = dev->pci_vendor;
44 break;
45 case NOUVEAU_GETPARAM_PCI_DEVICE:
46 getparam->value = dev->pci_device;
47 break;
48 case NOUVEAU_GETPARAM_BUS_TYPE:
49 if (drm_pci_device_is_agp(dev))
50 getparam->value = 0;
51 else
52 if (!pci_is_pcie(dev->pdev))
53 getparam->value = 1;
54 else
55 getparam->value = 2;
56 break;
57 case NOUVEAU_GETPARAM_FB_SIZE:
58 getparam->value = dev_priv->fb_available_size;
59 break;
60 case NOUVEAU_GETPARAM_AGP_SIZE:
61 getparam->value = dev_priv->gart_info.aper_size;
62 break;
63 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
64 getparam->value = 0; /* deprecated */
65 break;
66 case NOUVEAU_GETPARAM_PTIMER_TIME:
67 getparam->value = dev_priv->engine.timer.read(dev);
68 break;
69 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
70 getparam->value = 1;
71 break;
72 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
73 getparam->value = 1;
74 break;
75 case NOUVEAU_GETPARAM_GRAPH_UNITS:
76 /* NV40 and NV50 versions are quite different, but register
77 * address is the same. User is supposed to know the card
78 * family anyway... */
79 if (dev_priv->chipset >= 0x40) {
80 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
81 break;
82 }
83 /* FALLTHRU */
84 default:
85 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
86 return -EINVAL;
87 }
88
89 return 0;
90}
91
92int
93nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS)
94{
95 return -EINVAL;
96}
97
98int
99nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
100{
101 struct drm_nouveau_private *dev_priv = dev->dev_private;
102 struct drm_nouveau_channel_alloc *init = data;
103 struct nouveau_channel *chan;
104 int ret;
105
106 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
107 return -ENODEV;
108
109 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
110 return -EINVAL;
111
112 ret = nouveau_channel_alloc(dev, &chan, file_priv,
113 init->fb_ctxdma_handle,
114 init->tt_ctxdma_handle);
115 if (ret)
116 return ret;
117 init->channel = chan->id;
118
119 if (nouveau_vram_pushbuf == 0) {
120 if (chan->dma.ib_max)
121 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
122 NOUVEAU_GEM_DOMAIN_GART;
123 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
124 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
125 else
126 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
127 } else {
128 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
129 }
130
131 if (dev_priv->card_type < NV_C0) {
132 init->subchan[0].handle = 0x00000000;
133 init->subchan[0].grclass = 0x0000;
134 init->subchan[1].handle = NvSw;
135 init->subchan[1].grclass = NV_SW;
136 init->nr_subchan = 2;
137 }
138
139 /* Named memory object area */
140 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
141 &init->notifier_handle);
142
143 if (ret == 0)
144 atomic_inc(&chan->users); /* userspace reference */
145 nouveau_channel_put(&chan);
146 return ret;
147}
148
149int
150nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS)
151{
152 struct drm_nouveau_channel_free *req = data;
153 struct nouveau_channel *chan;
154
155 chan = nouveau_channel_get(file_priv, req->channel);
156 if (IS_ERR(chan))
157 return PTR_ERR(chan);
158
159 list_del(&chan->list);
160 atomic_dec(&chan->users);
161 nouveau_channel_put(&chan);
162 return 0;
163}
164
165int
166nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS)
167{
168 struct drm_nouveau_grobj_alloc *init = data;
169 struct nouveau_channel *chan;
170 int ret;
171
172 if (init->handle == ~0)
173 return -EINVAL;
174
175 /* compatibility with userspace that assumes 506e for all chipsets */
176 if (init->class == 0x506e) {
177 init->class = nouveau_software_class(dev);
178 if (init->class == 0x906e)
179 return 0;
180 } else
181 if (init->class == 0x906e) {
182 NV_ERROR(dev, "906e not supported yet\n");
183 return -EINVAL;
184 }
185
186 chan = nouveau_channel_get(file_priv, init->channel);
187 if (IS_ERR(chan))
188 return PTR_ERR(chan);
189
190 if (nouveau_ramht_find(chan, init->handle)) {
191 ret = -EEXIST;
192 goto out;
193 }
194
195 ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
196 if (ret) {
197 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
198 ret, init->channel, init->handle);
199 }
200
201out:
202 nouveau_channel_put(&chan);
203 return ret;
204}
205
206int
207nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
208{
209 struct drm_nouveau_private *dev_priv = dev->dev_private;
210 struct drm_nouveau_notifierobj_alloc *na = data;
211 struct nouveau_channel *chan;
212 int ret;
213
214 /* completely unnecessary for these chipsets... */
215 if (unlikely(dev_priv->card_type >= NV_C0))
216 return -EINVAL;
217
218 chan = nouveau_channel_get(file_priv, na->channel);
219 if (IS_ERR(chan))
220 return PTR_ERR(chan);
221
222 ret = nouveau_notifier_alloc(chan, na->handle, na->size, 0, 0x1000,
223 &na->offset);
224 nouveau_channel_put(&chan);
225 return ret;
226}
227
228int
229nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS)
230{
231 struct drm_nouveau_gpuobj_free *objfree = data;
232 struct nouveau_channel *chan;
233 int ret;
234
235 chan = nouveau_channel_get(file_priv, objfree->channel);
236 if (IS_ERR(chan))
237 return PTR_ERR(chan);
238
239 /* Synchronize with the user channel */
240 nouveau_channel_idle(chan);
241
242 ret = nouveau_ramht_remove(chan, objfree->handle);
243 nouveau_channel_put(&chan);
244 return ret;
245}
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h
new file mode 100644
index 000000000000..e6328b008a8c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h
@@ -0,0 +1,83 @@
1#ifndef __NOUVEAU_ABI16_H__
2#define __NOUVEAU_ABI16_H__
3
4#define ABI16_IOCTL_ARGS \
5 struct drm_device *dev, void *data, struct drm_file *file_priv
6int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
7int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
8int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
9int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
10int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
11int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
12int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
13
14struct drm_nouveau_channel_alloc {
15 uint32_t fb_ctxdma_handle;
16 uint32_t tt_ctxdma_handle;
17
18 int channel;
19 uint32_t pushbuf_domains;
20
21 /* Notifier memory */
22 uint32_t notifier_handle;
23
24 /* DRM-enforced subchannel assignments */
25 struct {
26 uint32_t handle;
27 uint32_t grclass;
28 } subchan[8];
29 uint32_t nr_subchan;
30};
31
32struct drm_nouveau_channel_free {
33 int channel;
34};
35
36struct drm_nouveau_grobj_alloc {
37 int channel;
38 uint32_t handle;
39 int class;
40};
41
42struct drm_nouveau_notifierobj_alloc {
43 uint32_t channel;
44 uint32_t handle;
45 uint32_t size;
46 uint32_t offset;
47};
48
49struct drm_nouveau_gpuobj_free {
50 int channel;
51 uint32_t handle;
52};
53
54#define NOUVEAU_GETPARAM_PCI_VENDOR 3
55#define NOUVEAU_GETPARAM_PCI_DEVICE 4
56#define NOUVEAU_GETPARAM_BUS_TYPE 5
57#define NOUVEAU_GETPARAM_FB_SIZE 8
58#define NOUVEAU_GETPARAM_AGP_SIZE 9
59#define NOUVEAU_GETPARAM_CHIPSET_ID 11
60#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
61#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
62#define NOUVEAU_GETPARAM_PTIMER_TIME 14
63#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
64#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
65struct drm_nouveau_getparam {
66 uint64_t param;
67 uint64_t value;
68};
69
70struct drm_nouveau_setparam {
71 uint64_t param;
72 uint64_t value;
73};
74
75#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
76#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
77#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
78#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
79#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
80#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
81#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
82
83#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 629d8a2df5bd..debd90225a88 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -395,98 +395,3 @@ nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
395 nouveau_channel_put(&chan); 395 nouveau_channel_put(&chan);
396 } 396 }
397} 397}
398
399
400/***********************************
401 * ioctls wrapping the functions
402 ***********************************/
403
404static int
405nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
406 struct drm_file *file_priv)
407{
408 struct drm_nouveau_private *dev_priv = dev->dev_private;
409 struct drm_nouveau_channel_alloc *init = data;
410 struct nouveau_channel *chan;
411 int ret;
412
413 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
414 return -ENODEV;
415
416 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
417 return -EINVAL;
418
419 ret = nouveau_channel_alloc(dev, &chan, file_priv,
420 init->fb_ctxdma_handle,
421 init->tt_ctxdma_handle);
422 if (ret)
423 return ret;
424 init->channel = chan->id;
425
426 if (nouveau_vram_pushbuf == 0) {
427 if (chan->dma.ib_max)
428 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
429 NOUVEAU_GEM_DOMAIN_GART;
430 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
431 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
432 else
433 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
434 } else {
435 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
436 }
437
438 if (dev_priv->card_type < NV_C0) {
439 init->subchan[0].handle = 0x00000000;
440 init->subchan[0].grclass = 0x0000;
441 init->subchan[1].handle = NvSw;
442 init->subchan[1].grclass = NV_SW;
443 init->nr_subchan = 2;
444 }
445
446 /* Named memory object area */
447 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
448 &init->notifier_handle);
449
450 if (ret == 0)
451 atomic_inc(&chan->users); /* userspace reference */
452 nouveau_channel_put(&chan);
453 return ret;
454}
455
456static int
457nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
458 struct drm_file *file_priv)
459{
460 struct drm_nouveau_channel_free *req = data;
461 struct nouveau_channel *chan;
462
463 chan = nouveau_channel_get(file_priv, req->channel);
464 if (IS_ERR(chan))
465 return PTR_ERR(chan);
466
467 list_del(&chan->list);
468 atomic_dec(&chan->users);
469 nouveau_channel_put(&chan);
470 return 0;
471}
472
473/***********************************
474 * finally, the ioctl table
475 ***********************************/
476
477struct drm_ioctl_desc nouveau_ioctls[] = {
478 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
479 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
480 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
481 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
482 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
483 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
484 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
485 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
486 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
487 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
488 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
489 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
490};
491
492int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index cad254c8e387..727447d296f1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -29,6 +29,7 @@
29#include "drm.h" 29#include "drm.h"
30#include "drm_crtc_helper.h" 30#include "drm_crtc_helper.h"
31#include "nouveau_drv.h" 31#include "nouveau_drv.h"
32#include "nouveau_abi16.h"
32#include "nouveau_hw.h" 33#include "nouveau_hw.h"
33#include "nouveau_fb.h" 34#include "nouveau_fb.h"
34#include "nouveau_fbcon.h" 35#include "nouveau_fbcon.h"
@@ -384,6 +385,21 @@ nouveau_pci_resume(struct pci_dev *pdev)
384 return 0; 385 return 0;
385} 386}
386 387
388static struct drm_ioctl_desc nouveau_ioctls[] = {
389 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
390 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
391 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
392 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
393 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
394 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
395 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
396 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
397 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
398 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
399 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
400 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
401};
402
387static const struct file_operations nouveau_driver_fops = { 403static const struct file_operations nouveau_driver_fops = {
388 .owner = THIS_MODULE, 404 .owner = THIS_MODULE,
389 .open = drm_open, 405 .open = drm_open,
@@ -463,7 +479,7 @@ static struct pci_driver nouveau_pci_driver = {
463 479
464static int __init nouveau_init(void) 480static int __init nouveau_init(void)
465{ 481{
466 driver.num_ioctls = nouveau_max_ioctl; 482 driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
467 483
468 if (nouveau_modeset == -1) { 484 if (nouveau_modeset == -1) {
469#ifdef CONFIG_VGA_CONSOLE 485#ifdef CONFIG_VGA_CONSOLE
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index b0f8dd0373cd..a5dc98495125 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -872,10 +872,6 @@ extern int nouveau_load(struct drm_device *, unsigned long flags);
872extern int nouveau_firstopen(struct drm_device *); 872extern int nouveau_firstopen(struct drm_device *);
873extern void nouveau_lastclose(struct drm_device *); 873extern void nouveau_lastclose(struct drm_device *);
874extern int nouveau_unload(struct drm_device *); 874extern int nouveau_unload(struct drm_device *);
875extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
876 struct drm_file *);
877extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
878 struct drm_file *);
879extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 875extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
880 uint32_t reg, uint32_t mask, uint32_t val); 876 uint32_t reg, uint32_t mask, uint32_t val);
881extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 877extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
@@ -915,14 +911,8 @@ extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
915 int cout, uint32_t start, uint32_t end, 911 int cout, uint32_t start, uint32_t end,
916 uint32_t *offset); 912 uint32_t *offset);
917extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 913extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
918extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
919 struct drm_file *);
920extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
921 struct drm_file *);
922 914
923/* nouveau_channel.c */ 915/* nouveau_channel.c */
924extern struct drm_ioctl_desc nouveau_ioctls[];
925extern int nouveau_max_ioctl;
926extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 916extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
927extern int nouveau_channel_alloc(struct drm_device *dev, 917extern int nouveau_channel_alloc(struct drm_device *dev,
928 struct nouveau_channel **chan, 918 struct nouveau_channel **chan,
@@ -993,10 +983,6 @@ extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
993extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 983extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
994 int class, u64 base, u64 size, int target, 984 int class, u64 base, u64 size, int target,
995 int access, u32 type, u32 comp); 985 int access, u32 type, u32 comp);
996extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
997 struct drm_file *);
998extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
999 struct drm_file *);
1000 986
1001/* nouveau_irq.c */ 987/* nouveau_irq.c */
1002extern int nouveau_irq_init(struct drm_device *); 988extern int nouveau_irq_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_gpuobj.c b/drivers/gpu/drm/nouveau/nouveau_gpuobj.c
index b190cc01c820..bd79fedb7054 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gpuobj.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gpuobj.c
@@ -758,66 +758,6 @@ nouveau_gpuobj_resume(struct drm_device *dev)
758 dev_priv->engine.instmem.flush(dev); 758 dev_priv->engine.instmem.flush(dev);
759} 759}
760 760
761int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
762 struct drm_file *file_priv)
763{
764 struct drm_nouveau_grobj_alloc *init = data;
765 struct nouveau_channel *chan;
766 int ret;
767
768 if (init->handle == ~0)
769 return -EINVAL;
770
771 /* compatibility with userspace that assumes 506e for all chipsets */
772 if (init->class == 0x506e) {
773 init->class = nouveau_software_class(dev);
774 if (init->class == 0x906e)
775 return 0;
776 } else
777 if (init->class == 0x906e) {
778 NV_ERROR(dev, "906e not supported yet\n");
779 return -EINVAL;
780 }
781
782 chan = nouveau_channel_get(file_priv, init->channel);
783 if (IS_ERR(chan))
784 return PTR_ERR(chan);
785
786 if (nouveau_ramht_find(chan, init->handle)) {
787 ret = -EEXIST;
788 goto out;
789 }
790
791 ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
792 if (ret) {
793 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
794 ret, init->channel, init->handle);
795 }
796
797out:
798 nouveau_channel_put(&chan);
799 return ret;
800}
801
802int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
803 struct drm_file *file_priv)
804{
805 struct drm_nouveau_gpuobj_free *objfree = data;
806 struct nouveau_channel *chan;
807 int ret;
808
809 chan = nouveau_channel_get(file_priv, objfree->channel);
810 if (IS_ERR(chan))
811 return PTR_ERR(chan);
812
813 /* Synchronize with the user channel */
814 nouveau_channel_idle(chan);
815
816 ret = nouveau_ramht_remove(chan, objfree->handle);
817 nouveau_channel_put(&chan);
818 return ret;
819}
820
821u32 761u32
822nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset) 762nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
823{ 763{
diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c
index 2ef883c4bbc1..aa549155dcc1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_notifier.c
+++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c
@@ -179,26 +179,3 @@ nouveau_notifier_offset(struct nouveau_gpuobj *nobj, uint32_t *poffset)
179 179
180 return 0; 180 return 0;
181} 181}
182
183int
184nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
185 struct drm_file *file_priv)
186{
187 struct drm_nouveau_private *dev_priv = dev->dev_private;
188 struct drm_nouveau_notifierobj_alloc *na = data;
189 struct nouveau_channel *chan;
190 int ret;
191
192 /* completely unnecessary for these chipsets... */
193 if (unlikely(dev_priv->card_type >= NV_C0))
194 return -EINVAL;
195
196 chan = nouveau_channel_get(file_priv, na->channel);
197 if (IS_ERR(chan))
198 return PTR_ERR(chan);
199
200 ret = nouveau_notifier_alloc(chan, na->handle, na->size, 0, 0x1000,
201 &na->offset);
202 nouveau_channel_put(&chan);
203 return ret;
204}
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 19706f0532ea..1cdfd6e757ce 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -1234,80 +1234,6 @@ int nouveau_unload(struct drm_device *dev)
1234 return 0; 1234 return 0;
1235} 1235}
1236 1236
1237int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1238 struct drm_file *file_priv)
1239{
1240 struct drm_nouveau_private *dev_priv = dev->dev_private;
1241 struct drm_nouveau_getparam *getparam = data;
1242
1243 switch (getparam->param) {
1244 case NOUVEAU_GETPARAM_CHIPSET_ID:
1245 getparam->value = dev_priv->chipset;
1246 break;
1247 case NOUVEAU_GETPARAM_PCI_VENDOR:
1248 getparam->value = dev->pci_vendor;
1249 break;
1250 case NOUVEAU_GETPARAM_PCI_DEVICE:
1251 getparam->value = dev->pci_device;
1252 break;
1253 case NOUVEAU_GETPARAM_BUS_TYPE:
1254 if (drm_pci_device_is_agp(dev))
1255 getparam->value = NV_AGP;
1256 else if (pci_is_pcie(dev->pdev))
1257 getparam->value = NV_PCIE;
1258 else
1259 getparam->value = NV_PCI;
1260 break;
1261 case NOUVEAU_GETPARAM_FB_SIZE:
1262 getparam->value = dev_priv->fb_available_size;
1263 break;
1264 case NOUVEAU_GETPARAM_AGP_SIZE:
1265 getparam->value = dev_priv->gart_info.aper_size;
1266 break;
1267 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1268 getparam->value = 0; /* deprecated */
1269 break;
1270 case NOUVEAU_GETPARAM_PTIMER_TIME:
1271 getparam->value = dev_priv->engine.timer.read(dev);
1272 break;
1273 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1274 getparam->value = 1;
1275 break;
1276 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1277 getparam->value = 1;
1278 break;
1279 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1280 /* NV40 and NV50 versions are quite different, but register
1281 * address is the same. User is supposed to know the card
1282 * family anyway... */
1283 if (dev_priv->chipset >= 0x40) {
1284 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1285 break;
1286 }
1287 /* FALLTHRU */
1288 default:
1289 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1290 return -EINVAL;
1291 }
1292
1293 return 0;
1294}
1295
1296int
1297nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1298 struct drm_file *file_priv)
1299{
1300 struct drm_nouveau_setparam *setparam = data;
1301
1302 switch (setparam->param) {
1303 default:
1304 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1305 return -EINVAL;
1306 }
1307
1308 return 0;
1309}
1310
1311/* Wait until (value(reg) & mask) == val, up until timeout has hit */ 1237/* Wait until (value(reg) & mask) == val, up until timeout has hit */
1312bool 1238bool
1313nouveau_wait_eq(struct drm_device *dev, uint64_t timeout, 1239nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 14:39:09 -0500