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authorRoland Stigge <stigge@antcom.de>2012-06-07 06:22:15 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-07-06 13:17:07 -0400
commit2944a44da09e46b6db2fd2c3334f242b09e05c43 (patch)
tree3ad0ccc685a59a3307ac550024cc157d26ebfb00 /drivers
parentfdbad98dff8007f2b8bee6698b5d25ebba0471c9 (diff)
mtd: add LPC32xx SLC NAND driver
This patch adds support for the SLC NAND controller inside the LPC32xx SoC. [dwmw2: 21st century pedantry] Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mtd/nand/Kconfig11
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/lpc32xx_slc.c1065
3 files changed, 1077 insertions, 0 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 31bb7e5b504a..b28b57ed51bc 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -454,6 +454,17 @@ config MTD_NAND_PXA3xx
454 This enables the driver for the NAND flash device found on 454 This enables the driver for the NAND flash device found on
455 PXA3xx processors 455 PXA3xx processors
456 456
457config MTD_NAND_SLC_LPC32XX
458 tristate "NXP LPC32xx SLC Controller"
459 depends on ARCH_LPC32XX
460 help
461 Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell
462 chips) NAND controller. This is the default for the PHYTEC 3250
463 reference board which contains a NAND256R3A2CZA6 chip.
464
465 Please check the actual NAND chip connected and its support
466 by the SLC NAND controller.
467
457config MTD_NAND_CM_X270 468config MTD_NAND_CM_X270
458 tristate "Support for NAND Flash on CM-X270 modules" 469 tristate "Support for NAND Flash on CM-X270 modules"
459 depends on MACH_ARMCORE 470 depends on MACH_ARMCORE
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d8739bd8..d29a893608e7 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
40obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o 40obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
41obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o 41obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
42obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o 42obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
43obj-$(CONFIG_MTD_NAND_SLC_LPC32XX) += lpc32xx_slc.o
43obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o 44obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o
44obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o 45obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
45obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o 46obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c
new file mode 100644
index 000000000000..1d837b92ac79
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_slc.c
@@ -0,0 +1,1065 @@
1/*
2 * NXP LPC32XX NAND SLC driver
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright © 2011 NXP Semiconductors
9 * Copyright © 2012 Roland Stigge
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/delay.h>
31#include <linux/io.h>
32#include <linux/mm.h>
33#include <linux/dma-mapping.h>
34#include <linux/dmaengine.h>
35#include <linux/mtd/nand_ecc.h>
36#include <linux/gpio.h>
37#include <linux/of.h>
38#include <linux/of_mtd.h>
39#include <linux/of_gpio.h>
40#include <linux/amba/pl08x.h>
41
42#define LPC32XX_MODNAME "lpc32xx-nand"
43
44/**********************************************************************
45* SLC NAND controller register offsets
46**********************************************************************/
47
48#define SLC_DATA(x) (x + 0x000)
49#define SLC_ADDR(x) (x + 0x004)
50#define SLC_CMD(x) (x + 0x008)
51#define SLC_STOP(x) (x + 0x00C)
52#define SLC_CTRL(x) (x + 0x010)
53#define SLC_CFG(x) (x + 0x014)
54#define SLC_STAT(x) (x + 0x018)
55#define SLC_INT_STAT(x) (x + 0x01C)
56#define SLC_IEN(x) (x + 0x020)
57#define SLC_ISR(x) (x + 0x024)
58#define SLC_ICR(x) (x + 0x028)
59#define SLC_TAC(x) (x + 0x02C)
60#define SLC_TC(x) (x + 0x030)
61#define SLC_ECC(x) (x + 0x034)
62#define SLC_DMA_DATA(x) (x + 0x038)
63
64/**********************************************************************
65* slc_ctrl register definitions
66**********************************************************************/
67#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
68#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
69#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
70
71/**********************************************************************
72* slc_cfg register definitions
73**********************************************************************/
74#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */
75#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
76#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
77#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
78#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
79#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */
80
81/**********************************************************************
82* slc_stat register definitions
83**********************************************************************/
84#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
85#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
86#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
87
88/**********************************************************************
89* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
90**********************************************************************/
91#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */
92#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */
93
94/**********************************************************************
95* slc_tac register definitions
96**********************************************************************/
97/* Clock setting for RDY write sample wait time in 2*n clocks */
98#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
99/* Write pulse width in clock cycles, 1 to 16 clocks */
100#define SLCTAC_WWIDTH(n) (((n) & 0xF) << 24)
101/* Write hold time of control and data signals, 1 to 16 clocks */
102#define SLCTAC_WHOLD(n) (((n) & 0xF) << 20)
103/* Write setup time of control and data signals, 1 to 16 clocks */
104#define SLCTAC_WSETUP(n) (((n) & 0xF) << 16)
105/* Clock setting for RDY read sample wait time in 2*n clocks */
106#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
107/* Read pulse width in clock cycles, 1 to 16 clocks */
108#define SLCTAC_RWIDTH(n) (((n) & 0xF) << 8)
109/* Read hold time of control and data signals, 1 to 16 clocks */
110#define SLCTAC_RHOLD(n) (((n) & 0xF) << 4)
111/* Read setup time of control and data signals, 1 to 16 clocks */
112#define SLCTAC_RSETUP(n) (((n) & 0xF) << 0)
113
114/**********************************************************************
115* slc_ecc register definitions
116**********************************************************************/
117/* ECC line party fetch macro */
118#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)
119#define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
120
121/*
122 * DMA requires storage space for the DMA local buffer and the hardware ECC
123 * storage area. The DMA local buffer is only used if DMA mapping fails
124 * during runtime.
125 */
126#define LPC32XX_DMA_DATA_SIZE 4096
127#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)
128
129/* Number of bytes used for ECC stored in NAND per 256 bytes */
130#define LPC32XX_SLC_DEV_ECC_BYTES 3
131
132/*
133 * If the NAND base clock frequency can't be fetched, this frequency will be
134 * used instead as the base. This rate is used to setup the timing registers
135 * used for NAND accesses.
136 */
137#define LPC32XX_DEF_BUS_RATE 133250000
138
139/* Milliseconds for DMA FIFO timeout (unlikely anyway) */
140#define LPC32XX_DMA_TIMEOUT 100
141
142/*
143 * NAND ECC Layout for small page NAND devices
144 * Note: For large and huge page devices, the default layouts are used
145 */
146static struct nand_ecclayout lpc32xx_nand_oob_16 = {
147 .eccbytes = 6,
148 .eccpos = {10, 11, 12, 13, 14, 15},
149 .oobfree = {
150 { .offset = 0, .length = 4 },
151 { .offset = 6, .length = 4 },
152 },
153};
154
155static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
156static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
157
158/*
159 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
160 * Note: Large page devices used the default layout
161 */
162static struct nand_bbt_descr bbt_smallpage_main_descr = {
163 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
164 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
165 .offs = 0,
166 .len = 4,
167 .veroffs = 6,
168 .maxblocks = 4,
169 .pattern = bbt_pattern
170};
171
172static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
173 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
174 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
175 .offs = 0,
176 .len = 4,
177 .veroffs = 6,
178 .maxblocks = 4,
179 .pattern = mirror_pattern
180};
181
182/*
183 * NAND platform configuration structure
184 */
185struct lpc32xx_nand_cfg_slc {
186 uint32_t wdr_clks;
187 uint32_t wwidth;
188 uint32_t whold;
189 uint32_t wsetup;
190 uint32_t rdr_clks;
191 uint32_t rwidth;
192 uint32_t rhold;
193 uint32_t rsetup;
194 bool use_bbt;
195 unsigned wp_gpio;
196 struct mtd_partition *parts;
197 unsigned num_parts;
198};
199
200struct lpc32xx_nand_host {
201 struct nand_chip nand_chip;
202 struct clk *clk;
203 struct mtd_info mtd;
204 void __iomem *io_base;
205 struct lpc32xx_nand_cfg_slc *ncfg;
206
207 struct completion comp;
208 struct dma_chan *dma_chan;
209 uint32_t dma_buf_len;
210 struct dma_slave_config dma_slave_config;
211 struct scatterlist sgl;
212
213 /*
214 * DMA and CPU addresses of ECC work area and data buffer
215 */
216 uint32_t *ecc_buf;
217 uint8_t *data_buf;
218 dma_addr_t io_base_dma;
219};
220
221static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
222{
223 uint32_t clkrate, tmp;
224
225 /* Reset SLC controller */
226 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
227 udelay(1000);
228
229 /* Basic setup */
230 writel(0, SLC_CFG(host->io_base));
231 writel(0, SLC_IEN(host->io_base));
232 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
233 SLC_ICR(host->io_base));
234
235 /* Get base clock for SLC block */
236 clkrate = clk_get_rate(host->clk);
237 if (clkrate == 0)
238 clkrate = LPC32XX_DEF_BUS_RATE;
239
240 /* Compute clock setup values */
241 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
242 SLCTAC_WWIDTH(1 + (clkrate / host->ncfg->wwidth)) |
243 SLCTAC_WHOLD(1 + (clkrate / host->ncfg->whold)) |
244 SLCTAC_WSETUP(1 + (clkrate / host->ncfg->wsetup)) |
245 SLCTAC_RDR(host->ncfg->rdr_clks) |
246 SLCTAC_RWIDTH(1 + (clkrate / host->ncfg->rwidth)) |
247 SLCTAC_RHOLD(1 + (clkrate / host->ncfg->rhold)) |
248 SLCTAC_RSETUP(1 + (clkrate / host->ncfg->rsetup));
249 writel(tmp, SLC_TAC(host->io_base));
250}
251
252/*
253 * Hardware specific access to control lines
254 */
255static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
256 unsigned int ctrl)
257{
258 uint32_t tmp;
259 struct nand_chip *chip = mtd->priv;
260 struct lpc32xx_nand_host *host = chip->priv;
261
262 /* Does CE state need to be changed? */
263 tmp = readl(SLC_CFG(host->io_base));
264 if (ctrl & NAND_NCE)
265 tmp |= SLCCFG_CE_LOW;
266 else
267 tmp &= ~SLCCFG_CE_LOW;
268 writel(tmp, SLC_CFG(host->io_base));
269
270 if (cmd != NAND_CMD_NONE) {
271 if (ctrl & NAND_CLE)
272 writel(cmd, SLC_CMD(host->io_base));
273 else
274 writel(cmd, SLC_ADDR(host->io_base));
275 }
276}
277
278/*
279 * Read the Device Ready pin
280 */
281static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
282{
283 struct nand_chip *chip = mtd->priv;
284 struct lpc32xx_nand_host *host = chip->priv;
285 int rdy = 0;
286
287 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
288 rdy = 1;
289
290 return rdy;
291}
292
293/*
294 * Enable NAND write protect
295 */
296static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
297{
298 gpio_set_value(host->ncfg->wp_gpio, 0);
299}
300
301/*
302 * Disable NAND write protect
303 */
304static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
305{
306 gpio_set_value(host->ncfg->wp_gpio, 1);
307}
308
309/*
310 * Prepares SLC for transfers with H/W ECC enabled
311 */
312static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
313{
314 /* Hardware ECC is enabled automatically in hardware as needed */
315}
316
317/*
318 * Calculates the ECC for the data
319 */
320static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
321 const unsigned char *buf,
322 unsigned char *code)
323{
324 /*
325 * ECC is calculated automatically in hardware during syndrome read
326 * and write operations, so it doesn't need to be calculated here.
327 */
328 return 0;
329}
330
331/*
332 * Read a single byte from NAND device
333 */
334static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
335{
336 struct nand_chip *chip = mtd->priv;
337 struct lpc32xx_nand_host *host = chip->priv;
338
339 return (uint8_t)readl(SLC_DATA(host->io_base));
340}
341
342/*
343 * Simple device read without ECC
344 */
345static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
346{
347 struct nand_chip *chip = mtd->priv;
348 struct lpc32xx_nand_host *host = chip->priv;
349
350 /* Direct device read with no ECC */
351 while (len-- > 0)
352 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
353}
354
355/*
356 * Simple device write without ECC
357 */
358static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
359{
360 struct nand_chip *chip = mtd->priv;
361 struct lpc32xx_nand_host *host = chip->priv;
362
363 /* Direct device write with no ECC */
364 while (len-- > 0)
365 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
366}
367
368/*
369 * Verify data in buffer to data on device
370 */
371static int lpc32xx_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
372{
373 struct nand_chip *chip = mtd->priv;
374 struct lpc32xx_nand_host *host = chip->priv;
375 int i;
376
377 /* DATA register must be read as 32 bits or it will fail */
378 for (i = 0; i < len; i++) {
379 if (buf[i] != (uint8_t)readl(SLC_DATA(host->io_base)))
380 return -EFAULT;
381 }
382
383 return 0;
384}
385
386/*
387 * Read the OOB data from the device without ECC using FIFO method
388 */
389static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
390 struct nand_chip *chip, int page)
391{
392 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
393 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
394
395 return 0;
396}
397
398/*
399 * Write the OOB data to the device without ECC using FIFO method
400 */
401static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
402 struct nand_chip *chip, int page)
403{
404 int status;
405
406 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
407 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
408
409 /* Send command to program the OOB data */
410 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
411
412 status = chip->waitfunc(mtd, chip);
413
414 return status & NAND_STATUS_FAIL ? -EIO : 0;
415}
416
417/*
418 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
419 */
420static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
421{
422 int i;
423
424 for (i = 0; i < (count * 3); i += 3) {
425 uint32_t ce = ecc[i / 3];
426 ce = ~(ce << 2) & 0xFFFFFF;
427 spare[i + 2] = (uint8_t)(ce & 0xFF);
428 ce >>= 8;
429 spare[i + 1] = (uint8_t)(ce & 0xFF);
430 ce >>= 8;
431 spare[i] = (uint8_t)(ce & 0xFF);
432 }
433}
434
435static void lpc32xx_dma_complete_func(void *completion)
436{
437 complete(completion);
438}
439
440static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
441 void *mem, int len, enum dma_transfer_direction dir)
442{
443 struct nand_chip *chip = mtd->priv;
444 struct lpc32xx_nand_host *host = chip->priv;
445 struct dma_async_tx_descriptor *desc;
446 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
447 int res;
448
449 host->dma_slave_config.direction = dir;
450 host->dma_slave_config.src_addr = dma;
451 host->dma_slave_config.dst_addr = dma;
452 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
453 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
454 host->dma_slave_config.src_maxburst = 4;
455 host->dma_slave_config.dst_maxburst = 4;
456 /* DMA controller does flow control: */
457 host->dma_slave_config.device_fc = false;
458 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
459 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
460 return -ENXIO;
461 }
462
463 sg_init_one(&host->sgl, mem, len);
464
465 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
466 DMA_BIDIRECTIONAL);
467 if (res != 1) {
468 dev_err(mtd->dev.parent, "Failed to map sg list\n");
469 return -ENXIO;
470 }
471 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
472 flags);
473 if (!desc) {
474 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
475 goto out1;
476 }
477
478 init_completion(&host->comp);
479 desc->callback = lpc32xx_dma_complete_func;
480 desc->callback_param = &host->comp;
481
482 dmaengine_submit(desc);
483 dma_async_issue_pending(host->dma_chan);
484
485 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
486
487 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
488 DMA_BIDIRECTIONAL);
489
490 return 0;
491out1:
492 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
493 DMA_BIDIRECTIONAL);
494 return -ENXIO;
495}
496
497/*
498 * DMA read/write transfers with ECC support
499 */
500static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
501 int read)
502{
503 struct nand_chip *chip = mtd->priv;
504 struct lpc32xx_nand_host *host = chip->priv;
505 int i, status = 0;
506 unsigned long timeout;
507 int res;
508 enum dma_transfer_direction dir =
509 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
510 uint8_t *dma_buf;
511 bool dma_mapped;
512
513 if ((void *)buf <= high_memory) {
514 dma_buf = buf;
515 dma_mapped = true;
516 } else {
517 dma_buf = host->data_buf;
518 dma_mapped = false;
519 if (!read)
520 memcpy(host->data_buf, buf, mtd->writesize);
521 }
522
523 if (read) {
524 writel(readl(SLC_CFG(host->io_base)) |
525 SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
526 SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
527 } else {
528 writel((readl(SLC_CFG(host->io_base)) |
529 SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
530 ~SLCCFG_DMA_DIR,
531 SLC_CFG(host->io_base));
532 }
533
534 /* Clear initial ECC */
535 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
536
537 /* Transfer size is data area only */
538 writel(mtd->writesize, SLC_TC(host->io_base));
539
540 /* Start transfer in the NAND controller */
541 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
542 SLC_CTRL(host->io_base));
543
544 for (i = 0; i < chip->ecc.steps; i++) {
545 /* Data */
546 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
547 dma_buf + i * chip->ecc.size,
548 mtd->writesize / chip->ecc.steps, dir);
549 if (res)
550 return res;
551
552 /* Always _read_ ECC */
553 if (i == chip->ecc.steps - 1)
554 break;
555 if (!read) /* ECC availability delayed on write */
556 udelay(10);
557 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
558 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
559 if (res)
560 return res;
561 }
562
563 /*
564 * According to NXP, the DMA can be finished here, but the NAND
565 * controller may still have buffered data. After porting to using the
566 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
567 * appears to be always true, according to tests. Keeping the check for
568 * safety reasons for now.
569 */
570 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
571 dev_warn(mtd->dev.parent, "FIFO not empty!\n");
572 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
573 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
574 time_before(jiffies, timeout))
575 cpu_relax();
576 if (!time_before(jiffies, timeout)) {
577 dev_err(mtd->dev.parent, "FIFO held data too long\n");
578 status = -EIO;
579 }
580 }
581
582 /* Read last calculated ECC value */
583 if (!read)
584 udelay(10);
585 host->ecc_buf[chip->ecc.steps - 1] =
586 readl(SLC_ECC(host->io_base));
587
588 /* Flush DMA */
589 dmaengine_terminate_all(host->dma_chan);
590
591 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
592 readl(SLC_TC(host->io_base))) {
593 /* Something is left in the FIFO, something is wrong */
594 dev_err(mtd->dev.parent, "DMA FIFO failure\n");
595 status = -EIO;
596 }
597
598 /* Stop DMA & HW ECC */
599 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
600 SLC_CTRL(host->io_base));
601 writel(readl(SLC_CFG(host->io_base)) &
602 ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
603 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
604
605 if (!dma_mapped && read)
606 memcpy(buf, host->data_buf, mtd->writesize);
607
608 return status;
609}
610
611/*
612 * Read the data and OOB data from the device, use ECC correction with the
613 * data, disable ECC for the OOB data
614 */
615static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
616 struct nand_chip *chip, uint8_t *buf,
617 int oob_required, int page)
618{
619 struct lpc32xx_nand_host *host = chip->priv;
620 int stat, i, status;
621 uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
622
623 /* Issue read command */
624 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
625
626 /* Read data and oob, calculate ECC */
627 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
628
629 /* Get OOB data */
630 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
631
632 /* Convert to stored ECC format */
633 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
634
635 /* Pointer to ECC data retrieved from NAND spare area */
636 oobecc = chip->oob_poi + chip->ecc.layout->eccpos[0];
637
638 for (i = 0; i < chip->ecc.steps; i++) {
639 stat = chip->ecc.correct(mtd, buf, oobecc,
640 &tmpecc[i * chip->ecc.bytes]);
641 if (stat < 0)
642 mtd->ecc_stats.failed++;
643 else
644 mtd->ecc_stats.corrected += stat;
645
646 buf += chip->ecc.size;
647 oobecc += chip->ecc.bytes;
648 }
649
650 return status;
651}
652
653/*
654 * Read the data and OOB data from the device, no ECC correction with the
655 * data or OOB data
656 */
657static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
658 struct nand_chip *chip,
659 uint8_t *buf, int oob_required,
660 int page)
661{
662 /* Issue read command */
663 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
664
665 /* Raw reads can just use the FIFO interface */
666 chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
667 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
668
669 return 0;
670}
671
672/*
673 * Write the data and OOB data to the device, use ECC with the data,
674 * disable ECC for the OOB data
675 */
676static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
677 struct nand_chip *chip,
678 const uint8_t *buf, int oob_required)
679{
680 struct lpc32xx_nand_host *host = chip->priv;
681 uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0];
682 int error;
683
684 /* Write data, calculate ECC on outbound data */
685 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
686 if (error)
687 return error;
688
689 /*
690 * The calculated ECC needs some manual work done to it before
691 * committing it to NAND. Process the calculated ECC and place
692 * the resultant values directly into the OOB buffer. */
693 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
694
695 /* Write ECC data to device */
696 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
697 return 0;
698}
699
700/*
701 * Write the data and OOB data to the device, no ECC correction with the
702 * data or OOB data
703 */
704static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
705 struct nand_chip *chip,
706 const uint8_t *buf,
707 int oob_required)
708{
709 /* Raw writes can just use the FIFO interface */
710 chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
711 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
712 return 0;
713}
714
715static bool lpc32xx_dma_filter(struct dma_chan *chan, void *param)
716{
717 struct pl08x_dma_chan *ch =
718 container_of(chan, struct pl08x_dma_chan, chan);
719
720 /* In LPC32xx's PL080 DMA wiring, the SLC NAND DMA signal is #1 */
721 if (ch->cd->min_signal == 1)
722 return true;
723 return false;
724}
725
726static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
727{
728 struct mtd_info *mtd = &host->mtd;
729 dma_cap_mask_t mask;
730
731 dma_cap_zero(mask);
732 dma_cap_set(DMA_SLAVE, mask);
733 host->dma_chan = dma_request_channel(mask, lpc32xx_dma_filter, NULL);
734 if (!host->dma_chan) {
735 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
736 return -EBUSY;
737 }
738
739 return 0;
740}
741
742#ifdef CONFIG_OF
743static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
744{
745 struct lpc32xx_nand_cfg_slc *pdata;
746 struct device_node *np = dev->of_node;
747
748 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
749 if (!pdata) {
750 dev_err(dev, "could not allocate memory for platform data\n");
751 return NULL;
752 }
753
754 of_property_read_u32(np, "nxp,wdr-clks", &pdata->wdr_clks);
755 of_property_read_u32(np, "nxp,wwidth", &pdata->wwidth);
756 of_property_read_u32(np, "nxp,whold", &pdata->whold);
757 of_property_read_u32(np, "nxp,wsetup", &pdata->wsetup);
758 of_property_read_u32(np, "nxp,rdr-clks", &pdata->rdr_clks);
759 of_property_read_u32(np, "nxp,rwidth", &pdata->rwidth);
760 of_property_read_u32(np, "nxp,rhold", &pdata->rhold);
761 of_property_read_u32(np, "nxp,rsetup", &pdata->rsetup);
762
763 if (!pdata->wdr_clks || !pdata->wwidth || !pdata->whold ||
764 !pdata->wsetup || !pdata->rdr_clks || !pdata->rwidth ||
765 !pdata->rhold || !pdata->rsetup) {
766 dev_err(dev, "chip parameters not specified correctly\n");
767 return NULL;
768 }
769
770 pdata->use_bbt = of_get_nand_on_flash_bbt(np);
771 pdata->wp_gpio = of_get_named_gpio_flags(np, "gpios", 0, NULL);
772
773 return pdata;
774}
775#else
776static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
777{
778 return NULL;
779}
780#endif
781
782/*
783 * Probe for NAND controller
784 */
785static int __devinit lpc32xx_nand_probe(struct platform_device *pdev)
786{
787 struct lpc32xx_nand_host *host;
788 struct mtd_info *mtd;
789 struct nand_chip *chip;
790 struct resource *rc;
791 struct mtd_part_parser_data ppdata = {};
792 int res;
793
794 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
795 if (rc == NULL) {
796 dev_err(&pdev->dev, "No memory resource found for device\n");
797 return -EBUSY;
798 }
799
800 /* Allocate memory for the device structure (and zero it) */
801 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
802 if (!host) {
803 dev_err(&pdev->dev, "failed to allocate device structure\n");
804 return -ENOMEM;
805 }
806 host->io_base_dma = rc->start;
807
808 host->io_base = devm_request_and_ioremap(&pdev->dev, rc);
809 if (host->io_base == NULL) {
810 dev_err(&pdev->dev, "ioremap failed\n");
811 return -ENOMEM;
812 }
813
814 if (pdev->dev.of_node)
815 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
816 else
817 host->ncfg = pdev->dev.platform_data;
818 if (!host->ncfg) {
819 dev_err(&pdev->dev, "Missing platform data\n");
820 return -ENOENT;
821 }
822 if (gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
823 dev_err(&pdev->dev, "GPIO not available\n");
824 return -EBUSY;
825 }
826 lpc32xx_wp_disable(host);
827
828 mtd = &host->mtd;
829 chip = &host->nand_chip;
830 chip->priv = host;
831 mtd->priv = chip;
832 mtd->owner = THIS_MODULE;
833 mtd->dev.parent = &pdev->dev;
834
835 /* Get NAND clock */
836 host->clk = clk_get(&pdev->dev, NULL);
837 if (IS_ERR(host->clk)) {
838 dev_err(&pdev->dev, "Clock failure\n");
839 res = -ENOENT;
840 goto err_exit1;
841 }
842 clk_enable(host->clk);
843
844 /* Set NAND IO addresses and command/ready functions */
845 chip->IO_ADDR_R = SLC_DATA(host->io_base);
846 chip->IO_ADDR_W = SLC_DATA(host->io_base);
847 chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
848 chip->dev_ready = lpc32xx_nand_device_ready;
849 chip->chip_delay = 20; /* 20us command delay time */
850
851 /* Init NAND controller */
852 lpc32xx_nand_setup(host);
853
854 platform_set_drvdata(pdev, host);
855
856 /* NAND callbacks for LPC32xx SLC hardware */
857 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
858 chip->read_byte = lpc32xx_nand_read_byte;
859 chip->read_buf = lpc32xx_nand_read_buf;
860 chip->write_buf = lpc32xx_nand_write_buf;
861 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
862 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
863 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
864 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
865 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
866 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
867 chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
868 chip->ecc.correct = nand_correct_data;
869 chip->ecc.strength = 1;
870 chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
871 chip->verify_buf = lpc32xx_verify_buf;
872
873 /* bitflip_threshold's default is defined as ecc_strength anyway.
874 * Unfortunately, it is set only later at add_mtd_device(). Meanwhile
875 * being 0, it causes bad block table scanning errors in
876 * nand_scan_tail(), so preparing it here already. */
877 mtd->bitflip_threshold = chip->ecc.strength;
878
879 /*
880 * Allocate a large enough buffer for a single huge page plus
881 * extra space for the spare area and ECC storage area
882 */
883 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
884 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
885 GFP_KERNEL);
886 if (host->data_buf == NULL) {
887 dev_err(&pdev->dev, "Error allocating memory\n");
888 res = -ENOMEM;
889 goto err_exit2;
890 }
891
892 res = lpc32xx_nand_dma_setup(host);
893 if (res) {
894 res = -EIO;
895 goto err_exit2;
896 }
897
898 /* Find NAND device */
899 if (nand_scan_ident(mtd, 1, NULL)) {
900 res = -ENXIO;
901 goto err_exit3;
902 }
903
904 /* OOB and ECC CPU and DMA work areas */
905 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
906
907 /*
908 * Small page FLASH has a unique OOB layout, but large and huge
909 * page FLASH use the standard layout. Small page FLASH uses a
910 * custom BBT marker layout.
911 */
912 if (mtd->writesize <= 512)
913 chip->ecc.layout = &lpc32xx_nand_oob_16;
914
915 /* These sizes remain the same regardless of page size */
916 chip->ecc.size = 256;
917 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
918 chip->ecc.prepad = chip->ecc.postpad = 0;
919
920 /* Avoid extra scan if using BBT, setup BBT support */
921 if (host->ncfg->use_bbt) {
922 chip->options |= NAND_SKIP_BBTSCAN;
923 chip->bbt_options |= NAND_BBT_USE_FLASH;
924
925 /*
926 * Use a custom BBT marker setup for small page FLASH that
927 * won't interfere with the ECC layout. Large and huge page
928 * FLASH use the standard layout.
929 */
930 if (mtd->writesize <= 512) {
931 chip->bbt_td = &bbt_smallpage_main_descr;
932 chip->bbt_md = &bbt_smallpage_mirror_descr;
933 }
934 }
935
936 /*
937 * Fills out all the uninitialized function pointers with the defaults
938 */
939 if (nand_scan_tail(mtd)) {
940 res = -ENXIO;
941 goto err_exit3;
942 }
943
944 /* Standard layout in FLASH for bad block tables */
945 if (host->ncfg->use_bbt) {
946 if (nand_default_bbt(mtd) < 0)
947 dev_err(&pdev->dev,
948 "Error initializing default bad block tables\n");
949 }
950
951 mtd->name = "nxp_lpc3220_slc";
952 ppdata.of_node = pdev->dev.of_node;
953 res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts,
954 host->ncfg->num_parts);
955 if (!res)
956 return res;
957
958 nand_release(mtd);
959
960err_exit3:
961 dma_release_channel(host->dma_chan);
962err_exit2:
963 clk_disable(host->clk);
964 clk_put(host->clk);
965 platform_set_drvdata(pdev, NULL);
966err_exit1:
967 lpc32xx_wp_enable(host);
968 gpio_free(host->ncfg->wp_gpio);
969
970 return res;
971}
972
973/*
974 * Remove NAND device.
975 */
976static int __devexit lpc32xx_nand_remove(struct platform_device *pdev)
977{
978 uint32_t tmp;
979 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
980 struct mtd_info *mtd = &host->mtd;
981
982 nand_release(mtd);
983 dma_release_channel(host->dma_chan);
984
985 /* Force CE high */
986 tmp = readl(SLC_CTRL(host->io_base));
987 tmp &= ~SLCCFG_CE_LOW;
988 writel(tmp, SLC_CTRL(host->io_base));
989
990 clk_disable(host->clk);
991 clk_put(host->clk);
992 platform_set_drvdata(pdev, NULL);
993 lpc32xx_wp_enable(host);
994 gpio_free(host->ncfg->wp_gpio);
995
996 return 0;
997}
998
999#ifdef CONFIG_PM
1000static int lpc32xx_nand_resume(struct platform_device *pdev)
1001{
1002 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
1003
1004 /* Re-enable NAND clock */
1005 clk_enable(host->clk);
1006
1007 /* Fresh init of NAND controller */
1008 lpc32xx_nand_setup(host);
1009
1010 /* Disable write protect */
1011 lpc32xx_wp_disable(host);
1012
1013 return 0;
1014}
1015
1016static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
1017{
1018 uint32_t tmp;
1019 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
1020
1021 /* Force CE high */
1022 tmp = readl(SLC_CTRL(host->io_base));
1023 tmp &= ~SLCCFG_CE_LOW;
1024 writel(tmp, SLC_CTRL(host->io_base));
1025
1026 /* Enable write protect for safety */
1027 lpc32xx_wp_enable(host);
1028
1029 /* Disable clock */
1030 clk_disable(host->clk);
1031
1032 return 0;
1033}
1034
1035#else
1036#define lpc32xx_nand_resume NULL
1037#define lpc32xx_nand_suspend NULL
1038#endif
1039
1040#if defined(CONFIG_OF)
1041static const struct of_device_id lpc32xx_nand_match[] = {
1042 { .compatible = "nxp,lpc3220-slc" },
1043 { /* sentinel */ },
1044};
1045MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
1046#endif
1047
1048static struct platform_driver lpc32xx_nand_driver = {
1049 .probe = lpc32xx_nand_probe,
1050 .remove = __devexit_p(lpc32xx_nand_remove),
1051 .resume = lpc32xx_nand_resume,
1052 .suspend = lpc32xx_nand_suspend,
1053 .driver = {
1054 .name = LPC32XX_MODNAME,
1055 .owner = THIS_MODULE,
1056 .of_match_table = of_match_ptr(lpc32xx_nand_match),
1057 },
1058};
1059
1060module_platform_driver(lpc32xx_nand_driver);
1061
1062MODULE_LICENSE("GPL");
1063MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1064MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1065MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 03:04:21 -0500