diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2011-05-20 12:36:11 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@gmail.com> | 2011-05-22 06:20:41 -0400 |
| commit | 2307790f0c8dea7d8052805a8209fbd67e815e72 (patch) | |
| tree | d0038955a1b8c54f2820cbd372e7a72a1246a74c /drivers | |
| parent | 6f15c506e0cec601fad9fabb7ded0d1811b8002f (diff) | |
drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only
For DP/eDP, always use the standard DP SS indices.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 42 |
1 files changed, 12 insertions, 30 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index f5819ba481d9..48f5ff023bca 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
| @@ -942,42 +942,24 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode | |||
| 942 | case ATOM_ENCODER_MODE_DP: | 942 | case ATOM_ENCODER_MODE_DP: |
| 943 | /* DP/eDP */ | 943 | /* DP/eDP */ |
| 944 | dp_clock = dig_connector->dp_clock / 10; | 944 | dp_clock = dig_connector->dp_clock / 10; |
| 945 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { | 945 | if (ASIC_IS_DCE4(rdev)) |
| 946 | if (ASIC_IS_DCE4(rdev)) { | 946 | ss_enabled = |
| 947 | /* first try ASIC_INTERNAL_SS_ON_DP */ | 947 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 948 | ASIC_INTERNAL_SS_ON_DP, | ||
| 949 | dp_clock); | ||
| 950 | else { | ||
| 951 | if (dp_clock == 16200) { | ||
| 948 | ss_enabled = | 952 | ss_enabled = |
| 949 | radeon_atombios_get_asic_ss_info(rdev, &ss, | 953 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 950 | ASIC_INTERNAL_SS_ON_DP, | 954 | ATOM_DP_SS_ID2); |
| 951 | dp_clock); | ||
| 952 | if (!ss_enabled) | 955 | if (!ss_enabled) |
| 953 | ss_enabled = | 956 | ss_enabled = |
| 954 | radeon_atombios_get_asic_ss_info(rdev, &ss, | 957 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 955 | dig->lcd_ss_id, | 958 | ATOM_DP_SS_ID1); |
| 956 | dp_clock); | ||
| 957 | } else | 959 | } else |
| 958 | ss_enabled = | 960 | ss_enabled = |
| 959 | radeon_atombios_get_ppll_ss_info(rdev, &ss, | 961 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 960 | dig->lcd_ss_id); | 962 | ATOM_DP_SS_ID1); |
| 961 | } else { | ||
| 962 | if (ASIC_IS_DCE4(rdev)) | ||
| 963 | ss_enabled = | ||
| 964 | radeon_atombios_get_asic_ss_info(rdev, &ss, | ||
| 965 | ASIC_INTERNAL_SS_ON_DP, | ||
| 966 | dp_clock); | ||
| 967 | else { | ||
| 968 | if (dp_clock == 16200) { | ||
| 969 | ss_enabled = | ||
| 970 | radeon_atombios_get_ppll_ss_info(rdev, &ss, | ||
| 971 | ATOM_DP_SS_ID2); | ||
| 972 | if (!ss_enabled) | ||
| 973 | ss_enabled = | ||
| 974 | radeon_atombios_get_ppll_ss_info(rdev, &ss, | ||
| 975 | ATOM_DP_SS_ID1); | ||
| 976 | } else | ||
| 977 | ss_enabled = | ||
| 978 | radeon_atombios_get_ppll_ss_info(rdev, &ss, | ||
| 979 | ATOM_DP_SS_ID1); | ||
| 980 | } | ||
| 981 | } | 963 | } |
| 982 | break; | 964 | break; |
| 983 | case ATOM_ENCODER_MODE_LVDS: | 965 | case ATOM_ENCODER_MODE_LVDS: |