drm/radeon: Add support for programming the FMT blocks

The FMT blocks control how data is sent from the backend of the display pipe to to monitor. Proper set up of the FMT blocks are required for 30bpp formats. Additionally, dithering can be enabled on for better display with 18 and 24bpp displays. The exception is LVDS/eDP which atom takes care of in the SelectCRTC_Source table. For now just enable truncation until we test dithering more. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
author: Alex Deucher <alexander.deucher@amd.com> 2013-09-23 12:22:11 -0400
committer: Alex Deucher <alexander.deucher@amd.com> 2013-11-01 12:43:12 -0400
commit: 134b480f4b92654b9590fad6c9374c7dc6722375 (patch)
tree: b5d423cad7200e8efd2e23d08d76c5df6a348bd7 /drivers
parent: 9d6104e0174b130ed864571b31811c3fd09fd611 (diff)
9 files changed, 333 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 28e2dc48e015..ffd99737014b 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -2392,6 +2392,15 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
        /* this is needed for the pll/ss setup to work correctly in some cases */
        atombios_set_encoder_crtc_source(encoder);
+        /* set up the FMT blocks */
+        if (ASIC_IS_DCE8(rdev))
+                dce8_program_fmt(encoder);
+        else if (ASIC_IS_DCE4(rdev))
+                dce4_program_fmt(encoder);
+        else if (ASIC_IS_DCE3(rdev))
+                dce3_program_fmt(encoder);
+        else if (ASIC_IS_AVIVO(rdev))
+                avivo_program_fmt(encoder);
 }
 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index d02fd1c045d5..ccd0871d44fe 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7418,6 +7418,67 @@ void cik_fini(struct radeon_device *rdev)
        rdev->bios = NULL;
 }
+void dce8_program_fmt(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+        int bpc = 0;
+        u32 tmp = 0;
+        bool dither = false;
+        if (connector)
+                bpc = radeon_get_monitor_bpc(connector);
+        /* LVDS/eDP FMT is set up by atom */
+        if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
+                return;
+        /* not needed for analog */
+        if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
+            (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
+                return;
+        if (bpc == 0)
+                return;
+        switch (bpc) {
+        case 6:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
+                                FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));
+                else
+                        tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
+                break;
+        case 8:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
+                                FMT_RGB_RANDOM_ENABLE |
+                                FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));
+                else
+                        tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
+                break;
+        case 10:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
+                                FMT_RGB_RANDOM_ENABLE |
+                                FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));
+                else
+                        tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
+                break;
+        default:
+                /* not needed */
+                break;
+        }
+        WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
+}
 /* display watermark setup */
 /**
 * dce8_line_buffer_adjust - Set up the line buffer
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 203d2a09a1f5..74172ccbc405 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -906,6 +906,39 @@
 #define DPG_PIPE_STUTTER_CONTROL                          0x6cd4
 #       define STUTTER_ENABLE                             (1 << 0)
+/* DCE8 FMT blocks */
+#define FMT_DYNAMIC_EXP_CNTL                 0x6fb4
+#       define FMT_DYNAMIC_EXP_EN            (1 << 0)
+#       define FMT_DYNAMIC_EXP_MODE          (1 << 4)
+        /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
+#define FMT_CONTROL                          0x6fb8
+#       define FMT_PIXEL_ENCODING            (1 << 16)
+        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
+#define FMT_BIT_DEPTH_CONTROL                0x6fc8
+#       define FMT_TRUNCATE_EN               (1 << 0)
+#       define FMT_TRUNCATE_MODE             (1 << 1)
+#       define FMT_TRUNCATE_DEPTH(x)         ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
+#       define FMT_SPATIAL_DITHER_EN         (1 << 8)
+#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)
+#       define FMT_SPATIAL_DITHER_DEPTH(x)   ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
+#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)
+#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)
+#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)
+#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)
+#       define FMT_TEMPORAL_DITHER_DEPTH(x)  ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
+#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
+#       define FMT_TEMPORAL_LEVEL            (1 << 24)
+#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)
+#       define FMT_25FRC_SEL(x)              ((x) << 26)
+#       define FMT_50FRC_SEL(x)              ((x) << 28)
+#       define FMT_75FRC_SEL(x)              ((x) << 30)
+#define FMT_CLAMP_CONTROL                    0x6fe4
+#       define FMT_CLAMP_DATA_EN             (1 << 0)
+#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)
+#       define FMT_CLAMP_6BPC                0
+#       define FMT_CLAMP_8BPC                1
+#       define FMT_CLAMP_10BPC               2
 #define GRBM_CNTL                                       0x8000
 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 555164e270a7..feedfcc6554b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1193,6 +1193,59 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
        }
 }
+void dce4_program_fmt(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+        int bpc = 0;
+        u32 tmp = 0;
+        bool dither = false;
+        if (connector)
+                bpc = radeon_get_monitor_bpc(connector);
+        /* LVDS/eDP FMT is set up by atom */
+        if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
+                return;
+        /* not needed for analog */
+        if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
+            (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
+                return;
+        if (bpc == 0)
+                return;
+        switch (bpc) {
+        case 6:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
+                                FMT_SPATIAL_DITHER_EN);
+                else
+                        tmp |= FMT_TRUNCATE_EN;
+                break;
+        case 8:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
+                                FMT_RGB_RANDOM_ENABLE |
+                                FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
+                else
+                        tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
+                break;
+        case 10:
+        default:
+                /* not needed */
+                break;
+        }
+        WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
+}
 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
 {
        if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 8768fd6a1e27..fa81893726f4 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1312,6 +1312,38 @@
 #       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
 #       define DC_HPDx_EN                                 (1 << 28)
+/* DCE4/5/6 FMT blocks */
+#define FMT_DYNAMIC_EXP_CNTL                 0x6fb4
+#       define FMT_DYNAMIC_EXP_EN            (1 << 0)
+#       define FMT_DYNAMIC_EXP_MODE          (1 << 4)
+        /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
+#define FMT_CONTROL                          0x6fb8
+#       define FMT_PIXEL_ENCODING            (1 << 16)
+        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
+#define FMT_BIT_DEPTH_CONTROL                0x6fc8
+#       define FMT_TRUNCATE_EN               (1 << 0)
+#       define FMT_TRUNCATE_DEPTH            (1 << 4)
+#       define FMT_SPATIAL_DITHER_EN         (1 << 8)
+#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)
+#       define FMT_SPATIAL_DITHER_DEPTH      (1 << 12)
+#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)
+#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)
+#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)
+#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)
+#       define FMT_TEMPORAL_DITHER_DEPTH     (1 << 20)
+#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
+#       define FMT_TEMPORAL_LEVEL            (1 << 24)
+#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)
+#       define FMT_25FRC_SEL(x)              ((x) << 26)
+#       define FMT_50FRC_SEL(x)              ((x) << 28)
+#       define FMT_75FRC_SEL(x)              ((x) << 30)
+#define FMT_CLAMP_CONTROL                    0x6fe4
+#       define FMT_CLAMP_DATA_EN             (1 << 0)
+#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)
+#       define FMT_CLAMP_6BPC                0
+#       define FMT_CLAMP_8BPC                1
+#       define FMT_CLAMP_10BPC               2
 /* ASYNC DMA */
 #define DMA_RB_RPTR                                       0xd008
 #define DMA_RB_WPTR                                       0xd00c
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 2a1b1876b431..bdf4b80202d5 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -124,6 +124,56 @@ int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
        return 0;
 }
+void dce3_program_fmt(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+        int bpc = 0;
+        u32 tmp = 0;
+        bool dither = false;
+        if (connector)
+                bpc = radeon_get_monitor_bpc(connector);
+        /* LVDS FMT is set up by atom */
+        if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
+                return;
+        /* not needed for analog */
+        if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
+            (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
+                return;
+        if (bpc == 0)
+                return;
+        switch (bpc) {
+        case 6:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= FMT_SPATIAL_DITHER_EN;
+                else
+                        tmp |= FMT_TRUNCATE_EN;
+                break;
+        case 8:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
+                else
+                        tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
+                break;
+        case 10:
+        default:
+                /* not needed */
+                break;
+        }
+        WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
+}
 /* get temperature in millidegrees */
 int rv6xx_get_temp(struct radeon_device *rdev)
 {
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index e673fe26ea84..8e01b126aaeb 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1199,6 +1199,34 @@
 #       define AFMT_AZ_FORMAT_WTRIG_ACK      (1 << 29)
 #       define AFMT_AZ_AUDIO_ENABLE_CHG_ACK  (1 << 30)
+/* DCE3 FMT blocks */
+#define FMT_CONTROL                          0x6700
+#       define FMT_PIXEL_ENCODING            (1 << 16)
+        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
+#define FMT_BIT_DEPTH_CONTROL                0x6710
+#       define FMT_TRUNCATE_EN               (1 << 0)
+#       define FMT_TRUNCATE_DEPTH            (1 << 4)
+#       define FMT_SPATIAL_DITHER_EN         (1 << 8)
+#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)
+#       define FMT_SPATIAL_DITHER_DEPTH      (1 << 12)
+#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)
+#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)
+#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)
+#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)
+#       define FMT_TEMPORAL_DITHER_DEPTH     (1 << 20)
+#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
+#       define FMT_TEMPORAL_LEVEL            (1 << 24)
+#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)
+#       define FMT_25FRC_SEL(x)              ((x) << 26)
+#       define FMT_50FRC_SEL(x)              ((x) << 28)
+#       define FMT_75FRC_SEL(x)              ((x) << 30)
+#define FMT_CLAMP_CONTROL                    0x672c
+#       define FMT_CLAMP_DATA_EN             (1 << 0)
+#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)
+#       define FMT_CLAMP_6BPC                0
+#       define FMT_CLAMP_8BPC                1
+#       define FMT_CLAMP_10BPC               2
 /* Power management */
 #define CG_SPLL_FUNC_CNTL                                 0x600
 #       define SPLL_RESET                                (1 << 0)
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index ef63d3f00b2f..03f74b0276c5 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -850,6 +850,12 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
                               struct drm_display_mode *mode,
                               struct drm_display_mode *adjusted_mode);
+/* fmt blocks */
+void avivo_program_fmt(struct drm_encoder *encoder);
+void dce3_program_fmt(struct drm_encoder *encoder);
+void dce4_program_fmt(struct drm_encoder *encoder);
+void dce8_program_fmt(struct drm_encoder *encoder);
 /* fbdev layer */
 int radeon_fbdev_init(struct radeon_device *rdev);
 void radeon_fbdev_fini(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 6acba8017b9a..df01aa398cc5 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -153,6 +153,67 @@ u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
        return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
 }
+void avivo_program_fmt(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+        int bpc = 0;
+        u32 tmp = 0;
+        bool dither = false;
+        if (connector)
+                bpc = radeon_get_monitor_bpc(connector);
+        /* LVDS FMT is set up by atom */
+        if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
+                return;
+        if (bpc == 0)
+                return;
+        switch (bpc) {
+        case 6:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
+                else
+                        tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
+                break;
+        case 8:
+                if (dither)
+                        /* XXX sort out optimal dither settings */
+                        tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
+                                AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
+                else
+                        tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
+                                AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
+                break;
+        case 10:
+        default:
+                /* not needed */
+                break;
+        }
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+                WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DDI:
+                WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
+                break;
+        default:
+                break;
+        }
+}
 void rs600_pm_misc(struct radeon_device *rdev)
 {
        int requested_index = rdev->pm.requested_power_state_index;
author	Alex Deucher <alexander.deucher@amd.com>	2013-09-23 12:22:11 -0400
committer	Alex Deucher <alexander.deucher@amd.com>	2013-11-01 12:43:12 -0400
commit	134b480f4b92654b9590fad6c9374c7dc6722375 (patch)
tree	b5d423cad7200e8efd2e23d08d76c5df6a348bd7 /drivers
parent	9d6104e0174b130ed864571b31811c3fd09fd611 (diff)

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 28e2dc48e015..ffd99737014b 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -2392,6 +2392,15 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2392		2392
2393	/* this is needed for the pll/ss setup to work correctly in some cases */	2393	/* this is needed for the pll/ss setup to work correctly in some cases */
2394	atombios_set_encoder_crtc_source(encoder);	2394	atombios_set_encoder_crtc_source(encoder);
		2395	/* set up the FMT blocks */
		2396	if (ASIC_IS_DCE8(rdev))
		2397	dce8_program_fmt(encoder);
		2398	else if (ASIC_IS_DCE4(rdev))
		2399	dce4_program_fmt(encoder);
		2400	else if (ASIC_IS_DCE3(rdev))
		2401	dce3_program_fmt(encoder);
		2402	else if (ASIC_IS_AVIVO(rdev))
		2403	avivo_program_fmt(encoder);
2395	}	2404	}
2396		2405
2397	static void radeon_atom_encoder_commit(struct drm_encoder *encoder)	2406	static void radeon_atom_encoder_commit(struct drm_encoder *encoder)


diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index d02fd1c045d5..ccd0871d44fe 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c
@@ -7418,6 +7418,67 @@ void cik_fini(struct radeon_device *rdev)
7418	rdev->bios = NULL;	7418	rdev->bios = NULL;
7419	}	7419	}
7420		7420
		7421	void dce8_program_fmt(struct drm_encoder *encoder)
		7422	{
		7423	struct drm_device *dev = encoder->dev;
		7424	struct radeon_device *rdev = dev->dev_private;
		7425	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		7426	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		7427	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		7428	int bpc = 0;
		7429	u32 tmp = 0;
		7430	bool dither = false;
		7431
		7432	if (connector)
		7433	bpc = radeon_get_monitor_bpc(connector);
		7434
		7435	/* LVDS/eDP FMT is set up by atom */
		7436	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
		7437	return;
		7438
		7439	/* not needed for analog */
		7440	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) \|\|
		7441	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
		7442	return;
		7443
		7444	if (bpc == 0)
		7445	return;
		7446
		7447	switch (bpc) {
		7448	case 6:
		7449	if (dither)
		7450	/* XXX sort out optimal dither settings */
		7451	tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \|
		7452	FMT_SPATIAL_DITHER_EN \| FMT_SPATIAL_DITHER_DEPTH(0));
		7453	else
		7454	tmp \|= (FMT_TRUNCATE_EN \| FMT_TRUNCATE_DEPTH(0));
		7455	break;
		7456	case 8:
		7457	if (dither)
		7458	/* XXX sort out optimal dither settings */
		7459	tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \|
		7460	FMT_RGB_RANDOM_ENABLE \|
		7461	FMT_SPATIAL_DITHER_EN \| FMT_SPATIAL_DITHER_DEPTH(1));
		7462	else
		7463	tmp \|= (FMT_TRUNCATE_EN \| FMT_TRUNCATE_DEPTH(1));
		7464	break;
		7465	case 10:
		7466	if (dither)
		7467	/* XXX sort out optimal dither settings */
		7468	tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \|
		7469	FMT_RGB_RANDOM_ENABLE \|
		7470	FMT_SPATIAL_DITHER_EN \| FMT_SPATIAL_DITHER_DEPTH(2));
		7471	else
		7472	tmp \|= (FMT_TRUNCATE_EN \| FMT_TRUNCATE_DEPTH(2));
		7473	break;
		7474	default:
		7475	/* not needed */
		7476	break;
		7477	}
		7478
		7479	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
		7480	}
		7481
7421	/* display watermark setup */	7482	/* display watermark setup */
7422	/**	7483	/**
7423	* dce8_line_buffer_adjust - Set up the line buffer	7484	* dce8_line_buffer_adjust - Set up the line buffer


diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 203d2a09a1f5..74172ccbc405 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h
@@ -906,6 +906,39 @@
906	#define DPG_PIPE_STUTTER_CONTROL 0x6cd4	906	#define DPG_PIPE_STUTTER_CONTROL 0x6cd4
907	# define STUTTER_ENABLE (1 << 0)	907	# define STUTTER_ENABLE (1 << 0)
908		908
		909	/* DCE8 FMT blocks */
		910	#define FMT_DYNAMIC_EXP_CNTL 0x6fb4
		911	# define FMT_DYNAMIC_EXP_EN (1 << 0)
		912	# define FMT_DYNAMIC_EXP_MODE (1 << 4)
		913	/* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
		914	#define FMT_CONTROL 0x6fb8
		915	# define FMT_PIXEL_ENCODING (1 << 16)
		916	/* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
		917	#define FMT_BIT_DEPTH_CONTROL 0x6fc8
		918	# define FMT_TRUNCATE_EN (1 << 0)
		919	# define FMT_TRUNCATE_MODE (1 << 1)
		920	# define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
		921	# define FMT_SPATIAL_DITHER_EN (1 << 8)
		922	# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
		923	# define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
		924	# define FMT_FRAME_RANDOM_ENABLE (1 << 13)
		925	# define FMT_RGB_RANDOM_ENABLE (1 << 14)
		926	# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
		927	# define FMT_TEMPORAL_DITHER_EN (1 << 16)
		928	# define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
		929	# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
		930	# define FMT_TEMPORAL_LEVEL (1 << 24)
		931	# define FMT_TEMPORAL_DITHER_RESET (1 << 25)
		932	# define FMT_25FRC_SEL(x) ((x) << 26)
		933	# define FMT_50FRC_SEL(x) ((x) << 28)
		934	# define FMT_75FRC_SEL(x) ((x) << 30)
		935	#define FMT_CLAMP_CONTROL 0x6fe4
		936	# define FMT_CLAMP_DATA_EN (1 << 0)
		937	# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
		938	# define FMT_CLAMP_6BPC 0
		939	# define FMT_CLAMP_8BPC 1
		940	# define FMT_CLAMP_10BPC 2
		941
909	#define GRBM_CNTL 0x8000	942	#define GRBM_CNTL 0x8000
910	#define GRBM_READ_TIMEOUT(x) ((x) << 0)	943	#define GRBM_READ_TIMEOUT(x) ((x) << 0)
911		944


diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 555164e270a7..feedfcc6554b 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1193,6 +1193,59 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
1193	}	1193	}
1194	}	1194	}
1195		1195
		1196	void dce4_program_fmt(struct drm_encoder *encoder)
		1197	{
		1198	struct drm_device *dev = encoder->dev;
		1199	struct radeon_device *rdev = dev->dev_private;
		1200	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1201	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1202	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		1203	int bpc = 0;
		1204	u32 tmp = 0;
		1205	bool dither = false;
		1206
		1207	if (connector)
		1208	bpc = radeon_get_monitor_bpc(connector);
		1209
		1210	/* LVDS/eDP FMT is set up by atom */
		1211	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
		1212	return;
		1213
		1214	/* not needed for analog */
		1215	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) \|\|
		1216	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
		1217	return;
		1218
		1219	if (bpc == 0)
		1220	return;
		1221
		1222	switch (bpc) {
		1223	case 6:
		1224	if (dither)
		1225	/* XXX sort out optimal dither settings */
		1226	tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \|
		1227	FMT_SPATIAL_DITHER_EN);
		1228	else
		1229	tmp \|= FMT_TRUNCATE_EN;
		1230	break;
		1231	case 8:
		1232	if (dither)
		1233	/* XXX sort out optimal dither settings */
		1234	tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \|
		1235	FMT_RGB_RANDOM_ENABLE \|
		1236	FMT_SPATIAL_DITHER_EN \| FMT_SPATIAL_DITHER_DEPTH);
		1237	else
		1238	tmp \|= (FMT_TRUNCATE_EN \| FMT_TRUNCATE_DEPTH);
		1239	break;
		1240	case 10:
		1241	default:
		1242	/* not needed */
		1243	break;
		1244	}
		1245
		1246	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
		1247	}
		1248
1196	static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)	1249	static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1197	{	1250	{
1198	if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)	1251	if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)


diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 8768fd6a1e27..fa81893726f4 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1312,6 +1312,38 @@
1312	# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)	1312	# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
1313	# define DC_HPDx_EN (1 << 28)	1313	# define DC_HPDx_EN (1 << 28)
1314		1314
		1315	/* DCE4/5/6 FMT blocks */
		1316	#define FMT_DYNAMIC_EXP_CNTL 0x6fb4
		1317	# define FMT_DYNAMIC_EXP_EN (1 << 0)
		1318	# define FMT_DYNAMIC_EXP_MODE (1 << 4)
		1319	/* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
		1320	#define FMT_CONTROL 0x6fb8
		1321	# define FMT_PIXEL_ENCODING (1 << 16)
		1322	/* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
		1323	#define FMT_BIT_DEPTH_CONTROL 0x6fc8
		1324	# define FMT_TRUNCATE_EN (1 << 0)
		1325	# define FMT_TRUNCATE_DEPTH (1 << 4)
		1326	# define FMT_SPATIAL_DITHER_EN (1 << 8)
		1327	# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
		1328	# define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
		1329	# define FMT_FRAME_RANDOM_ENABLE (1 << 13)
		1330	# define FMT_RGB_RANDOM_ENABLE (1 << 14)
		1331	# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
		1332	# define FMT_TEMPORAL_DITHER_EN (1 << 16)
		1333	# define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
		1334	# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
		1335	# define FMT_TEMPORAL_LEVEL (1 << 24)
		1336	# define FMT_TEMPORAL_DITHER_RESET (1 << 25)
		1337	# define FMT_25FRC_SEL(x) ((x) << 26)
		1338	# define FMT_50FRC_SEL(x) ((x) << 28)
		1339	# define FMT_75FRC_SEL(x) ((x) << 30)
		1340	#define FMT_CLAMP_CONTROL 0x6fe4
		1341	# define FMT_CLAMP_DATA_EN (1 << 0)
		1342	# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
		1343	# define FMT_CLAMP_6BPC 0
		1344	# define FMT_CLAMP_8BPC 1
		1345	# define FMT_CLAMP_10BPC 2
		1346
1315	/* ASYNC DMA */	1347	/* ASYNC DMA */
1316	#define DMA_RB_RPTR 0xd008	1348	#define DMA_RB_RPTR 0xd008
1317	#define DMA_RB_WPTR 0xd00c	1349	#define DMA_RB_WPTR 0xd00c


diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 2a1b1876b431..bdf4b80202d5 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c
@@ -124,6 +124,56 @@ int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
124	return 0;	124	return 0;
125	}	125	}
126		126
		127	void dce3_program_fmt(struct drm_encoder *encoder)
		128	{
		129	struct drm_device *dev = encoder->dev;
		130	struct radeon_device *rdev = dev->dev_private;
		131	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		132	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		133	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		134	int bpc = 0;
		135	u32 tmp = 0;
		136	bool dither = false;
		137
		138	if (connector)
		139	bpc = radeon_get_monitor_bpc(connector);
		140
		141	/* LVDS FMT is set up by atom */
		142	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
		143	return;
		144
		145	/* not needed for analog */
		146	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) \|\|
		147	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
		148	return;
		149
		150	if (bpc == 0)
		151	return;
		152
		153	switch (bpc) {
		154	case 6:
		155	if (dither)
		156	/* XXX sort out optimal dither settings */
		157	tmp \|= FMT_SPATIAL_DITHER_EN;
		158	else
		159	tmp \|= FMT_TRUNCATE_EN;
		160	break;
		161	case 8:
		162	if (dither)
		163	/* XXX sort out optimal dither settings */
		164	tmp \|= (FMT_SPATIAL_DITHER_EN \| FMT_SPATIAL_DITHER_DEPTH);
		165	else
		166	tmp \|= (FMT_TRUNCATE_EN \| FMT_TRUNCATE_DEPTH);
		167	break;
		168	case 10:
		169	default:
		170	/* not needed */
		171	break;
		172	}
		173
		174	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
		175	}
		176
127	/* get temperature in millidegrees */	177	/* get temperature in millidegrees */
128	int rv6xx_get_temp(struct radeon_device *rdev)	178	int rv6xx_get_temp(struct radeon_device *rdev)
129	{	179	{


diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index e673fe26ea84..8e01b126aaeb 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1199,6 +1199,34 @@
1199	# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)	1199	# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
1200	# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)	1200	# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
1201		1201
		1202	/* DCE3 FMT blocks */
		1203	#define FMT_CONTROL 0x6700
		1204	# define FMT_PIXEL_ENCODING (1 << 16)
		1205	/* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
		1206	#define FMT_BIT_DEPTH_CONTROL 0x6710
		1207	# define FMT_TRUNCATE_EN (1 << 0)
		1208	# define FMT_TRUNCATE_DEPTH (1 << 4)
		1209	# define FMT_SPATIAL_DITHER_EN (1 << 8)
		1210	# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
		1211	# define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
		1212	# define FMT_FRAME_RANDOM_ENABLE (1 << 13)
		1213	# define FMT_RGB_RANDOM_ENABLE (1 << 14)
		1214	# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
		1215	# define FMT_TEMPORAL_DITHER_EN (1 << 16)
		1216	# define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
		1217	# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
		1218	# define FMT_TEMPORAL_LEVEL (1 << 24)
		1219	# define FMT_TEMPORAL_DITHER_RESET (1 << 25)
		1220	# define FMT_25FRC_SEL(x) ((x) << 26)
		1221	# define FMT_50FRC_SEL(x) ((x) << 28)
		1222	# define FMT_75FRC_SEL(x) ((x) << 30)
		1223	#define FMT_CLAMP_CONTROL 0x672c
		1224	# define FMT_CLAMP_DATA_EN (1 << 0)
		1225	# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
		1226	# define FMT_CLAMP_6BPC 0
		1227	# define FMT_CLAMP_8BPC 1
		1228	# define FMT_CLAMP_10BPC 2
		1229
1202	/* Power management */	1230	/* Power management */
1203	#define CG_SPLL_FUNC_CNTL 0x600	1231	#define CG_SPLL_FUNC_CNTL 0x600
1204	# define SPLL_RESET (1 << 0)	1232	# define SPLL_RESET (1 << 0)


diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index ef63d3f00b2f..03f74b0276c5 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -850,6 +850,12 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
850	struct drm_display_mode *mode,	850	struct drm_display_mode *mode,
851	struct drm_display_mode *adjusted_mode);	851	struct drm_display_mode *adjusted_mode);
852		852
		853	/* fmt blocks */
		854	void avivo_program_fmt(struct drm_encoder *encoder);
		855	void dce3_program_fmt(struct drm_encoder *encoder);
		856	void dce4_program_fmt(struct drm_encoder *encoder);
		857	void dce8_program_fmt(struct drm_encoder *encoder);
		858
853	/* fbdev layer */	859	/* fbdev layer */
854	int radeon_fbdev_init(struct radeon_device *rdev);	860	int radeon_fbdev_init(struct radeon_device *rdev);
855	void radeon_fbdev_fini(struct radeon_device *rdev);	861	void radeon_fbdev_fini(struct radeon_device *rdev);


diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 6acba8017b9a..df01aa398cc5 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c
@@ -153,6 +153,67 @@ u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
153	return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;	153	return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
154	}	154	}
155		155
		156	void avivo_program_fmt(struct drm_encoder *encoder)
		157	{
		158	struct drm_device *dev = encoder->dev;
		159	struct radeon_device *rdev = dev->dev_private;
		160	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		161	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		162	int bpc = 0;
		163	u32 tmp = 0;
		164	bool dither = false;
		165
		166	if (connector)
		167	bpc = radeon_get_monitor_bpc(connector);
		168
		169	/* LVDS FMT is set up by atom */
		170	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
		171	return;
		172
		173	if (bpc == 0)
		174	return;
		175
		176	switch (bpc) {
		177	case 6:
		178	if (dither)
		179	/* XXX sort out optimal dither settings */
		180	tmp \|= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
		181	else
		182	tmp \|= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
		183	break;
		184	case 8:
		185	if (dither)
		186	/* XXX sort out optimal dither settings */
		187	tmp \|= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN \|
		188	AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
		189	else
		190	tmp \|= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN \|
		191	AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
		192	break;
		193	case 10:
		194	default:
		195	/* not needed */
		196	break;
		197	}
		198
		199	switch (radeon_encoder->encoder_id) {
		200	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		201	WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
		202	break;
		203	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		204	WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
		205	break;
		206	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		207	WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
		208	break;
		209	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		210	WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
		211	break;
		212	default:
		213	break;
		214	}
		215	}
		216
156	void rs600_pm_misc(struct radeon_device *rdev)	217	void rs600_pm_misc(struct radeon_device *rdev)
157	{	218	{
158	int requested_index = rdev->pm.requested_power_state_index;	219	int requested_index = rdev->pm.requested_power_state_index;