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authorLinus Walleij <linus.walleij@linaro.org>2011-08-12 04:29:10 -0400
committerSamuel Ortiz <sameo@linux.intel.com>2011-10-24 08:09:19 -0400
commit10b3ecdbd4a54d682903daff99fa6066e6cb68c2 (patch)
tree2493e03a95e5c04b21a0ec6190ed5ce9dfc4431e /drivers
parent624e87c25133b30a748ddb97068b92ac07d9d524 (diff)
mfd: Fix db5500-prcmu defines
This fixes two erroneous defines for the PLLs and adds new defines for the reset pin controls. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mfd/db5500-prcmu.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c
index dc215878835a..bb115b2f04e9 100644
--- a/drivers/mfd/db5500-prcmu.c
+++ b/drivers/mfd/db5500-prcmu.c
@@ -109,15 +109,18 @@ enum mb5_header {
109#define PRCMU_DSI_CLOCK_SETTING 0x00000128 109#define PRCMU_DSI_CLOCK_SETTING 0x00000128
110/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */ 110/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
111#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135 111#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135
112#define PRCMU_PLLDSI_FREQ_SETTING 0x0004013C 112#define PRCMU_PLLDSI_FREQ_SETTING 0x00020121
113#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002 113#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002
114#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000101 114#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000201
115#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101 115#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101
116 116
117#define PRCMU_ENABLE_PLLDSI 0x00000001 117#define PRCMU_ENABLE_PLLDSI 0x00000001
118#define PRCMU_DISABLE_PLLDSI 0x00000000 118#define PRCMU_DISABLE_PLLDSI 0x00000000
119 119
120#define PRCMU_DSI_RESET_SW 0x00000003 120#define PRCMU_DSI_RESET_SW 0x00000003
121#define PRCMU_RESOUTN0_PIN 0x00000001
122#define PRCMU_RESOUTN1_PIN 0x00000002
123#define PRCMU_RESOUTN2_PIN 0x00000004
121 124
122#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 125#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
123 126