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authorKe Wei <kewei.mv@gmail.com>2008-02-27 07:50:25 -0500
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2008-02-29 12:03:20 -0500
commit00da714b31b944400ee789e477f58247cff30b1b (patch)
tree67fb128c50d064e23be35eb221cc8e03bc03a044 /drivers
parentee54cc6af95a7fa09da298493b853a9e64fa8abd (diff)
[SCSI] mvsas: fix phy sas address
The phy sas address is showing wrongly (wrong endianness). Fix up the endian transforms to make this correct. Signed-off-by: Ke Wei <kewei@marvell.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers')
-rwxr-xr-x[-rw-r--r--]drivers/scsi/mvsas.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/scsi/mvsas.c b/drivers/scsi/mvsas.c
index d4a6ac3c9c47..5ec0665b3a3d 100644..100755
--- a/drivers/scsi/mvsas.c
+++ b/drivers/scsi/mvsas.c
@@ -40,7 +40,7 @@
40#include <asm/io.h> 40#include <asm/io.h>
41 41
42#define DRV_NAME "mvsas" 42#define DRV_NAME "mvsas"
43#define DRV_VERSION "0.5" 43#define DRV_VERSION "0.5.1"
44#define _MV_DUMP 0 44#define _MV_DUMP 0
45#define MVS_DISABLE_NVRAM 45#define MVS_DISABLE_NVRAM
46#define MVS_DISABLE_MSI 46#define MVS_DISABLE_MSI
@@ -1005,7 +1005,7 @@ err_out:
1005 return rc; 1005 return rc;
1006#else 1006#else
1007 /* FIXME , For SAS target mode */ 1007 /* FIXME , For SAS target mode */
1008 memcpy(buf, "\x00\x00\xab\x11\x30\x04\x05\x50", 8); 1008 memcpy(buf, "\x50\x05\x04\x30\x11\xab\x00\x00", 8);
1009 return 0; 1009 return 0;
1010#endif 1010#endif
1011} 1011}
@@ -1330,7 +1330,7 @@ static int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
1330 1330
1331 mvs_hba_cq_dump(mvi); 1331 mvs_hba_cq_dump(mvi);
1332 1332
1333 if (unlikely(rx_desc & RXQ_DONE)) 1333 if (likely(rx_desc & RXQ_DONE))
1334 mvs_slot_complete(mvi, rx_desc); 1334 mvs_slot_complete(mvi, rx_desc);
1335 if (rx_desc & RXQ_ATTN) { 1335 if (rx_desc & RXQ_ATTN) {
1336 attn = true; 1336 attn = true;
@@ -2720,9 +2720,8 @@ static int __devinit mvs_hw_init(struct mvs_info *mvi)
2720 msleep(100); 2720 msleep(100);
2721 /* init and reset phys */ 2721 /* init and reset phys */
2722 for (i = 0; i < mvi->chip->n_phy; i++) { 2722 for (i = 0; i < mvi->chip->n_phy; i++) {
2723 /* FIXME: is this the correct dword order? */ 2723 u32 lo = be32_to_cpu(*(u32 *)&mvi->sas_addr[4]);
2724 u32 lo = *((u32 *)&mvi->sas_addr[0]); 2724 u32 hi = be32_to_cpu(*(u32 *)&mvi->sas_addr[0]);
2725 u32 hi = *((u32 *)&mvi->sas_addr[4]);
2726 2725
2727 mvs_detect_porttype(mvi, i); 2726 mvs_detect_porttype(mvi, i);
2728 2727