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authorChuanxiao.Dong <chuanxiao.dong@intel.com>2010-08-06 06:48:21 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-08-06 11:30:00 -0400
commit66406524e50e32fde0dc01859ad3608ddefe107f (patch)
tree9ffc02c8565c925d23e84a4d7c0c5e4caf1ebaf8 /drivers
parent0af18d27c36f28a8807297f21fa22979acd977f3 (diff)
mtd: denali: Remove device_info_tag structure
Hi David, I sent 4 patches using my intel email account. If there is any problem about the format of these patches, I will resend them after I arrived at home by using my gmail account, and I will keep on using gmail account to send patches. Thanks. >From 242e3bf5e17f54b1df8cf285154a7c7a61ff62e9 Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong <chuanxiao.dong@intel.com> Date: Fri, 6 Aug 2010 15:29:41 +0800 Subject: [PATCH 1/4] mtd: denali: Remove device_info_tag structure. Most of the variables in this structure are useless, so just remove this structure and relevant codes. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mtd/nand/denali.c299
-rw-r--r--drivers/mtd/nand/denali.h43
2 files changed, 37 insertions, 305 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index c41d2780eaee..14b227c8c29e 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -364,43 +364,12 @@ static void set_ecc_config(struct denali_nand_info *denali)
364 denali_write32(8, denali->flash_reg + ECC_CORRECTION); 364 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
365#endif 365#endif
366 366
367 if ((ioread32(denali->flash_reg + ECC_CORRECTION) &
368 ECC_CORRECTION__VALUE) == 1) {
369 denali->dev_info.wECCBytesPerSector = 4;
370 denali->dev_info.wECCBytesPerSector *=
371 denali->dev_info.wDevicesConnected;
372 denali->dev_info.wNumPageSpareFlag =
373 denali->dev_info.wPageSpareSize -
374 denali->dev_info.wPageDataSize /
375 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
376 denali->dev_info.wECCBytesPerSector
377 - denali->dev_info.wSpareSkipBytes;
378 } else {
379 denali->dev_info.wECCBytesPerSector =
380 (ioread32(denali->flash_reg + ECC_CORRECTION) &
381 ECC_CORRECTION__VALUE) * 13 / 8;
382 if ((denali->dev_info.wECCBytesPerSector) % 2 == 0)
383 denali->dev_info.wECCBytesPerSector += 2;
384 else
385 denali->dev_info.wECCBytesPerSector += 1;
386
387 denali->dev_info.wECCBytesPerSector *=
388 denali->dev_info.wDevicesConnected;
389 denali->dev_info.wNumPageSpareFlag =
390 denali->dev_info.wPageSpareSize -
391 denali->dev_info.wPageDataSize /
392 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
393 denali->dev_info.wECCBytesPerSector
394 - denali->dev_info.wSpareSkipBytes;
395 }
396} 367}
397 368
398/* queries the NAND device to see what ONFI modes it supports. */ 369/* queries the NAND device to see what ONFI modes it supports. */
399static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) 370static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
400{ 371{
401 int i; 372 int i;
402 uint16_t blks_lun_l, blks_lun_h, n_of_luns;
403 uint32_t blockperlun, id;
404 373
405 denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET); 374 denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET);
406 375
@@ -458,26 +427,6 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
458 denali_write32(INTR_STATUS3__TIME_OUT, 427 denali_write32(INTR_STATUS3__TIME_OUT,
459 denali->flash_reg + INTR_STATUS3); 428 denali->flash_reg + INTR_STATUS3);
460 429
461 denali->dev_info.wONFIDevFeatures =
462 ioread32(denali->flash_reg + ONFI_DEVICE_FEATURES);
463 denali->dev_info.wONFIOptCommands =
464 ioread32(denali->flash_reg + ONFI_OPTIONAL_COMMANDS);
465 denali->dev_info.wONFITimingMode =
466 ioread32(denali->flash_reg + ONFI_TIMING_MODE);
467 denali->dev_info.wONFIPgmCacheTimingMode =
468 ioread32(denali->flash_reg + ONFI_PGM_CACHE_TIMING_MODE);
469
470 n_of_luns = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
471 ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS;
472 blks_lun_l = ioread32(denali->flash_reg +
473 ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L);
474 blks_lun_h = ioread32(denali->flash_reg +
475 ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U);
476
477 blockperlun = (blks_lun_h << 16) | blks_lun_l;
478
479 denali->dev_info.wTotalBlocks = n_of_luns * blockperlun;
480
481 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & 430 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
482 ONFI_TIMING_MODE__VALUE)) 431 ONFI_TIMING_MODE__VALUE))
483 return FAIL; 432 return FAIL;
@@ -490,16 +439,6 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
490 439
491 nand_onfi_timing_set(denali, i); 440 nand_onfi_timing_set(denali, i);
492 441
493 index_addr(denali, MODE_11 | 0, 0x90);
494 index_addr(denali, MODE_11 | 1, 0);
495
496 for (i = 0; i < 3; i++)
497 index_addr_read_data(denali, MODE_11 | 2, &id);
498
499 nand_dbg_print(NAND_DBG_DEBUG, "3rd ID: 0x%x\n", id);
500
501 denali->dev_info.MLCDevice = id & 0x0C;
502
503 /* By now, all the ONFI devices we know support the page cache */ 442 /* By now, all the ONFI devices we know support the page cache */
504 /* rw feature. So here we enable the pipeline_rw_ahead feature */ 443 /* rw feature. So here we enable the pipeline_rw_ahead feature */
505 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ 444 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
@@ -510,9 +449,6 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
510 449
511static void get_samsung_nand_para(struct denali_nand_info *denali) 450static void get_samsung_nand_para(struct denali_nand_info *denali)
512{ 451{
513 uint8_t no_of_planes;
514 uint32_t blk_size;
515 uint64_t plane_size, capacity;
516 uint32_t id_bytes[5]; 452 uint32_t id_bytes[5];
517 int i; 453 int i;
518 454
@@ -537,15 +473,6 @@ static void get_samsung_nand_para(struct denali_nand_info *denali)
537 denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT); 473 denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT);
538 denali_write32(2, denali->flash_reg + CS_SETUP_CNT); 474 denali_write32(2, denali->flash_reg + CS_SETUP_CNT);
539 } 475 }
540
541 no_of_planes = 1 << ((id_bytes[4] & 0x0c) >> 2);
542 plane_size = (uint64_t)64 << ((id_bytes[4] & 0x70) >> 4);
543 blk_size = 64 << ((ioread32(denali->flash_reg + DEVICE_PARAM_1) &
544 0x30) >> 4);
545 capacity = (uint64_t)128 * plane_size * no_of_planes;
546
547 do_div(capacity, blk_size);
548 denali->dev_info.wTotalBlocks = capacity;
549} 476}
550 477
551static void get_toshiba_nand_para(struct denali_nand_info *denali) 478static void get_toshiba_nand_para(struct denali_nand_info *denali)
@@ -594,13 +521,12 @@ static void get_hynix_nand_para(struct denali_nand_info *denali,
594#elif SUPPORT_8BITECC 521#elif SUPPORT_8BITECC
595 denali_write32(8, denali->flash_reg + ECC_CORRECTION); 522 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
596#endif 523#endif
597 denali->dev_info.MLCDevice = 1;
598 break; 524 break;
599 default: 525 default:
600 nand_dbg_print(NAND_DBG_WARN, 526 nand_dbg_print(NAND_DBG_WARN,
601 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." 527 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
602 "Will use default parameter values instead.\n", 528 "Will use default parameter values instead.\n",
603 denali->dev_info.wDeviceID); 529 device_id);
604 } 530 }
605} 531}
606 532
@@ -650,130 +576,31 @@ static void find_valid_banks(struct denali_nand_info *denali)
650 576
651static void detect_partition_feature(struct denali_nand_info *denali) 577static void detect_partition_feature(struct denali_nand_info *denali)
652{ 578{
579 /* For MRST platform, denali->fwblks represent the
580 * number of blocks firmware is taken,
581 * FW is in protect partition and MTD driver has no
582 * permission to access it. So let driver know how many
583 * blocks it can't touch.
584 * */
653 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { 585 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
654 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) & 586 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) &
655 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) { 587 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) {
656 denali->dev_info.wSpectraStartBlock = 588 denali->fwblks =
657 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & 589 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
658 MIN_MAX_BANK_1__MIN_VALUE) * 590 MIN_MAX_BANK_1__MIN_VALUE) *
659 denali->dev_info.wTotalBlocks) 591 denali->blksperchip)
660 + 592 +
661 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) & 593 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) &
662 MIN_BLK_ADDR_1__VALUE); 594 MIN_BLK_ADDR_1__VALUE);
663 595 } else
664 denali->dev_info.wSpectraEndBlock = 596 denali->fwblks = SPECTRA_START_BLOCK;
665 (((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & 597 } else
666 MIN_MAX_BANK_1__MAX_VALUE) >> 2) * 598 denali->fwblks = SPECTRA_START_BLOCK;
667 denali->dev_info.wTotalBlocks)
668 +
669 (ioread32(denali->flash_reg + MAX_BLK_ADDR_1) &
670 MAX_BLK_ADDR_1__VALUE);
671
672 denali->dev_info.wTotalBlocks *=
673 denali->total_used_banks;
674
675 if (denali->dev_info.wSpectraEndBlock >=
676 denali->dev_info.wTotalBlocks) {
677 denali->dev_info.wSpectraEndBlock =
678 denali->dev_info.wTotalBlocks - 1;
679 }
680
681 denali->dev_info.wDataBlockNum =
682 denali->dev_info.wSpectraEndBlock -
683 denali->dev_info.wSpectraStartBlock + 1;
684 } else {
685 denali->dev_info.wTotalBlocks *=
686 denali->total_used_banks;
687 denali->dev_info.wSpectraStartBlock =
688 SPECTRA_START_BLOCK;
689 denali->dev_info.wSpectraEndBlock =
690 denali->dev_info.wTotalBlocks - 1;
691 denali->dev_info.wDataBlockNum =
692 denali->dev_info.wSpectraEndBlock -
693 denali->dev_info.wSpectraStartBlock + 1;
694 }
695 } else {
696 denali->dev_info.wTotalBlocks *= denali->total_used_banks;
697 denali->dev_info.wSpectraStartBlock = SPECTRA_START_BLOCK;
698 denali->dev_info.wSpectraEndBlock =
699 denali->dev_info.wTotalBlocks - 1;
700 denali->dev_info.wDataBlockNum =
701 denali->dev_info.wSpectraEndBlock -
702 denali->dev_info.wSpectraStartBlock + 1;
703 }
704}
705
706static void dump_device_info(struct denali_nand_info *denali)
707{
708 nand_dbg_print(NAND_DBG_DEBUG, "denali->dev_info:\n");
709 nand_dbg_print(NAND_DBG_DEBUG, "DeviceMaker: 0x%x\n",
710 denali->dev_info.wDeviceMaker);
711 nand_dbg_print(NAND_DBG_DEBUG, "DeviceID: 0x%x\n",
712 denali->dev_info.wDeviceID);
713 nand_dbg_print(NAND_DBG_DEBUG, "DeviceType: 0x%x\n",
714 denali->dev_info.wDeviceType);
715 nand_dbg_print(NAND_DBG_DEBUG, "SpectraStartBlock: %d\n",
716 denali->dev_info.wSpectraStartBlock);
717 nand_dbg_print(NAND_DBG_DEBUG, "SpectraEndBlock: %d\n",
718 denali->dev_info.wSpectraEndBlock);
719 nand_dbg_print(NAND_DBG_DEBUG, "TotalBlocks: %d\n",
720 denali->dev_info.wTotalBlocks);
721 nand_dbg_print(NAND_DBG_DEBUG, "PagesPerBlock: %d\n",
722 denali->dev_info.wPagesPerBlock);
723 nand_dbg_print(NAND_DBG_DEBUG, "PageSize: %d\n",
724 denali->dev_info.wPageSize);
725 nand_dbg_print(NAND_DBG_DEBUG, "PageDataSize: %d\n",
726 denali->dev_info.wPageDataSize);
727 nand_dbg_print(NAND_DBG_DEBUG, "PageSpareSize: %d\n",
728 denali->dev_info.wPageSpareSize);
729 nand_dbg_print(NAND_DBG_DEBUG, "NumPageSpareFlag: %d\n",
730 denali->dev_info.wNumPageSpareFlag);
731 nand_dbg_print(NAND_DBG_DEBUG, "ECCBytesPerSector: %d\n",
732 denali->dev_info.wECCBytesPerSector);
733 nand_dbg_print(NAND_DBG_DEBUG, "BlockSize: %d\n",
734 denali->dev_info.wBlockSize);
735 nand_dbg_print(NAND_DBG_DEBUG, "BlockDataSize: %d\n",
736 denali->dev_info.wBlockDataSize);
737 nand_dbg_print(NAND_DBG_DEBUG, "DataBlockNum: %d\n",
738 denali->dev_info.wDataBlockNum);
739 nand_dbg_print(NAND_DBG_DEBUG, "PlaneNum: %d\n",
740 denali->dev_info.bPlaneNum);
741 nand_dbg_print(NAND_DBG_DEBUG, "DeviceMainAreaSize: %d\n",
742 denali->dev_info.wDeviceMainAreaSize);
743 nand_dbg_print(NAND_DBG_DEBUG, "DeviceSpareAreaSize: %d\n",
744 denali->dev_info.wDeviceSpareAreaSize);
745 nand_dbg_print(NAND_DBG_DEBUG, "DevicesConnected: %d\n",
746 denali->dev_info.wDevicesConnected);
747 nand_dbg_print(NAND_DBG_DEBUG, "DeviceWidth: %d\n",
748 denali->dev_info.wDeviceWidth);
749 nand_dbg_print(NAND_DBG_DEBUG, "HWRevision: 0x%x\n",
750 denali->dev_info.wHWRevision);
751 nand_dbg_print(NAND_DBG_DEBUG, "HWFeatures: 0x%x\n",
752 denali->dev_info.wHWFeatures);
753 nand_dbg_print(NAND_DBG_DEBUG, "ONFIDevFeatures: 0x%x\n",
754 denali->dev_info.wONFIDevFeatures);
755 nand_dbg_print(NAND_DBG_DEBUG, "ONFIOptCommands: 0x%x\n",
756 denali->dev_info.wONFIOptCommands);
757 nand_dbg_print(NAND_DBG_DEBUG, "ONFITimingMode: 0x%x\n",
758 denali->dev_info.wONFITimingMode);
759 nand_dbg_print(NAND_DBG_DEBUG, "ONFIPgmCacheTimingMode: 0x%x\n",
760 denali->dev_info.wONFIPgmCacheTimingMode);
761 nand_dbg_print(NAND_DBG_DEBUG, "MLCDevice: %s\n",
762 denali->dev_info.MLCDevice ? "Yes" : "No");
763 nand_dbg_print(NAND_DBG_DEBUG, "SpareSkipBytes: %d\n",
764 denali->dev_info.wSpareSkipBytes);
765 nand_dbg_print(NAND_DBG_DEBUG, "BitsInPageNumber: %d\n",
766 denali->dev_info.nBitsInPageNumber);
767 nand_dbg_print(NAND_DBG_DEBUG, "BitsInPageDataSize: %d\n",
768 denali->dev_info.nBitsInPageDataSize);
769 nand_dbg_print(NAND_DBG_DEBUG, "BitsInBlockDataSize: %d\n",
770 denali->dev_info.nBitsInBlockDataSize);
771} 599}
772 600
773static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) 601static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
774{ 602{
775 uint16_t status = PASS; 603 uint16_t status = PASS;
776 uint8_t no_of_planes;
777 uint32_t id_bytes[5], addr; 604 uint32_t id_bytes[5], addr;
778 uint8_t i, maf_id, device_id; 605 uint8_t i, maf_id, device_id;
779 606
@@ -803,8 +630,6 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
803 get_toshiba_nand_para(denali); 630 get_toshiba_nand_para(denali);
804 } else if (maf_id == 0xAD) { /* Hynix NAND */ 631 } else if (maf_id == 0xAD) { /* Hynix NAND */
805 get_hynix_nand_para(denali, device_id); 632 get_hynix_nand_para(denali, device_id);
806 } else {
807 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
808 } 633 }
809 634
810 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" 635 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
@@ -819,79 +644,12 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
819 ioread32(denali->flash_reg + RDWR_EN_HI_CNT), 644 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
820 ioread32(denali->flash_reg + CS_SETUP_CNT)); 645 ioread32(denali->flash_reg + CS_SETUP_CNT));
821 646
822 denali->dev_info.wHWRevision = ioread32(denali->flash_reg + REVISION);
823 denali->dev_info.wHWFeatures = ioread32(denali->flash_reg + FEATURES);
824
825 denali->dev_info.wDeviceMainAreaSize =
826 ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
827 denali->dev_info.wDeviceSpareAreaSize =
828 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
829
830 denali->dev_info.wPageDataSize =
831 ioread32(denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
832
833 /* Note: When using the Micon 4K NAND device, the controller will report
834 * Page Spare Size as 216 bytes. But Micron's Spec say it's 218 bytes.
835 * And if force set it to 218 bytes, the controller can not work
836 * correctly. So just let it be. But keep in mind that this bug may
837 * cause
838 * other problems in future. - Yunpeng 2008-10-10
839 */
840 denali->dev_info.wPageSpareSize =
841 ioread32(denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
842
843 denali->dev_info.wPagesPerBlock =
844 ioread32(denali->flash_reg + PAGES_PER_BLOCK);
845
846 denali->dev_info.wPageSize =
847 denali->dev_info.wPageDataSize + denali->dev_info.wPageSpareSize;
848 denali->dev_info.wBlockSize =
849 denali->dev_info.wPageSize * denali->dev_info.wPagesPerBlock;
850 denali->dev_info.wBlockDataSize =
851 denali->dev_info.wPagesPerBlock * denali->dev_info.wPageDataSize;
852
853 denali->dev_info.wDeviceWidth =
854 ioread32(denali->flash_reg + DEVICE_WIDTH);
855 denali->dev_info.wDeviceType =
856 ((ioread32(denali->flash_reg + DEVICE_WIDTH) > 0) ? 16 : 8);
857
858 denali->dev_info.wDevicesConnected =
859 ioread32(denali->flash_reg + DEVICES_CONNECTED);
860
861 denali->dev_info.wSpareSkipBytes =
862 ioread32(denali->flash_reg + SPARE_AREA_SKIP_BYTES) *
863 denali->dev_info.wDevicesConnected;
864
865 denali->dev_info.nBitsInPageNumber =
866 ilog2(denali->dev_info.wPagesPerBlock);
867 denali->dev_info.nBitsInPageDataSize =
868 ilog2(denali->dev_info.wPageDataSize);
869 denali->dev_info.nBitsInBlockDataSize =
870 ilog2(denali->dev_info.wBlockDataSize);
871
872 set_ecc_config(denali); 647 set_ecc_config(denali);
873 648
874 no_of_planes = ioread32(denali->flash_reg + NUMBER_OF_PLANES) &
875 NUMBER_OF_PLANES__VALUE;
876
877 switch (no_of_planes) {
878 case 0:
879 case 1:
880 case 3:
881 case 7:
882 denali->dev_info.bPlaneNum = no_of_planes + 1;
883 break;
884 default:
885 status = FAIL;
886 break;
887 }
888
889 find_valid_banks(denali); 649 find_valid_banks(denali);
890 650
891 detect_partition_feature(denali); 651 detect_partition_feature(denali);
892 652
893 dump_device_info(denali);
894
895 /* If the user specified to override the default timings 653 /* If the user specified to override the default timings
896 * with a specific ONFI mode, we apply those changes here. 654 * with a specific ONFI mode, we apply those changes here.
897 */ 655 */
@@ -1963,16 +1721,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1963 1721
1964 denali_nand_timing_set(denali); 1722 denali_nand_timing_set(denali);
1965 1723
1966 /* MTD supported page sizes vary by kernel. We validate our
1967 * kernel supports the device here.
1968 */
1969 if (denali->dev_info.wPageSize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1970 ret = -ENODEV;
1971 printk(KERN_ERR "Spectra: device size not supported by this "
1972 "version of MTD.");
1973 goto failed_nand;
1974 }
1975
1976 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" 1724 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
1977 "acc_clks: %d, re_2_we: %d, we_2_re: %d," 1725 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
1978 "addr_2_data: %d, rdwr_en_lo_cnt: %d, " 1726 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
@@ -2003,6 +1751,16 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2003 goto failed_nand; 1751 goto failed_nand;
2004 } 1752 }
2005 1753
1754 /* MTD supported page sizes vary by kernel. We validate our
1755 * kernel supports the device here.
1756 */
1757 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1758 ret = -ENODEV;
1759 printk(KERN_ERR "Spectra: device size not supported by this "
1760 "version of MTD.");
1761 goto failed_nand;
1762 }
1763
2006 /* second stage of the NAND scan 1764 /* second stage of the NAND scan
2007 * this stage requires information regarding ECC and 1765 * this stage requires information regarding ECC and
2008 * bad block management. */ 1766 * bad block management. */
@@ -2015,7 +1773,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2015 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN; 1773 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
2016 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 1774 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
2017 1775
2018 if (denali->dev_info.MLCDevice) { 1776 if (denali->nand.cellinfo & 0xc) {
2019 denali->nand.ecc.layout = &nand_oob_mlc_14bit; 1777 denali->nand.ecc.layout = &nand_oob_mlc_14bit;
2020 denali->nand.ecc.bytes = ECC_BYTES_MLC; 1778 denali->nand.ecc.bytes = ECC_BYTES_MLC;
2021 } else {/* SLC */ 1779 } else {/* SLC */
@@ -2023,6 +1781,15 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2023 denali->nand.ecc.bytes = ECC_BYTES_SLC; 1781 denali->nand.ecc.bytes = ECC_BYTES_SLC;
2024 } 1782 }
2025 1783
1784 /* Let driver know the total blocks number and
1785 * how many blocks contained by each nand chip.
1786 * blksperchip will help driver to know how many
1787 * blocks is taken by FW.
1788 * */
1789 denali->totalblks = denali->mtd.size >>
1790 denali->nand.phys_erase_shift;
1791 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1792
2026 /* These functions are required by the NAND core framework, otherwise, 1793 /* These functions are required by the NAND core framework, otherwise,
2027 * the NAND core will assert. However, we don't need them, so we'll stub 1794 * the NAND core will assert. However, we don't need them, so we'll stub
2028 * them out. */ 1795 * them out. */
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index 626c915294da..fcac24199d12 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -620,44 +620,6 @@
620#define MIN_MAX_BANK_7__MIN_VALUE 0x0003 620#define MIN_MAX_BANK_7__MIN_VALUE 0x0003
621#define MIN_MAX_BANK_7__MAX_VALUE 0x000c 621#define MIN_MAX_BANK_7__MAX_VALUE 0x000c
622 622
623/* flash.h */
624struct device_info_tag {
625 uint16_t wDeviceMaker;
626 uint16_t wDeviceID;
627 uint8_t bDeviceParam0;
628 uint8_t bDeviceParam1;
629 uint8_t bDeviceParam2;
630 uint32_t wDeviceType;
631 uint32_t wSpectraStartBlock;
632 uint32_t wSpectraEndBlock;
633 uint32_t wTotalBlocks;
634 uint16_t wPagesPerBlock;
635 uint16_t wPageSize;
636 uint16_t wPageDataSize;
637 uint16_t wPageSpareSize;
638 uint16_t wNumPageSpareFlag;
639 uint16_t wECCBytesPerSector;
640 uint32_t wBlockSize;
641 uint32_t wBlockDataSize;
642 uint32_t wDataBlockNum;
643 uint8_t bPlaneNum;
644 uint16_t wDeviceMainAreaSize;
645 uint16_t wDeviceSpareAreaSize;
646 uint16_t wDevicesConnected;
647 uint16_t wDeviceWidth;
648 uint16_t wHWRevision;
649 uint16_t wHWFeatures;
650 uint16_t wONFIDevFeatures;
651 uint16_t wONFIOptCommands;
652 uint16_t wONFITimingMode;
653 uint16_t wONFIPgmCacheTimingMode;
654 uint16_t MLCDevice;
655 uint16_t wSpareSkipBytes;
656 uint8_t nBitsInPageNumber;
657 uint8_t nBitsInPageDataSize;
658 uint8_t nBitsInBlockDataSize;
659};
660
661/* ffsdefs.h */ 623/* ffsdefs.h */
662#define CLEAR 0 /*use this to clear a field instead of "fail"*/ 624#define CLEAR 0 /*use this to clear a field instead of "fail"*/
663#define SET 1 /*use this to set a field instead of "pass"*/ 625#define SET 1 /*use this to set a field instead of "pass"*/
@@ -784,7 +746,6 @@ struct nand_buf {
784struct denali_nand_info { 746struct denali_nand_info {
785 struct mtd_info mtd; 747 struct mtd_info mtd;
786 struct nand_chip nand; 748 struct nand_chip nand;
787 struct device_info_tag dev_info;
788 int flash_bank; /* currently selected chip */ 749 int flash_bank; /* currently selected chip */
789 int status; 750 int status;
790 int platform; 751 int platform;
@@ -802,6 +763,10 @@ struct denali_nand_info {
802 uint32_t irq_status; 763 uint32_t irq_status;
803 int irq_debug_array[32]; 764 int irq_debug_array[32];
804 int idx; 765 int idx;
766
767 uint32_t fwblks; /* represent how many blocks FW used */
768 uint32_t totalblks;
769 uint32_t blksperchip;
805}; 770};
806 771
807#endif /*_LLD_NAND_*/ 772#endif /*_LLD_NAND_*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 04:30:37 -0500