diff options
author | Chuanxiao Dong <chuanxiao.dong@intel.com> | 2010-08-06 03:45:19 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2010-08-06 11:30:12 -0400 |
commit | 4c03bbdfed5497c3fed502226af1ef3fe8d23d08 (patch) | |
tree | ac5a977a85498a30cd88ce07aa9eed0ff20708bd /drivers | |
parent | 66406524e50e32fde0dc01859ad3608ddefe107f (diff) |
mtd: denali: Remove unuseful code in get_xx_nand_para functions
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mtd/nand/denali.c | 81 |
1 files changed, 7 insertions, 74 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 14b227c8c29e..a60f3f0186bb 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c | |||
@@ -370,63 +370,9 @@ static void set_ecc_config(struct denali_nand_info *denali) | |||
370 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | 370 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) |
371 | { | 371 | { |
372 | int i; | 372 | int i; |
373 | 373 | /* we needn't to do a reset here because driver has already | |
374 | denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET); | 374 | * reset all the banks before |
375 | 375 | * */ | |
376 | while (!((ioread32(denali->flash_reg + INTR_STATUS0) & | ||
377 | INTR_STATUS0__RST_COMP) | | ||
378 | (ioread32(denali->flash_reg + INTR_STATUS0) & | ||
379 | INTR_STATUS0__TIME_OUT))) | ||
380 | ; | ||
381 | |||
382 | if (ioread32(denali->flash_reg + INTR_STATUS0) & | ||
383 | INTR_STATUS0__RST_COMP) { | ||
384 | denali_write32(DEVICE_RESET__BANK1, | ||
385 | denali->flash_reg + DEVICE_RESET); | ||
386 | while (!((ioread32(denali->flash_reg + INTR_STATUS1) & | ||
387 | INTR_STATUS1__RST_COMP) | | ||
388 | (ioread32(denali->flash_reg + INTR_STATUS1) & | ||
389 | INTR_STATUS1__TIME_OUT))) | ||
390 | ; | ||
391 | |||
392 | if (ioread32(denali->flash_reg + INTR_STATUS1) & | ||
393 | INTR_STATUS1__RST_COMP) { | ||
394 | denali_write32(DEVICE_RESET__BANK2, | ||
395 | denali->flash_reg + DEVICE_RESET); | ||
396 | while (!((ioread32(denali->flash_reg + INTR_STATUS2) & | ||
397 | INTR_STATUS2__RST_COMP) | | ||
398 | (ioread32(denali->flash_reg + INTR_STATUS2) & | ||
399 | INTR_STATUS2__TIME_OUT))) | ||
400 | ; | ||
401 | |||
402 | if (ioread32(denali->flash_reg + INTR_STATUS2) & | ||
403 | INTR_STATUS2__RST_COMP) { | ||
404 | denali_write32(DEVICE_RESET__BANK3, | ||
405 | denali->flash_reg + DEVICE_RESET); | ||
406 | while (!((ioread32(denali->flash_reg + | ||
407 | INTR_STATUS3) & | ||
408 | INTR_STATUS3__RST_COMP) | | ||
409 | (ioread32(denali->flash_reg + | ||
410 | INTR_STATUS3) & | ||
411 | INTR_STATUS3__TIME_OUT))) | ||
412 | ; | ||
413 | } else { | ||
414 | printk(KERN_ERR "Getting a time out for bank 2!\n"); | ||
415 | } | ||
416 | } else { | ||
417 | printk(KERN_ERR "Getting a time out for bank 1!\n"); | ||
418 | } | ||
419 | } | ||
420 | |||
421 | denali_write32(INTR_STATUS0__TIME_OUT, | ||
422 | denali->flash_reg + INTR_STATUS0); | ||
423 | denali_write32(INTR_STATUS1__TIME_OUT, | ||
424 | denali->flash_reg + INTR_STATUS1); | ||
425 | denali_write32(INTR_STATUS2__TIME_OUT, | ||
426 | denali->flash_reg + INTR_STATUS2); | ||
427 | denali_write32(INTR_STATUS3__TIME_OUT, | ||
428 | denali->flash_reg + INTR_STATUS3); | ||
429 | |||
430 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & | 376 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
431 | ONFI_TIMING_MODE__VALUE)) | 377 | ONFI_TIMING_MODE__VALUE)) |
432 | return FAIL; | 378 | return FAIL; |
@@ -447,23 +393,10 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |||
447 | return PASS; | 393 | return PASS; |
448 | } | 394 | } |
449 | 395 | ||
450 | static void get_samsung_nand_para(struct denali_nand_info *denali) | 396 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
397 | uint8_t device_id) | ||
451 | { | 398 | { |
452 | uint32_t id_bytes[5]; | 399 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
453 | int i; | ||
454 | |||
455 | index_addr(denali, (uint32_t)(MODE_11 | 0), 0x90); | ||
456 | index_addr(denali, (uint32_t)(MODE_11 | 1), 0); | ||
457 | for (i = 0; i < 5; i++) | ||
458 | index_addr_read_data(denali, (uint32_t)(MODE_11 | 2), | ||
459 | &id_bytes[i]); | ||
460 | |||
461 | nand_dbg_print(NAND_DBG_DEBUG, | ||
462 | "ID bytes: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", | ||
463 | id_bytes[0], id_bytes[1], id_bytes[2], | ||
464 | id_bytes[3], id_bytes[4]); | ||
465 | |||
466 | if ((id_bytes[1] & 0xff) == 0xd3) { /* Samsung K9WAG08U1A */ | ||
467 | /* Set timing register values according to datasheet */ | 400 | /* Set timing register values according to datasheet */ |
468 | denali_write32(5, denali->flash_reg + ACC_CLKS); | 401 | denali_write32(5, denali->flash_reg + ACC_CLKS); |
469 | denali_write32(20, denali->flash_reg + RE_2_WE); | 402 | denali_write32(20, denali->flash_reg + RE_2_WE); |
@@ -625,7 +558,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
625 | if (FAIL == get_onfi_nand_para(denali)) | 558 | if (FAIL == get_onfi_nand_para(denali)) |
626 | return FAIL; | 559 | return FAIL; |
627 | } else if (maf_id == 0xEC) { /* Samsung NAND */ | 560 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
628 | get_samsung_nand_para(denali); | 561 | get_samsung_nand_para(denali, device_id); |
629 | } else if (maf_id == 0x98) { /* Toshiba NAND */ | 562 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
630 | get_toshiba_nand_para(denali); | 563 | get_toshiba_nand_para(denali); |
631 | } else if (maf_id == 0xAD) { /* Hynix NAND */ | 564 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |