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authorSamuel Ortiz <sameo@openedhand.com>2008-12-07 14:50:25 -0500
committerSamuel Ortiz <samuel@sortiz.org>2009-01-04 06:17:40 -0500
commit6354ab5c63bc986bf539026a1b289cc142f6e87c (patch)
tree8ccdbc8b6540a1a7ea540f7350b1e2ed09feb29b /drivers
parentb73eac7871d002835be17d4602cced2c15c0db4b (diff)
mfd: Fix twl4030-core.c build error
This is a fix for: twl4030-core.c:(.text+0x16a797): undefined reference to `clk_get_rate' twl4030-core.c:(.text+0x16a797): undefined reference to `clk_put' on x86 and x86_64, as the clock API is not defined on those platforms. Signed-off-by: Samuel Ortiz <sameo@openedhand.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mfd/twl4030-core.c19
1 files changed, 13 insertions, 6 deletions
diff --git a/drivers/mfd/twl4030-core.c b/drivers/mfd/twl4030-core.c
index fdfbd313ae09..b59c385cbc12 100644
--- a/drivers/mfd/twl4030-core.c
+++ b/drivers/mfd/twl4030-core.c
@@ -658,12 +658,7 @@ static void __init clocks_init(void)
658 osc = clk_get(NULL, "osc_ck"); 658 osc = clk_get(NULL, "osc_ck");
659 else 659 else
660 osc = clk_get(NULL, "osc_sys_ck"); 660 osc = clk_get(NULL, "osc_sys_ck");
661#else 661
662 /* REVISIT for non-OMAP systems, pass the clock rate from
663 * board init code, using platform_data.
664 */
665 osc = ERR_PTR(-EIO);
666#endif
667 if (IS_ERR(osc)) { 662 if (IS_ERR(osc)) {
668 printk(KERN_WARNING "Skipping twl4030 internal clock init and " 663 printk(KERN_WARNING "Skipping twl4030 internal clock init and "
669 "using bootloader value (unknown osc rate)\n"); 664 "using bootloader value (unknown osc rate)\n");
@@ -673,6 +668,18 @@ static void __init clocks_init(void)
673 rate = clk_get_rate(osc); 668 rate = clk_get_rate(osc);
674 clk_put(osc); 669 clk_put(osc);
675 670
671#else
672 /* REVISIT for non-OMAP systems, pass the clock rate from
673 * board init code, using platform_data.
674 */
675 osc = ERR_PTR(-EIO);
676
677 printk(KERN_WARNING "Skipping twl4030 internal clock init and "
678 "using bootloader value (unknown osc rate)\n");
679
680 return;
681#endif
682
676 switch (rate) { 683 switch (rate) {
677 case 19200000: 684 case 19200000:
678 ctrl = HFCLK_FREQ_19p2_MHZ; 685 ctrl = HFCLK_FREQ_19p2_MHZ;