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authorSujith <Sujith.Manoharan@atheros.com>2009-03-30 05:58:25 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-04-22 16:54:30 -0400
commitd8baa9392666d1c50ef42e9f6fbbb0cf536327b9 (patch)
treea70f7ef031e128defc2bc46dedb3ce1f15432d2a /drivers
parent6ed6a05e5c8061cdcd69a418c90c5f11979ce650 (diff)
ath9k: Cleanup debug messages
Clean debug messages to use appropriate levels, remove useless messages, and trim the number of debug levels. Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath9k/ani.c8
-rw-r--r--drivers/net/wireless/ath9k/beacon.c7
-rw-r--r--drivers/net/wireless/ath9k/debug.h24
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c24
-rw-r--r--drivers/net/wireless/ath9k/hw.c101
-rw-r--r--drivers/net/wireless/ath9k/mac.c63
-rw-r--r--drivers/net/wireless/ath9k/main.c6
-rw-r--r--drivers/net/wireless/ath9k/phy.c4
-rw-r--r--drivers/net/wireless/ath9k/phy.h3
-rw-r--r--drivers/net/wireless/ath9k/recv.c4
10 files changed, 115 insertions, 129 deletions
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
index 6c5e887d50d7..1aeafb511ddd 100644
--- a/drivers/net/wireless/ath9k/ani.c
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -569,8 +569,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
569 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 569 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
570 "phyCnt1 0x%x, resetting " 570 "phyCnt1 0x%x, resetting "
571 "counter value to 0x%x\n", 571 "counter value to 0x%x\n",
572 phyCnt1, 572 phyCnt1, aniState->ofdmPhyErrBase);
573 aniState->ofdmPhyErrBase);
574 REG_WRITE(ah, AR_PHY_ERR_1, 573 REG_WRITE(ah, AR_PHY_ERR_1,
575 aniState->ofdmPhyErrBase); 574 aniState->ofdmPhyErrBase);
576 REG_WRITE(ah, AR_PHY_ERR_MASK_1, 575 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
@@ -580,8 +579,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
580 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 579 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
581 "phyCnt2 0x%x, resetting " 580 "phyCnt2 0x%x, resetting "
582 "counter value to 0x%x\n", 581 "counter value to 0x%x\n",
583 phyCnt2, 582 phyCnt2, aniState->cckPhyErrBase);
584 aniState->cckPhyErrBase);
585 REG_WRITE(ah, AR_PHY_ERR_2, 583 REG_WRITE(ah, AR_PHY_ERR_2,
586 aniState->cckPhyErrBase); 584 aniState->cckPhyErrBase);
587 REG_WRITE(ah, AR_PHY_ERR_MASK_2, 585 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
@@ -667,7 +665,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
667 u32 cc = REG_READ(ah, AR_CCCNT); 665 u32 cc = REG_READ(ah, AR_CCCNT);
668 666
669 if (cycles == 0 || cycles > cc) { 667 if (cycles == 0 || cycles > cc) {
670 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 668 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
671 "cycle counter wrap. ExtBusy = 0\n"); 669 "cycle counter wrap. ExtBusy = 0\n");
672 good = 0; 670 good = 0;
673 } else { 671 } else {
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c
index ec995730632d..5b2752b43be4 100644
--- a/drivers/net/wireless/ath9k/beacon.c
+++ b/drivers/net/wireless/ath9k/beacon.c
@@ -43,7 +43,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
43 43
44 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { 44 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
45 DPRINTF(sc, ATH_DBG_FATAL, 45 DPRINTF(sc, ATH_DBG_FATAL,
46 "unable to update h/w beacon queue parameters\n"); 46 "Unable to update h/w beacon queue parameters\n");
47 return 0; 47 return 0;
48 } else { 48 } else {
49 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); 49 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -132,11 +132,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
132 avp = (void *)vif->drv_priv; 132 avp = (void *)vif->drv_priv;
133 cabq = sc->beacon.cabq; 133 cabq = sc->beacon.cabq;
134 134
135 if (avp->av_bcbuf == NULL) { 135 if (avp->av_bcbuf == NULL)
136 DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n",
137 avp, avp->av_bcbuf);
138 return NULL; 136 return NULL;
139 }
140 137
141 /* Release the old beacon first */ 138 /* Release the old beacon first */
142 139
diff --git a/drivers/net/wireless/ath9k/debug.h b/drivers/net/wireless/ath9k/debug.h
index 7b0e5419d2bc..23298b90b52b 100644
--- a/drivers/net/wireless/ath9k/debug.h
+++ b/drivers/net/wireless/ath9k/debug.h
@@ -19,20 +19,16 @@
19 19
20enum ATH_DEBUG { 20enum ATH_DEBUG {
21 ATH_DBG_RESET = 0x00000001, 21 ATH_DBG_RESET = 0x00000001,
22 ATH_DBG_REG_IO = 0x00000002, 22 ATH_DBG_QUEUE = 0x00000002,
23 ATH_DBG_QUEUE = 0x00000004, 23 ATH_DBG_EEPROM = 0x00000004,
24 ATH_DBG_EEPROM = 0x00000008, 24 ATH_DBG_CALIBRATE = 0x00000008,
25 ATH_DBG_CALIBRATE = 0x00000010, 25 ATH_DBG_INTERRUPT = 0x00000010,
26 ATH_DBG_CHANNEL = 0x00000020, 26 ATH_DBG_REGULATORY = 0x00000020,
27 ATH_DBG_INTERRUPT = 0x00000040, 27 ATH_DBG_ANI = 0x00000040,
28 ATH_DBG_REGULATORY = 0x00000080, 28 ATH_DBG_XMIT = 0x00000080,
29 ATH_DBG_ANI = 0x00000100, 29 ATH_DBG_BEACON = 0x00000100,
30 ATH_DBG_POWER_MGMT = 0x00000200, 30 ATH_DBG_CONFIG = 0x00000200,
31 ATH_DBG_XMIT = 0x00000400, 31 ATH_DBG_FATAL = 0x00000400,
32 ATH_DBG_BEACON = 0x00001000,
33 ATH_DBG_CONFIG = 0x00002000,
34 ATH_DBG_KEYCACHE = 0x00004000,
35 ATH_DBG_FATAL = 0x00008000,
36 ATH_DBG_ANY = 0xffffffff 32 ATH_DBG_ANY = 0xffffffff
37}; 33};
38 34
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index ffc36b0361c7..44fee5ae8925 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -783,11 +783,11 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
783 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 783 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
784 REG_WRITE(ah, regOffset, reg32); 784 REG_WRITE(ah, regOffset, reg32);
785 785
786 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 786 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
787 "PDADC (%d,%4x): %4.4x %8.8x\n", 787 "PDADC (%d,%4x): %4.4x %8.8x\n",
788 i, regChainOffset, regOffset, 788 i, regChainOffset, regOffset,
789 reg32); 789 reg32);
790 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 790 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
791 "PDADC: Chain %d | " 791 "PDADC: Chain %d | "
792 "PDADC %3d Value %3d | " 792 "PDADC %3d Value %3d | "
793 "PDADC %3d Value %3d | " 793 "PDADC %3d Value %3d | "
@@ -910,7 +910,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
910 ah->eep_ops->get_eeprom_rev(ah) <= 2) 910 ah->eep_ops->get_eeprom_rev(ah) <= 2)
911 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 911 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
912 912
913 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 913 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
914 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " 914 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
915 "EXT_ADDITIVE %d\n", 915 "EXT_ADDITIVE %d\n",
916 ctlMode, numCtlModes, isHt40CtlMode, 916 ctlMode, numCtlModes, isHt40CtlMode,
@@ -918,7 +918,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
918 918
919 for (i = 0; (i < AR5416_NUM_CTLS) && 919 for (i = 0; (i < AR5416_NUM_CTLS) &&
920 pEepData->ctlIndex[i]; i++) { 920 pEepData->ctlIndex[i]; i++) {
921 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 921 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
922 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " 922 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
923 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " 923 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
924 "chan %d\n", 924 "chan %d\n",
@@ -941,7 +941,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
941 IS_CHAN_2GHZ(chan), 941 IS_CHAN_2GHZ(chan),
942 AR5416_EEP4K_NUM_BAND_EDGES); 942 AR5416_EEP4K_NUM_BAND_EDGES);
943 943
944 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 944 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
945 " MATCH-EE_IDX %d: ch %d is2 %d " 945 " MATCH-EE_IDX %d: ch %d is2 %d "
946 "2xMinEdge %d chainmask %d chains %d\n", 946 "2xMinEdge %d chainmask %d chains %d\n",
947 i, freq, IS_CHAN_2GHZ(chan), 947 i, freq, IS_CHAN_2GHZ(chan),
@@ -961,7 +961,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
961 961
962 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 962 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
963 963
964 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 964 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
965 " SEL-Min ctlMode %d pCtlMode %d " 965 " SEL-Min ctlMode %d pCtlMode %d "
966 "2xMaxEdge %d sP %d minCtlPwr %d\n", 966 "2xMaxEdge %d sP %d minCtlPwr %d\n",
967 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, 967 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
@@ -2234,11 +2234,11 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2234 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 2234 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
2235 REG_WRITE(ah, regOffset, reg32); 2235 REG_WRITE(ah, regOffset, reg32);
2236 2236
2237 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 2237 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2238 "PDADC (%d,%4x): %4.4x %8.8x\n", 2238 "PDADC (%d,%4x): %4.4x %8.8x\n",
2239 i, regChainOffset, regOffset, 2239 i, regChainOffset, regOffset,
2240 reg32); 2240 reg32);
2241 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 2241 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2242 "PDADC: Chain %d | PDADC %3d " 2242 "PDADC: Chain %d | PDADC %3d "
2243 "Value %3d | PDADC %3d Value %3d | " 2243 "Value %3d | PDADC %3d Value %3d | "
2244 "PDADC %3d Value %3d | PDADC %3d " 2244 "PDADC %3d Value %3d | PDADC %3d "
@@ -2415,14 +2415,14 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2415 ah->eep_ops->get_eeprom_rev(ah) <= 2) 2415 ah->eep_ops->get_eeprom_rev(ah) <= 2)
2416 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 2416 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2417 2417
2418 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2418 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2419 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " 2419 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2420 "EXT_ADDITIVE %d\n", 2420 "EXT_ADDITIVE %d\n",
2421 ctlMode, numCtlModes, isHt40CtlMode, 2421 ctlMode, numCtlModes, isHt40CtlMode,
2422 (pCtlMode[ctlMode] & EXT_ADDITIVE)); 2422 (pCtlMode[ctlMode] & EXT_ADDITIVE));
2423 2423
2424 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 2424 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2425 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2425 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2426 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " 2426 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2427 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " 2427 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2428 "chan %d\n", 2428 "chan %d\n",
@@ -2441,7 +2441,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2441 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], 2441 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2442 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); 2442 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2443 2443
2444 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2444 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2445 " MATCH-EE_IDX %d: ch %d is2 %d " 2445 " MATCH-EE_IDX %d: ch %d is2 %d "
2446 "2xMinEdge %d chainmask %d chains %d\n", 2446 "2xMinEdge %d chainmask %d chains %d\n",
2447 i, freq, IS_CHAN_2GHZ(chan), 2447 i, freq, IS_CHAN_2GHZ(chan),
@@ -2460,7 +2460,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2460 2460
2461 minCtlPower = min(twiceMaxEdgePower, scaledPower); 2461 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2462 2462
2463 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2463 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2464 " SEL-Min ctlMode %d pCtlMode %d " 2464 " SEL-Min ctlMode %d pCtlMode %d "
2465 "2xMaxEdge %d sP %d minCtlPwr %d\n", 2465 "2xMaxEdge %d sP %d minCtlPwr %d\n",
2466 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, 2466 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 22ef93f3d47c..169d8efa69dc 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -97,7 +97,7 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
97 udelay(AH_TIME_QUANTUM); 97 udelay(AH_TIME_QUANTUM);
98 } 98 }
99 99
100 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 100 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val); 102 timeout, reg, REG_READ(ah, reg), mask, val);
103 103
@@ -181,7 +181,7 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
181 } 181 }
182 break; 182 break;
183 default: 183 default:
184 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 184 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
185 "Unknown phy %u (rate ix %u)\n", 185 "Unknown phy %u (rate ix %u)\n",
186 rates->info[rateix].phy, rateix); 186 rates->info[rateix].phy, rateix);
187 txTime = 0; 187 txTime = 0;
@@ -306,7 +306,7 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
306 REG_WRITE(ah, addr, wrData); 306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr); 307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) { 308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 309 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
310 "address test failed " 310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr, wrData, rdData); 312 addr, wrData, rdData);
@@ -318,7 +318,7 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
318 REG_WRITE(ah, addr, wrData); 318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr); 319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) { 320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 321 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
322 "address test failed " 322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr, wrData, rdData); 324 addr, wrData, rdData);
@@ -453,8 +453,8 @@ static int ath9k_hw_rfattach(struct ath_hw *ah)
453 453
454 rfStatus = ath9k_hw_init_rf(ah, &ecode); 454 rfStatus = ath9k_hw_init_rf(ah, &ecode);
455 if (!rfStatus) { 455 if (!rfStatus) {
456 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 456 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
457 "RF setup failed, status %u\n", ecode); 457 "RF setup failed, status: %u\n", ecode);
458 return ecode; 458 return ecode;
459 } 459 }
460 460
@@ -478,10 +478,9 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
478 case AR_RAD2122_SREV_MAJOR: 478 case AR_RAD2122_SREV_MAJOR:
479 break; 479 break;
480 default: 480 default:
481 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 481 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
482 "5G Radio Chip Rev 0x%02X is not " 482 "Radio Chip Rev 0x%02X not supported\n",
483 "supported by this driver\n", 483 val & AR_RADIO_SREV_MAJOR);
484 ah->hw_version.analog5GhzRev);
485 return -EOPNOTSUPP; 484 return -EOPNOTSUPP;
486 } 485 }
487 486
@@ -503,12 +502,8 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
503 ah->macaddr[2 * i] = eeval >> 8; 502 ah->macaddr[2 * i] = eeval >> 8;
504 ah->macaddr[2 * i + 1] = eeval & 0xff; 503 ah->macaddr[2 * i + 1] = eeval & 0xff;
505 } 504 }
506 if (sum == 0 || sum == 0xffff * 3) { 505 if (sum == 0 || sum == 0xffff * 3)
507 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
508 "mac address read failed: %pM\n",
509 ah->macaddr);
510 return -EADDRNOTAVAIL; 506 return -EADDRNOTAVAIL;
511 }
512 507
513 return 0; 508 return 0;
514} 509}
@@ -565,11 +560,8 @@ static int ath9k_hw_post_attach(struct ath_hw *ah)
565{ 560{
566 int ecode; 561 int ecode;
567 562
568 if (!ath9k_hw_chip_test(ah)) { 563 if (!ath9k_hw_chip_test(ah))
569 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
570 "hardware self-test failed\n");
571 return -ENODEV; 564 return -ENODEV;
572 }
573 565
574 ecode = ath9k_hw_rf_claim(ah); 566 ecode = ath9k_hw_rf_claim(ah);
575 if (ecode != 0) 567 if (ecode != 0)
@@ -611,13 +603,13 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
611 ah->intr_mitigation = true; 603 ah->intr_mitigation = true;
612 604
613 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
614 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); 606 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
615 ecode = -EIO; 607 ecode = -EIO;
616 goto bad; 608 goto bad;
617 } 609 }
618 610
619 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 611 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
620 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); 612 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
621 ecode = -EIO; 613 ecode = -EIO;
622 goto bad; 614 goto bad;
623 } 615 }
@@ -640,7 +632,7 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
640 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && 632 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
641 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && 633 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
642 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { 634 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
643 DPRINTF(sc, ATH_DBG_RESET, 635 DPRINTF(sc, ATH_DBG_FATAL,
644 "Mac Chip Rev 0x%02x.%x is not supported by " 636 "Mac Chip Rev 0x%02x.%x is not supported by "
645 "this driver\n", ah->hw_version.macVersion, 637 "this driver\n", ah->hw_version.macVersion,
646 ah->hw_version.macRev); 638 ah->hw_version.macRev);
@@ -680,10 +672,6 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
680 if (AR_SREV_9280_10_OR_LATER(ah)) 672 if (AR_SREV_9280_10_OR_LATER(ah))
681 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 673 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
682 674
683 DPRINTF(sc, ATH_DBG_RESET,
684 "This Mac Chip Rev 0x%02x.%x is \n",
685 ah->hw_version.macVersion, ah->hw_version.macRev);
686
687 if (AR_SREV_9285_12_OR_LATER(ah)) { 675 if (AR_SREV_9285_12_OR_LATER(ah)) {
688 676
689 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 677 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
@@ -875,8 +863,8 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
875 863
876 ecode = ath9k_hw_init_macaddr(ah); 864 ecode = ath9k_hw_init_macaddr(ah);
877 if (ecode != 0) { 865 if (ecode != 0) {
878 DPRINTF(sc, ATH_DBG_RESET, 866 DPRINTF(sc, ATH_DBG_FATAL,
879 "failed initializing mac address\n"); 867 "Failed to initialize MAC address\n");
880 goto bad; 868 goto bad;
881 } 869 }
882 870
@@ -1193,23 +1181,23 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1193 switch (ah->hw_version.devid) { 1181 switch (ah->hw_version.devid) {
1194 case AR9280_DEVID_PCI: 1182 case AR9280_DEVID_PCI:
1195 if (reg == 0x7894) { 1183 if (reg == 0x7894) {
1196 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1184 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1197 "ini VAL: %x EEPROM: %x\n", value, 1185 "ini VAL: %x EEPROM: %x\n", value,
1198 (pBase->version & 0xff)); 1186 (pBase->version & 0xff));
1199 1187
1200 if ((pBase->version & 0xff) > 0x0a) { 1188 if ((pBase->version & 0xff) > 0x0a) {
1201 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1189 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1202 "PWDCLKIND: %d\n", 1190 "PWDCLKIND: %d\n",
1203 pBase->pwdclkind); 1191 pBase->pwdclkind);
1204 value &= ~AR_AN_TOP2_PWDCLKIND; 1192 value &= ~AR_AN_TOP2_PWDCLKIND;
1205 value |= AR_AN_TOP2_PWDCLKIND & 1193 value |= AR_AN_TOP2_PWDCLKIND &
1206 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1194 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1207 } else { 1195 } else {
1208 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1196 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1209 "PWDCLKIND Earlier Rev\n"); 1197 "PWDCLKIND Earlier Rev\n");
1210 } 1198 }
1211 1199
1212 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1200 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1213 "final ini VAL: %x\n", value); 1201 "final ini VAL: %x\n", value);
1214 } 1202 }
1215 break; 1203 break;
@@ -1356,13 +1344,13 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1356 min((u32) MAX_RATE_POWER, 1344 min((u32) MAX_RATE_POWER,
1357 (u32) ah->regulatory.power_limit)); 1345 (u32) ah->regulatory.power_limit));
1358 if (status != 0) { 1346 if (status != 0) {
1359 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1347 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1360 "error init'ing transmit power\n"); 1348 "Error initializing transmit power\n");
1361 return -EIO; 1349 return -EIO;
1362 } 1350 }
1363 1351
1364 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1352 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1365 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 1353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1366 "ar5416SetRfRegs failed\n"); 1354 "ar5416SetRfRegs failed\n");
1367 return -EIO; 1355 return -EIO;
1368 } 1356 }
@@ -1668,7 +1656,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1668 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1656 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1669 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1657 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1670 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1658 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1671 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 1659 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1672 "Could not kill baseband RX\n"); 1660 "Could not kill baseband RX\n");
1673 return false; 1661 return false;
1674 } 1662 }
@@ -1677,14 +1665,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1677 1665
1678 if (AR_SREV_9280_10_OR_LATER(ah)) { 1666 if (AR_SREV_9280_10_OR_LATER(ah)) {
1679 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 1667 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1680 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1668 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1681 "failed to set channel\n"); 1669 "Failed to set channel\n");
1682 return false; 1670 return false;
1683 } 1671 }
1684 } else { 1672 } else {
1685 if (!(ath9k_hw_set_channel(ah, chan))) { 1673 if (!(ath9k_hw_set_channel(ah, chan))) {
1686 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1674 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1687 "failed to set channel\n"); 1675 "Failed to set channel\n");
1688 return false; 1676 return false;
1689 } 1677 }
1690 } 1678 }
@@ -1696,7 +1684,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1696 min((u32) MAX_RATE_POWER, 1684 min((u32) MAX_RATE_POWER,
1697 (u32) ah->regulatory.power_limit)) != 0) { 1685 (u32) ah->regulatory.power_limit)) != 0) {
1698 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1686 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1699 "error init'ing transmit power\n"); 1687 "Error initializing transmit power\n");
1700 return false; 1688 return false;
1701 } 1689 }
1702 1690
@@ -2224,7 +2212,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2224 ath9k_hw_mark_phy_inactive(ah); 2212 ath9k_hw_mark_phy_inactive(ah);
2225 2213
2226 if (!ath9k_hw_chip_reset(ah, chan)) { 2214 if (!ath9k_hw_chip_reset(ah, chan)) {
2227 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n"); 2215 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2228 return -EINVAL; 2216 return -EINVAL;
2229 } 2217 }
2230 2218
@@ -2367,8 +2355,8 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2367 u32 keyType; 2355 u32 keyType;
2368 2356
2369 if (entry >= ah->caps.keycache_size) { 2357 if (entry >= ah->caps.keycache_size) {
2370 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2358 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2371 "entry %u out of range\n", entry); 2359 "keychache entry %u out of range\n", entry);
2372 return false; 2360 return false;
2373 } 2361 }
2374 2362
@@ -2404,8 +2392,8 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2404 u32 macHi, macLo; 2392 u32 macHi, macLo;
2405 2393
2406 if (entry >= ah->caps.keycache_size) { 2394 if (entry >= ah->caps.keycache_size) {
2407 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2395 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2408 "entry %u out of range\n", entry); 2396 "keychache entry %u out of range\n", entry);
2409 return false; 2397 return false;
2410 } 2398 }
2411 2399
@@ -2436,8 +2424,8 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2436 u32 keyType; 2424 u32 keyType;
2437 2425
2438 if (entry >= pCap->keycache_size) { 2426 if (entry >= pCap->keycache_size) {
2439 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2427 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2440 "entry %u out of range\n", entry); 2428 "keycache entry %u out of range\n", entry);
2441 return false; 2429 return false;
2442 } 2430 }
2443 2431
@@ -2447,7 +2435,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2447 break; 2435 break;
2448 case ATH9K_CIPHER_AES_CCM: 2436 case ATH9K_CIPHER_AES_CCM:
2449 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2437 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2450 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2438 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2451 "AES-CCM not supported by mac rev 0x%x\n", 2439 "AES-CCM not supported by mac rev 0x%x\n",
2452 ah->hw_version.macRev); 2440 ah->hw_version.macRev);
2453 return false; 2441 return false;
@@ -2458,14 +2446,14 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2458 keyType = AR_KEYTABLE_TYPE_TKIP; 2446 keyType = AR_KEYTABLE_TYPE_TKIP;
2459 if (ATH9K_IS_MIC_ENABLED(ah) 2447 if (ATH9K_IS_MIC_ENABLED(ah)
2460 && entry + 64 >= pCap->keycache_size) { 2448 && entry + 64 >= pCap->keycache_size) {
2461 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2449 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2462 "entry %u inappropriate for TKIP\n", entry); 2450 "entry %u inappropriate for TKIP\n", entry);
2463 return false; 2451 return false;
2464 } 2452 }
2465 break; 2453 break;
2466 case ATH9K_CIPHER_WEP: 2454 case ATH9K_CIPHER_WEP:
2467 if (k->kv_len < LEN_WEP40) { 2455 if (k->kv_len < LEN_WEP40) {
2468 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2456 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2469 "WEP key length %u too small\n", k->kv_len); 2457 "WEP key length %u too small\n", k->kv_len);
2470 return false; 2458 return false;
2471 } 2459 }
@@ -2480,7 +2468,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2480 keyType = AR_KEYTABLE_TYPE_CLR; 2468 keyType = AR_KEYTABLE_TYPE_CLR;
2481 break; 2469 break;
2482 default: 2470 default:
2483 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2471 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2484 "cipher %u not supported\n", k->kv_type); 2472 "cipher %u not supported\n", k->kv_type);
2485 return false; 2473 return false;
2486 } 2474 }
@@ -2698,7 +2686,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2698 AR_RTC_FORCE_WAKE_EN); 2686 AR_RTC_FORCE_WAKE_EN);
2699 } 2687 }
2700 if (i == 0) { 2688 if (i == 0) {
2701 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2689 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2702 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); 2690 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2703 return false; 2691 return false;
2704 } 2692 }
@@ -2719,9 +2707,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2719 "UNDEFINED" 2707 "UNDEFINED"
2720 }; 2708 };
2721 2709
2722 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", 2710 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2723 modes[ah->power_mode], modes[mode], 2711 modes[ah->power_mode], modes[mode]);
2724 setChip ? "set chip " : "");
2725 2712
2726 switch (mode) { 2713 switch (mode) {
2727 case ATH9K_PM_AWAKE: 2714 case ATH9K_PM_AWAKE:
@@ -2735,7 +2722,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2735 ath9k_set_power_network_sleep(ah, setChip); 2722 ath9k_set_power_network_sleep(ah, setChip);
2736 break; 2723 break;
2737 default: 2724 default:
2738 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2725 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2739 "Unknown power mode %u\n", mode); 2726 "Unknown power mode %u\n", mode);
2740 return false; 2727 return false;
2741 } 2728 }
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index e0a6dee45839..8ae4ec21667b 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -49,7 +49,7 @@ bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
49 49
50bool ath9k_hw_txstart(struct ath_hw *ah, u32 q) 50bool ath9k_hw_txstart(struct ath_hw *ah, u32 q)
51{ 51{
52 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); 52 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q);
53 53
54 REG_WRITE(ah, AR_Q_TXE, 1 << q); 54 REG_WRITE(ah, AR_Q_TXE, 1 << q);
55 55
@@ -110,13 +110,15 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
110 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 110 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
111 111
112 if (q >= pCap->total_queues) { 112 if (q >= pCap->total_queues) {
113 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); 113 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, "
114 "invalid queue: %u\n", q);
114 return false; 115 return false;
115 } 116 }
116 117
117 qi = &ah->txq[q]; 118 qi = &ah->txq[q];
118 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 119 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
119 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 120 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, "
121 "inactive queue: %u\n", q);
120 return false; 122 return false;
121 } 123 }
122 124
@@ -146,7 +148,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
146 break; 148 break;
147 149
148 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 150 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
149 "TSF have moved while trying to set " 151 "TSF has moved while trying to set "
150 "quiet time TSF: 0x%08x\n", tsfLow); 152 "quiet time TSF: 0x%08x\n", tsfLow);
151 } 153 }
152 154
@@ -158,8 +160,8 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
158 wait = wait_time; 160 wait = wait_time;
159 while (ath9k_hw_numtxpending(ah, q)) { 161 while (ath9k_hw_numtxpending(ah, q)) {
160 if ((--wait) == 0) { 162 if ((--wait) == 0) {
161 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 163 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
162 "Failed to stop Tx DMA in 100 " 164 "Failed to stop TX DMA in 100 "
163 "msec after killing last frame\n"); 165 "msec after killing last frame\n");
164 break; 166 break;
165 } 167 }
@@ -454,17 +456,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
454 struct ath9k_tx_queue_info *qi; 456 struct ath9k_tx_queue_info *qi;
455 457
456 if (q >= pCap->total_queues) { 458 if (q >= pCap->total_queues) {
457 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); 459 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, "
460 "invalid queue: %u\n", q);
458 return false; 461 return false;
459 } 462 }
460 463
461 qi = &ah->txq[q]; 464 qi = &ah->txq[q];
462 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 465 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
463 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 466 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, "
467 "inactive queue: %u\n", q);
464 return false; 468 return false;
465 } 469 }
466 470
467 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %p\n", qi); 471 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
468 472
469 qi->tqi_ver = qinfo->tqi_ver; 473 qi->tqi_ver = qinfo->tqi_ver;
470 qi->tqi_subtype = qinfo->tqi_subtype; 474 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -521,13 +525,15 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
521 struct ath9k_tx_queue_info *qi; 525 struct ath9k_tx_queue_info *qi;
522 526
523 if (q >= pCap->total_queues) { 527 if (q >= pCap->total_queues) {
524 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); 528 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, "
529 "invalid queue: %u\n", q);
525 return false; 530 return false;
526 } 531 }
527 532
528 qi = &ah->txq[q]; 533 qi = &ah->txq[q];
529 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 534 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
530 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 535 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, "
536 "inactive queue: %u\n", q);
531 return false; 537 return false;
532 } 538 }
533 539
@@ -575,22 +581,23 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
575 ATH9K_TX_QUEUE_INACTIVE) 581 ATH9K_TX_QUEUE_INACTIVE)
576 break; 582 break;
577 if (q == pCap->total_queues) { 583 if (q == pCap->total_queues) {
578 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 584 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
579 "no available tx queue\n"); 585 "No available TX queue\n");
580 return -1; 586 return -1;
581 } 587 }
582 break; 588 break;
583 default: 589 default:
584 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "bad tx queue type %u\n", type); 590 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Invalid TX queue type: %u\n",
591 type);
585 return -1; 592 return -1;
586 } 593 }
587 594
588 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); 595 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
589 596
590 qi = &ah->txq[q]; 597 qi = &ah->txq[q];
591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 598 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
592 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 599 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
593 "tx queue %u already active\n", q); 600 "TX queue: %u already active\n", q);
594 return -1; 601 return -1;
595 } 602 }
596 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 603 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -620,16 +627,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
620 struct ath9k_tx_queue_info *qi; 627 struct ath9k_tx_queue_info *qi;
621 628
622 if (q >= pCap->total_queues) { 629 if (q >= pCap->total_queues) {
623 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); 630 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, "
631 "invalid queue: %u\n", q);
624 return false; 632 return false;
625 } 633 }
626 qi = &ah->txq[q]; 634 qi = &ah->txq[q];
627 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 635 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
628 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); 636 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, "
637 "inactive queue: %u\n", q);
629 return false; 638 return false;
630 } 639 }
631 640
632 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); 641 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
633 642
634 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 643 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
635 ah->txok_interrupt_mask &= ~(1 << q); 644 ah->txok_interrupt_mask &= ~(1 << q);
@@ -650,17 +659,19 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
650 u32 cwMin, chanCwMin, value; 659 u32 cwMin, chanCwMin, value;
651 660
652 if (q >= pCap->total_queues) { 661 if (q >= pCap->total_queues) {
653 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); 662 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, "
663 "invalid queue: %u\n", q);
654 return false; 664 return false;
655 } 665 }
656 666
657 qi = &ah->txq[q]; 667 qi = &ah->txq[q];
658 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 668 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
659 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); 669 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, "
670 "inactive queue: %u\n", q);
660 return true; 671 return true;
661 } 672 }
662 673
663 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "reset queue %u\n", q); 674 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
664 675
665 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 676 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
666 if (chan && IS_CHAN_B(chan)) 677 if (chan && IS_CHAN_B(chan))
@@ -894,7 +905,7 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
894 905
895 reg = REG_READ(ah, AR_OBS_BUS_1); 906 reg = REG_READ(ah, AR_OBS_BUS_1);
896 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 907 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
897 "rx failed to go idle in 10 ms RXSM=0x%x\n", reg); 908 "RX failed to go idle in 10 ms RXSM=0x%x\n", reg);
898 909
899 return false; 910 return false;
900 } 911 }
@@ -949,8 +960,8 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
949 } 960 }
950 961
951 if (i == 0) { 962 if (i == 0) {
952 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 963 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
953 "dma failed to stop in %d ms " 964 "DMA failed to stop in %d ms "
954 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", 965 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
955 AH_RX_STOP_DMA_TIMEOUT / 1000, 966 AH_RX_STOP_DMA_TIMEOUT / 1000,
956 REG_READ(ah, AR_CR), 967 REG_READ(ah, AR_CR),
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index 74fe777b54e4..1b43cb41363c 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -674,7 +674,7 @@ static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
674 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 674 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
675 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { 675 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
676 /* TX MIC entry failed. No need to proceed further */ 676 /* TX MIC entry failed. No need to proceed further */
677 DPRINTF(sc, ATH_DBG_KEYCACHE, 677 DPRINTF(sc, ATH_DBG_FATAL,
678 "Setting TX MIC Key Failed\n"); 678 "Setting TX MIC Key Failed\n");
679 return 0; 679 return 0;
680 } 680 }
@@ -1400,7 +1400,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1400 /* Get the hardware key cache size. */ 1400 /* Get the hardware key cache size. */
1401 sc->keymax = ah->caps.keycache_size; 1401 sc->keymax = ah->caps.keycache_size;
1402 if (sc->keymax > ATH_KEYMAX) { 1402 if (sc->keymax > ATH_KEYMAX) {
1403 DPRINTF(sc, ATH_DBG_KEYCACHE, 1403 DPRINTF(sc, ATH_DBG_ANY,
1404 "Warning, using only %u entries in %u key cache\n", 1404 "Warning, using only %u entries in %u key cache\n",
1405 ATH_KEYMAX, sc->keymax); 1405 ATH_KEYMAX, sc->keymax);
1406 sc->keymax = ATH_KEYMAX; 1406 sc->keymax = ATH_KEYMAX;
@@ -2602,7 +2602,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2602 2602
2603 mutex_lock(&sc->mutex); 2603 mutex_lock(&sc->mutex);
2604 ath9k_ps_wakeup(sc); 2604 ath9k_ps_wakeup(sc);
2605 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n"); 2605 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2606 2606
2607 switch (cmd) { 2607 switch (cmd) {
2608 case SET_KEY: 2608 case SET_KEY:
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c
index 8bcba906929a..5ec9ce91d979 100644
--- a/drivers/net/wireless/ath9k/phy.c
+++ b/drivers/net/wireless/ath9k/phy.c
@@ -46,7 +46,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
46 channelSel = ((freq - 704) * 2 - 3040) / 10; 46 channelSel = ((freq - 704) * 2 - 3040) / 10;
47 bModeSynth = 1; 47 bModeSynth = 1;
48 } else { 48 } else {
49 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 49 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
50 "Invalid channel %u MHz\n", freq); 50 "Invalid channel %u MHz\n", freq);
51 return false; 51 return false;
52 } 52 }
@@ -79,7 +79,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
79 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 79 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
80 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 80 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
81 } else { 81 } else {
82 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 82 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
83 "Invalid channel %u MHz\n", freq); 83 "Invalid channel %u MHz\n", freq);
84 return false; 84 return false;
85 } 85 }
diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h
index 0f7f8e0c9c95..296d0e985f25 100644
--- a/drivers/net/wireless/ath9k/phy.h
+++ b/drivers/net/wireless/ath9k/phy.h
@@ -556,9 +556,6 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
556 int r; \ 556 int r; \
557 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 557 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
558 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \ 558 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
559 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, \
560 "RF 0x%x V 0x%x\n", \
561 INI_RA((iniarray), r, 0), (regData)[r]); \
562 DO_DELAY(regWr); \ 559 DO_DELAY(regWr); \
563 } \ 560 } \
564 } while (0) 561 } while (0)
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c
index dd1f30156740..efa57ae8901c 100644
--- a/drivers/net/wireless/ath9k/recv.c
+++ b/drivers/net/wireless/ath9k/recv.c
@@ -320,7 +320,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
320 bf->bf_buf_addr))) { 320 bf->bf_buf_addr))) {
321 dev_kfree_skb_any(skb); 321 dev_kfree_skb_any(skb);
322 bf->bf_mpdu = NULL; 322 bf->bf_mpdu = NULL;
323 DPRINTF(sc, ATH_DBG_CONFIG, 323 DPRINTF(sc, ATH_DBG_FATAL,
324 "dma_mapping_error() on RX init\n"); 324 "dma_mapping_error() on RX init\n");
325 error = -ENOMEM; 325 error = -ENOMEM;
326 break; 326 break;
@@ -675,7 +675,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
675 bf->bf_buf_addr))) { 675 bf->bf_buf_addr))) {
676 dev_kfree_skb_any(requeue_skb); 676 dev_kfree_skb_any(requeue_skb);
677 bf->bf_mpdu = NULL; 677 bf->bf_mpdu = NULL;
678 DPRINTF(sc, ATH_DBG_CONFIG, 678 DPRINTF(sc, ATH_DBG_FATAL,
679 "dma_mapping_error() on RX\n"); 679 "dma_mapping_error() on RX\n");
680 break; 680 break;
681 } 681 }