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authorManu Abraham <abraham.manu@gmail.com>2007-09-22 20:28:11 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-12-29 14:53:15 -0500
commit41e1151b33cce7e19cfba1648d05abd34a0ba492 (patch)
tree14bf8c6d7bc2b0cf704690621d7e15a835d4a18c /drivers
parent0b8f15dcebb58ef8956203803c6de8f41a173dbc (diff)
V4L/DVB (9395): Add initial support for two KNC1 DVB-S2 boards
Add initial support for: * KNC1 DVB-S2 Plus * KNC1 DVB-S2 OEM (known as Satelco DVB-S2) Signed-off-by: Manu Abraham <manu@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/dvb/frontends/tda8261.c14
-rw-r--r--drivers/media/dvb/frontends/tda8261.h9
-rw-r--r--drivers/media/dvb/ttpci/budget-av.c613
-rw-r--r--drivers/media/dvb/ttpci/budget.h1
4 files changed, 624 insertions, 13 deletions
diff --git a/drivers/media/dvb/frontends/tda8261.c b/drivers/media/dvb/frontends/tda8261.c
index 616d88b07158..1b3d491445af 100644
--- a/drivers/media/dvb/frontends/tda8261.c
+++ b/drivers/media/dvb/frontends/tda8261.c
@@ -26,9 +26,9 @@
26#include "tda8261.h" 26#include "tda8261.h"
27 27
28struct tda8261_state { 28struct tda8261_state {
29 struct dvb_frontend *fe; 29 struct dvb_frontend *fe;
30 struct i2c_adapter *i2c; 30 struct i2c_adapter *i2c;
31 struct tda8261_config *config; 31 const struct tda8261_config *config;
32 32
33 /* state cache */ 33 /* state cache */
34 u32 frequency; 34 u32 frequency;
@@ -37,7 +37,7 @@ struct tda8261_state {
37 37
38static int tda8261_read(struct tda8261_state *state, u8 *buf) 38static int tda8261_read(struct tda8261_state *state, u8 *buf)
39{ 39{
40 struct tda8261_config *config = state->config; 40 const struct tda8261_config *config = state->config;
41 int err = 0; 41 int err = 0;
42 struct i2c_msg msg[] = { 42 struct i2c_msg msg[] = {
43 { .addr = config->addr, .flags = 0, .buf = NULL, .len = 0 }, 43 { .addr = config->addr, .flags = 0, .buf = NULL, .len = 0 },
@@ -52,7 +52,7 @@ static int tda8261_read(struct tda8261_state *state, u8 *buf)
52 52
53static int tda8261_write(struct tda8261_state *state, u8 *buf) 53static int tda8261_write(struct tda8261_state *state, u8 *buf)
54{ 54{
55 struct tda8261_config *config = state->config; 55 const struct tda8261_config *config = state->config;
56 int err = 0; 56 int err = 0;
57 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 }; 57 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 };
58 58
@@ -111,7 +111,7 @@ static int tda8261_set_state(struct dvb_frontend *fe,
111 struct tuner_state *tstate) 111 struct tuner_state *tstate)
112{ 112{
113 struct tda8261_state *state = fe->tuner_priv; 113 struct tda8261_state *state = fe->tuner_priv;
114 struct tda8261_config *config = state->config; 114 const struct tda8261_config *config = state->config;
115 u32 frequency, N, status = 0; 115 u32 frequency, N, status = 0;
116 u8 buf[4]; 116 u8 buf[4];
117 int err = 0; 117 int err = 0;
@@ -182,7 +182,7 @@ static struct dvb_tuner_ops tda8261_ops = {
182}; 182};
183 183
184struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe, 184struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe,
185 struct tda8261_config *config, 185 const struct tda8261_config *config,
186 struct i2c_adapter *i2c) 186 struct i2c_adapter *i2c)
187{ 187{
188 struct tda8261_state *state = NULL; 188 struct tda8261_state *state = NULL;
diff --git a/drivers/media/dvb/frontends/tda8261.h b/drivers/media/dvb/frontends/tda8261.h
index b8d8e37b045b..1381d8e22a83 100644
--- a/drivers/media/dvb/frontends/tda8261.h
+++ b/drivers/media/dvb/frontends/tda8261.h
@@ -15,11 +15,8 @@ struct tda8261_config {
15 enum tda8261_step step_size; 15 enum tda8261_step step_size;
16}; 16};
17 17
18/* move out from here! */ 18extern struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe,
19static const struct tda8261_config sd1878c_config = { 19 const struct tda8261_config *config,
20// .name = "SD1878C", 20 struct i2c_adapter *i2c);
21 .addr = 0x60,
22 .step_size = TDA8261_STEP_1000 /* kHz */
23};
24 21
25#endif// __TDA8261_H 22#endif// __TDA8261_H
diff --git a/drivers/media/dvb/ttpci/budget-av.c b/drivers/media/dvb/ttpci/budget-av.c
index 1032ea77837e..9e7fab0e31e1 100644
--- a/drivers/media/dvb/ttpci/budget-av.c
+++ b/drivers/media/dvb/ttpci/budget-av.c
@@ -35,6 +35,9 @@
35 35
36#include "budget.h" 36#include "budget.h"
37#include "stv0299.h" 37#include "stv0299.h"
38#include "stb0899_drv.h"
39#include "stb0899_reg.h"
40#include "tda8261.h"
38#include "tda1002x.h" 41#include "tda1002x.h"
39#include "tda1004x.h" 42#include "tda1004x.h"
40#include "tua6100.h" 43#include "tua6100.h"
@@ -882,6 +885,603 @@ static struct stv0299_config philips_sd1878_config = {
882 .set_symbol_rate = philips_sd1878_ci_set_symbol_rate, 885 .set_symbol_rate = philips_sd1878_ci_set_symbol_rate,
883}; 886};
884 887
888/* KNC1 DVB-S (STB0899) Inittab */
889static const struct stb0899_s1_reg knc1_stb0899_s1_init_1[] = {
890
891// 0x0000000b , /* SYSREG */
892 { STB0899_DEV_ID , 0x81 },
893 { STB0899_DISCNTRL1 , 0x32 },
894 { STB0899_DISCNTRL2 , 0x80 },
895 { STB0899_DISRX_ST0 , 0x04 },
896 { STB0899_DISRX_ST1 , 0x00 },
897 { STB0899_DISPARITY , 0x00 },
898 { STB0899_DISFIFO , 0x00 },
899 { STB0899_DISSTATUS , 0x20 },
900 { STB0899_DISF22 , 0x8c },
901 { STB0899_DISF22RX , 0x9a },
902 //SYSREG ?
903 { STB0899_ACRPRESC , 0x11 },
904 { STB0899_ACRDIV1 , 0x0a },
905 { STB0899_ACRDIV2 , 0x05 },
906 { STB0899_DACR1 , 0x00 },
907 { STB0899_DACR2 , 0x00 },
908 { STB0899_OUTCFG , 0x00 },
909 { STB0899_MODECFG , 0x00 },
910 { STB0899_IRQSTATUS_3 , 0x30 },
911 { STB0899_IRQSTATUS_2 , 0x00 },
912 { STB0899_IRQSTATUS_1 , 0x00 },
913 { STB0899_IRQSTATUS_0 , 0x00 },
914 { STB0899_IRQMSK_3 , 0xf3 },
915 { STB0899_IRQMSK_2 , 0xfc },
916 { STB0899_IRQMSK_1 , 0xff },
917 { STB0899_IRQMSK_0 , 0xff },
918 { STB0899_IRQCFG , 0x00 },
919 { STB0899_I2CCFG , 0x88 },
920 { STB0899_I2CRPT , 0x5c },
921 { STB0899_IOPVALUE5 , 0x00 },
922 { STB0899_IOPVALUE4 , 0x20 },
923 { STB0899_IOPVALUE3 , 0xc9 },
924 { STB0899_IOPVALUE2 , 0x90 },
925 { STB0899_IOPVALUE1 , 0x40 },
926 { STB0899_IOPVALUE0 , 0x00 },
927 { STB0899_GPIO00CFG , 0x82 },
928 { STB0899_GPIO01CFG , 0x82 },
929 { STB0899_GPIO02CFG , 0x82 },
930 { STB0899_GPIO03CFG , 0x82 },
931 { STB0899_GPIO04CFG , 0x82 },
932 { STB0899_GPIO05CFG , 0x82 },
933 { STB0899_GPIO06CFG , 0x82 },
934 { STB0899_GPIO07CFG , 0x82 },
935 { STB0899_GPIO08CFG , 0x82 },
936 { STB0899_GPIO09CFG , 0x82 },
937 { STB0899_GPIO10CFG , 0x82 },
938 { STB0899_GPIO11CFG , 0x82 },
939 { STB0899_GPIO12CFG , 0x82 },
940 { STB0899_GPIO13CFG , 0x82 },
941 { STB0899_GPIO14CFG , 0x82 },
942 { STB0899_GPIO15CFG , 0x82 },
943 { STB0899_GPIO16CFG , 0x82 },
944 { STB0899_GPIO17CFG , 0x82 },
945 { STB0899_GPIO18CFG , 0x82 },
946 { STB0899_GPIO19CFG , 0x82 },
947 { STB0899_GPIO20CFG , 0x82 },
948 { STB0899_SDATCFG , 0xb8 },
949 { STB0899_SCLTCFG , 0xba },
950 { STB0899_AGCRFCFG , 0x1c }, /* 0x11 */
951 { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */
952 { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */
953 { STB0899_DIRCLKCFG , 0x82 },
954 { STB0899_CLKOUT27CFG , 0x7e },
955 { STB0899_STDBYCFG , 0x82 },
956 { STB0899_CS0CFG , 0x82 },
957 { STB0899_CS1CFG , 0x82 },
958 { STB0899_DISEQCOCFG , 0x20 },
959 { STB0899_GPIO32CFG , 0x82 },
960 { STB0899_GPIO33CFG , 0x82 },
961 { STB0899_GPIO34CFG , 0x82 },
962 { STB0899_GPIO35CFG , 0x82 },
963 { STB0899_GPIO36CFG , 0x82 },
964 { STB0899_GPIO37CFG , 0x82 },
965 { STB0899_GPIO38CFG , 0x82 },
966 { STB0899_GPIO39CFG , 0x82 },
967 { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
968 { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
969 { STB0899_FILTCTRL , 0x00 },
970 { STB0899_SYSCTRL , 0x00 },
971 { STB0899_STOPCLK1 , 0x20 },
972 { STB0899_STOPCLK2 , 0x00 },
973 { STB0899_INTBUFSTATUS , 0x00 },
974 { STB0899_INTBUFCTRL , 0x0a },
975 { 0xffff , 0xff },
976};
977
978static const struct stb0899_s2_reg knc1_stb0899_s2_init_2[] = {
979
980 { STB0899_OFF0_DMD_STATUS , STB0899_BASE_DMD_STATUS , 0x00000103 }, /* DMDSTATUS */
981 { STB0899_OFF0_CRL_FREQ , STB0899_BASE_CRL_FREQ , 0x3ed1da56 }, /* CRLFREQ */
982 { STB0899_OFF0_BTR_FREQ , STB0899_BASE_BTR_FREQ , 0x00004000 }, /* BTRFREQ */
983 { STB0899_OFF0_IF_AGC_GAIN , STB0899_BASE_IF_AGC_GAIN , 0x00002ade }, /* IFAGCGAIN */
984 { STB0899_OFF0_BB_AGC_GAIN , STB0899_BASE_BB_AGC_GAIN , 0x000001bc }, /* BBAGCGAIN */
985 { STB0899_OFF0_DC_OFFSET , STB0899_BASE_DC_OFFSET , 0x00000200 }, /* DCOFFSET */
986 { STB0899_OFF0_DMD_CNTRL , STB0899_BASE_DMD_CNTRL , 0x0000000f }, /* DMDCNTRL */
987
988 { STB0899_OFF0_IF_AGC_CNTRL , STB0899_BASE_IF_AGC_CNTRL , 0x03fb4a20 }, /* IFAGCCNTRL */
989 { STB0899_OFF0_BB_AGC_CNTRL , STB0899_BASE_BB_AGC_CNTRL , 0x00200c97 }, /* BBAGCCNTRL */
990
991 { STB0899_OFF0_CRL_CNTRL , STB0899_BASE_CRL_CNTRL , 0x00000016 }, /* CRLCNTRL */
992 { STB0899_OFF0_CRL_PHS_INIT , STB0899_BASE_CRL_PHS_INIT , 0x00000000 }, /* CRLPHSINIT */
993 { STB0899_OFF0_CRL_FREQ_INIT , STB0899_BASE_CRL_FREQ_INIT , 0x00000000 }, /* CRLFREQINIT */
994 { STB0899_OFF0_CRL_LOOP_GAIN , STB0899_BASE_CRL_LOOP_GAIN , 0x00000000 }, /* CRLLOOPGAIN */
995 { STB0899_OFF0_CRL_NOM_FREQ , STB0899_BASE_CRL_NOM_FREQ , 0x3ed097b6 }, /* CRLNOMFREQ */
996 { STB0899_OFF0_CRL_SWP_RATE , STB0899_BASE_CRL_SWP_RATE , 0x00000000 }, /* CRLSWPRATE */
997 { STB0899_OFF0_CRL_MAX_SWP , STB0899_BASE_CRL_MAX_SWP , 0x00000000 }, /* CRLMAXSWP */
998 { STB0899_OFF0_CRL_LK_CNTRL , STB0899_BASE_CRL_LK_CNTRL , 0x0f6cdc01 }, /* CRLLKCNTRL */
999 { STB0899_OFF0_DECIM_CNTRL , STB0899_BASE_DECIM_CNTRL , 0x00000000 }, /* DECIMCNTRL */
1000 { STB0899_OFF0_BTR_CNTRL , STB0899_BASE_BTR_CNTRL , 0x00003993 }, /* BTRCNTRL */
1001 { STB0899_OFF0_BTR_LOOP_GAIN , STB0899_BASE_BTR_LOOP_GAIN , 0x000d3c6f }, /* BTRLOOPGAIN */
1002 { STB0899_OFF0_BTR_PHS_INIT , STB0899_BASE_BTR_PHS_INIT , 0x00000000 }, /* BTRPHSINIT */
1003 { STB0899_OFF0_BTR_FREQ_INIT , STB0899_BASE_BTR_FREQ_INIT , 0x00000000 }, /* BTRFREQINIT */
1004 { STB0899_OFF0_BTR_NOM_FREQ , STB0899_BASE_BTR_NOM_FREQ , 0x0238e38e }, /* BTRNOMFREQ */
1005 { STB0899_OFF0_BTR_LK_CNTRL , STB0899_BASE_BTR_LK_CNTRL , 0x00000000 }, /* BTRLKCNTRL */
1006 { STB0899_OFF0_DECN_CNTRL , STB0899_BASE_DECN_CNTRL , 0x00000000 }, /* DECNCNTRL */
1007 { STB0899_OFF0_TP_CNTRL , STB0899_BASE_TP_CNTRL , 0x00000000 }, /* TPCNTRL */
1008 { STB0899_OFF0_TP_BUF_STATUS , STB0899_BASE_TP_BUF_STATUS , 0x00000000 }, /* TPBUFSTATUS */
1009 { STB0899_OFF0_DC_ESTIM , STB0899_BASE_DC_ESTIM , 0x00000000 }, /* DCESTIM */
1010 { STB0899_OFF0_FLL_CNTRL , STB0899_BASE_FLL_CNTRL , 0x00000000 }, /* FLLCNTRL */
1011 { STB0899_OFF0_FLL_FREQ_WD , STB0899_BASE_FLL_FREQ_WD , 0x40070000 }, /* FLLFREQWD */
1012 { STB0899_OFF0_ANTI_ALIAS_SEL , STB0899_BASE_ANTI_ALIAS_SEL , 0x00000001 }, /* ANTIALIASSEL */
1013 { STB0899_OFF0_RRC_ALPHA , STB0899_BASE_RRC_ALPHA , 0x00000002 }, /* RRCALPHA */
1014 { STB0899_OFF0_DC_ADAPT_LSHFT , STB0899_BASE_DC_ADAPT_LSHFT , 0x00000000 }, /* DCADAPTISHFT */
1015 { STB0899_OFF0_IMB_OFFSET , STB0899_BASE_IMB_OFFSET , 0x0000fe01 }, /* IMBOFFSET */
1016 { STB0899_OFF0_IMB_ESTIMATE , STB0899_BASE_IMB_ESTIMATE , 0x00000000 }, /* IMBESTIMATE */
1017 { STB0899_OFF0_IMB_CNTRL , STB0899_BASE_IMB_CNTRL , 0x00000001 }, /* IMBCNTRL */
1018 { STB0899_OFF0_IF_AGC_CNTRL2 , STB0899_BASE_IF_AGC_CNTRL2 , 0x00005007 }, /* IFAGCCNTRL2 */
1019 { STB0899_OFF0_DMD_CNTRL2 , STB0899_BASE_DMD_CNTRL2 , 0x00000002 }, /* DMDCNTRL2 */
1020 { STB0899_OFF0_TP_BUFFER , STB0899_BASE_TP_BUFFER , 0x00000000 }, /* TPBUFFER */
1021 { STB0899_OFF0_TP_BUFFER1 , STB0899_BASE_TP_BUFFER1 , 0x00000000 }, /* TPBUFFER1 */
1022 { STB0899_OFF0_TP_BUFFER2 , STB0899_BASE_TP_BUFFER2 , 0x00000000 }, /* TPBUFFER2 */
1023 { STB0899_OFF0_TP_BUFFER3 , STB0899_BASE_TP_BUFFER3 , 0x00000000 }, /* TPBUFFER3 */
1024 { STB0899_OFF0_TP_BUFFER4 , STB0899_BASE_TP_BUFFER4 , 0x00000000 }, /* TPBUFFER4 */
1025 { STB0899_OFF0_TP_BUFFER5 , STB0899_BASE_TP_BUFFER5 , 0x00000000 }, /* TPBUFFER5 */
1026 { STB0899_OFF0_TP_BUFFER6 , STB0899_BASE_TP_BUFFER6 , 0x00000000 }, /* TPBUFFER6 */
1027 { STB0899_OFF0_TP_BUFFER7 , STB0899_BASE_TP_BUFFER7 , 0x00000000 }, /* TPBUFFER7 */
1028 { STB0899_OFF0_TP_BUFFER8 , STB0899_BASE_TP_BUFFER8 , 0x00000000 }, /* TPBUFFER8 */
1029 { STB0899_OFF0_TP_BUFFER9 , STB0899_BASE_TP_BUFFER9 , 0x00000000 }, /* TPBUFFER9 */
1030 { STB0899_OFF0_TP_BUFFER10 , STB0899_BASE_TP_BUFFER10 , 0x00000000 }, /* TPBUFFER10 */
1031 { STB0899_OFF0_TP_BUFFER11 , STB0899_BASE_TP_BUFFER11 , 0x00000000 }, /* TPBUFFER11 */
1032 { STB0899_OFF0_TP_BUFFER12 , STB0899_BASE_TP_BUFFER12 , 0x00000000 }, /* TPBUFFER12 */
1033 { STB0899_OFF0_TP_BUFFER13 , STB0899_BASE_TP_BUFFER13 , 0x00000000 }, /* TPBUFFER13 */
1034 { STB0899_OFF0_TP_BUFFER14 , STB0899_BASE_TP_BUFFER14 , 0x00000000 }, /* TPBUFFER14 */
1035 { STB0899_OFF0_TP_BUFFER15 , STB0899_BASE_TP_BUFFER15 , 0x00000000 }, /* TPBUFFER15 */
1036 { STB0899_OFF0_TP_BUFFER16 , STB0899_BASE_TP_BUFFER16 , 0x0000ff00 }, /* TPBUFFER16 */
1037 { STB0899_OFF0_TP_BUFFER17 , STB0899_BASE_TP_BUFFER17 , 0x00000100 }, /* TPBUFFER17 */
1038 { STB0899_OFF0_TP_BUFFER18 , STB0899_BASE_TP_BUFFER18 , 0x0000fe01 }, /* TPBUFFER18 */
1039 { STB0899_OFF0_TP_BUFFER19 , STB0899_BASE_TP_BUFFER19 , 0x000004fe }, /* TPBUFFER19 */
1040 { STB0899_OFF0_TP_BUFFER20 , STB0899_BASE_TP_BUFFER20 , 0x0000cfe7 }, /* TPBUFFER20 */
1041 { STB0899_OFF0_TP_BUFFER21 , STB0899_BASE_TP_BUFFER21 , 0x0000bec6 }, /* TPBUFFER21 */
1042 { STB0899_OFF0_TP_BUFFER22 , STB0899_BASE_TP_BUFFER22 , 0x0000c2bf }, /* TPBUFFER22 */
1043 { STB0899_OFF0_TP_BUFFER23 , STB0899_BASE_TP_BUFFER23 , 0x0000c1c1 }, /* TPBUFFER23 */
1044 { STB0899_OFF0_TP_BUFFER24 , STB0899_BASE_TP_BUFFER24 , 0x0000c1c1 }, /* TPBUFFER24 */
1045 { STB0899_OFF0_TP_BUFFER25 , STB0899_BASE_TP_BUFFER25 , 0x0000c1c1 }, /* TPBUFFER25 */
1046 { STB0899_OFF0_TP_BUFFER26 , STB0899_BASE_TP_BUFFER26 , 0x0000c1c1 }, /* TPBUFFER26 */
1047 { STB0899_OFF0_TP_BUFFER27 , STB0899_BASE_TP_BUFFER27 , 0x0000c1c0 }, /* TPBUFFER27 */
1048 { STB0899_OFF0_TP_BUFFER28 , STB0899_BASE_TP_BUFFER28 , 0x0000c0c0 }, /* TPBUFFER28 */
1049 { STB0899_OFF0_TP_BUFFER29 , STB0899_BASE_TP_BUFFER29 , 0x0000c1c1 }, /* TPBUFFER29 */
1050 { STB0899_OFF0_TP_BUFFER30 , STB0899_BASE_TP_BUFFER30 , 0x0000c1c1 }, /* TPBUFFER30 */
1051 { STB0899_OFF0_TP_BUFFER31 , STB0899_BASE_TP_BUFFER31 , 0x0000c0c1 }, /* TPBUFFER31 */
1052 { STB0899_OFF0_TP_BUFFER32 , STB0899_BASE_TP_BUFFER32 , 0x0000c0c1 }, /* TPBUFFER32 */
1053 { STB0899_OFF0_TP_BUFFER33 , STB0899_BASE_TP_BUFFER33 , 0x0000c1c1 }, /* TPBUFFER33 */
1054 { STB0899_OFF0_TP_BUFFER34 , STB0899_BASE_TP_BUFFER34 , 0x0000c1c1 }, /* TPBUFFER34 */
1055 { STB0899_OFF0_TP_BUFFER35 , STB0899_BASE_TP_BUFFER35 , 0x0000c0c1 }, /* TPBUFFER35 */
1056 { STB0899_OFF0_TP_BUFFER36 , STB0899_BASE_TP_BUFFER36 , 0x0000c1c1 }, /* TPBUFFER36 */
1057 { STB0899_OFF0_TP_BUFFER37 , STB0899_BASE_TP_BUFFER37 , 0x0000c0c1 }, /* TPBUFFER37 */
1058 { STB0899_OFF0_TP_BUFFER38 , STB0899_BASE_TP_BUFFER38 , 0x0000c1c1 }, /* TPBUFFER38 */
1059 { STB0899_OFF0_TP_BUFFER39 , STB0899_BASE_TP_BUFFER39 , 0x0000c0c0 }, /* TPBUFFER39 */
1060 { STB0899_OFF0_TP_BUFFER40 , STB0899_BASE_TP_BUFFER40 , 0x0000c1c0 }, /* TPBUFFER40 */
1061 { STB0899_OFF0_TP_BUFFER41 , STB0899_BASE_TP_BUFFER41 , 0x0000c1c1 }, /* TPBUFFER41 */
1062 { STB0899_OFF0_TP_BUFFER42 , STB0899_BASE_TP_BUFFER42 , 0x0000c0c0 }, /* TPBUFFER42 */
1063 { STB0899_OFF0_TP_BUFFER43 , STB0899_BASE_TP_BUFFER43 , 0x0000c1c0 }, /* TPBUFFER43 */
1064 { STB0899_OFF0_TP_BUFFER44 , STB0899_BASE_TP_BUFFER44 , 0x0000c0c1 }, /* TPBUFFER44 */
1065 { STB0899_OFF0_TP_BUFFER45 , STB0899_BASE_TP_BUFFER45 , 0x0000c1be }, /* TPBUFFER45 */
1066 { STB0899_OFF0_TP_BUFFER46 , STB0899_BASE_TP_BUFFER46 , 0x0000c1c9 }, /* TPBUFFER46 */
1067 { STB0899_OFF0_TP_BUFFER47 , STB0899_BASE_TP_BUFFER47 , 0x0000c0da }, /* TPBUFFER47 */
1068 { STB0899_OFF0_TP_BUFFER48 , STB0899_BASE_TP_BUFFER48 , 0x0000c0ba }, /* TPBUFFER48 */
1069 { STB0899_OFF0_TP_BUFFER49 , STB0899_BASE_TP_BUFFER49 , 0x0000c1c4 }, /* TPBUFFER49 */
1070 { STB0899_OFF0_TP_BUFFER50 , STB0899_BASE_TP_BUFFER50 , 0x0000c1bf }, /* TPBUFFER50 */
1071 { STB0899_OFF0_TP_BUFFER51 , STB0899_BASE_TP_BUFFER51 , 0x0000c0c1 }, /* TPBUFFER51 */
1072 { STB0899_OFF0_TP_BUFFER52 , STB0899_BASE_TP_BUFFER52 , 0x0000c1c0 }, /* TPBUFFER52 */
1073 { STB0899_OFF0_TP_BUFFER53 , STB0899_BASE_TP_BUFFER53 , 0x0000c0c1 }, /* TPBUFFER53 */
1074 { STB0899_OFF0_TP_BUFFER54 , STB0899_BASE_TP_BUFFER54 , 0x0000c1c1 }, /* TPBUFFER54 */
1075 { STB0899_OFF0_TP_BUFFER55 , STB0899_BASE_TP_BUFFER55 , 0x0000c1c1 }, /* TPBUFFER55 */
1076 { STB0899_OFF0_TP_BUFFER56 , STB0899_BASE_TP_BUFFER56 , 0x0000c1c1 }, /* TPBUFFER56 */
1077 { STB0899_OFF0_TP_BUFFER57 , STB0899_BASE_TP_BUFFER57 , 0x0000c1c1 }, /* TPBUFFER57 */
1078 { STB0899_OFF0_TP_BUFFER58 , STB0899_BASE_TP_BUFFER58 , 0x0000c1c1 }, /* TPBUFFER58 */
1079 { STB0899_OFF0_TP_BUFFER59 , STB0899_BASE_TP_BUFFER59 , 0x0000c1c1 }, /* TPBUFFER59 */
1080 { STB0899_OFF0_TP_BUFFER60 , STB0899_BASE_TP_BUFFER60 , 0x0000c1c1 }, /* TPBUFFER60 */
1081 { STB0899_OFF0_TP_BUFFER61 , STB0899_BASE_TP_BUFFER61 , 0x0000c1c1 }, /* TPBUFFER61 */
1082 { STB0899_OFF0_TP_BUFFER62 , STB0899_BASE_TP_BUFFER62 , 0x0000c1c1 }, /* TPBUFFER62 */
1083 { STB0899_OFF0_TP_BUFFER63 , STB0899_BASE_TP_BUFFER63 , 0x0000c1c0 }, /* TPBUFFER63 */
1084 { STB0899_OFF0_RESET_CNTRL , STB0899_BASE_RESET_CNTRL , 0x00000001 }, /* RESETCNTRL */
1085 { STB0899_OFF0_ACM_ENABLE , STB0899_BASE_ACM_ENABLE , 0x00005654 }, /* ACMENABLE */
1086 { STB0899_OFF0_DESCR_CNTRL , STB0899_BASE_DESCR_CNTRL , 0x00000000 }, /* DESCRCNTRL */
1087 { STB0899_OFF0_CSM_CNTRL1 , STB0899_BASE_CSM_CNTRL1 , 0x00020019 }, /* CSMCNTRL1 */
1088 { STB0899_OFF0_CSM_CNTRL2 , STB0899_BASE_CSM_CNTRL2 , 0x004b3237 }, /* CSMCNTRL2 */
1089 { STB0899_OFF0_CSM_CNTRL3 , STB0899_BASE_CSM_CNTRL3 , 0x0003dd17 }, /* CSMCNTRL3 */
1090 { STB0899_OFF0_CSM_CNTRL4 , STB0899_BASE_CSM_CNTRL4 , 0x00008008 }, /* CSMCNTRL4 */
1091 { STB0899_OFF0_UWP_CNTRL1 , STB0899_BASE_UWP_CNTRL1 , 0x002a3106 }, /* UWPCNTRL1 */
1092 { STB0899_OFF0_UWP_CNTRL2 , STB0899_BASE_UWP_CNTRL2 , 0x0006140a }, /* UWPCNTRL2 */
1093 { STB0899_OFF0_UWP_STAT1 , STB0899_BASE_UWP_STAT1 , 0x00008000 }, /* UWPSTAT1 */
1094 { STB0899_OFF0_UWP_STAT2 , STB0899_BASE_UWP_STAT2 , 0x00000000 }, /* UWPSTAT2 */
1095 { STB0899_OFF0_DMD_STAT2 , STB0899_BASE_DMD_STAT2 , 0x00000000 }, /* DMDSTAT2 */
1096 { STB0899_OFF0_FREQ_ADJ_SCALE , STB0899_BASE_FREQ_ADJ_SCALE , 0x00000471 }, /* FREQADJSCALE */
1097 { STB0899_OFF0_UWP_CNTRL3 , STB0899_BASE_UWP_CNTRL3 , 0x017b0465 }, /* UWPCNTRL3 */
1098 { STB0899_OFF0_SYM_CLK_SEL , STB0899_BASE_SYM_CLK_SEL , 0x00000002 }, /* SYMCLKSEL */
1099 { STB0899_OFF0_SOF_SRCH_TO , STB0899_BASE_SOF_SRCH_TO , 0x00196464 }, /* SOFSRCHTO */
1100 { STB0899_OFF0_ACQ_CNTRL1 , STB0899_BASE_ACQ_CNTRL1 , 0x00000603 }, /* ACQCNTRL1 */
1101 { STB0899_OFF0_ACQ_CNTRL2 , STB0899_BASE_ACQ_CNTRL2 , 0x02046666 }, /* ACQCNTRL2 */
1102 { STB0899_OFF0_ACQ_CNTRL3 , STB0899_BASE_ACQ_CNTRL3 , 0x10046583 }, /* ACQCNTRL3 */
1103 { STB0899_OFF0_FE_SETTLE , STB0899_BASE_FE_SETTLE , 0x00010404 }, /* FESETTLE */
1104 { STB0899_OFF0_AC_DWELL , STB0899_BASE_AC_DWELL , 0x0002aa8a }, /* ACDWELL */
1105 { STB0899_OFF0_ACQUIRE_TRIG , STB0899_BASE_ACQUIRE_TRIG , 0x00000000 }, /* ACQUIRETRIG */
1106 { STB0899_OFF0_LOCK_LOST , STB0899_BASE_LOCK_LOST , 0x00000001 }, /* LOCKLOST */
1107 { STB0899_OFF0_ACQ_STAT1 , STB0899_BASE_ACQ_STAT1 , 0x00000500 }, /* ACQSTAT1 */
1108 { STB0899_OFF0_ACQ_TIMEOUT , STB0899_BASE_ACQ_TIMEOUT , 0x0028a0a0 }, /* ACQTIMEOUT */
1109 { STB0899_OFF0_ACQ_TIME , STB0899_BASE_ACQ_TIME , 0x00000000 }, /* ACQTIME */
1110 { STB0899_OFF0_FINAL_AGC_CNTRL , STB0899_BASE_FINAL_AGC_CNTRL , 0x00800c17 }, /* FINALAGCCNTRL*/
1111 { STB0899_OFF0_FINAL_AGC_GAIN , STB0899_BASE_FINAL_AGC_GAIN , 0x00000000 }, /* FINALAGCCGAIN*/
1112 { STB0899_OFF0_EQUALIZER_INIT , STB0899_BASE_EQUALIZER_INIT , 0x00000000 }, /* EQUILIZERINIT*/
1113 { STB0899_OFF0_EQ_CNTRL , STB0899_BASE_EQ_CNTRL , 0x00054802 }, /* EQCNTL */
1114 { STB0899_OFF0_EQ_I_INIT_COEFF_0, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF0 */
1115 { STB0899_OFF1_EQ_I_INIT_COEFF_1, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF1 */
1116 { STB0899_OFF2_EQ_I_INIT_COEFF_2, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF2 */
1117 { STB0899_OFF3_EQ_I_INIT_COEFF_3, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF3 */
1118 { STB0899_OFF4_EQ_I_INIT_COEFF_4, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF4 */
1119 { STB0899_OFF5_EQ_I_INIT_COEFF_5, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000400 }, /* EQIINITCOEFF5 */
1120 { STB0899_OFF6_EQ_I_INIT_COEFF_6, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF6 */
1121 { STB0899_OFF7_EQ_I_INIT_COEFF_7, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF7 */
1122 { STB0899_OFF8_EQ_I_INIT_COEFF_8, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF8 */
1123 { STB0899_OFF9_EQ_I_INIT_COEFF_9, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF9 */
1124 { STB0899_OFFa_EQ_I_INIT_COEFF_10,STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF10*/
1125 { STB0899_OFF0_EQ_Q_INIT_COEFF_0, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF0 */
1126 { STB0899_OFF1_EQ_Q_INIT_COEFF_1, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF1 */
1127 { STB0899_OFF2_EQ_Q_INIT_COEFF_2, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF2 */
1128 { STB0899_OFF3_EQ_Q_INIT_COEFF_3, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF3 */
1129 { STB0899_OFF4_EQ_Q_INIT_COEFF_4, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF4 */
1130 { STB0899_OFF5_EQ_Q_INIT_COEFF_5, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF5 */
1131 { STB0899_OFF6_EQ_Q_INIT_COEFF_6, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF6 */
1132 { STB0899_OFF7_EQ_Q_INIT_COEFF_7, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF7 */
1133 { STB0899_OFF8_EQ_Q_INIT_COEFF_8, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF8 */
1134 { STB0899_OFF9_EQ_Q_INIT_COEFF_9, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF9 */
1135 { STB0899_OFFa_EQ_Q_INIT_COEFF_10,STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF10*/
1136 { STB0899_OFF0_EQ_I_OUT_COEFF_0 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT0 */
1137 { STB0899_OFF1_EQ_I_OUT_COEFF_1 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT1 */
1138 { STB0899_OFF2_EQ_I_OUT_COEFF_2 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT2 */
1139 { STB0899_OFF3_EQ_I_OUT_COEFF_3 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT3 */
1140 { STB0899_OFF4_EQ_I_OUT_COEFF_4 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT4 */
1141 { STB0899_OFF5_EQ_I_OUT_COEFF_5 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT5 */
1142 { STB0899_OFF6_EQ_I_OUT_COEFF_6 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT6 */
1143 { STB0899_OFF7_EQ_I_OUT_COEFF_7 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT7 */
1144 { STB0899_OFF8_EQ_I_OUT_COEFF_8 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT8 */
1145 { STB0899_OFF9_EQ_I_OUT_COEFF_9 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT9 */
1146 { STB0899_OFFa_EQ_I_OUT_COEFF_10,STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT10*/
1147 { STB0899_OFF0_EQ_Q_OUT_COEFF_0 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT0 */
1148 { STB0899_OFF1_EQ_Q_OUT_COEFF_1 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT1 */
1149 { STB0899_OFF2_EQ_Q_OUT_COEFF_2 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT2 */
1150 { STB0899_OFF3_EQ_Q_OUT_COEFF_3 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT3 */
1151 { STB0899_OFF4_EQ_Q_OUT_COEFF_4 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT4 */
1152 { STB0899_OFF5_EQ_Q_OUT_COEFF_5 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT5 */
1153 { STB0899_OFF6_EQ_Q_OUT_COEFF_6 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT6 */
1154 { STB0899_OFF7_EQ_Q_OUT_COEFF_7 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT7 */
1155 { STB0899_OFF8_EQ_Q_OUT_COEFF_8 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT8 */
1156 { STB0899_OFF9_EQ_Q_OUT_COEFF_9 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT9 */
1157 { STB0899_OFFa_EQ_Q_OUT_COEFF_10, STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT10*/
1158 { 0xffff , 0xffffffff , 0xffffffff },
1159};
1160
1161static const struct stb0899_s1_reg knc1_stb0899_s1_init_3[] = {
1162 { STB0899_DEMOD , 0x00 },
1163 { STB0899_RCOMPC , 0xc9 },
1164 { STB0899_AGC1CN , 0x41 },
1165 { STB0899_AGC1REF , 0x10 },
1166 { STB0899_RTC , 0x7a },
1167 { STB0899_TMGCFG , 0x4e },
1168 { STB0899_AGC2REF , 0x34 },
1169 { STB0899_TLSR , 0x84 },
1170 { STB0899_CFD , 0xee },
1171 { STB0899_ACLC , 0x87 },
1172 { STB0899_BCLC , 0x94 },
1173 { STB0899_EQON , 0x41 },
1174 { STB0899_LDT , 0xdd },
1175 { STB0899_LDT2 , 0xc9 },
1176 { STB0899_EQUALREF , 0xb4 },
1177 { STB0899_TMGRAMP , 0x10 },
1178 { STB0899_TMGTHD , 0x30 },
1179 { STB0899_IDCCOMP , 0xfb },
1180 { STB0899_QDCCOMP , 0x03 },
1181 { STB0899_POWERI , 0x3b },
1182 { STB0899_POWERQ , 0x3d },
1183 { STB0899_RCOMP , 0x81 },
1184 { STB0899_AGCIQIN , 0x80 },
1185 { STB0899_AGC2I1 , 0x04 },
1186 { STB0899_AGC2I2 , 0xf5 },
1187 { STB0899_TLIR , 0x25 },
1188 { STB0899_RTF , 0x80 },
1189 { STB0899_DSTATUS , 0x00 },
1190 { STB0899_LDI , 0xca },
1191 { STB0899_CFRM , 0xf1 },
1192 { STB0899_CFRL , 0xf3 },
1193 { STB0899_NIRM , 0x2a },
1194 { STB0899_NIRL , 0x05 },
1195 { STB0899_ISYMB , 0x17 },
1196 { STB0899_QSYMB , 0xfa },
1197 { STB0899_SFRH , 0x2f },
1198 { STB0899_SFRM , 0x68 },
1199 { STB0899_SFRL , 0x40 },
1200 { STB0899_SFRUPH , 0x2f },
1201 { STB0899_SFRUPM , 0x68 },
1202 { STB0899_SFRUPL , 0x40 },
1203 { STB0899_EQUAI1 , 0xfd },
1204 { STB0899_EQUAQ1 , 0x04 },
1205 { STB0899_EQUAI2 , 0x0f },
1206 { STB0899_EQUAQ2 , 0xff },
1207 { STB0899_EQUAI3 , 0xdf },
1208 { STB0899_EQUAQ3 , 0xfa },
1209 { STB0899_EQUAI4 , 0x37 },
1210 { STB0899_EQUAQ4 , 0x0d },
1211 { STB0899_EQUAI5 , 0xbd },
1212 { STB0899_EQUAQ5 , 0xf7 },
1213 { STB0899_DSTATUS2 , 0x00 },
1214 { STB0899_VSTATUS , 0x00 },
1215 { STB0899_VERROR , 0xff },
1216 { STB0899_IQSWAP , 0x2a },
1217 { STB0899_ECNT1M , 0x00 },
1218 { STB0899_ECNT1L , 0x00 },
1219 { STB0899_ECNT2M , 0x00 },
1220 { STB0899_ECNT2L , 0x00 },
1221 { STB0899_ECNT3M , 0x00 },
1222 { STB0899_ECNT3L , 0x00 },
1223 { STB0899_FECAUTO1 , 0x06 },
1224 { STB0899_FECM , 0x01 },
1225 { STB0899_VTH12 , 0xf0 },
1226 { STB0899_VTH23 , 0xa0 },
1227 { STB0899_VTH34 , 0x78 },
1228 { STB0899_VTH56 , 0x4e },
1229 { STB0899_VTH67 , 0x48 },
1230 { STB0899_VTH78 , 0x38 },
1231 { STB0899_PRVIT , 0xff },
1232 { STB0899_VITSYNC , 0x19 },
1233 { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
1234 { STB0899_TSULC , 0x42 },
1235 { STB0899_RSLLC , 0x40 },
1236 { STB0899_TSLPL , 0x12 },
1237 { STB0899_TSCFGH , 0x0c },
1238 { STB0899_TSCFGM , 0x00 },
1239 { STB0899_TSCFGL , 0x0c },
1240 { STB0899_TSOUT , 0x0d }, /* 0x0d for CAM */
1241 { STB0899_RSSYNCDEL , 0x00 },
1242 { STB0899_TSINHDELH , 0x02 },
1243 { STB0899_TSINHDELM , 0x00 },
1244 { STB0899_TSINHDELL , 0x00 },
1245 { STB0899_TSLLSTKM , 0x00 },
1246 { STB0899_TSLLSTKL , 0x00 },
1247 { STB0899_TSULSTKM , 0x00 },
1248 { STB0899_TSULSTKL , 0xab },
1249 { STB0899_PCKLENUL , 0x00 },
1250 { STB0899_PCKLENLL , 0xcc },
1251 { STB0899_RSPCKLEN , 0xcc },
1252 { STB0899_TSSTATUS , 0x80 },
1253 { STB0899_ERRCTRL1 , 0xb6 },
1254 { STB0899_ERRCTRL2 , 0x96 },
1255 { STB0899_ERRCTRL3 , 0x89 },
1256 { STB0899_DMONMSK1 , 0x27 },
1257 { STB0899_DMONMSK0 , 0x03 },
1258 { STB0899_DEMAPVIT , 0x5c },
1259 { STB0899_PLPARM , 0x1f },
1260 { STB0899_PDELCTRL , 0x48 },
1261 { STB0899_PDELCTRL2 , 0x00 },
1262 { STB0899_BBHCTRL1 , 0x00 },
1263 { STB0899_BBHCTRL2 , 0x00 },
1264 { STB0899_HYSTTHRESH , 0x77 },
1265 { STB0899_MATCSTM , 0x00 },
1266 { STB0899_MATCSTL , 0x00 },
1267 { STB0899_UPLCSTM , 0x00 },
1268 { STB0899_UPLCSTL , 0x00 },
1269 { STB0899_DFLCSTM , 0x00 },
1270 { STB0899_DFLCSTL , 0x00 },
1271 { STB0899_SYNCCST , 0x00 },
1272 { STB0899_SYNCDCSTM , 0x00 },
1273 { STB0899_SYNCDCSTL , 0x00 },
1274 { STB0899_ISI_ENTRY , 0x00 },
1275 { STB0899_ISI_BIT_EN , 0x00 },
1276 { STB0899_MATSTRM , 0x00 },
1277 { STB0899_MATSTRL , 0x00 },
1278 { STB0899_UPLSTRM , 0x00 },
1279 { STB0899_UPLSTRL , 0x00 },
1280 { STB0899_DFLSTRM , 0x00 },
1281 { STB0899_DFLSTRL , 0x00 },
1282 { STB0899_SYNCSTR , 0x00 },
1283 { STB0899_SYNCDSTRM , 0x00 },
1284 { STB0899_SYNCDSTRL , 0x00 },
1285 { STB0899_CFGPDELSTATUS1 , 0x10 },
1286 { STB0899_CFGPDELSTATUS2 , 0x00 },
1287 { STB0899_BBFERRORM , 0x00 },
1288 { STB0899_BBFERRORL , 0x00 },
1289 { STB0899_UPKTERRORM , 0x00 },
1290 { STB0899_UPKTERRORL , 0x00 },
1291 { 0xffff , 0xff },
1292};
1293
1294static const struct stb0899_s2_reg knc1_stb0899_s2_init_4[] = {
1295 { STB0899_OFF0_BLOCK_LNGTH , STB0899_BASE_BLOCK_LNGTH , 0x00000008 }, /* BLOCKLNGTH */
1296 { STB0899_OFF0_ROW_STR , STB0899_BASE_ROW_STR , 0x000000b4 }, /* ROWSTR */
1297 { STB0899_OFF0_BN_END_ADDR , STB0899_BASE_BN_END_ADDR , 0x000004b5 }, /* BNANDADDR */
1298 { STB0899_OFF0_CN_END_ADDR , STB0899_BASE_CN_END_ADDR , 0x00000b4b }, /* CNANDADDR */
1299 { STB0899_OFF0_INFO_LENGTH , STB0899_BASE_INFO_LENGTH , 0x00000078 }, /* INFOLENGTH */
1300 { STB0899_OFF0_BOT_ADDR , STB0899_BASE_BOT_ADDR , 0x000001e0 }, /* BOT_ADDR */
1301 { STB0899_OFF0_BCH_BLK_LN , STB0899_BASE_BCH_BLK_LN , 0x0000a8c0 }, /* BCHBLKLN */
1302 { STB0899_OFF0_BCH_T , STB0899_BASE_BCH_T , 0x0000000c }, /* BCHT */
1303 { STB0899_OFF0_CNFG_MODE , STB0899_BASE_CNFG_MODE , 0x00000001 }, /* CNFGMODE */
1304 { STB0899_OFF0_LDPC_STAT , STB0899_BASE_LDPC_STAT , 0x0000000d }, /* LDPCSTAT */
1305 { STB0899_OFF0_ITER_SCALE , STB0899_BASE_ITER_SCALE , 0x00000040 }, /* ITERSCALE */
1306 { STB0899_OFF0_INPUT_MODE , STB0899_BASE_INPUT_MODE , 0x00000000 }, /* INPUTMODE */
1307 { STB0899_OFF0_LDPCDECRST , STB0899_BASE_LDPCDECRST , 0x00000000 }, /* LDPCDECRST */
1308 { STB0899_OFF0_CLK_PER_BYTE_RW , STB0899_BASE_CLK_PER_BYTE_RW , 0x00000008 }, /* CLKPERBYTE */
1309 { STB0899_OFF0_BCH_ERRORS , STB0899_BASE_BCH_ERRORS , 0x00000000 }, /* BCHERRORS */
1310 { STB0899_OFF0_LDPC_ERRORS , STB0899_BASE_LDPC_ERRORS , 0x00000000 }, /* LDPCERRORS */
1311 { STB0899_OFF0_BCH_MODE , STB0899_BASE_BCH_MODE , 0x00000000 }, /* BCHMODE */
1312 { STB0899_OFF0_ERR_ACC_PER , STB0899_BASE_ERR_ACC_PER , 0x00000008 }, /* ERRACCPER */
1313 { STB0899_OFF0_BCH_ERR_ACC , STB0899_BASE_BCH_ERR_ACC , 0x00000000 }, /* BCHERRACC */
1314 { STB0899_OFF0_FEC_TP_SEL , STB0899_BASE_FEC_TP_SEL , 0x00000000 }, /* FECTPSEL */
1315 { 0xffff , 0xffffffff , 0xffffffff },
1316};
1317
1318static const struct stb0899_s1_reg knc1_stb0899_s1_init_5[] = {
1319 { STB0899_TSTCK , 0x00 },
1320 { STB0899_TSTRES , 0x00 },
1321 { STB0899_TSTOUT , 0x00 },
1322 { STB0899_TSTIN , 0x00 },
1323 { STB0899_TSTSYS , 0x00 },
1324 { STB0899_TSTCHIP , 0x00 },
1325 { STB0899_TSTFREE , 0x00 },
1326 { STB0899_TSTI2C , 0x00 },
1327 { STB0899_BITSPEEDM , 0x00 },
1328 { STB0899_BITSPEEDL , 0x00 },
1329 { STB0899_TBUSBIT , 0x00 },
1330 { STB0899_TSTDIS , 0x00 },
1331 { STB0899_TSTDISRX , 0x00 },
1332 { STB0899_TSTJETON , 0x00 },
1333 { STB0899_TSTDCADJ , 0x00 },
1334 { STB0899_TSTAGC1 , 0x00 },
1335 { STB0899_TSTAGC1N , 0x00 },
1336 { STB0899_TSTPOLYPH , 0x00 },
1337 { STB0899_TSTR , 0x00 },
1338 { STB0899_TSTAGC2 , 0x00 },
1339 { STB0899_TSTCTL1 , 0x00 },
1340 { STB0899_TSTCTL2 , 0x00 },
1341 { STB0899_TSTCTL3 , 0x00 },
1342 { STB0899_TSTDEMAP , 0x00 },
1343 { STB0899_TSTDEMAP2 , 0x00 },
1344 { STB0899_TSTDEMMON , 0x00 },
1345 { STB0899_TSTRATE , 0x00 },
1346 { STB0899_TSTSELOUT , 0x00 },
1347 { STB0899_TSYNC , 0x00 },
1348 { STB0899_TSTERR , 0x00 },
1349 { STB0899_TSTRAM1 , 0x00 },
1350 { STB0899_TSTVSELOUT , 0x00 },
1351 { STB0899_TSTFORCEIN , 0x00 },
1352 { STB0899_TSTRS1 , 0x00 },
1353 { STB0899_TSTRS2 , 0x00 },
1354 { STB0899_TSTRS3 , 0x00 },
1355 { STB0899_GHOSTREG , 0x81 },
1356 { 0xffff , 0xff },
1357};
1358
1359#define KNC1_DVBS2_ESNO_AVE 3
1360#define KNC1_DVBS2_ESNO_QUANT 32
1361#define KNC1_DVBS2_AVFRAMES_COARSE 10
1362#define KNC1_DVBS2_AVFRAMES_FINE 20
1363#define KNC1_DVBS2_MISS_THRESHOLD 6
1364#define KNC1_DVBS2_UWP_THRESHOLD_ACQ 1125
1365#define KNC1_DVBS2_UWP_THRESHOLD_TRACK 758
1366#define KNC1_DVBS2_UWP_THRESHOLD_SOF 1350
1367#define KNC1_DVBS2_SOF_SEARCH_TIMEOUT 1664100
1368
1369#define KNC1_DVBS2_BTR_NCO_BITS 28
1370#define KNC1_DVBS2_BTR_GAIN_SHIFT_OFFSET 15
1371#define KNC1_DVBS2_CRL_NCO_BITS 30
1372#define KNC1_DVBS2_LDPC_MAX_ITER 70
1373
1374static int tda8261_get_frequency(struct dvb_frontend *fe, u32 *frequency)
1375{
1376 struct dvb_frontend_ops *frontend_ops = NULL;
1377 struct dvb_tuner_ops *tuner_ops = NULL;
1378 struct tuner_state t_state;
1379 int err = 0;
1380
1381 if (&fe->ops)
1382 frontend_ops = &fe->ops;
1383 if (&frontend_ops->tuner_ops)
1384 tuner_ops = &frontend_ops->tuner_ops;
1385 if (tuner_ops->get_state) {
1386 if ((err = tuner_ops->get_state(fe, DVBFE_TUNER_FREQUENCY, &t_state)) < 0) {
1387 printk("%s: Invalid parameter\n", __func__);
1388 return err;
1389 }
1390 *frequency = t_state.frequency;
1391 printk("%s: Frequency=%d\n", __func__, t_state.frequency);
1392 }
1393 return 0;
1394}
1395
1396static int tda8261_set_frequency(struct dvb_frontend *fe, u32 frequency)
1397{
1398 struct dvb_frontend_ops *frontend_ops = NULL;
1399 struct dvb_tuner_ops *tuner_ops = NULL;
1400 struct tuner_state t_state;
1401 int err = 0;
1402
1403 t_state.frequency = frequency;
1404 if (&fe->ops)
1405 frontend_ops = &fe->ops;
1406 if (&frontend_ops->tuner_ops)
1407 tuner_ops = &frontend_ops->tuner_ops;
1408 if (tuner_ops->set_state) {
1409 if ((err = tuner_ops->set_state(fe, DVBFE_TUNER_FREQUENCY, &t_state)) < 0) {
1410 printk("%s: Invalid parameter\n", __func__);
1411 return err;
1412 }
1413 }
1414 printk("%s: Frequency=%d\n", __func__, t_state.frequency);
1415 return 0;
1416}
1417
1418static int tda8261_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
1419{
1420 struct dvb_frontend_ops *frontend_ops = &fe->ops;
1421 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
1422 struct tuner_state t_state;
1423 int err = 0;
1424
1425 if (&fe->ops)
1426 frontend_ops = &fe->ops;
1427 if (&frontend_ops->tuner_ops)
1428 tuner_ops = &frontend_ops->tuner_ops;
1429 if (tuner_ops->get_state) {
1430 if ((err = tuner_ops->get_state(fe, DVBFE_TUNER_BANDWIDTH, &t_state)) < 0) {
1431 printk("%s: Invalid parameter\n", __func__);
1432 return err;
1433 }
1434 *bandwidth = t_state.bandwidth;
1435 }
1436 printk("%s: Bandwidth=%d\n", __func__, t_state.bandwidth);
1437 return 0;
1438}
1439
1440/* STB0899 demodulator config for the KNC1 and clones */
1441static struct stb0899_config knc1_dvbs2_config = {
1442 .init_dev = knc1_stb0899_s1_init_1,
1443 .init_s2_demod = knc1_stb0899_s2_init_2,
1444 .init_s1_demod = knc1_stb0899_s1_init_3,
1445 .init_s2_fec = knc1_stb0899_s2_init_4,
1446 .init_tst = knc1_stb0899_s1_init_5,
1447
1448 .demod_address = 0x68,
1449// .ts_output_mode = STB0899_OUT_PARALLEL, /* types = SERIAL/PARALLEL */
1450 .block_sync_mode = STB0899_SYNC_FORCED, /* DSS, SYNC_FORCED/UNSYNCED */
1451// .ts_pfbit_toggle = STB0899_MPEG_NORMAL, /* DirecTV, MPEG toggling seq */
1452
1453 .xtal_freq = 27000000,
1454 .inversion = 1,
1455
1456 .esno_ave = KNC1_DVBS2_ESNO_AVE,
1457 .esno_quant = KNC1_DVBS2_ESNO_QUANT,
1458 .avframes_coarse = KNC1_DVBS2_AVFRAMES_COARSE,
1459 .avframes_fine = KNC1_DVBS2_AVFRAMES_FINE,
1460 .miss_threshold = KNC1_DVBS2_MISS_THRESHOLD,
1461 .uwp_threshold_acq = KNC1_DVBS2_UWP_THRESHOLD_ACQ,
1462 .uwp_threshold_track = KNC1_DVBS2_UWP_THRESHOLD_TRACK,
1463 .uwp_threshold_sof = KNC1_DVBS2_UWP_THRESHOLD_SOF,
1464 .sof_search_timeout = KNC1_DVBS2_SOF_SEARCH_TIMEOUT,
1465
1466 .btr_nco_bits = KNC1_DVBS2_BTR_NCO_BITS,
1467 .btr_gain_shift_offset = KNC1_DVBS2_BTR_GAIN_SHIFT_OFFSET,
1468 .crl_nco_bits = KNC1_DVBS2_CRL_NCO_BITS,
1469 .ldpc_max_iter = KNC1_DVBS2_LDPC_MAX_ITER,
1470
1471 .tuner_get_frequency = tda8261_get_frequency,
1472 .tuner_set_frequency = tda8261_set_frequency,
1473 .tuner_set_bandwidth = NULL,
1474 .tuner_get_bandwidth = tda8261_get_bandwidth,
1475 .tuner_set_rfsiggain = NULL,
1476};
1477
1478/* SD1878 tuner config */
1479static const struct tda8261_config sd1878c_config = {
1480// .name = "SD1878C",
1481 .addr = 0x60,
1482 .step_size = TDA8261_STEP_1000 /* kHz */
1483};
1484
885static u8 read_pwm(struct budget_av *budget_av) 1485static u8 read_pwm(struct budget_av *budget_av)
886{ 1486{
887 u8 b = 0xff; 1487 u8 b = 0xff;
@@ -905,6 +1505,8 @@ static u8 read_pwm(struct budget_av *budget_av)
905#define SUBID_DVBS_TV_STAR 0x0014 1505#define SUBID_DVBS_TV_STAR 0x0014
906#define SUBID_DVBS_TV_STAR_PLUS_X4 0x0015 1506#define SUBID_DVBS_TV_STAR_PLUS_X4 0x0015
907#define SUBID_DVBS_TV_STAR_CI 0x0016 1507#define SUBID_DVBS_TV_STAR_CI 0x0016
1508#define SUBID_DVBS2_KNC1 0x0018
1509#define SUBID_DVBS2_KNC1_OEM 0x0019
908#define SUBID_DVBS_EASYWATCH_1 0x001a 1510#define SUBID_DVBS_EASYWATCH_1 0x001a
909#define SUBID_DVBS_EASYWATCH_2 0x001b 1511#define SUBID_DVBS_EASYWATCH_2 0x001b
910#define SUBID_DVBS_EASYWATCH 0x001e 1512#define SUBID_DVBS_EASYWATCH 0x001e
@@ -941,6 +1543,8 @@ static void frontend_init(struct budget_av *budget_av)
941 case SUBID_DVBT_KNC1_PLUS: 1543 case SUBID_DVBT_KNC1_PLUS:
942 case SUBID_DVBC_EASYWATCH: 1544 case SUBID_DVBC_EASYWATCH:
943 case SUBID_DVBC_KNC1_PLUS_MK3: 1545 case SUBID_DVBC_KNC1_PLUS_MK3:
1546 case SUBID_DVBS2_KNC1:
1547 case SUBID_DVBS2_KNC1_OEM:
944 saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTHI); 1548 saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTHI);
945 break; 1549 break;
946 } 1550 }
@@ -993,7 +1597,13 @@ static void frontend_init(struct budget_av *budget_av)
993 fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params; 1597 fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params;
994 } 1598 }
995 break; 1599 break;
1600 case SUBID_DVBS2_KNC1:
1601 case SUBID_DVBS2_KNC1_OEM:
1602 budget_av->reinitialise_demod = 1;
1603 if ((fe = stb0899_attach(&knc1_dvbs2_config, &budget_av->budget.i2c_adap)))
1604 tda8261_attach(fe, &sd1878c_config, &budget_av->budget.i2c_adap);
996 1605
1606 break;
997 case SUBID_DVBS_CINERGY1200: 1607 case SUBID_DVBS_CINERGY1200:
998 fe = dvb_attach(stv0299_attach, &cinergy_1200s_config, 1608 fe = dvb_attach(stv0299_attach, &cinergy_1200s_config,
999 &budget_av->budget.i2c_adap); 1609 &budget_av->budget.i2c_adap);
@@ -1260,6 +1870,7 @@ static struct saa7146_ext_vv vv_data = {
1260static struct saa7146_extension budget_extension; 1870static struct saa7146_extension budget_extension;
1261 1871
1262MAKE_BUDGET_INFO(knc1s, "KNC1 DVB-S", BUDGET_KNC1S); 1872MAKE_BUDGET_INFO(knc1s, "KNC1 DVB-S", BUDGET_KNC1S);
1873MAKE_BUDGET_INFO(knc1s2,"KNC1 DVB-S2", BUDGET_KNC1S2);
1263MAKE_BUDGET_INFO(knc1c, "KNC1 DVB-C", BUDGET_KNC1C); 1874MAKE_BUDGET_INFO(knc1c, "KNC1 DVB-C", BUDGET_KNC1C);
1264MAKE_BUDGET_INFO(knc1t, "KNC1 DVB-T", BUDGET_KNC1T); 1875MAKE_BUDGET_INFO(knc1t, "KNC1 DVB-T", BUDGET_KNC1T);
1265MAKE_BUDGET_INFO(kncxs, "KNC TV STAR DVB-S", BUDGET_TVSTAR); 1876MAKE_BUDGET_INFO(kncxs, "KNC TV STAR DVB-S", BUDGET_TVSTAR);
@@ -1290,6 +1901,8 @@ static struct pci_device_id pci_tbl[] = {
1290 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0014), 1901 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0014),
1291 MAKE_EXTENSION_PCI(knc1spx4, 0x1894, 0x0015), 1902 MAKE_EXTENSION_PCI(knc1spx4, 0x1894, 0x0015),
1292 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0016), 1903 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0016),
1904 MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0018),
1905 MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0019),
1293 MAKE_EXTENSION_PCI(satewpls, 0x1894, 0x001e), 1906 MAKE_EXTENSION_PCI(satewpls, 0x1894, 0x001e),
1294 MAKE_EXTENSION_PCI(satewpls1, 0x1894, 0x001a), 1907 MAKE_EXTENSION_PCI(satewpls1, 0x1894, 0x001a),
1295 MAKE_EXTENSION_PCI(satewps, 0x1894, 0x001b), 1908 MAKE_EXTENSION_PCI(satewps, 0x1894, 0x001b),
diff --git a/drivers/media/dvb/ttpci/budget.h b/drivers/media/dvb/ttpci/budget.h
index 86435bf16260..3ad0c6789ba7 100644
--- a/drivers/media/dvb/ttpci/budget.h
+++ b/drivers/media/dvb/ttpci/budget.h
@@ -103,6 +103,7 @@ static struct saa7146_pci_extension_data x_var = { \
103#define BUDGET_CIN1200C_MK3 15 103#define BUDGET_CIN1200C_MK3 15
104#define BUDGET_KNC1C_MK3 16 104#define BUDGET_KNC1C_MK3 16
105#define BUDGET_KNC1CP_MK3 17 105#define BUDGET_KNC1CP_MK3 17
106#define BUDGET_KNC1S2 18
106 107
107#define BUDGET_VIDEO_PORTA 0 108#define BUDGET_VIDEO_PORTA 0
108#define BUDGET_VIDEO_PORTB 1 109#define BUDGET_VIDEO_PORTB 1
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 04:57:40 -0500