diff options
author | Andrew Vasquez <andrew.vasquez@qlogic.com> | 2009-06-03 12:55:26 -0400 |
---|---|---|
committer | James Bottomley <James.Bottomley@HansenPartnership.com> | 2009-06-08 15:46:54 -0400 |
commit | aed10881129c52f0e5dc1c96ac706b5ce7708a13 (patch) | |
tree | 7c5e83f9d1f318f581792a0e2988aa44dd5ac7e6 /drivers | |
parent | e8233ca40bfe7b9dade6cefc984e305516c4eceb (diff) |
[SCSI] qla2xxx: Query supported RISC registers bits in determining a paused-state.
ISP24xx and above must query the host-status register, not HCCR.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 6 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_fw.h | 1 |
2 files changed, 2 insertions, 5 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 68671a2b8b7f..4a990f4da4ea 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c | |||
@@ -149,11 +149,9 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |||
149 | int rval = QLA_SUCCESS; | 149 | int rval = QLA_SUCCESS; |
150 | uint32_t cnt; | 150 | uint32_t cnt; |
151 | 151 | ||
152 | if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) | ||
153 | return rval; | ||
154 | |||
155 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); | 152 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
156 | for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && | 153 | for (cnt = 30000; |
154 | ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && | ||
157 | rval == QLA_SUCCESS; cnt--) { | 155 | rval == QLA_SUCCESS; cnt--) { |
158 | if (cnt) | 156 | if (cnt) |
159 | udelay(100); | 157 | udelay(100); |
diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h index 9e56d4a4cb75..dfde2dd865cb 100644 --- a/drivers/scsi/qla2xxx/qla_fw.h +++ b/drivers/scsi/qla2xxx/qla_fw.h | |||
@@ -878,7 +878,6 @@ struct device_reg_24xx { | |||
878 | /* HCCR statuses. */ | 878 | /* HCCR statuses. */ |
879 | #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ | 879 | #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ |
880 | #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ | 880 | #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ |
881 | #define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */ | ||
882 | /* HCCR commands. */ | 881 | /* HCCR commands. */ |
883 | /* NOOP. */ | 882 | /* NOOP. */ |
884 | #define HCCRX_NOOP 0x00000000 | 883 | #define HCCRX_NOOP 0x00000000 |