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authorLuis R. Rodriguez <lrodriguez@atheros.com>2008-12-23 18:58:40 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-01-29 15:59:29 -0500
commitae8d2858c54f52dc4df513a818cc4e1257fd9143 (patch)
treee58f270784474a5d244b8d296b8e10bb6c912fa2 /drivers
parentce111badf5ac387e9eefe1f2bba751f595994cb2 (diff)
ath9k: consolidate arguments on hw reset
HW reset calls pass the same variables or structs which we can obtain easily from ah. Although this also applies during channel changes as we will keep around the ath9k_channel passed as an argument for now. We now also now propagate the hw reset errors down. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h7
-rw-r--r--drivers/net/wireless/ath9k/hw.c68
-rw-r--r--drivers/net/wireless/ath9k/main.c110
-rw-r--r--drivers/net/wireless/ath9k/xmit.c16
4 files changed, 74 insertions, 127 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index d27813502953..0f6a99a3f21a 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -843,11 +843,8 @@ void ath9k_hw_rfdetach(struct ath_hal *ah);
843 843
844/* HW Reset */ 844/* HW Reset */
845 845
846bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, 846int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
847 enum ath9k_ht_macmode macmode, 847 bool bChannelChange);
848 u8 txchainmask, u8 rxchainmask,
849 enum ath9k_ht_extprotspacing extprotspacing,
850 bool bChannelChange, int *status);
851 848
852/* Key Cache Management */ 849/* Key Cache Management */
853 850
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 34474edefc97..46029ec13545 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -2222,23 +2222,20 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha
2222 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2222 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2223} 2223}
2224 2224
2225bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, 2225int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2226 enum ath9k_ht_macmode macmode, 2226 bool bChannelChange)
2227 u8 txchainmask, u8 rxchainmask,
2228 enum ath9k_ht_extprotspacing extprotspacing,
2229 bool bChannelChange, int *status)
2230{ 2227{
2231 u32 saveLedState; 2228 u32 saveLedState;
2229 struct ath_softc *sc = ah->ah_sc;
2232 struct ath_hal_5416 *ahp = AH5416(ah); 2230 struct ath_hal_5416 *ahp = AH5416(ah);
2233 struct ath9k_channel *curchan = ah->ah_curchan; 2231 struct ath9k_channel *curchan = ah->ah_curchan;
2234 u32 saveDefAntenna; 2232 u32 saveDefAntenna;
2235 u32 macStaId1; 2233 u32 macStaId1;
2236 int ecode; 2234 int i, rx_chainmask, r;
2237 int i, rx_chainmask;
2238 2235
2239 ahp->ah_extprotspacing = extprotspacing; 2236 ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2240 ahp->ah_txchainmask = txchainmask; 2237 ahp->ah_txchainmask = sc->sc_tx_chainmask;
2241 ahp->ah_rxchainmask = rxchainmask; 2238 ahp->ah_rxchainmask = sc->sc_rx_chainmask;
2242 2239
2243 if (AR_SREV_9280(ah)) { 2240 if (AR_SREV_9280(ah)) {
2244 ahp->ah_txchainmask &= 0x3; 2241 ahp->ah_txchainmask &= 0x3;
@@ -2249,14 +2246,11 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2249 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 2246 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2250 "invalid channel %u/0x%x; no mapping\n", 2247 "invalid channel %u/0x%x; no mapping\n",
2251 chan->channel, chan->channelFlags); 2248 chan->channel, chan->channelFlags);
2252 ecode = -EINVAL; 2249 return -EINVAL;
2253 goto bad;
2254 } 2250 }
2255 2251
2256 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 2252 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2257 ecode = -EIO; 2253 return -EIO;
2258 goto bad;
2259 }
2260 2254
2261 if (curchan) 2255 if (curchan)
2262 ath9k_hw_getnf(ah, curchan); 2256 ath9k_hw_getnf(ah, curchan);
@@ -2270,10 +2264,10 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2270 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && 2264 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2271 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) { 2265 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2272 2266
2273 if (ath9k_hw_channel_change(ah, chan, macmode)) { 2267 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2274 ath9k_hw_loadnf(ah, ah->ah_curchan); 2268 ath9k_hw_loadnf(ah, ah->ah_curchan);
2275 ath9k_hw_start_nfcal(ah); 2269 ath9k_hw_start_nfcal(ah);
2276 return true; 2270 return 0;
2277 } 2271 }
2278 } 2272 }
2279 2273
@@ -2291,8 +2285,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2291 2285
2292 if (!ath9k_hw_chip_reset(ah, chan)) { 2286 if (!ath9k_hw_chip_reset(ah, chan)) {
2293 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n"); 2287 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2294 ecode = -EINVAL; 2288 return -EINVAL;
2295 goto bad;
2296 } 2289 }
2297 2290
2298 if (AR_SREV_9280(ah)) { 2291 if (AR_SREV_9280(ah)) {
@@ -2308,11 +2301,9 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2308 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 2301 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2309 } 2302 }
2310 2303
2311 ecode = ath9k_hw_process_ini(ah, chan, macmode); 2304 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2312 if (ecode != 0) { 2305 if (r)
2313 ecode = -EINVAL; 2306 return r;
2314 goto bad;
2315 }
2316 2307
2317 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2308 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2318 ath9k_hw_set_delta_slope(ah, chan); 2309 ath9k_hw_set_delta_slope(ah, chan);
@@ -2325,8 +2316,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2325 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { 2316 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2326 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2317 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2327 "error setting board options\n"); 2318 "error setting board options\n");
2328 ecode = -EIO; 2319 return -EIO;
2329 goto bad;
2330 } 2320 }
2331 2321
2332 ath9k_hw_decrease_chain_power(ah, chan); 2322 ath9k_hw_decrease_chain_power(ah, chan);
@@ -2354,15 +2344,11 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2354 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2344 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2355 2345
2356 if (AR_SREV_9280_10_OR_LATER(ah)) { 2346 if (AR_SREV_9280_10_OR_LATER(ah)) {
2357 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 2347 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2358 ecode = -EIO; 2348 return -EIO;
2359 goto bad;
2360 }
2361 } else { 2349 } else {
2362 if (!(ath9k_hw_set_channel(ah, chan))) { 2350 if (!(ath9k_hw_set_channel(ah, chan)))
2363 ecode = -EIO; 2351 return -EIO;
2364 goto bad;
2365 }
2366 } 2352 }
2367 2353
2368 for (i = 0; i < AR_NUM_DCU; i++) 2354 for (i = 0; i < AR_NUM_DCU; i++)
@@ -2396,10 +2382,8 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2396 2382
2397 ath9k_hw_init_bb(ah, chan); 2383 ath9k_hw_init_bb(ah, chan);
2398 2384
2399 if (!ath9k_hw_init_cal(ah, chan)){ 2385 if (!ath9k_hw_init_cal(ah, chan))
2400 ecode = -EIO;; 2386 return -EIO;;
2401 goto bad;
2402 }
2403 2387
2404 rx_chainmask = ahp->ah_rxchainmask; 2388 rx_chainmask = ahp->ah_rxchainmask;
2405 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2389 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
@@ -2428,11 +2412,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2428#endif 2412#endif
2429 } 2413 }
2430 2414
2431 return true; 2415 return 0;
2432bad:
2433 if (status)
2434 *status = ecode;
2435 return false;
2436} 2416}
2437 2417
2438/************************/ 2418/************************/
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index 0087a907aac4..c65b27bd9f5f 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -260,6 +260,8 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
260 struct ath_hal *ah = sc->sc_ah; 260 struct ath_hal *ah = sc->sc_ah;
261 bool fastcc = true, stopped; 261 bool fastcc = true, stopped;
262 struct ieee80211_hw *hw = sc->hw; 262 struct ieee80211_hw *hw = sc->hw;
263 struct ieee80211_channel *channel = hw->conf.channel;
264 int r;
263 265
264 if (sc->sc_flags & SC_OP_INVALID) 266 if (sc->sc_flags & SC_OP_INVALID)
265 return -EIO; 267 return -EIO;
@@ -268,7 +270,6 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
268 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags || 270 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
269 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) || 271 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
270 (sc->sc_flags & SC_OP_FULL_RESET)) { 272 (sc->sc_flags & SC_OP_FULL_RESET)) {
271 int status;
272 /* 273 /*
273 * This is only performed if the channel settings have 274 * This is only performed if the channel settings have
274 * actually changed. 275 * actually changed.
@@ -290,22 +291,20 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
290 fastcc = false; 291 fastcc = false;
291 292
292 DPRINTF(sc, ATH_DBG_CONFIG, 293 DPRINTF(sc, ATH_DBG_CONFIG,
293 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n", 294 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
294 sc->sc_ah->ah_curchan->channel, 295 sc->sc_ah->ah_curchan->channel,
295 hchan->channel, hchan->channelFlags, sc->tx_chan_width); 296 channel->center_freq, sc->tx_chan_width);
296 297
297 spin_lock_bh(&sc->sc_resetlock); 298 spin_lock_bh(&sc->sc_resetlock);
298 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width, 299
299 sc->sc_tx_chainmask, sc->sc_rx_chainmask, 300 r = ath9k_hw_reset(ah, hchan, fastcc);
300 sc->sc_ht_extprotspacing, fastcc, &status)) { 301 if (r) {
301 DPRINTF(sc, ATH_DBG_FATAL, 302 DPRINTF(sc, ATH_DBG_FATAL,
302 "Unable to reset channel %u (%uMhz) " 303 "Unable to reset channel (%u Mhz) "
303 "flags 0x%x hal status %u\n", 304 "reset status %u\n",
304 ath9k_hw_mhz2ieee(ah, hchan->channel, 305 channel->center_freq, r);
305 hchan->channelFlags),
306 hchan->channel, hchan->channelFlags, status);
307 spin_unlock_bh(&sc->sc_resetlock); 306 spin_unlock_bh(&sc->sc_resetlock);
308 return -EIO; 307 return r;
309 } 308 }
310 spin_unlock_bh(&sc->sc_resetlock); 309 spin_unlock_bh(&sc->sc_resetlock);
311 310
@@ -1069,23 +1068,18 @@ fail:
1069static void ath_radio_enable(struct ath_softc *sc) 1068static void ath_radio_enable(struct ath_softc *sc)
1070{ 1069{
1071 struct ath_hal *ah = sc->sc_ah; 1070 struct ath_hal *ah = sc->sc_ah;
1072 int status; 1071 struct ieee80211_channel *channel = sc->hw->conf.channel;
1072 int r;
1073 1073
1074 spin_lock_bh(&sc->sc_resetlock); 1074 spin_lock_bh(&sc->sc_resetlock);
1075 if (!ath9k_hw_reset(ah, ah->ah_curchan, 1075
1076 sc->tx_chan_width, 1076 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1077 sc->sc_tx_chainmask, 1077
1078 sc->sc_rx_chainmask, 1078 if (r) {
1079 sc->sc_ht_extprotspacing,
1080 false, &status)) {
1081 DPRINTF(sc, ATH_DBG_FATAL, 1079 DPRINTF(sc, ATH_DBG_FATAL,
1082 "Unable to reset channel %u (%uMhz) " 1080 "Unable to reset channel %u (%uMhz) ",
1083 "flags 0x%x hal status %u\n", 1081 "reset status %u\n",
1084 ath9k_hw_mhz2ieee(ah, 1082 channel->center_freq, r);
1085 ah->ah_curchan->channel,
1086 ah->ah_curchan->channelFlags),
1087 ah->ah_curchan->channel,
1088 ah->ah_curchan->channelFlags, status);
1089 } 1083 }
1090 spin_unlock_bh(&sc->sc_resetlock); 1084 spin_unlock_bh(&sc->sc_resetlock);
1091 1085
@@ -1113,8 +1107,8 @@ static void ath_radio_enable(struct ath_softc *sc)
1113static void ath_radio_disable(struct ath_softc *sc) 1107static void ath_radio_disable(struct ath_softc *sc)
1114{ 1108{
1115 struct ath_hal *ah = sc->sc_ah; 1109 struct ath_hal *ah = sc->sc_ah;
1116 int status; 1110 struct ieee80211_channel *channel = sc->hw->conf.channel;
1117 1111 int r;
1118 1112
1119 ieee80211_stop_queues(sc->hw); 1113 ieee80211_stop_queues(sc->hw);
1120 1114
@@ -1130,20 +1124,12 @@ static void ath_radio_disable(struct ath_softc *sc)
1130 ath_flushrecv(sc); /* flush recv queue */ 1124 ath_flushrecv(sc); /* flush recv queue */
1131 1125
1132 spin_lock_bh(&sc->sc_resetlock); 1126 spin_lock_bh(&sc->sc_resetlock);
1133 if (!ath9k_hw_reset(ah, ah->ah_curchan, 1127 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1134 sc->tx_chan_width, 1128 if (r) {
1135 sc->sc_tx_chainmask,
1136 sc->sc_rx_chainmask,
1137 sc->sc_ht_extprotspacing,
1138 false, &status)) {
1139 DPRINTF(sc, ATH_DBG_FATAL, 1129 DPRINTF(sc, ATH_DBG_FATAL,
1140 "Unable to reset channel %u (%uMhz) " 1130 "Unable to reset channel %u (%uMhz) "
1141 "flags 0x%x hal status %u\n", 1131 "reset status %u\n",
1142 ath9k_hw_mhz2ieee(ah, 1132 channel->center_freq, r);
1143 ah->ah_curchan->channel,
1144 ah->ah_curchan->channelFlags),
1145 ah->ah_curchan->channel,
1146 ah->ah_curchan->channelFlags, status);
1147 } 1133 }
1148 spin_unlock_bh(&sc->sc_resetlock); 1134 spin_unlock_bh(&sc->sc_resetlock);
1149 1135
@@ -1622,8 +1608,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1622{ 1608{
1623 struct ath_hal *ah = sc->sc_ah; 1609 struct ath_hal *ah = sc->sc_ah;
1624 struct ieee80211_hw *hw = sc->hw; 1610 struct ieee80211_hw *hw = sc->hw;
1625 int status; 1611 int r;
1626 int error = 0;
1627 1612
1628 ath9k_hw_set_interrupts(ah, 0); 1613 ath9k_hw_set_interrupts(ah, 0);
1629 ath_draintxq(sc, retry_tx); 1614 ath_draintxq(sc, retry_tx);
@@ -1631,14 +1616,10 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1631 ath_flushrecv(sc); 1616 ath_flushrecv(sc);
1632 1617
1633 spin_lock_bh(&sc->sc_resetlock); 1618 spin_lock_bh(&sc->sc_resetlock);
1634 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, 1619 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1635 sc->tx_chan_width, 1620 if (r)
1636 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1637 sc->sc_ht_extprotspacing, false, &status)) {
1638 DPRINTF(sc, ATH_DBG_FATAL, 1621 DPRINTF(sc, ATH_DBG_FATAL,
1639 "Unable to reset hardware; hal status %u\n", status); 1622 "Unable to reset hardware; reset status %u\n", r);
1640 error = -EIO;
1641 }
1642 spin_unlock_bh(&sc->sc_resetlock); 1623 spin_unlock_bh(&sc->sc_resetlock);
1643 1624
1644 if (ath_startrecv(sc) != 0) 1625 if (ath_startrecv(sc) != 0)
@@ -1669,7 +1650,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1669 } 1650 }
1670 } 1651 }
1671 1652
1672 return error; 1653 return r;
1673} 1654}
1674 1655
1675/* 1656/*
@@ -1852,7 +1833,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1852 struct ath_softc *sc = hw->priv; 1833 struct ath_softc *sc = hw->priv;
1853 struct ieee80211_channel *curchan = hw->conf.channel; 1834 struct ieee80211_channel *curchan = hw->conf.channel;
1854 struct ath9k_channel *init_channel; 1835 struct ath9k_channel *init_channel;
1855 int error = 0, pos, status; 1836 int r, pos;
1856 1837
1857 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with " 1838 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1858 "initial channel: %d MHz\n", curchan->center_freq); 1839 "initial channel: %d MHz\n", curchan->center_freq);
@@ -1862,8 +1843,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1862 pos = ath_get_channel(sc, curchan); 1843 pos = ath_get_channel(sc, curchan);
1863 if (pos == -1) { 1844 if (pos == -1) {
1864 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq); 1845 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1865 error = -EINVAL; 1846 return -EINVAL;
1866 goto error;
1867 } 1847 }
1868 1848
1869 sc->tx_chan_width = ATH9K_HT_MACMODE_20; 1849 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
@@ -1882,17 +1862,14 @@ static int ath9k_start(struct ieee80211_hw *hw)
1882 * and then setup of the interrupt mask. 1862 * and then setup of the interrupt mask.
1883 */ 1863 */
1884 spin_lock_bh(&sc->sc_resetlock); 1864 spin_lock_bh(&sc->sc_resetlock);
1885 if (!ath9k_hw_reset(sc->sc_ah, init_channel, 1865 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1886 sc->tx_chan_width, 1866 if (r) {
1887 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1888 sc->sc_ht_extprotspacing, false, &status)) {
1889 DPRINTF(sc, ATH_DBG_FATAL, 1867 DPRINTF(sc, ATH_DBG_FATAL,
1890 "Unable to reset hardware; hal status %u " 1868 "Unable to reset hardware; reset status %u "
1891 "(freq %u flags 0x%x)\n", status, 1869 "(freq %u MHz)\n", r,
1892 init_channel->channel, init_channel->channelFlags); 1870 curchan->center_freq);
1893 error = -EIO;
1894 spin_unlock_bh(&sc->sc_resetlock); 1871 spin_unlock_bh(&sc->sc_resetlock);
1895 goto error; 1872 return r;
1896 } 1873 }
1897 spin_unlock_bh(&sc->sc_resetlock); 1874 spin_unlock_bh(&sc->sc_resetlock);
1898 1875
@@ -1912,8 +1889,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1912 if (ath_startrecv(sc) != 0) { 1889 if (ath_startrecv(sc) != 0) {
1913 DPRINTF(sc, ATH_DBG_FATAL, 1890 DPRINTF(sc, ATH_DBG_FATAL,
1914 "Unable to start recv logic\n"); 1891 "Unable to start recv logic\n");
1915 error = -EIO; 1892 return -EIO;
1916 goto error;
1917 } 1893 }
1918 1894
1919 /* Setup our intr mask. */ 1895 /* Setup our intr mask. */
@@ -1957,11 +1933,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
1957 ieee80211_wake_queues(sc->hw); 1933 ieee80211_wake_queues(sc->hw);
1958 1934
1959#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1935#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1960 error = ath_start_rfkill_poll(sc); 1936 r = ath_start_rfkill_poll(sc);
1961#endif 1937#endif
1962 1938 return r;
1963error:
1964 return error;
1965} 1939}
1966 1940
1967static int ath9k_tx(struct ieee80211_hw *hw, 1941static int ath9k_tx(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c
index 3e192fd9591c..e28889bc0ac5 100644
--- a/drivers/net/wireless/ath9k/xmit.c
+++ b/drivers/net/wireless/ath9k/xmit.c
@@ -1140,7 +1140,7 @@ static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1140static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx) 1140static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1141{ 1141{
1142 struct ath_hal *ah = sc->sc_ah; 1142 struct ath_hal *ah = sc->sc_ah;
1143 int i, status, npend = 0; 1143 int i, npend = 0;
1144 1144
1145 if (!(sc->sc_flags & SC_OP_INVALID)) { 1145 if (!(sc->sc_flags & SC_OP_INVALID)) {
1146 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1146 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
@@ -1155,20 +1155,16 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1155 } 1155 }
1156 1156
1157 if (npend) { 1157 if (npend) {
1158 int r;
1158 /* TxDMA not stopped, reset the hal */ 1159 /* TxDMA not stopped, reset the hal */
1159 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1160 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1160 1161
1161 spin_lock_bh(&sc->sc_resetlock); 1162 spin_lock_bh(&sc->sc_resetlock);
1162 if (!ath9k_hw_reset(ah, 1163 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true);
1163 sc->sc_ah->ah_curchan, 1164 if (r)
1164 sc->tx_chan_width,
1165 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1166 sc->sc_ht_extprotspacing, true, &status)) {
1167
1168 DPRINTF(sc, ATH_DBG_FATAL, 1165 DPRINTF(sc, ATH_DBG_FATAL,
1169 "Unable to reset hardware; hal status %u\n", 1166 "Unable to reset hardware; reset status %u\n",
1170 status); 1167 r);
1171 }
1172 spin_unlock_bh(&sc->sc_resetlock); 1168 spin_unlock_bh(&sc->sc_resetlock);
1173 } 1169 }
1174 1170