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authorMichael Barkowski <michael.barkowski@freescale.com>2007-04-13 02:26:15 -0400
committerJeff Garzik <jeff@garzik.org>2007-04-28 11:01:04 -0400
commit7563907eb8aad8f15b6a39fa6d863c091d83ef48 (patch)
tree6fc5b8f2f5c0bd7845cefba8352cad7b2b84deda /drivers
parent702ff12ce7e9643084232a8d50b0b1eec26026ae (diff)
ucc_geth: Fix interrupt coalescing size and alignment
The rx interrupt coalescing table alignment was "guessed" to be 4, but should be 64. The size should be 8 * number of queues + 4. Verified in the MPC8323E manual. Signed-off-by: Michael Barkowski <Michael.Barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ucc_geth.c4
-rw-r--r--drivers/net/ucc_geth.h3
2 files changed, 3 insertions, 4 deletions
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 60be1e775380..1a16ab20b39e 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -2958,8 +2958,8 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2958 /* Size varies with number of Rx queues */ 2958 /* Size varies with number of Rx queues */
2959 ugeth->rx_irq_coalescing_tbl_offset = 2959 ugeth->rx_irq_coalescing_tbl_offset =
2960 qe_muram_alloc(ug_info->numQueuesRx * 2960 qe_muram_alloc(ug_info->numQueuesRx *
2961 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry), 2961 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2962 UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2962 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2963 if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) { 2963 if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) {
2964 ugeth_err 2964 ugeth_err
2965 ("%s: Can not allocate DPRAM memory for" 2965 ("%s: Can not allocate DPRAM memory for"
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index 7cf3dbc9fd4c..a29e1c3ca4b7 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -867,8 +867,7 @@ struct ucc_geth_hardware_statistics {
867#define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */ 867#define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */
868#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 868#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */
869#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 869#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */
870#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 4 /* This is a 870#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64
871 guess */
872#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */ 871#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */
873#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */ 872#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */
874#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This 873#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This